irq.c 8.0 KB

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  1. /*
  2. * arch/mips/emma2rh/markeins/irq.c
  3. * This file defines the irq handler for EMMA2RH.
  4. *
  5. * Copyright (C) NEC Electronics Corporation 2004-2006
  6. *
  7. * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
  8. *
  9. * Copyright 2001 MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/irq.h>
  28. #include <linux/types.h>
  29. #include <linux/ptrace.h>
  30. #include <linux/delay.h>
  31. #include <asm/irq_cpu.h>
  32. #include <asm/system.h>
  33. #include <asm/mipsregs.h>
  34. #include <asm/addrspace.h>
  35. #include <asm/bootinfo.h>
  36. #include <asm/emma/emma2rh.h>
  37. static void emma2rh_irq_enable(unsigned int irq)
  38. {
  39. u32 reg_value;
  40. u32 reg_bitmask;
  41. u32 reg_index;
  42. irq -= EMMA2RH_IRQ_BASE;
  43. reg_index = EMMA2RH_BHIF_INT_EN_0 +
  44. (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
  45. reg_value = emma2rh_in32(reg_index);
  46. reg_bitmask = 0x1 << (irq % 32);
  47. emma2rh_out32(reg_index, reg_value | reg_bitmask);
  48. }
  49. static void emma2rh_irq_disable(unsigned int irq)
  50. {
  51. u32 reg_value;
  52. u32 reg_bitmask;
  53. u32 reg_index;
  54. irq -= EMMA2RH_IRQ_BASE;
  55. reg_index = EMMA2RH_BHIF_INT_EN_0 +
  56. (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
  57. reg_value = emma2rh_in32(reg_index);
  58. reg_bitmask = 0x1 << (irq % 32);
  59. emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
  60. }
  61. struct irq_chip emma2rh_irq_controller = {
  62. .name = "emma2rh_irq",
  63. .ack = emma2rh_irq_disable,
  64. .mask = emma2rh_irq_disable,
  65. .mask_ack = emma2rh_irq_disable,
  66. .unmask = emma2rh_irq_enable,
  67. };
  68. void emma2rh_irq_init(void)
  69. {
  70. u32 i;
  71. for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
  72. set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
  73. &emma2rh_irq_controller,
  74. handle_level_irq);
  75. }
  76. static void emma2rh_sw_irq_enable(unsigned int irq)
  77. {
  78. u32 reg;
  79. irq -= EMMA2RH_SW_IRQ_BASE;
  80. reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
  81. reg |= 1 << irq;
  82. emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
  83. }
  84. static void emma2rh_sw_irq_disable(unsigned int irq)
  85. {
  86. u32 reg;
  87. irq -= EMMA2RH_SW_IRQ_BASE;
  88. reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
  89. reg &= ~(1 << irq);
  90. emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
  91. }
  92. struct irq_chip emma2rh_sw_irq_controller = {
  93. .name = "emma2rh_sw_irq",
  94. .ack = emma2rh_sw_irq_disable,
  95. .mask = emma2rh_sw_irq_disable,
  96. .mask_ack = emma2rh_sw_irq_disable,
  97. .unmask = emma2rh_sw_irq_enable,
  98. };
  99. void emma2rh_sw_irq_init(void)
  100. {
  101. u32 i;
  102. for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
  103. set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
  104. &emma2rh_sw_irq_controller,
  105. handle_level_irq);
  106. }
  107. static void emma2rh_gpio_irq_enable(unsigned int irq)
  108. {
  109. u32 reg;
  110. irq -= EMMA2RH_GPIO_IRQ_BASE;
  111. reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  112. reg |= 1 << irq;
  113. emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
  114. }
  115. static void emma2rh_gpio_irq_disable(unsigned int irq)
  116. {
  117. u32 reg;
  118. irq -= EMMA2RH_GPIO_IRQ_BASE;
  119. reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  120. reg &= ~(1 << irq);
  121. emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
  122. }
  123. static void emma2rh_gpio_irq_ack(unsigned int irq)
  124. {
  125. u32 reg;
  126. irq -= EMMA2RH_GPIO_IRQ_BASE;
  127. emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
  128. reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  129. reg &= ~(1 << irq);
  130. emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
  131. }
  132. static void emma2rh_gpio_irq_end(unsigned int irq)
  133. {
  134. u32 reg;
  135. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
  136. irq -= EMMA2RH_GPIO_IRQ_BASE;
  137. reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  138. reg |= 1 << irq;
  139. emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
  140. }
  141. }
  142. struct irq_chip emma2rh_gpio_irq_controller = {
  143. .name = "emma2rh_gpio_irq",
  144. .ack = emma2rh_gpio_irq_ack,
  145. .mask = emma2rh_gpio_irq_disable,
  146. .mask_ack = emma2rh_gpio_irq_ack,
  147. .unmask = emma2rh_gpio_irq_enable,
  148. .end = emma2rh_gpio_irq_end,
  149. };
  150. void emma2rh_gpio_irq_init(void)
  151. {
  152. u32 i;
  153. for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
  154. set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
  155. &emma2rh_gpio_irq_controller);
  156. }
  157. static struct irqaction irq_cascade = {
  158. .handler = no_action,
  159. .flags = 0,
  160. .mask = CPU_MASK_NONE,
  161. .name = "cascade",
  162. .dev_id = NULL,
  163. .next = NULL,
  164. };
  165. /*
  166. * the first level int-handler will jump here if it is a emma2rh irq
  167. */
  168. void emma2rh_irq_dispatch(void)
  169. {
  170. u32 intStatus;
  171. u32 bitmask;
  172. u32 i;
  173. intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
  174. emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
  175. #ifdef EMMA2RH_SW_CASCADE
  176. if (intStatus &
  177. (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
  178. u32 swIntStatus;
  179. swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
  180. & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
  181. for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
  182. if (swIntStatus & bitmask) {
  183. do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
  184. return;
  185. }
  186. }
  187. }
  188. #endif
  189. for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
  190. if (intStatus & bitmask) {
  191. do_IRQ(EMMA2RH_IRQ_BASE + i);
  192. return;
  193. }
  194. }
  195. intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
  196. emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
  197. #ifdef EMMA2RH_GPIO_CASCADE
  198. if (intStatus &
  199. (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
  200. u32 gpioIntStatus;
  201. gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
  202. & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  203. for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
  204. if (gpioIntStatus & bitmask) {
  205. do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
  206. return;
  207. }
  208. }
  209. }
  210. #endif
  211. for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
  212. if (intStatus & bitmask) {
  213. do_IRQ(EMMA2RH_IRQ_BASE + i);
  214. return;
  215. }
  216. }
  217. intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
  218. emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
  219. for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
  220. if (intStatus & bitmask) {
  221. do_IRQ(EMMA2RH_IRQ_BASE + i);
  222. return;
  223. }
  224. }
  225. }
  226. void __init arch_init_irq(void)
  227. {
  228. u32 reg;
  229. /* by default, interrupts are disabled. */
  230. emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
  231. emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
  232. emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
  233. emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
  234. emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
  235. emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
  236. emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
  237. clear_c0_status(0xff00);
  238. set_c0_status(0x0400);
  239. #define GPIO_PCI (0xf<<15)
  240. /* setup GPIO interrupt for PCI interface */
  241. /* direction input */
  242. reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
  243. emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
  244. /* disable interrupt */
  245. reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  246. emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
  247. /* level triggerd */
  248. reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
  249. emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
  250. reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
  251. emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
  252. /* interrupt clear */
  253. emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
  254. /* init all controllers */
  255. emma2rh_irq_init();
  256. emma2rh_sw_irq_init();
  257. emma2rh_gpio_irq_init();
  258. mips_cpu_irq_init();
  259. /* setup cascade interrupts */
  260. setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
  261. setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
  262. setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
  263. }
  264. asmlinkage void plat_irq_dispatch(void)
  265. {
  266. unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  267. if (pending & STATUSF_IP7)
  268. do_IRQ(CPU_IRQ_BASE + 7);
  269. else if (pending & STATUSF_IP2)
  270. emma2rh_irq_dispatch();
  271. else if (pending & STATUSF_IP1)
  272. do_IRQ(CPU_IRQ_BASE + 1);
  273. else if (pending & STATUSF_IP0)
  274. do_IRQ(CPU_IRQ_BASE + 0);
  275. else
  276. spurious_interrupt();
  277. }