bfin_sport.h 4.6 KB

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  1. /*
  2. * File: include/asm-blackfin/bfin_sport.h
  3. * Based on:
  4. * Author: Roy Huang (roy.huang@analog.com)
  5. *
  6. * Created: Thu Aug. 24 2006
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #ifndef __BFIN_SPORT_H__
  30. #define __BFIN_SPORT_H__
  31. #define SPORT_MAJOR 237
  32. #define SPORT_NR_DEVS 2
  33. /* Sport mode: it can be set to TDM, i2s or others */
  34. #define NORM_MODE 0x0
  35. #define TDM_MODE 0x1
  36. #define I2S_MODE 0x2
  37. /* Data format, normal, a-law or u-law */
  38. #define NORM_FORMAT 0x0
  39. #define ALAW_FORMAT 0x2
  40. #define ULAW_FORMAT 0x3
  41. struct sport_register;
  42. /* Function driver which use sport must initialize the structure */
  43. struct sport_config {
  44. /*TDM (multichannels), I2S or other mode */
  45. unsigned int mode:3;
  46. /* if TDM mode is selected, channels must be set */
  47. int channels; /* Must be in 8 units */
  48. unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
  49. /* I2S mode */
  50. unsigned int right_first:1; /* Right stereo channel first */
  51. /* In mormal mode, the following item need to be set */
  52. unsigned int lsb_first:1; /* order of transmit or receive data */
  53. unsigned int fsync:1; /* Frame sync required */
  54. unsigned int data_indep:1; /* data independent frame sync generated */
  55. unsigned int act_low:1; /* Active low TFS */
  56. unsigned int late_fsync:1; /* Late frame sync */
  57. unsigned int tckfe:1;
  58. unsigned int sec_en:1; /* Secondary side enabled */
  59. /* Choose clock source */
  60. unsigned int int_clk:1; /* Internal or external clock */
  61. /* If external clock is used, the following fields are ignored */
  62. int serial_clk;
  63. int fsync_clk;
  64. unsigned int data_format:2; /*Normal, u-law or a-law */
  65. int word_len; /* How length of the word in bits, 3-32 bits */
  66. int dma_enabled;
  67. };
  68. struct sport_register {
  69. unsigned short tcr1;
  70. unsigned short reserved0;
  71. unsigned short tcr2;
  72. unsigned short reserved1;
  73. unsigned short tclkdiv;
  74. unsigned short reserved2;
  75. unsigned short tfsdiv;
  76. unsigned short reserved3;
  77. unsigned long tx;
  78. unsigned long reserved_l0;
  79. unsigned long rx;
  80. unsigned long reserved_l1;
  81. unsigned short rcr1;
  82. unsigned short reserved4;
  83. unsigned short rcr2;
  84. unsigned short reserved5;
  85. unsigned short rclkdiv;
  86. unsigned short reserved6;
  87. unsigned short rfsdiv;
  88. unsigned short reserved7;
  89. unsigned short stat;
  90. unsigned short reserved8;
  91. unsigned short chnl;
  92. unsigned short reserved9;
  93. unsigned short mcmc1;
  94. unsigned short reserved10;
  95. unsigned short mcmc2;
  96. unsigned short reserved11;
  97. unsigned long mtcs0;
  98. unsigned long mtcs1;
  99. unsigned long mtcs2;
  100. unsigned long mtcs3;
  101. unsigned long mrcs0;
  102. unsigned long mrcs1;
  103. unsigned long mrcs2;
  104. unsigned long mrcs3;
  105. };
  106. #define SPORT_IOC_MAGIC 'P'
  107. #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
  108. /* Test purpose */
  109. #define ENABLE_AD73311 _IOWR('P', 0x02, int)
  110. struct sport_dev {
  111. struct cdev cdev; /* Char device structure */
  112. int sport_num;
  113. int dma_rx_chan;
  114. int dma_tx_chan;
  115. int rx_irq;
  116. unsigned char *rx_buf; /* Buffer store the received data */
  117. int rx_len; /* How many bytes will be received */
  118. int rx_received; /* How many bytes has been received */
  119. int tx_irq;
  120. const unsigned char *tx_buf;
  121. int tx_len;
  122. int tx_sent;
  123. int sport_err_irq;
  124. struct mutex mutex; /* mutual exclusion semaphore */
  125. struct task_struct *task;
  126. wait_queue_head_t waitq;
  127. int wait_con;
  128. struct sport_register *regs;
  129. struct sport_config config;
  130. };
  131. #define SPORT_TCR1 0
  132. #define SPORT_TCR2 1
  133. #define SPORT_TCLKDIV 2
  134. #define SPORT_TFSDIV 3
  135. #define SPORT_RCR1 8
  136. #define SPORT_RCR2 9
  137. #define SPORT_RCLKDIV 10
  138. #define SPORT_RFSDIV 11
  139. #define SPORT_CHANNEL 13
  140. #define SPORT_MCMC1 14
  141. #define SPORT_MCMC2 15
  142. #define SPORT_MTCS0 16
  143. #define SPORT_MTCS1 17
  144. #define SPORT_MTCS2 18
  145. #define SPORT_MTCS3 19
  146. #define SPORT_MRCS0 20
  147. #define SPORT_MRCS1 21
  148. #define SPORT_MRCS2 22
  149. #define SPORT_MRCS3 23
  150. #endif /*__BFIN_SPORT_H__*/