sh_clk.h 4.4 KB

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  1. #ifndef __SH_CLOCK_H
  2. #define __SH_CLOCK_H
  3. #include <linux/list.h>
  4. #include <linux/seq_file.h>
  5. #include <linux/cpufreq.h>
  6. #include <linux/types.h>
  7. #include <linux/kref.h>
  8. #include <linux/clk.h>
  9. #include <linux/err.h>
  10. struct clk;
  11. struct clk_mapping {
  12. phys_addr_t phys;
  13. void __iomem *base;
  14. unsigned long len;
  15. struct kref ref;
  16. };
  17. #define sh_clk_ops clk_ops
  18. struct clk_ops {
  19. #ifdef CONFIG_SH_CLK_CPG_LEGACY
  20. void (*init)(struct clk *clk);
  21. #endif
  22. int (*enable)(struct clk *clk);
  23. void (*disable)(struct clk *clk);
  24. unsigned long (*recalc)(struct clk *clk);
  25. int (*set_rate)(struct clk *clk, unsigned long rate);
  26. int (*set_parent)(struct clk *clk, struct clk *parent);
  27. long (*round_rate)(struct clk *clk, unsigned long rate);
  28. };
  29. struct clk {
  30. struct list_head node;
  31. struct clk *parent;
  32. struct clk **parent_table; /* list of parents to */
  33. unsigned short parent_num; /* choose between */
  34. unsigned char src_shift; /* source clock field in the */
  35. unsigned char src_width; /* configuration register */
  36. struct clk_ops *ops;
  37. struct list_head children;
  38. struct list_head sibling; /* node for children */
  39. int usecount;
  40. unsigned long rate;
  41. unsigned long flags;
  42. void __iomem *enable_reg;
  43. unsigned int enable_bit;
  44. void __iomem *mapped_reg;
  45. unsigned long arch_flags;
  46. void *priv;
  47. struct clk_mapping *mapping;
  48. struct cpufreq_frequency_table *freq_table;
  49. unsigned int nr_freqs;
  50. };
  51. #define CLK_ENABLE_ON_INIT (1 << 0)
  52. /* drivers/sh/clk.c */
  53. unsigned long followparent_recalc(struct clk *);
  54. void recalculate_root_clocks(void);
  55. void propagate_rate(struct clk *);
  56. int clk_reparent(struct clk *child, struct clk *parent);
  57. int clk_register(struct clk *);
  58. void clk_unregister(struct clk *);
  59. void clk_enable_init_clocks(void);
  60. struct clk_div_mult_table {
  61. unsigned int *divisors;
  62. unsigned int nr_divisors;
  63. unsigned int *multipliers;
  64. unsigned int nr_multipliers;
  65. };
  66. struct cpufreq_frequency_table;
  67. void clk_rate_table_build(struct clk *clk,
  68. struct cpufreq_frequency_table *freq_table,
  69. int nr_freqs,
  70. struct clk_div_mult_table *src_table,
  71. unsigned long *bitmap);
  72. long clk_rate_table_round(struct clk *clk,
  73. struct cpufreq_frequency_table *freq_table,
  74. unsigned long rate);
  75. int clk_rate_table_find(struct clk *clk,
  76. struct cpufreq_frequency_table *freq_table,
  77. unsigned long rate);
  78. long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
  79. unsigned int div_max, unsigned long rate);
  80. long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
  81. unsigned int mult_max, unsigned long rate);
  82. long clk_round_parent(struct clk *clk, unsigned long target,
  83. unsigned long *best_freq, unsigned long *parent_freq,
  84. unsigned int div_min, unsigned int div_max);
  85. #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
  86. { \
  87. .parent = _parent, \
  88. .enable_reg = (void __iomem *)_enable_reg, \
  89. .enable_bit = _enable_bit, \
  90. .flags = _flags, \
  91. }
  92. int sh_clk_mstp32_register(struct clk *clks, int nr);
  93. #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
  94. { \
  95. .parent = _parent, \
  96. .enable_reg = (void __iomem *)_reg, \
  97. .enable_bit = _shift, \
  98. .arch_flags = _div_bitmap, \
  99. .flags = _flags, \
  100. }
  101. struct clk_div4_table {
  102. struct clk_div_mult_table *div_mult_table;
  103. void (*kick)(struct clk *clk);
  104. };
  105. int sh_clk_div4_register(struct clk *clks, int nr,
  106. struct clk_div4_table *table);
  107. int sh_clk_div4_enable_register(struct clk *clks, int nr,
  108. struct clk_div4_table *table);
  109. int sh_clk_div4_reparent_register(struct clk *clks, int nr,
  110. struct clk_div4_table *table);
  111. #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
  112. _num_parents, _src_shift, _src_width) \
  113. { \
  114. .enable_reg = (void __iomem *)_reg, \
  115. .flags = _flags, \
  116. .parent_table = _parents, \
  117. .parent_num = _num_parents, \
  118. .src_shift = _src_shift, \
  119. .src_width = _src_width, \
  120. }
  121. #define SH_CLK_DIV6(_parent, _reg, _flags) \
  122. { \
  123. .parent = _parent, \
  124. .enable_reg = (void __iomem *)_reg, \
  125. .flags = _flags, \
  126. }
  127. int sh_clk_div6_register(struct clk *clks, int nr);
  128. int sh_clk_div6_reparent_register(struct clk *clks, int nr);
  129. #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
  130. #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
  131. #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
  132. #endif /* __SH_CLOCK_H */