mthca_main.c 33 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  52. int mthca_debug_level = 0;
  53. module_param_named(debug_level, mthca_debug_level, int, 0644);
  54. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  55. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  56. #ifdef CONFIG_PCI_MSI
  57. static int msi_x = 0;
  58. module_param(msi_x, int, 0444);
  59. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  60. static int msi = 0;
  61. module_param(msi, int, 0444);
  62. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  63. #else /* CONFIG_PCI_MSI */
  64. #define msi_x (0)
  65. #define msi (0)
  66. #endif /* CONFIG_PCI_MSI */
  67. static int tune_pci = 0;
  68. module_param(tune_pci, int, 0444);
  69. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  70. static const char mthca_version[] __devinitdata =
  71. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  72. DRV_VERSION " (" DRV_RELDATE ")\n";
  73. static struct mthca_profile default_profile = {
  74. .num_qp = 1 << 16,
  75. .rdb_per_qp = 4,
  76. .num_cq = 1 << 16,
  77. .num_mcg = 1 << 13,
  78. .num_mpt = 1 << 17,
  79. .num_mtt = 1 << 20,
  80. .num_udav = 1 << 15, /* Tavor only */
  81. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  82. .uarc_size = 1 << 18, /* Arbel only */
  83. };
  84. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  85. {
  86. int cap;
  87. u16 val;
  88. if (!tune_pci)
  89. return 0;
  90. /* First try to max out Read Byte Count */
  91. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  92. if (cap) {
  93. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  94. mthca_err(mdev, "Couldn't read PCI-X command register, "
  95. "aborting.\n");
  96. return -ENODEV;
  97. }
  98. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  99. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  100. mthca_err(mdev, "Couldn't write PCI-X command register, "
  101. "aborting.\n");
  102. return -ENODEV;
  103. }
  104. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  105. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  106. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  107. if (cap) {
  108. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  109. mthca_err(mdev, "Couldn't read PCI Express device control "
  110. "register, aborting.\n");
  111. return -ENODEV;
  112. }
  113. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  114. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  115. mthca_err(mdev, "Couldn't write PCI Express device control "
  116. "register, aborting.\n");
  117. return -ENODEV;
  118. }
  119. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  120. mthca_info(mdev, "No PCI Express capability, "
  121. "not setting Max Read Request Size.\n");
  122. return 0;
  123. }
  124. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  125. {
  126. int err;
  127. u8 status;
  128. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  129. if (err) {
  130. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  131. return err;
  132. }
  133. if (status) {
  134. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  135. "aborting.\n", status);
  136. return -EINVAL;
  137. }
  138. if (dev_lim->min_page_sz > PAGE_SIZE) {
  139. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  140. "kernel PAGE_SIZE of %ld, aborting.\n",
  141. dev_lim->min_page_sz, PAGE_SIZE);
  142. return -ENODEV;
  143. }
  144. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  145. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  146. "aborting.\n",
  147. dev_lim->num_ports, MTHCA_MAX_PORTS);
  148. return -ENODEV;
  149. }
  150. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  151. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  152. "PCI resource 2 size of 0x%llx, aborting.\n",
  153. dev_lim->uar_size,
  154. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  155. return -ENODEV;
  156. }
  157. mdev->limits.num_ports = dev_lim->num_ports;
  158. mdev->limits.vl_cap = dev_lim->max_vl;
  159. mdev->limits.mtu_cap = dev_lim->max_mtu;
  160. mdev->limits.gid_table_len = dev_lim->max_gids;
  161. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  162. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  163. mdev->limits.max_sg = dev_lim->max_sg;
  164. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  165. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  166. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  167. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  168. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  169. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  170. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  171. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  172. /*
  173. * Subtract 1 from the limit because we need to allocate a
  174. * spare CQE so the HCA HW can tell the difference between an
  175. * empty CQ and a full CQ.
  176. */
  177. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  178. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  179. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  180. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  181. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  182. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  183. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  184. mdev->limits.port_width_cap = dev_lim->max_port_width;
  185. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  186. mdev->limits.flags = dev_lim->flags;
  187. /*
  188. * For old FW that doesn't return static rate support, use a
  189. * value of 0x3 (only static rate values of 0 or 1 are handled),
  190. * except on Sinai, where even old FW can handle static rate
  191. * values of 2 and 3.
  192. */
  193. if (dev_lim->stat_rate_support)
  194. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  195. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  196. mdev->limits.stat_rate_support = 0xf;
  197. else
  198. mdev->limits.stat_rate_support = 0x3;
  199. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  200. May be doable since hardware supports it for SRQ.
  201. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  202. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  203. supported by driver. */
  204. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  205. IB_DEVICE_PORT_ACTIVE_EVENT |
  206. IB_DEVICE_SYS_IMAGE_GUID |
  207. IB_DEVICE_RC_RNR_NAK_GEN;
  208. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  209. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  210. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  211. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  212. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  213. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  214. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  215. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  216. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  217. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  218. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  219. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  220. return 0;
  221. }
  222. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  223. {
  224. u8 status;
  225. int err;
  226. struct mthca_dev_lim dev_lim;
  227. struct mthca_profile profile;
  228. struct mthca_init_hca_param init_hca;
  229. err = mthca_SYS_EN(mdev, &status);
  230. if (err) {
  231. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  232. return err;
  233. }
  234. if (status) {
  235. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  236. "aborting.\n", status);
  237. return -EINVAL;
  238. }
  239. err = mthca_QUERY_FW(mdev, &status);
  240. if (err) {
  241. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  242. goto err_disable;
  243. }
  244. if (status) {
  245. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  246. "aborting.\n", status);
  247. err = -EINVAL;
  248. goto err_disable;
  249. }
  250. err = mthca_QUERY_DDR(mdev, &status);
  251. if (err) {
  252. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  253. goto err_disable;
  254. }
  255. if (status) {
  256. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  257. "aborting.\n", status);
  258. err = -EINVAL;
  259. goto err_disable;
  260. }
  261. err = mthca_dev_lim(mdev, &dev_lim);
  262. if (err) {
  263. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  264. goto err_disable;
  265. }
  266. profile = default_profile;
  267. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  268. profile.uarc_size = 0;
  269. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  270. profile.num_srq = dev_lim.max_srqs;
  271. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  272. if (err < 0)
  273. goto err_disable;
  274. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  275. if (err) {
  276. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  277. goto err_disable;
  278. }
  279. if (status) {
  280. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  281. "aborting.\n", status);
  282. err = -EINVAL;
  283. goto err_disable;
  284. }
  285. return 0;
  286. err_disable:
  287. mthca_SYS_DIS(mdev, &status);
  288. return err;
  289. }
  290. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  291. {
  292. u8 status;
  293. int err;
  294. /* FIXME: use HCA-attached memory for FW if present */
  295. mdev->fw.arbel.fw_icm =
  296. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  297. GFP_HIGHUSER | __GFP_NOWARN);
  298. if (!mdev->fw.arbel.fw_icm) {
  299. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  300. return -ENOMEM;
  301. }
  302. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  303. if (err) {
  304. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  305. goto err_free;
  306. }
  307. if (status) {
  308. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  309. err = -EINVAL;
  310. goto err_free;
  311. }
  312. err = mthca_RUN_FW(mdev, &status);
  313. if (err) {
  314. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  315. goto err_unmap_fa;
  316. }
  317. if (status) {
  318. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  319. err = -EINVAL;
  320. goto err_unmap_fa;
  321. }
  322. return 0;
  323. err_unmap_fa:
  324. mthca_UNMAP_FA(mdev, &status);
  325. err_free:
  326. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  327. return err;
  328. }
  329. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  330. struct mthca_dev_lim *dev_lim,
  331. struct mthca_init_hca_param *init_hca,
  332. u64 icm_size)
  333. {
  334. u64 aux_pages;
  335. u8 status;
  336. int err;
  337. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  338. if (err) {
  339. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  340. return err;
  341. }
  342. if (status) {
  343. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  344. "aborting.\n", status);
  345. return -EINVAL;
  346. }
  347. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  348. (unsigned long long) icm_size >> 10,
  349. (unsigned long long) aux_pages << 2);
  350. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  351. GFP_HIGHUSER | __GFP_NOWARN);
  352. if (!mdev->fw.arbel.aux_icm) {
  353. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  354. return -ENOMEM;
  355. }
  356. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  357. if (err) {
  358. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  359. goto err_free_aux;
  360. }
  361. if (status) {
  362. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  363. err = -EINVAL;
  364. goto err_free_aux;
  365. }
  366. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  367. if (err) {
  368. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  369. goto err_unmap_aux;
  370. }
  371. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  372. MTHCA_MTT_SEG_SIZE,
  373. mdev->limits.num_mtt_segs,
  374. mdev->limits.reserved_mtts, 1);
  375. if (!mdev->mr_table.mtt_table) {
  376. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  377. err = -ENOMEM;
  378. goto err_unmap_eq;
  379. }
  380. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  381. dev_lim->mpt_entry_sz,
  382. mdev->limits.num_mpts,
  383. mdev->limits.reserved_mrws, 1);
  384. if (!mdev->mr_table.mpt_table) {
  385. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  386. err = -ENOMEM;
  387. goto err_unmap_mtt;
  388. }
  389. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  390. dev_lim->qpc_entry_sz,
  391. mdev->limits.num_qps,
  392. mdev->limits.reserved_qps, 0);
  393. if (!mdev->qp_table.qp_table) {
  394. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  395. err = -ENOMEM;
  396. goto err_unmap_mpt;
  397. }
  398. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  399. dev_lim->eqpc_entry_sz,
  400. mdev->limits.num_qps,
  401. mdev->limits.reserved_qps, 0);
  402. if (!mdev->qp_table.eqp_table) {
  403. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  404. err = -ENOMEM;
  405. goto err_unmap_qp;
  406. }
  407. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  408. MTHCA_RDB_ENTRY_SIZE,
  409. mdev->limits.num_qps <<
  410. mdev->qp_table.rdb_shift,
  411. 0, 0);
  412. if (!mdev->qp_table.rdb_table) {
  413. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  414. err = -ENOMEM;
  415. goto err_unmap_eqp;
  416. }
  417. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  418. dev_lim->cqc_entry_sz,
  419. mdev->limits.num_cqs,
  420. mdev->limits.reserved_cqs, 0);
  421. if (!mdev->cq_table.table) {
  422. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  423. err = -ENOMEM;
  424. goto err_unmap_rdb;
  425. }
  426. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  427. mdev->srq_table.table =
  428. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  429. dev_lim->srq_entry_sz,
  430. mdev->limits.num_srqs,
  431. mdev->limits.reserved_srqs, 0);
  432. if (!mdev->srq_table.table) {
  433. mthca_err(mdev, "Failed to map SRQ context memory, "
  434. "aborting.\n");
  435. err = -ENOMEM;
  436. goto err_unmap_cq;
  437. }
  438. }
  439. /*
  440. * It's not strictly required, but for simplicity just map the
  441. * whole multicast group table now. The table isn't very big
  442. * and it's a lot easier than trying to track ref counts.
  443. */
  444. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  445. MTHCA_MGM_ENTRY_SIZE,
  446. mdev->limits.num_mgms +
  447. mdev->limits.num_amgms,
  448. mdev->limits.num_mgms +
  449. mdev->limits.num_amgms,
  450. 0);
  451. if (!mdev->mcg_table.table) {
  452. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  453. err = -ENOMEM;
  454. goto err_unmap_srq;
  455. }
  456. return 0;
  457. err_unmap_srq:
  458. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  459. mthca_free_icm_table(mdev, mdev->srq_table.table);
  460. err_unmap_cq:
  461. mthca_free_icm_table(mdev, mdev->cq_table.table);
  462. err_unmap_rdb:
  463. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  464. err_unmap_eqp:
  465. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  466. err_unmap_qp:
  467. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  468. err_unmap_mpt:
  469. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  470. err_unmap_mtt:
  471. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  472. err_unmap_eq:
  473. mthca_unmap_eq_icm(mdev);
  474. err_unmap_aux:
  475. mthca_UNMAP_ICM_AUX(mdev, &status);
  476. err_free_aux:
  477. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  478. return err;
  479. }
  480. static void mthca_free_icms(struct mthca_dev *mdev)
  481. {
  482. u8 status;
  483. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  484. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  485. mthca_free_icm_table(mdev, mdev->srq_table.table);
  486. mthca_free_icm_table(mdev, mdev->cq_table.table);
  487. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  488. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  489. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  490. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  491. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  492. mthca_unmap_eq_icm(mdev);
  493. mthca_UNMAP_ICM_AUX(mdev, &status);
  494. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  495. }
  496. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  497. {
  498. struct mthca_dev_lim dev_lim;
  499. struct mthca_profile profile;
  500. struct mthca_init_hca_param init_hca;
  501. u64 icm_size;
  502. u8 status;
  503. int err;
  504. err = mthca_QUERY_FW(mdev, &status);
  505. if (err) {
  506. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  507. return err;
  508. }
  509. if (status) {
  510. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  511. "aborting.\n", status);
  512. return -EINVAL;
  513. }
  514. err = mthca_ENABLE_LAM(mdev, &status);
  515. if (err) {
  516. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  517. return err;
  518. }
  519. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  520. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  521. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  522. } else if (status) {
  523. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  524. "aborting.\n", status);
  525. return -EINVAL;
  526. }
  527. err = mthca_load_fw(mdev);
  528. if (err) {
  529. mthca_err(mdev, "Failed to start FW, aborting.\n");
  530. goto err_disable;
  531. }
  532. err = mthca_dev_lim(mdev, &dev_lim);
  533. if (err) {
  534. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  535. goto err_stop_fw;
  536. }
  537. profile = default_profile;
  538. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  539. profile.num_udav = 0;
  540. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  541. profile.num_srq = dev_lim.max_srqs;
  542. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  543. if ((int) icm_size < 0) {
  544. err = icm_size;
  545. goto err_stop_fw;
  546. }
  547. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  548. if (err)
  549. goto err_stop_fw;
  550. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  551. if (err) {
  552. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  553. goto err_free_icm;
  554. }
  555. if (status) {
  556. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  557. "aborting.\n", status);
  558. err = -EINVAL;
  559. goto err_free_icm;
  560. }
  561. return 0;
  562. err_free_icm:
  563. mthca_free_icms(mdev);
  564. err_stop_fw:
  565. mthca_UNMAP_FA(mdev, &status);
  566. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  567. err_disable:
  568. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  569. mthca_DISABLE_LAM(mdev, &status);
  570. return err;
  571. }
  572. static void mthca_close_hca(struct mthca_dev *mdev)
  573. {
  574. u8 status;
  575. mthca_CLOSE_HCA(mdev, 0, &status);
  576. if (mthca_is_memfree(mdev)) {
  577. mthca_free_icms(mdev);
  578. mthca_UNMAP_FA(mdev, &status);
  579. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  580. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  581. mthca_DISABLE_LAM(mdev, &status);
  582. } else
  583. mthca_SYS_DIS(mdev, &status);
  584. }
  585. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  586. {
  587. u8 status;
  588. int err;
  589. struct mthca_adapter adapter;
  590. if (mthca_is_memfree(mdev))
  591. err = mthca_init_arbel(mdev);
  592. else
  593. err = mthca_init_tavor(mdev);
  594. if (err)
  595. return err;
  596. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  597. if (err) {
  598. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  599. goto err_close;
  600. }
  601. if (status) {
  602. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  603. "aborting.\n", status);
  604. err = -EINVAL;
  605. goto err_close;
  606. }
  607. mdev->eq_table.inta_pin = adapter.inta_pin;
  608. mdev->rev_id = adapter.revision_id;
  609. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  610. return 0;
  611. err_close:
  612. mthca_close_hca(mdev);
  613. return err;
  614. }
  615. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  616. {
  617. int err;
  618. u8 status;
  619. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  620. err = mthca_init_uar_table(dev);
  621. if (err) {
  622. mthca_err(dev, "Failed to initialize "
  623. "user access region table, aborting.\n");
  624. return err;
  625. }
  626. err = mthca_uar_alloc(dev, &dev->driver_uar);
  627. if (err) {
  628. mthca_err(dev, "Failed to allocate driver access region, "
  629. "aborting.\n");
  630. goto err_uar_table_free;
  631. }
  632. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  633. if (!dev->kar) {
  634. mthca_err(dev, "Couldn't map kernel access region, "
  635. "aborting.\n");
  636. err = -ENOMEM;
  637. goto err_uar_free;
  638. }
  639. err = mthca_init_pd_table(dev);
  640. if (err) {
  641. mthca_err(dev, "Failed to initialize "
  642. "protection domain table, aborting.\n");
  643. goto err_kar_unmap;
  644. }
  645. err = mthca_init_mr_table(dev);
  646. if (err) {
  647. mthca_err(dev, "Failed to initialize "
  648. "memory region table, aborting.\n");
  649. goto err_pd_table_free;
  650. }
  651. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  652. if (err) {
  653. mthca_err(dev, "Failed to create driver PD, "
  654. "aborting.\n");
  655. goto err_mr_table_free;
  656. }
  657. err = mthca_init_eq_table(dev);
  658. if (err) {
  659. mthca_err(dev, "Failed to initialize "
  660. "event queue table, aborting.\n");
  661. goto err_pd_free;
  662. }
  663. err = mthca_cmd_use_events(dev);
  664. if (err) {
  665. mthca_err(dev, "Failed to switch to event-driven "
  666. "firmware commands, aborting.\n");
  667. goto err_eq_table_free;
  668. }
  669. err = mthca_NOP(dev, &status);
  670. if (err || status) {
  671. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  672. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  673. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  674. dev->pdev->irq);
  675. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  676. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  677. else
  678. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  679. goto err_cmd_poll;
  680. }
  681. mthca_dbg(dev, "NOP command IRQ test passed\n");
  682. err = mthca_init_cq_table(dev);
  683. if (err) {
  684. mthca_err(dev, "Failed to initialize "
  685. "completion queue table, aborting.\n");
  686. goto err_cmd_poll;
  687. }
  688. err = mthca_init_srq_table(dev);
  689. if (err) {
  690. mthca_err(dev, "Failed to initialize "
  691. "shared receive queue table, aborting.\n");
  692. goto err_cq_table_free;
  693. }
  694. err = mthca_init_qp_table(dev);
  695. if (err) {
  696. mthca_err(dev, "Failed to initialize "
  697. "queue pair table, aborting.\n");
  698. goto err_srq_table_free;
  699. }
  700. err = mthca_init_av_table(dev);
  701. if (err) {
  702. mthca_err(dev, "Failed to initialize "
  703. "address vector table, aborting.\n");
  704. goto err_qp_table_free;
  705. }
  706. err = mthca_init_mcg_table(dev);
  707. if (err) {
  708. mthca_err(dev, "Failed to initialize "
  709. "multicast group table, aborting.\n");
  710. goto err_av_table_free;
  711. }
  712. return 0;
  713. err_av_table_free:
  714. mthca_cleanup_av_table(dev);
  715. err_qp_table_free:
  716. mthca_cleanup_qp_table(dev);
  717. err_srq_table_free:
  718. mthca_cleanup_srq_table(dev);
  719. err_cq_table_free:
  720. mthca_cleanup_cq_table(dev);
  721. err_cmd_poll:
  722. mthca_cmd_use_polling(dev);
  723. err_eq_table_free:
  724. mthca_cleanup_eq_table(dev);
  725. err_pd_free:
  726. mthca_pd_free(dev, &dev->driver_pd);
  727. err_mr_table_free:
  728. mthca_cleanup_mr_table(dev);
  729. err_pd_table_free:
  730. mthca_cleanup_pd_table(dev);
  731. err_kar_unmap:
  732. iounmap(dev->kar);
  733. err_uar_free:
  734. mthca_uar_free(dev, &dev->driver_uar);
  735. err_uar_table_free:
  736. mthca_cleanup_uar_table(dev);
  737. return err;
  738. }
  739. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  740. int ddr_hidden)
  741. {
  742. int err;
  743. /*
  744. * We can't just use pci_request_regions() because the MSI-X
  745. * table is right in the middle of the first BAR. If we did
  746. * pci_request_region and grab all of the first BAR, then
  747. * setting up MSI-X would fail, since the PCI core wants to do
  748. * request_mem_region on the MSI-X vector table.
  749. *
  750. * So just request what we need right now, and request any
  751. * other regions we need when setting up EQs.
  752. */
  753. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  754. MTHCA_HCR_SIZE, DRV_NAME))
  755. return -EBUSY;
  756. err = pci_request_region(pdev, 2, DRV_NAME);
  757. if (err)
  758. goto err_bar2_failed;
  759. if (!ddr_hidden) {
  760. err = pci_request_region(pdev, 4, DRV_NAME);
  761. if (err)
  762. goto err_bar4_failed;
  763. }
  764. return 0;
  765. err_bar4_failed:
  766. pci_release_region(pdev, 2);
  767. err_bar2_failed:
  768. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  769. MTHCA_HCR_SIZE);
  770. return err;
  771. }
  772. static void mthca_release_regions(struct pci_dev *pdev,
  773. int ddr_hidden)
  774. {
  775. if (!ddr_hidden)
  776. pci_release_region(pdev, 4);
  777. pci_release_region(pdev, 2);
  778. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  779. MTHCA_HCR_SIZE);
  780. }
  781. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  782. {
  783. struct msix_entry entries[3];
  784. int err;
  785. entries[0].entry = 0;
  786. entries[1].entry = 1;
  787. entries[2].entry = 2;
  788. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  789. if (err) {
  790. if (err > 0)
  791. mthca_info(mdev, "Only %d MSI-X vectors available, "
  792. "not using MSI-X\n", err);
  793. return err;
  794. }
  795. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  796. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  797. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  798. return 0;
  799. }
  800. /* Types of supported HCA */
  801. enum {
  802. TAVOR, /* MT23108 */
  803. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  804. ARBEL_NATIVE, /* MT25208 with extended features */
  805. SINAI /* MT25204 */
  806. };
  807. #define MTHCA_FW_VER(major, minor, subminor) \
  808. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  809. static struct {
  810. u64 latest_fw;
  811. u32 flags;
  812. } mthca_hca_table[] = {
  813. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 4, 0),
  814. .flags = 0 },
  815. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 400),
  816. .flags = MTHCA_FLAG_PCIE },
  817. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0),
  818. .flags = MTHCA_FLAG_MEMFREE |
  819. MTHCA_FLAG_PCIE },
  820. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 800),
  821. .flags = MTHCA_FLAG_MEMFREE |
  822. MTHCA_FLAG_PCIE |
  823. MTHCA_FLAG_SINAI_OPT }
  824. };
  825. static int __devinit mthca_init_one(struct pci_dev *pdev,
  826. const struct pci_device_id *id)
  827. {
  828. static int mthca_version_printed = 0;
  829. int ddr_hidden = 0;
  830. int err;
  831. struct mthca_dev *mdev;
  832. if (!mthca_version_printed) {
  833. printk(KERN_INFO "%s", mthca_version);
  834. ++mthca_version_printed;
  835. }
  836. printk(KERN_INFO PFX "Initializing %s\n",
  837. pci_name(pdev));
  838. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  839. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  840. pci_name(pdev), id->driver_data);
  841. return -ENODEV;
  842. }
  843. err = pci_enable_device(pdev);
  844. if (err) {
  845. dev_err(&pdev->dev, "Cannot enable PCI device, "
  846. "aborting.\n");
  847. return err;
  848. }
  849. /*
  850. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  851. * be present)
  852. */
  853. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  854. pci_resource_len(pdev, 0) != 1 << 20) {
  855. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  856. err = -ENODEV;
  857. goto err_disable_pdev;
  858. }
  859. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  860. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  861. err = -ENODEV;
  862. goto err_disable_pdev;
  863. }
  864. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  865. ddr_hidden = 1;
  866. err = mthca_request_regions(pdev, ddr_hidden);
  867. if (err) {
  868. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  869. "aborting.\n");
  870. goto err_disable_pdev;
  871. }
  872. pci_set_master(pdev);
  873. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  874. if (err) {
  875. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  876. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  877. if (err) {
  878. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  879. goto err_free_res;
  880. }
  881. }
  882. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  883. if (err) {
  884. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  885. "consistent PCI DMA mask.\n");
  886. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  887. if (err) {
  888. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  889. "aborting.\n");
  890. goto err_free_res;
  891. }
  892. }
  893. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  894. if (!mdev) {
  895. dev_err(&pdev->dev, "Device struct alloc failed, "
  896. "aborting.\n");
  897. err = -ENOMEM;
  898. goto err_free_res;
  899. }
  900. mdev->pdev = pdev;
  901. mdev->mthca_flags = mthca_hca_table[id->driver_data].flags;
  902. if (ddr_hidden)
  903. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  904. /*
  905. * Now reset the HCA before we touch the PCI capabilities or
  906. * attempt a firmware command, since a boot ROM may have left
  907. * the HCA in an undefined state.
  908. */
  909. err = mthca_reset(mdev);
  910. if (err) {
  911. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  912. goto err_free_dev;
  913. }
  914. if (msi_x && !mthca_enable_msi_x(mdev))
  915. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  916. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  917. !pci_enable_msi(pdev))
  918. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  919. if (mthca_cmd_init(mdev)) {
  920. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  921. goto err_free_dev;
  922. }
  923. err = mthca_tune_pci(mdev);
  924. if (err)
  925. goto err_cmd;
  926. err = mthca_init_hca(mdev);
  927. if (err)
  928. goto err_cmd;
  929. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  930. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  931. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  932. (int) (mdev->fw_ver & 0xffff),
  933. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  934. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  935. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  936. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  937. }
  938. err = mthca_setup_hca(mdev);
  939. if (err)
  940. goto err_close;
  941. err = mthca_register_device(mdev);
  942. if (err)
  943. goto err_cleanup;
  944. err = mthca_create_agents(mdev);
  945. if (err)
  946. goto err_unregister;
  947. pci_set_drvdata(pdev, mdev);
  948. return 0;
  949. err_unregister:
  950. mthca_unregister_device(mdev);
  951. err_cleanup:
  952. mthca_cleanup_mcg_table(mdev);
  953. mthca_cleanup_av_table(mdev);
  954. mthca_cleanup_qp_table(mdev);
  955. mthca_cleanup_srq_table(mdev);
  956. mthca_cleanup_cq_table(mdev);
  957. mthca_cmd_use_polling(mdev);
  958. mthca_cleanup_eq_table(mdev);
  959. mthca_pd_free(mdev, &mdev->driver_pd);
  960. mthca_cleanup_mr_table(mdev);
  961. mthca_cleanup_pd_table(mdev);
  962. mthca_cleanup_uar_table(mdev);
  963. err_close:
  964. mthca_close_hca(mdev);
  965. err_cmd:
  966. mthca_cmd_cleanup(mdev);
  967. err_free_dev:
  968. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  969. pci_disable_msix(pdev);
  970. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  971. pci_disable_msi(pdev);
  972. ib_dealloc_device(&mdev->ib_dev);
  973. err_free_res:
  974. mthca_release_regions(pdev, ddr_hidden);
  975. err_disable_pdev:
  976. pci_disable_device(pdev);
  977. pci_set_drvdata(pdev, NULL);
  978. return err;
  979. }
  980. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  981. {
  982. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  983. u8 status;
  984. int p;
  985. if (mdev) {
  986. mthca_free_agents(mdev);
  987. mthca_unregister_device(mdev);
  988. for (p = 1; p <= mdev->limits.num_ports; ++p)
  989. mthca_CLOSE_IB(mdev, p, &status);
  990. mthca_cleanup_mcg_table(mdev);
  991. mthca_cleanup_av_table(mdev);
  992. mthca_cleanup_qp_table(mdev);
  993. mthca_cleanup_srq_table(mdev);
  994. mthca_cleanup_cq_table(mdev);
  995. mthca_cmd_use_polling(mdev);
  996. mthca_cleanup_eq_table(mdev);
  997. mthca_pd_free(mdev, &mdev->driver_pd);
  998. mthca_cleanup_mr_table(mdev);
  999. mthca_cleanup_pd_table(mdev);
  1000. iounmap(mdev->kar);
  1001. mthca_uar_free(mdev, &mdev->driver_uar);
  1002. mthca_cleanup_uar_table(mdev);
  1003. mthca_close_hca(mdev);
  1004. mthca_cmd_cleanup(mdev);
  1005. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1006. pci_disable_msix(pdev);
  1007. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  1008. pci_disable_msi(pdev);
  1009. ib_dealloc_device(&mdev->ib_dev);
  1010. mthca_release_regions(pdev, mdev->mthca_flags &
  1011. MTHCA_FLAG_DDR_HIDDEN);
  1012. pci_disable_device(pdev);
  1013. pci_set_drvdata(pdev, NULL);
  1014. }
  1015. }
  1016. static struct pci_device_id mthca_pci_table[] = {
  1017. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1018. .driver_data = TAVOR },
  1019. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1020. .driver_data = TAVOR },
  1021. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1022. .driver_data = ARBEL_COMPAT },
  1023. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1024. .driver_data = ARBEL_COMPAT },
  1025. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1026. .driver_data = ARBEL_NATIVE },
  1027. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1028. .driver_data = ARBEL_NATIVE },
  1029. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1030. .driver_data = SINAI },
  1031. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1032. .driver_data = SINAI },
  1033. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1034. .driver_data = SINAI },
  1035. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1036. .driver_data = SINAI },
  1037. { 0, }
  1038. };
  1039. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1040. static struct pci_driver mthca_driver = {
  1041. .name = DRV_NAME,
  1042. .id_table = mthca_pci_table,
  1043. .probe = mthca_init_one,
  1044. .remove = __devexit_p(mthca_remove_one)
  1045. };
  1046. static int __init mthca_init(void)
  1047. {
  1048. int ret;
  1049. ret = pci_register_driver(&mthca_driver);
  1050. return ret < 0 ? ret : 0;
  1051. }
  1052. static void __exit mthca_cleanup(void)
  1053. {
  1054. pci_unregister_driver(&mthca_driver);
  1055. }
  1056. module_init(mthca_init);
  1057. module_exit(mthca_cleanup);