netxen_nic_init.c 46 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include "netxen_nic.h"
  28. #include "netxen_nic_hw.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define NETXEN_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  35. #define NETXEN_ADDR_ERROR (0xffffffff)
  36. #define crb_addr_transform(name) \
  37. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  38. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  39. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  40. static void
  41. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  42. struct nx_host_rds_ring *rds_ring);
  43. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  44. static void crb_addr_transform_setup(void)
  45. {
  46. crb_addr_transform(XDMA);
  47. crb_addr_transform(TIMR);
  48. crb_addr_transform(SRE);
  49. crb_addr_transform(SQN3);
  50. crb_addr_transform(SQN2);
  51. crb_addr_transform(SQN1);
  52. crb_addr_transform(SQN0);
  53. crb_addr_transform(SQS3);
  54. crb_addr_transform(SQS2);
  55. crb_addr_transform(SQS1);
  56. crb_addr_transform(SQS0);
  57. crb_addr_transform(RPMX7);
  58. crb_addr_transform(RPMX6);
  59. crb_addr_transform(RPMX5);
  60. crb_addr_transform(RPMX4);
  61. crb_addr_transform(RPMX3);
  62. crb_addr_transform(RPMX2);
  63. crb_addr_transform(RPMX1);
  64. crb_addr_transform(RPMX0);
  65. crb_addr_transform(ROMUSB);
  66. crb_addr_transform(SN);
  67. crb_addr_transform(QMN);
  68. crb_addr_transform(QMS);
  69. crb_addr_transform(PGNI);
  70. crb_addr_transform(PGND);
  71. crb_addr_transform(PGN3);
  72. crb_addr_transform(PGN2);
  73. crb_addr_transform(PGN1);
  74. crb_addr_transform(PGN0);
  75. crb_addr_transform(PGSI);
  76. crb_addr_transform(PGSD);
  77. crb_addr_transform(PGS3);
  78. crb_addr_transform(PGS2);
  79. crb_addr_transform(PGS1);
  80. crb_addr_transform(PGS0);
  81. crb_addr_transform(PS);
  82. crb_addr_transform(PH);
  83. crb_addr_transform(NIU);
  84. crb_addr_transform(I2Q);
  85. crb_addr_transform(EG);
  86. crb_addr_transform(MN);
  87. crb_addr_transform(MS);
  88. crb_addr_transform(CAS2);
  89. crb_addr_transform(CAS1);
  90. crb_addr_transform(CAS0);
  91. crb_addr_transform(CAM);
  92. crb_addr_transform(C2C1);
  93. crb_addr_transform(C2C0);
  94. crb_addr_transform(SMB);
  95. crb_addr_transform(OCM0);
  96. crb_addr_transform(I2C0);
  97. }
  98. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  99. {
  100. struct netxen_recv_context *recv_ctx;
  101. struct nx_host_rds_ring *rds_ring;
  102. struct netxen_rx_buffer *rx_buf;
  103. int i, ring;
  104. recv_ctx = &adapter->recv_ctx;
  105. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  106. rds_ring = &recv_ctx->rds_rings[ring];
  107. for (i = 0; i < rds_ring->num_desc; ++i) {
  108. rx_buf = &(rds_ring->rx_buf_arr[i]);
  109. if (rx_buf->state == NETXEN_BUFFER_FREE)
  110. continue;
  111. pci_unmap_single(adapter->pdev,
  112. rx_buf->dma,
  113. rds_ring->dma_size,
  114. PCI_DMA_FROMDEVICE);
  115. if (rx_buf->skb != NULL)
  116. dev_kfree_skb_any(rx_buf->skb);
  117. }
  118. }
  119. }
  120. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  121. {
  122. struct netxen_cmd_buffer *cmd_buf;
  123. struct netxen_skb_frag *buffrag;
  124. int i, j;
  125. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  126. cmd_buf = tx_ring->cmd_buf_arr;
  127. for (i = 0; i < tx_ring->num_desc; i++) {
  128. buffrag = cmd_buf->frag_array;
  129. if (buffrag->dma) {
  130. pci_unmap_single(adapter->pdev, buffrag->dma,
  131. buffrag->length, PCI_DMA_TODEVICE);
  132. buffrag->dma = 0ULL;
  133. }
  134. for (j = 0; j < cmd_buf->frag_count; j++) {
  135. buffrag++;
  136. if (buffrag->dma) {
  137. pci_unmap_page(adapter->pdev, buffrag->dma,
  138. buffrag->length,
  139. PCI_DMA_TODEVICE);
  140. buffrag->dma = 0ULL;
  141. }
  142. }
  143. if (cmd_buf->skb) {
  144. dev_kfree_skb_any(cmd_buf->skb);
  145. cmd_buf->skb = NULL;
  146. }
  147. cmd_buf++;
  148. }
  149. }
  150. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  151. {
  152. struct netxen_recv_context *recv_ctx;
  153. struct nx_host_rds_ring *rds_ring;
  154. struct nx_host_tx_ring *tx_ring;
  155. int ring;
  156. recv_ctx = &adapter->recv_ctx;
  157. if (recv_ctx->rds_rings == NULL)
  158. goto skip_rds;
  159. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  160. rds_ring = &recv_ctx->rds_rings[ring];
  161. vfree(rds_ring->rx_buf_arr);
  162. rds_ring->rx_buf_arr = NULL;
  163. }
  164. kfree(recv_ctx->rds_rings);
  165. skip_rds:
  166. if (adapter->tx_ring == NULL)
  167. return;
  168. tx_ring = adapter->tx_ring;
  169. vfree(tx_ring->cmd_buf_arr);
  170. kfree(tx_ring);
  171. adapter->tx_ring = NULL;
  172. }
  173. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  174. {
  175. struct netxen_recv_context *recv_ctx;
  176. struct nx_host_rds_ring *rds_ring;
  177. struct nx_host_sds_ring *sds_ring;
  178. struct nx_host_tx_ring *tx_ring;
  179. struct netxen_rx_buffer *rx_buf;
  180. int ring, i, size;
  181. struct netxen_cmd_buffer *cmd_buf_arr;
  182. struct net_device *netdev = adapter->netdev;
  183. struct pci_dev *pdev = adapter->pdev;
  184. size = sizeof(struct nx_host_tx_ring);
  185. tx_ring = kzalloc(size, GFP_KERNEL);
  186. if (tx_ring == NULL) {
  187. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  188. netdev->name);
  189. return -ENOMEM;
  190. }
  191. adapter->tx_ring = tx_ring;
  192. tx_ring->num_desc = adapter->num_txd;
  193. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  194. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  195. if (cmd_buf_arr == NULL) {
  196. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  197. netdev->name);
  198. return -ENOMEM;
  199. }
  200. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  201. tx_ring->cmd_buf_arr = cmd_buf_arr;
  202. recv_ctx = &adapter->recv_ctx;
  203. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  204. rds_ring = kzalloc(size, GFP_KERNEL);
  205. if (rds_ring == NULL) {
  206. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  207. netdev->name);
  208. return -ENOMEM;
  209. }
  210. recv_ctx->rds_rings = rds_ring;
  211. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  212. rds_ring = &recv_ctx->rds_rings[ring];
  213. switch (ring) {
  214. case RCV_RING_NORMAL:
  215. rds_ring->num_desc = adapter->num_rxd;
  216. if (adapter->ahw.cut_through) {
  217. rds_ring->dma_size =
  218. NX_CT_DEFAULT_RX_BUF_LEN;
  219. rds_ring->skb_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. } else {
  222. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  223. rds_ring->dma_size =
  224. NX_P3_RX_BUF_MAX_LEN;
  225. else
  226. rds_ring->dma_size =
  227. NX_P2_RX_BUF_MAX_LEN;
  228. rds_ring->skb_size =
  229. rds_ring->dma_size + NET_IP_ALIGN;
  230. }
  231. break;
  232. case RCV_RING_JUMBO:
  233. rds_ring->num_desc = adapter->num_jumbo_rxd;
  234. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  235. rds_ring->dma_size =
  236. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  237. else
  238. rds_ring->dma_size =
  239. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  240. if (adapter->capabilities & NX_CAP0_HW_LRO)
  241. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  242. rds_ring->skb_size =
  243. rds_ring->dma_size + NET_IP_ALIGN;
  244. break;
  245. case RCV_RING_LRO:
  246. rds_ring->num_desc = adapter->num_lro_rxd;
  247. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  248. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  249. break;
  250. }
  251. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  252. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  253. if (rds_ring->rx_buf_arr == NULL) {
  254. printk(KERN_ERR "%s: Failed to allocate "
  255. "rx buffer ring %d\n",
  256. netdev->name, ring);
  257. /* free whatever was already allocated */
  258. goto err_out;
  259. }
  260. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  261. INIT_LIST_HEAD(&rds_ring->free_list);
  262. /*
  263. * Now go through all of them, set reference handles
  264. * and put them in the queues.
  265. */
  266. rx_buf = rds_ring->rx_buf_arr;
  267. for (i = 0; i < rds_ring->num_desc; i++) {
  268. list_add_tail(&rx_buf->list,
  269. &rds_ring->free_list);
  270. rx_buf->ref_handle = i;
  271. rx_buf->state = NETXEN_BUFFER_FREE;
  272. rx_buf++;
  273. }
  274. spin_lock_init(&rds_ring->lock);
  275. }
  276. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  277. sds_ring = &recv_ctx->sds_rings[ring];
  278. sds_ring->irq = adapter->msix_entries[ring].vector;
  279. sds_ring->adapter = adapter;
  280. sds_ring->num_desc = adapter->num_rxd;
  281. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  282. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  283. }
  284. return 0;
  285. err_out:
  286. netxen_free_sw_resources(adapter);
  287. return -ENOMEM;
  288. }
  289. /*
  290. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  291. * address to external PCI CRB address.
  292. */
  293. static u32 netxen_decode_crb_addr(u32 addr)
  294. {
  295. int i;
  296. u32 base_addr, offset, pci_base;
  297. crb_addr_transform_setup();
  298. pci_base = NETXEN_ADDR_ERROR;
  299. base_addr = addr & 0xfff00000;
  300. offset = addr & 0x000fffff;
  301. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  302. if (crb_addr_xform[i] == base_addr) {
  303. pci_base = i << 20;
  304. break;
  305. }
  306. }
  307. if (pci_base == NETXEN_ADDR_ERROR)
  308. return pci_base;
  309. else
  310. return (pci_base + offset);
  311. }
  312. #define NETXEN_MAX_ROM_WAIT_USEC 100
  313. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  314. {
  315. long timeout = 0;
  316. long done = 0;
  317. cond_resched();
  318. while (done == 0) {
  319. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  320. done &= 2;
  321. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  322. dev_err(&adapter->pdev->dev,
  323. "Timeout reached waiting for rom done");
  324. return -EIO;
  325. }
  326. udelay(1);
  327. }
  328. return 0;
  329. }
  330. static int do_rom_fast_read(struct netxen_adapter *adapter,
  331. int addr, int *valp)
  332. {
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  335. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  336. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  337. if (netxen_wait_rom_done(adapter)) {
  338. printk("Error waiting for rom done\n");
  339. return -EIO;
  340. }
  341. /* reset abyte_cnt and dummy_byte_cnt */
  342. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  343. udelay(10);
  344. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  345. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  346. return 0;
  347. }
  348. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  349. u8 *bytes, size_t size)
  350. {
  351. int addridx;
  352. int ret = 0;
  353. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  354. int v;
  355. ret = do_rom_fast_read(adapter, addridx, &v);
  356. if (ret != 0)
  357. break;
  358. *(__le32 *)bytes = cpu_to_le32(v);
  359. bytes += 4;
  360. }
  361. return ret;
  362. }
  363. int
  364. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  365. u8 *bytes, size_t size)
  366. {
  367. int ret;
  368. ret = netxen_rom_lock(adapter);
  369. if (ret < 0)
  370. return ret;
  371. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  372. netxen_rom_unlock(adapter);
  373. return ret;
  374. }
  375. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  376. {
  377. int ret;
  378. if (netxen_rom_lock(adapter) != 0)
  379. return -EIO;
  380. ret = do_rom_fast_read(adapter, addr, valp);
  381. netxen_rom_unlock(adapter);
  382. return ret;
  383. }
  384. #define NETXEN_BOARDTYPE 0x4008
  385. #define NETXEN_BOARDNUM 0x400c
  386. #define NETXEN_CHIPNUM 0x4010
  387. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  388. {
  389. int addr, val;
  390. int i, n, init_delay = 0;
  391. struct crb_addr_pair *buf;
  392. unsigned offset;
  393. u32 off;
  394. /* resetall */
  395. netxen_rom_lock(adapter);
  396. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  397. netxen_rom_unlock(adapter);
  398. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  399. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  400. (n != 0xcafecafe) ||
  401. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  402. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  403. "n: %08x\n", netxen_nic_driver_name, n);
  404. return -EIO;
  405. }
  406. offset = n & 0xffffU;
  407. n = (n >> 16) & 0xffffU;
  408. } else {
  409. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  410. !(n & 0x80000000)) {
  411. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  412. "n: %08x\n", netxen_nic_driver_name, n);
  413. return -EIO;
  414. }
  415. offset = 1;
  416. n &= ~0x80000000;
  417. }
  418. if (n >= 1024) {
  419. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  420. " initialized.\n", __func__, n);
  421. return -EIO;
  422. }
  423. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  424. if (buf == NULL) {
  425. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  426. netxen_nic_driver_name);
  427. return -ENOMEM;
  428. }
  429. for (i = 0; i < n; i++) {
  430. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  431. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  432. kfree(buf);
  433. return -EIO;
  434. }
  435. buf[i].addr = addr;
  436. buf[i].data = val;
  437. }
  438. for (i = 0; i < n; i++) {
  439. off = netxen_decode_crb_addr(buf[i].addr);
  440. if (off == NETXEN_ADDR_ERROR) {
  441. printk(KERN_ERR"CRB init value out of range %x\n",
  442. buf[i].addr);
  443. continue;
  444. }
  445. off += NETXEN_PCI_CRBSPACE;
  446. if (off & 1)
  447. continue;
  448. /* skipping cold reboot MAGIC */
  449. if (off == NETXEN_CAM_RAM(0x1fc))
  450. continue;
  451. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  452. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  453. continue;
  454. /* do not reset PCI */
  455. if (off == (ROMUSB_GLB + 0xbc))
  456. continue;
  457. if (off == (ROMUSB_GLB + 0xa8))
  458. continue;
  459. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  460. continue;
  461. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  462. continue;
  463. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  464. continue;
  465. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  466. continue;
  467. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  468. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  469. buf[i].data = 0x1020;
  470. /* skip the function enable register */
  471. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  472. continue;
  473. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  474. continue;
  475. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  476. continue;
  477. }
  478. init_delay = 1;
  479. /* After writing this register, HW needs time for CRB */
  480. /* to quiet down (else crb_window returns 0xffffffff) */
  481. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  482. init_delay = 1000;
  483. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  484. /* hold xdma in reset also */
  485. buf[i].data = NETXEN_NIC_XDMA_RESET;
  486. buf[i].data = 0x8000ff;
  487. }
  488. }
  489. NXWR32(adapter, off, buf[i].data);
  490. msleep(init_delay);
  491. }
  492. kfree(buf);
  493. /* disable_peg_cache_all */
  494. /* unreset_net_cache */
  495. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  496. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  497. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  498. }
  499. /* p2dn replyCount */
  500. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  501. /* disable_peg_cache 0 */
  502. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  503. /* disable_peg_cache 1 */
  504. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  505. /* peg_clr_all */
  506. /* peg_clr 0 */
  507. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  509. /* peg_clr 1 */
  510. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  512. /* peg_clr 2 */
  513. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  514. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  515. /* peg_clr 3 */
  516. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  517. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  518. return 0;
  519. }
  520. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  521. {
  522. uint32_t i;
  523. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  524. __le32 entries = cpu_to_le32(directory->num_entries);
  525. for (i = 0; i < entries; i++) {
  526. __le32 offs = cpu_to_le32(directory->findex) +
  527. (i * cpu_to_le32(directory->entry_size));
  528. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  529. if (tab_type == section)
  530. return (struct uni_table_desc *) &unirom[offs];
  531. }
  532. return NULL;
  533. }
  534. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  535. static int
  536. netxen_nic_validate_header(struct netxen_adapter *adapter)
  537. {
  538. const u8 *unirom = adapter->fw->data;
  539. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  540. u32 fw_file_size = adapter->fw->size;
  541. u32 tab_size;
  542. __le32 entries;
  543. __le32 entry_size;
  544. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  545. return -EINVAL;
  546. entries = cpu_to_le32(directory->num_entries);
  547. entry_size = cpu_to_le32(directory->entry_size);
  548. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  549. if (fw_file_size < tab_size)
  550. return -EINVAL;
  551. return 0;
  552. }
  553. static int
  554. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  555. {
  556. struct uni_table_desc *tab_desc;
  557. struct uni_data_desc *descr;
  558. const u8 *unirom = adapter->fw->data;
  559. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  560. NX_UNI_BOOTLD_IDX_OFF));
  561. u32 offs;
  562. u32 tab_size;
  563. u32 data_size;
  564. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  565. if (!tab_desc)
  566. return -EINVAL;
  567. tab_size = cpu_to_le32(tab_desc->findex) +
  568. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  569. if (adapter->fw->size < tab_size)
  570. return -EINVAL;
  571. offs = cpu_to_le32(tab_desc->findex) +
  572. (cpu_to_le32(tab_desc->entry_size) * (idx));
  573. descr = (struct uni_data_desc *)&unirom[offs];
  574. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  575. if (adapter->fw->size < data_size)
  576. return -EINVAL;
  577. return 0;
  578. }
  579. static int
  580. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  581. {
  582. struct uni_table_desc *tab_desc;
  583. struct uni_data_desc *descr;
  584. const u8 *unirom = adapter->fw->data;
  585. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  586. NX_UNI_FIRMWARE_IDX_OFF));
  587. u32 offs;
  588. u32 tab_size;
  589. u32 data_size;
  590. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  591. if (!tab_desc)
  592. return -EINVAL;
  593. tab_size = cpu_to_le32(tab_desc->findex) +
  594. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  595. if (adapter->fw->size < tab_size)
  596. return -EINVAL;
  597. offs = cpu_to_le32(tab_desc->findex) +
  598. (cpu_to_le32(tab_desc->entry_size) * (idx));
  599. descr = (struct uni_data_desc *)&unirom[offs];
  600. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  601. if (adapter->fw->size < data_size)
  602. return -EINVAL;
  603. return 0;
  604. }
  605. static int
  606. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  607. {
  608. struct uni_table_desc *ptab_descr;
  609. const u8 *unirom = adapter->fw->data;
  610. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  611. 1 : netxen_p3_has_mn(adapter);
  612. __le32 entries;
  613. __le32 entry_size;
  614. u32 tab_size;
  615. u32 i;
  616. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  617. if (ptab_descr == NULL)
  618. return -EINVAL;
  619. entries = cpu_to_le32(ptab_descr->num_entries);
  620. entry_size = cpu_to_le32(ptab_descr->entry_size);
  621. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  622. if (adapter->fw->size < tab_size)
  623. return -EINVAL;
  624. nomn:
  625. for (i = 0; i < entries; i++) {
  626. __le32 flags, file_chiprev, offs;
  627. u8 chiprev = adapter->ahw.revision_id;
  628. uint32_t flagbit;
  629. offs = cpu_to_le32(ptab_descr->findex) +
  630. (i * cpu_to_le32(ptab_descr->entry_size));
  631. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  632. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  633. NX_UNI_CHIP_REV_OFF));
  634. flagbit = mn_present ? 1 : 2;
  635. if ((chiprev == file_chiprev) &&
  636. ((1ULL << flagbit) & flags)) {
  637. adapter->file_prd_off = offs;
  638. return 0;
  639. }
  640. }
  641. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  642. mn_present = 0;
  643. goto nomn;
  644. }
  645. return -EINVAL;
  646. }
  647. static int
  648. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  649. {
  650. if (netxen_nic_validate_header(adapter)) {
  651. dev_err(&adapter->pdev->dev,
  652. "unified image: header validation failed\n");
  653. return -EINVAL;
  654. }
  655. if (netxen_nic_validate_product_offs(adapter)) {
  656. dev_err(&adapter->pdev->dev,
  657. "unified image: product validation failed\n");
  658. return -EINVAL;
  659. }
  660. if (netxen_nic_validate_bootld(adapter)) {
  661. dev_err(&adapter->pdev->dev,
  662. "unified image: bootld validation failed\n");
  663. return -EINVAL;
  664. }
  665. if (netxen_nic_validate_fw(adapter)) {
  666. dev_err(&adapter->pdev->dev,
  667. "unified image: firmware validation failed\n");
  668. return -EINVAL;
  669. }
  670. return 0;
  671. }
  672. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  673. u32 section, u32 idx_offset)
  674. {
  675. const u8 *unirom = adapter->fw->data;
  676. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  677. idx_offset));
  678. struct uni_table_desc *tab_desc;
  679. __le32 offs;
  680. tab_desc = nx_get_table_desc(unirom, section);
  681. if (tab_desc == NULL)
  682. return NULL;
  683. offs = cpu_to_le32(tab_desc->findex) +
  684. (cpu_to_le32(tab_desc->entry_size) * idx);
  685. return (struct uni_data_desc *)&unirom[offs];
  686. }
  687. static u8 *
  688. nx_get_bootld_offs(struct netxen_adapter *adapter)
  689. {
  690. u32 offs = NETXEN_BOOTLD_START;
  691. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  692. offs = cpu_to_le32((nx_get_data_desc(adapter,
  693. NX_UNI_DIR_SECT_BOOTLD,
  694. NX_UNI_BOOTLD_IDX_OFF))->findex);
  695. return (u8 *)&adapter->fw->data[offs];
  696. }
  697. static u8 *
  698. nx_get_fw_offs(struct netxen_adapter *adapter)
  699. {
  700. u32 offs = NETXEN_IMAGE_START;
  701. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  702. offs = cpu_to_le32((nx_get_data_desc(adapter,
  703. NX_UNI_DIR_SECT_FW,
  704. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  705. return (u8 *)&adapter->fw->data[offs];
  706. }
  707. static __le32
  708. nx_get_fw_size(struct netxen_adapter *adapter)
  709. {
  710. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  711. return cpu_to_le32((nx_get_data_desc(adapter,
  712. NX_UNI_DIR_SECT_FW,
  713. NX_UNI_FIRMWARE_IDX_OFF))->size);
  714. else
  715. return cpu_to_le32(
  716. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  717. }
  718. static __le32
  719. nx_get_fw_version(struct netxen_adapter *adapter)
  720. {
  721. struct uni_data_desc *fw_data_desc;
  722. const struct firmware *fw = adapter->fw;
  723. __le32 major, minor, sub;
  724. const u8 *ver_str;
  725. int i, ret = 0;
  726. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  727. fw_data_desc = nx_get_data_desc(adapter,
  728. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  729. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  730. cpu_to_le32(fw_data_desc->size) - 17;
  731. for (i = 0; i < 12; i++) {
  732. if (!strncmp(&ver_str[i], "REV=", 4)) {
  733. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  734. &major, &minor, &sub);
  735. break;
  736. }
  737. }
  738. if (ret != 3)
  739. return 0;
  740. return major + (minor << 8) + (sub << 16);
  741. } else
  742. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  743. }
  744. static __le32
  745. nx_get_bios_version(struct netxen_adapter *adapter)
  746. {
  747. const struct firmware *fw = adapter->fw;
  748. __le32 bios_ver, prd_off = adapter->file_prd_off;
  749. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  750. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  751. + NX_UNI_BIOS_VERSION_OFF));
  752. return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) +
  753. (bios_ver >> 24);
  754. } else
  755. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  756. }
  757. int
  758. netxen_need_fw_reset(struct netxen_adapter *adapter)
  759. {
  760. u32 count, old_count;
  761. u32 val, version, major, minor, build;
  762. int i, timeout;
  763. u8 fw_type;
  764. /* NX2031 firmware doesn't support heartbit */
  765. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  766. return 1;
  767. if (adapter->need_fw_reset)
  768. return 1;
  769. /* last attempt had failed */
  770. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  771. return 1;
  772. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  773. for (i = 0; i < 10; i++) {
  774. timeout = msleep_interruptible(200);
  775. if (timeout) {
  776. NXWR32(adapter, CRB_CMDPEG_STATE,
  777. PHAN_INITIALIZE_FAILED);
  778. return -EINTR;
  779. }
  780. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  781. if (count != old_count)
  782. break;
  783. }
  784. /* firmware is dead */
  785. if (count == old_count)
  786. return 1;
  787. /* check if we have got newer or different file firmware */
  788. if (adapter->fw) {
  789. val = nx_get_fw_version(adapter);
  790. version = NETXEN_DECODE_VERSION(val);
  791. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  792. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  793. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  794. if (version > NETXEN_VERSION_CODE(major, minor, build))
  795. return 1;
  796. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  797. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  798. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  799. fw_type = (val & 0x4) ?
  800. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  801. if (adapter->fw_type != fw_type)
  802. return 1;
  803. }
  804. }
  805. return 0;
  806. }
  807. static char *fw_name[] = {
  808. NX_P2_MN_ROMIMAGE_NAME,
  809. NX_P3_CT_ROMIMAGE_NAME,
  810. NX_P3_MN_ROMIMAGE_NAME,
  811. NX_UNIFIED_ROMIMAGE_NAME,
  812. NX_FLASH_ROMIMAGE_NAME,
  813. };
  814. int
  815. netxen_load_firmware(struct netxen_adapter *adapter)
  816. {
  817. u64 *ptr64;
  818. u32 i, flashaddr, size;
  819. const struct firmware *fw = adapter->fw;
  820. struct pci_dev *pdev = adapter->pdev;
  821. dev_info(&pdev->dev, "loading firmware from %s\n",
  822. fw_name[adapter->fw_type]);
  823. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  824. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  825. if (fw) {
  826. __le64 data;
  827. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  828. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  829. flashaddr = NETXEN_BOOTLD_START;
  830. for (i = 0; i < size; i++) {
  831. data = cpu_to_le64(ptr64[i]);
  832. if (adapter->pci_mem_write(adapter, flashaddr, data))
  833. return -EIO;
  834. flashaddr += 8;
  835. }
  836. size = (__force u32)nx_get_fw_size(adapter) / 8;
  837. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  838. flashaddr = NETXEN_IMAGE_START;
  839. for (i = 0; i < size; i++) {
  840. data = cpu_to_le64(ptr64[i]);
  841. if (adapter->pci_mem_write(adapter,
  842. flashaddr, data))
  843. return -EIO;
  844. flashaddr += 8;
  845. }
  846. size = (__force u32)nx_get_fw_size(adapter) % 8;
  847. if (size) {
  848. data = cpu_to_le64(ptr64[i]);
  849. if (adapter->pci_mem_write(adapter,
  850. flashaddr, data))
  851. return -EIO;
  852. }
  853. } else {
  854. u64 data;
  855. u32 hi, lo;
  856. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  857. flashaddr = NETXEN_BOOTLD_START;
  858. for (i = 0; i < size; i++) {
  859. if (netxen_rom_fast_read(adapter,
  860. flashaddr, (int *)&lo) != 0)
  861. return -EIO;
  862. if (netxen_rom_fast_read(adapter,
  863. flashaddr + 4, (int *)&hi) != 0)
  864. return -EIO;
  865. /* hi, lo are already in host endian byteorder */
  866. data = (((u64)hi << 32) | lo);
  867. if (adapter->pci_mem_write(adapter,
  868. flashaddr, data))
  869. return -EIO;
  870. flashaddr += 8;
  871. }
  872. }
  873. msleep(1);
  874. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  875. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  876. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  877. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  878. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  879. else {
  880. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  881. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  882. }
  883. return 0;
  884. }
  885. static int
  886. netxen_validate_firmware(struct netxen_adapter *adapter)
  887. {
  888. __le32 val;
  889. u32 ver, min_ver, bios;
  890. struct pci_dev *pdev = adapter->pdev;
  891. const struct firmware *fw = adapter->fw;
  892. u8 fw_type = adapter->fw_type;
  893. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  894. if (netxen_nic_validate_unified_romimage(adapter))
  895. return -EINVAL;
  896. } else {
  897. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  898. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  899. return -EINVAL;
  900. if (fw->size < NX_FW_MIN_SIZE)
  901. return -EINVAL;
  902. }
  903. val = nx_get_fw_version(adapter);
  904. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  905. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  906. else
  907. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  908. ver = NETXEN_DECODE_VERSION(val);
  909. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  910. dev_err(&pdev->dev,
  911. "%s: firmware version %d.%d.%d unsupported\n",
  912. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  913. return -EINVAL;
  914. }
  915. val = nx_get_bios_version(adapter);
  916. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  917. if ((__force u32)val != bios) {
  918. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  919. fw_name[fw_type]);
  920. return -EINVAL;
  921. }
  922. /* check if flashed firmware is newer */
  923. if (netxen_rom_fast_read(adapter,
  924. NX_FW_VERSION_OFFSET, (int *)&val))
  925. return -EIO;
  926. val = NETXEN_DECODE_VERSION(val);
  927. if (val > ver) {
  928. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  929. fw_name[fw_type]);
  930. return -EINVAL;
  931. }
  932. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  933. return 0;
  934. }
  935. static void
  936. nx_get_next_fwtype(struct netxen_adapter *adapter)
  937. {
  938. u8 fw_type;
  939. switch (adapter->fw_type) {
  940. case NX_UNKNOWN_ROMIMAGE:
  941. fw_type = NX_UNIFIED_ROMIMAGE;
  942. break;
  943. case NX_UNIFIED_ROMIMAGE:
  944. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  945. fw_type = NX_FLASH_ROMIMAGE;
  946. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  947. fw_type = NX_P2_MN_ROMIMAGE;
  948. else if (netxen_p3_has_mn(adapter))
  949. fw_type = NX_P3_MN_ROMIMAGE;
  950. else
  951. fw_type = NX_P3_CT_ROMIMAGE;
  952. break;
  953. case NX_P3_MN_ROMIMAGE:
  954. fw_type = NX_P3_CT_ROMIMAGE;
  955. break;
  956. case NX_P2_MN_ROMIMAGE:
  957. case NX_P3_CT_ROMIMAGE:
  958. default:
  959. fw_type = NX_FLASH_ROMIMAGE;
  960. break;
  961. }
  962. adapter->fw_type = fw_type;
  963. }
  964. static int
  965. netxen_p3_has_mn(struct netxen_adapter *adapter)
  966. {
  967. u32 capability, flashed_ver;
  968. capability = 0;
  969. /* NX2031 always had MN */
  970. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  971. return 1;
  972. netxen_rom_fast_read(adapter,
  973. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  974. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  975. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  976. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  977. if (capability & NX_PEG_TUNE_MN_PRESENT)
  978. return 1;
  979. }
  980. return 0;
  981. }
  982. void netxen_request_firmware(struct netxen_adapter *adapter)
  983. {
  984. struct pci_dev *pdev = adapter->pdev;
  985. int rc = 0;
  986. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  987. next:
  988. nx_get_next_fwtype(adapter);
  989. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  990. adapter->fw = NULL;
  991. } else {
  992. rc = request_firmware(&adapter->fw,
  993. fw_name[adapter->fw_type], &pdev->dev);
  994. if (rc != 0)
  995. goto next;
  996. rc = netxen_validate_firmware(adapter);
  997. if (rc != 0) {
  998. release_firmware(adapter->fw);
  999. msleep(1);
  1000. goto next;
  1001. }
  1002. }
  1003. }
  1004. void
  1005. netxen_release_firmware(struct netxen_adapter *adapter)
  1006. {
  1007. if (adapter->fw)
  1008. release_firmware(adapter->fw);
  1009. adapter->fw = NULL;
  1010. }
  1011. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1012. {
  1013. u64 addr;
  1014. u32 hi, lo;
  1015. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1016. return 0;
  1017. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1018. NETXEN_HOST_DUMMY_DMA_SIZE,
  1019. &adapter->dummy_dma.phys_addr);
  1020. if (adapter->dummy_dma.addr == NULL) {
  1021. dev_err(&adapter->pdev->dev,
  1022. "ERROR: Could not allocate dummy DMA memory\n");
  1023. return -ENOMEM;
  1024. }
  1025. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1026. hi = (addr >> 32) & 0xffffffff;
  1027. lo = addr & 0xffffffff;
  1028. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1029. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1030. return 0;
  1031. }
  1032. /*
  1033. * NetXen DMA watchdog control:
  1034. *
  1035. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1036. * Bit 1 : disable_request => 1 req disable dma watchdog
  1037. * Bit 2 : enable_request => 1 req enable dma watchdog
  1038. * Bit 3-31 : unused
  1039. */
  1040. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1041. {
  1042. int i = 100;
  1043. u32 ctrl;
  1044. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1045. return;
  1046. if (!adapter->dummy_dma.addr)
  1047. return;
  1048. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1049. if ((ctrl & 0x1) != 0) {
  1050. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1051. while ((ctrl & 0x1) != 0) {
  1052. msleep(50);
  1053. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1054. if (--i == 0)
  1055. break;
  1056. };
  1057. }
  1058. if (i) {
  1059. pci_free_consistent(adapter->pdev,
  1060. NETXEN_HOST_DUMMY_DMA_SIZE,
  1061. adapter->dummy_dma.addr,
  1062. adapter->dummy_dma.phys_addr);
  1063. adapter->dummy_dma.addr = NULL;
  1064. } else
  1065. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1066. }
  1067. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1068. {
  1069. u32 val = 0;
  1070. int retries = 60;
  1071. if (pegtune_val)
  1072. return 0;
  1073. do {
  1074. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1075. switch (val) {
  1076. case PHAN_INITIALIZE_COMPLETE:
  1077. case PHAN_INITIALIZE_ACK:
  1078. return 0;
  1079. case PHAN_INITIALIZE_FAILED:
  1080. goto out_err;
  1081. default:
  1082. break;
  1083. }
  1084. msleep(500);
  1085. } while (--retries);
  1086. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1087. out_err:
  1088. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1089. return -EIO;
  1090. }
  1091. static int
  1092. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1093. {
  1094. u32 val = 0;
  1095. int retries = 2000;
  1096. do {
  1097. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1098. if (val == PHAN_PEG_RCV_INITIALIZED)
  1099. return 0;
  1100. msleep(10);
  1101. } while (--retries);
  1102. if (!retries) {
  1103. printk(KERN_ERR "Receive Peg initialization not "
  1104. "complete, state: 0x%x.\n", val);
  1105. return -EIO;
  1106. }
  1107. return 0;
  1108. }
  1109. int netxen_init_firmware(struct netxen_adapter *adapter)
  1110. {
  1111. int err;
  1112. err = netxen_receive_peg_ready(adapter);
  1113. if (err)
  1114. return err;
  1115. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1116. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1117. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1118. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1119. return err;
  1120. }
  1121. static void
  1122. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1123. {
  1124. u32 cable_OUI;
  1125. u16 cable_len;
  1126. u16 link_speed;
  1127. u8 link_status, module, duplex, autoneg;
  1128. struct net_device *netdev = adapter->netdev;
  1129. adapter->has_link_events = 1;
  1130. cable_OUI = msg->body[1] & 0xffffffff;
  1131. cable_len = (msg->body[1] >> 32) & 0xffff;
  1132. link_speed = (msg->body[1] >> 48) & 0xffff;
  1133. link_status = msg->body[2] & 0xff;
  1134. duplex = (msg->body[2] >> 16) & 0xff;
  1135. autoneg = (msg->body[2] >> 24) & 0xff;
  1136. module = (msg->body[2] >> 8) & 0xff;
  1137. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1138. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1139. netdev->name, cable_OUI, cable_len);
  1140. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1141. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1142. netdev->name, cable_len);
  1143. }
  1144. netxen_advert_link_change(adapter, link_status);
  1145. /* update link parameters */
  1146. if (duplex == LINKEVENT_FULL_DUPLEX)
  1147. adapter->link_duplex = DUPLEX_FULL;
  1148. else
  1149. adapter->link_duplex = DUPLEX_HALF;
  1150. adapter->module_type = module;
  1151. adapter->link_autoneg = autoneg;
  1152. adapter->link_speed = link_speed;
  1153. }
  1154. static void
  1155. netxen_handle_fw_message(int desc_cnt, int index,
  1156. struct nx_host_sds_ring *sds_ring)
  1157. {
  1158. nx_fw_msg_t msg;
  1159. struct status_desc *desc;
  1160. int i = 0, opcode;
  1161. while (desc_cnt > 0 && i < 8) {
  1162. desc = &sds_ring->desc_head[index];
  1163. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1164. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1165. index = get_next_index(index, sds_ring->num_desc);
  1166. desc_cnt--;
  1167. }
  1168. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1169. switch (opcode) {
  1170. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1171. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1172. break;
  1173. default:
  1174. break;
  1175. }
  1176. }
  1177. static int
  1178. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1179. struct nx_host_rds_ring *rds_ring,
  1180. struct netxen_rx_buffer *buffer)
  1181. {
  1182. struct sk_buff *skb;
  1183. dma_addr_t dma;
  1184. struct pci_dev *pdev = adapter->pdev;
  1185. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1186. if (!buffer->skb)
  1187. return 1;
  1188. skb = buffer->skb;
  1189. if (!adapter->ahw.cut_through)
  1190. skb_reserve(skb, 2);
  1191. dma = pci_map_single(pdev, skb->data,
  1192. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1193. if (pci_dma_mapping_error(pdev, dma)) {
  1194. dev_kfree_skb_any(skb);
  1195. buffer->skb = NULL;
  1196. return 1;
  1197. }
  1198. buffer->skb = skb;
  1199. buffer->dma = dma;
  1200. buffer->state = NETXEN_BUFFER_BUSY;
  1201. return 0;
  1202. }
  1203. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1204. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1205. {
  1206. struct netxen_rx_buffer *buffer;
  1207. struct sk_buff *skb;
  1208. buffer = &rds_ring->rx_buf_arr[index];
  1209. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1210. PCI_DMA_FROMDEVICE);
  1211. skb = buffer->skb;
  1212. if (!skb)
  1213. goto no_skb;
  1214. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1215. adapter->stats.csummed++;
  1216. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1217. } else
  1218. skb->ip_summed = CHECKSUM_NONE;
  1219. skb->dev = adapter->netdev;
  1220. buffer->skb = NULL;
  1221. no_skb:
  1222. buffer->state = NETXEN_BUFFER_FREE;
  1223. return skb;
  1224. }
  1225. static struct netxen_rx_buffer *
  1226. netxen_process_rcv(struct netxen_adapter *adapter,
  1227. struct nx_host_sds_ring *sds_ring,
  1228. int ring, u64 sts_data0)
  1229. {
  1230. struct net_device *netdev = adapter->netdev;
  1231. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1232. struct netxen_rx_buffer *buffer;
  1233. struct sk_buff *skb;
  1234. struct nx_host_rds_ring *rds_ring;
  1235. int index, length, cksum, pkt_offset;
  1236. if (unlikely(ring >= adapter->max_rds_rings))
  1237. return NULL;
  1238. rds_ring = &recv_ctx->rds_rings[ring];
  1239. index = netxen_get_sts_refhandle(sts_data0);
  1240. if (unlikely(index >= rds_ring->num_desc))
  1241. return NULL;
  1242. buffer = &rds_ring->rx_buf_arr[index];
  1243. length = netxen_get_sts_totallength(sts_data0);
  1244. cksum = netxen_get_sts_status(sts_data0);
  1245. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1246. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1247. if (!skb)
  1248. return buffer;
  1249. if (length > rds_ring->skb_size)
  1250. skb_put(skb, rds_ring->skb_size);
  1251. else
  1252. skb_put(skb, length);
  1253. if (pkt_offset)
  1254. skb_pull(skb, pkt_offset);
  1255. skb->truesize = skb->len + sizeof(struct sk_buff);
  1256. skb->protocol = eth_type_trans(skb, netdev);
  1257. napi_gro_receive(&sds_ring->napi, skb);
  1258. adapter->stats.rx_pkts++;
  1259. adapter->stats.rxbytes += length;
  1260. return buffer;
  1261. }
  1262. #define TCP_HDR_SIZE 20
  1263. #define TCP_TS_OPTION_SIZE 12
  1264. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1265. static struct netxen_rx_buffer *
  1266. netxen_process_lro(struct netxen_adapter *adapter,
  1267. struct nx_host_sds_ring *sds_ring,
  1268. int ring, u64 sts_data0, u64 sts_data1)
  1269. {
  1270. struct net_device *netdev = adapter->netdev;
  1271. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1272. struct netxen_rx_buffer *buffer;
  1273. struct sk_buff *skb;
  1274. struct nx_host_rds_ring *rds_ring;
  1275. struct iphdr *iph;
  1276. struct tcphdr *th;
  1277. bool push, timestamp;
  1278. int l2_hdr_offset, l4_hdr_offset;
  1279. int index;
  1280. u16 lro_length, length, data_offset;
  1281. u32 seq_number;
  1282. if (unlikely(ring > adapter->max_rds_rings))
  1283. return NULL;
  1284. rds_ring = &recv_ctx->rds_rings[ring];
  1285. index = netxen_get_lro_sts_refhandle(sts_data0);
  1286. if (unlikely(index > rds_ring->num_desc))
  1287. return NULL;
  1288. buffer = &rds_ring->rx_buf_arr[index];
  1289. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1290. lro_length = netxen_get_lro_sts_length(sts_data0);
  1291. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1292. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1293. push = netxen_get_lro_sts_push_flag(sts_data0);
  1294. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1295. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1296. if (!skb)
  1297. return buffer;
  1298. if (timestamp)
  1299. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1300. else
  1301. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1302. skb_put(skb, lro_length + data_offset);
  1303. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1304. skb_pull(skb, l2_hdr_offset);
  1305. skb->protocol = eth_type_trans(skb, netdev);
  1306. iph = (struct iphdr *)skb->data;
  1307. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1308. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1309. iph->tot_len = htons(length);
  1310. iph->check = 0;
  1311. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1312. th->psh = push;
  1313. th->seq = htonl(seq_number);
  1314. length = skb->len;
  1315. netif_receive_skb(skb);
  1316. adapter->stats.lro_pkts++;
  1317. adapter->stats.rxbytes += length;
  1318. return buffer;
  1319. }
  1320. #define netxen_merge_rx_buffers(list, head) \
  1321. do { list_splice_tail_init(list, head); } while (0);
  1322. int
  1323. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1324. {
  1325. struct netxen_adapter *adapter = sds_ring->adapter;
  1326. struct list_head *cur;
  1327. struct status_desc *desc;
  1328. struct netxen_rx_buffer *rxbuf;
  1329. u32 consumer = sds_ring->consumer;
  1330. int count = 0;
  1331. u64 sts_data0, sts_data1;
  1332. int opcode, ring = 0, desc_cnt;
  1333. while (count < max) {
  1334. desc = &sds_ring->desc_head[consumer];
  1335. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1336. if (!(sts_data0 & STATUS_OWNER_HOST))
  1337. break;
  1338. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1339. opcode = netxen_get_sts_opcode(sts_data0);
  1340. switch (opcode) {
  1341. case NETXEN_NIC_RXPKT_DESC:
  1342. case NETXEN_OLD_RXPKT_DESC:
  1343. case NETXEN_NIC_SYN_OFFLOAD:
  1344. ring = netxen_get_sts_type(sts_data0);
  1345. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1346. ring, sts_data0);
  1347. break;
  1348. case NETXEN_NIC_LRO_DESC:
  1349. ring = netxen_get_lro_sts_type(sts_data0);
  1350. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1351. rxbuf = netxen_process_lro(adapter, sds_ring,
  1352. ring, sts_data0, sts_data1);
  1353. break;
  1354. case NETXEN_NIC_RESPONSE_DESC:
  1355. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1356. default:
  1357. goto skip;
  1358. }
  1359. WARN_ON(desc_cnt > 1);
  1360. if (rxbuf)
  1361. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1362. skip:
  1363. for (; desc_cnt > 0; desc_cnt--) {
  1364. desc = &sds_ring->desc_head[consumer];
  1365. desc->status_desc_data[0] =
  1366. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1367. consumer = get_next_index(consumer, sds_ring->num_desc);
  1368. }
  1369. count++;
  1370. }
  1371. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1372. struct nx_host_rds_ring *rds_ring =
  1373. &adapter->recv_ctx.rds_rings[ring];
  1374. if (!list_empty(&sds_ring->free_list[ring])) {
  1375. list_for_each(cur, &sds_ring->free_list[ring]) {
  1376. rxbuf = list_entry(cur,
  1377. struct netxen_rx_buffer, list);
  1378. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1379. }
  1380. spin_lock(&rds_ring->lock);
  1381. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1382. &rds_ring->free_list);
  1383. spin_unlock(&rds_ring->lock);
  1384. }
  1385. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1386. }
  1387. if (count) {
  1388. sds_ring->consumer = consumer;
  1389. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1390. }
  1391. return count;
  1392. }
  1393. /* Process Command status ring */
  1394. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1395. {
  1396. u32 sw_consumer, hw_consumer;
  1397. int count = 0, i;
  1398. struct netxen_cmd_buffer *buffer;
  1399. struct pci_dev *pdev = adapter->pdev;
  1400. struct net_device *netdev = adapter->netdev;
  1401. struct netxen_skb_frag *frag;
  1402. int done = 0;
  1403. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1404. if (!spin_trylock(&adapter->tx_clean_lock))
  1405. return 1;
  1406. sw_consumer = tx_ring->sw_consumer;
  1407. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1408. while (sw_consumer != hw_consumer) {
  1409. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1410. if (buffer->skb) {
  1411. frag = &buffer->frag_array[0];
  1412. pci_unmap_single(pdev, frag->dma, frag->length,
  1413. PCI_DMA_TODEVICE);
  1414. frag->dma = 0ULL;
  1415. for (i = 1; i < buffer->frag_count; i++) {
  1416. frag++; /* Get the next frag */
  1417. pci_unmap_page(pdev, frag->dma, frag->length,
  1418. PCI_DMA_TODEVICE);
  1419. frag->dma = 0ULL;
  1420. }
  1421. adapter->stats.xmitfinished++;
  1422. dev_kfree_skb_any(buffer->skb);
  1423. buffer->skb = NULL;
  1424. }
  1425. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1426. if (++count >= MAX_STATUS_HANDLE)
  1427. break;
  1428. }
  1429. if (count && netif_running(netdev)) {
  1430. tx_ring->sw_consumer = sw_consumer;
  1431. smp_mb();
  1432. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1433. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1434. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1435. netif_wake_queue(netdev);
  1436. adapter->tx_timeo_cnt = 0;
  1437. }
  1438. __netif_tx_unlock(tx_ring->txq);
  1439. }
  1440. }
  1441. /*
  1442. * If everything is freed up to consumer then check if the ring is full
  1443. * If the ring is full then check if more needs to be freed and
  1444. * schedule the call back again.
  1445. *
  1446. * This happens when there are 2 CPUs. One could be freeing and the
  1447. * other filling it. If the ring is full when we get out of here and
  1448. * the card has already interrupted the host then the host can miss the
  1449. * interrupt.
  1450. *
  1451. * There is still a possible race condition and the host could miss an
  1452. * interrupt. The card has to take care of this.
  1453. */
  1454. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1455. done = (sw_consumer == hw_consumer);
  1456. spin_unlock(&adapter->tx_clean_lock);
  1457. return (done);
  1458. }
  1459. void
  1460. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1461. struct nx_host_rds_ring *rds_ring)
  1462. {
  1463. struct rcv_desc *pdesc;
  1464. struct netxen_rx_buffer *buffer;
  1465. int producer, count = 0;
  1466. netxen_ctx_msg msg = 0;
  1467. struct list_head *head;
  1468. producer = rds_ring->producer;
  1469. spin_lock(&rds_ring->lock);
  1470. head = &rds_ring->free_list;
  1471. while (!list_empty(head)) {
  1472. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1473. if (!buffer->skb) {
  1474. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1475. break;
  1476. }
  1477. count++;
  1478. list_del(&buffer->list);
  1479. /* make a rcv descriptor */
  1480. pdesc = &rds_ring->desc_head[producer];
  1481. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1482. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1483. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1484. producer = get_next_index(producer, rds_ring->num_desc);
  1485. }
  1486. spin_unlock(&rds_ring->lock);
  1487. if (count) {
  1488. rds_ring->producer = producer;
  1489. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1490. (producer-1) & (rds_ring->num_desc-1));
  1491. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1492. /*
  1493. * Write a doorbell msg to tell phanmon of change in
  1494. * receive ring producer
  1495. * Only for firmware version < 4.0.0
  1496. */
  1497. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1498. netxen_set_msg_privid(msg);
  1499. netxen_set_msg_count(msg,
  1500. ((producer - 1) &
  1501. (rds_ring->num_desc - 1)));
  1502. netxen_set_msg_ctxid(msg, adapter->portnum);
  1503. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1504. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1505. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1506. }
  1507. }
  1508. }
  1509. static void
  1510. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1511. struct nx_host_rds_ring *rds_ring)
  1512. {
  1513. struct rcv_desc *pdesc;
  1514. struct netxen_rx_buffer *buffer;
  1515. int producer, count = 0;
  1516. struct list_head *head;
  1517. producer = rds_ring->producer;
  1518. if (!spin_trylock(&rds_ring->lock))
  1519. return;
  1520. head = &rds_ring->free_list;
  1521. while (!list_empty(head)) {
  1522. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1523. if (!buffer->skb) {
  1524. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1525. break;
  1526. }
  1527. count++;
  1528. list_del(&buffer->list);
  1529. /* make a rcv descriptor */
  1530. pdesc = &rds_ring->desc_head[producer];
  1531. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1532. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1533. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1534. producer = get_next_index(producer, rds_ring->num_desc);
  1535. }
  1536. if (count) {
  1537. rds_ring->producer = producer;
  1538. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1539. (producer - 1) & (rds_ring->num_desc - 1));
  1540. }
  1541. spin_unlock(&rds_ring->lock);
  1542. }
  1543. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1544. {
  1545. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1546. return;
  1547. }