tifm_sd.c 26 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.8"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_DATAMASK 0x401d /* set bits: CERR, EOFB, BRS, CB, EOC */
  34. #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
  35. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  46. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  47. #define TIFM_MMCSD_RSP_R0 0x0000
  48. #define TIFM_MMCSD_RSP_R1 0x0100
  49. #define TIFM_MMCSD_RSP_R2 0x0200
  50. #define TIFM_MMCSD_RSP_R3 0x0300
  51. #define TIFM_MMCSD_RSP_R4 0x0400
  52. #define TIFM_MMCSD_RSP_R5 0x0500
  53. #define TIFM_MMCSD_RSP_R6 0x0600
  54. #define TIFM_MMCSD_RSP_BUSY 0x0800
  55. #define TIFM_MMCSD_CMD_BC 0x0000
  56. #define TIFM_MMCSD_CMD_BCR 0x1000
  57. #define TIFM_MMCSD_CMD_AC 0x2000
  58. #define TIFM_MMCSD_CMD_ADTC 0x3000
  59. typedef enum {
  60. IDLE = 0,
  61. CMD, /* main command ended */
  62. BRS, /* block transfer finished */
  63. SCMD, /* stop command ended */
  64. CARD, /* card left busy state */
  65. FIFO, /* FIFO operation completed (uncertain) */
  66. READY
  67. } card_state_t;
  68. enum {
  69. FIFO_RDY = 0x0001, /* hardware dependent value */
  70. EJECT = 0x0004,
  71. EJECT_DONE = 0x0008,
  72. CARD_BUSY = 0x0010,
  73. OPENDRAIN = 0x0040, /* hardware dependent value */
  74. CARD_EVENT = 0x0100, /* hardware dependent value */
  75. CARD_RO = 0x0200, /* hardware dependent value */
  76. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  77. struct tifm_sd {
  78. struct tifm_dev *dev;
  79. unsigned int flags;
  80. card_state_t state;
  81. unsigned int clk_freq;
  82. unsigned int clk_div;
  83. unsigned long timeout_jiffies;
  84. struct tasklet_struct finish_tasklet;
  85. struct timer_list timer;
  86. struct mmc_request *req;
  87. wait_queue_head_t notify;
  88. size_t written_blocks;
  89. size_t buffer_size;
  90. size_t buffer_pos;
  91. };
  92. static char* tifm_sd_data_buffer(struct mmc_data *data)
  93. {
  94. return page_address(data->sg->page) + data->sg->offset;
  95. }
  96. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  97. unsigned int host_status)
  98. {
  99. struct mmc_command *cmd = host->req->cmd;
  100. unsigned int t_val = 0, cnt = 0;
  101. char *buffer;
  102. if (host_status & TIFM_MMCSD_BRS) {
  103. /* in non-dma rx mode BRS fires when fifo is still not empty */
  104. if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
  105. buffer = tifm_sd_data_buffer(host->req->data);
  106. while (host->buffer_size > host->buffer_pos) {
  107. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  108. buffer[host->buffer_pos++] = t_val & 0xff;
  109. buffer[host->buffer_pos++] =
  110. (t_val >> 8) & 0xff;
  111. }
  112. }
  113. return 1;
  114. } else if (no_dma) {
  115. buffer = tifm_sd_data_buffer(host->req->data);
  116. if ((cmd->data->flags & MMC_DATA_READ) &&
  117. (host_status & TIFM_MMCSD_AF)) {
  118. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  119. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  120. if (host->buffer_size > host->buffer_pos) {
  121. buffer[host->buffer_pos++] =
  122. t_val & 0xff;
  123. buffer[host->buffer_pos++] =
  124. (t_val >> 8) & 0xff;
  125. }
  126. }
  127. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  128. && (host_status & TIFM_MMCSD_AE)) {
  129. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  130. if (host->buffer_size > host->buffer_pos) {
  131. t_val = buffer[host->buffer_pos++]
  132. & 0x00ff;
  133. t_val |= ((buffer[host->buffer_pos++])
  134. << 8) & 0xff00;
  135. writel(t_val,
  136. sock->addr + SOCK_MMCSD_DATA);
  137. }
  138. }
  139. }
  140. }
  141. return 0;
  142. }
  143. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  144. {
  145. unsigned int rc = 0;
  146. switch (mmc_resp_type(cmd)) {
  147. case MMC_RSP_NONE:
  148. rc |= TIFM_MMCSD_RSP_R0;
  149. break;
  150. case MMC_RSP_R1B:
  151. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  152. case MMC_RSP_R1:
  153. rc |= TIFM_MMCSD_RSP_R1;
  154. break;
  155. case MMC_RSP_R2:
  156. rc |= TIFM_MMCSD_RSP_R2;
  157. break;
  158. case MMC_RSP_R3:
  159. rc |= TIFM_MMCSD_RSP_R3;
  160. break;
  161. default:
  162. BUG();
  163. }
  164. switch (mmc_cmd_type(cmd)) {
  165. case MMC_CMD_BC:
  166. rc |= TIFM_MMCSD_CMD_BC;
  167. break;
  168. case MMC_CMD_BCR:
  169. rc |= TIFM_MMCSD_CMD_BCR;
  170. break;
  171. case MMC_CMD_AC:
  172. rc |= TIFM_MMCSD_CMD_AC;
  173. break;
  174. case MMC_CMD_ADTC:
  175. rc |= TIFM_MMCSD_CMD_ADTC;
  176. break;
  177. default:
  178. BUG();
  179. }
  180. return rc;
  181. }
  182. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  183. {
  184. struct tifm_dev *sock = host->dev;
  185. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  186. (host->flags & OPENDRAIN);
  187. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  188. cmd_mask |= TIFM_MMCSD_READ;
  189. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  190. cmd->opcode, cmd->arg, cmd_mask);
  191. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  192. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  193. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  194. }
  195. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  196. {
  197. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  198. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  199. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  200. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  201. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  202. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  203. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  204. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  205. }
  206. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  207. unsigned int host_status)
  208. {
  209. struct mmc_command *cmd = host->req->cmd;
  210. change_state:
  211. switch (host->state) {
  212. case IDLE:
  213. return;
  214. case CMD:
  215. if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
  216. tifm_sd_fetch_resp(cmd, sock);
  217. if (cmd->data) {
  218. host->state = BRS;
  219. } else {
  220. host->state = READY;
  221. }
  222. goto change_state;
  223. }
  224. break;
  225. case BRS:
  226. if (tifm_sd_transfer_data(sock, host, host_status)) {
  227. if (cmd->data->flags & MMC_DATA_WRITE) {
  228. host->state = CARD;
  229. } else {
  230. if (no_dma) {
  231. if (host->req->stop) {
  232. tifm_sd_exec(host, host->req->stop);
  233. host->state = SCMD;
  234. } else {
  235. host->state = READY;
  236. }
  237. } else {
  238. host->state = FIFO;
  239. }
  240. }
  241. goto change_state;
  242. }
  243. break;
  244. case SCMD:
  245. if (host_status & TIFM_MMCSD_EOC) {
  246. tifm_sd_fetch_resp(host->req->stop, sock);
  247. host->state = READY;
  248. goto change_state;
  249. }
  250. break;
  251. case CARD:
  252. dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
  253. host->written_blocks);
  254. if (!(host->flags & CARD_BUSY)
  255. && (host->written_blocks == cmd->data->blocks)) {
  256. if (no_dma) {
  257. if (host->req->stop) {
  258. tifm_sd_exec(host, host->req->stop);
  259. host->state = SCMD;
  260. } else {
  261. host->state = READY;
  262. }
  263. } else {
  264. host->state = FIFO;
  265. }
  266. goto change_state;
  267. }
  268. break;
  269. case FIFO:
  270. if (host->flags & FIFO_RDY) {
  271. host->flags &= ~FIFO_RDY;
  272. if (host->req->stop) {
  273. tifm_sd_exec(host, host->req->stop);
  274. host->state = SCMD;
  275. } else {
  276. host->state = READY;
  277. }
  278. goto change_state;
  279. }
  280. break;
  281. case READY:
  282. tasklet_schedule(&host->finish_tasklet);
  283. return;
  284. }
  285. }
  286. /* Called from interrupt handler */
  287. static void tifm_sd_data_event(struct tifm_dev *sock)
  288. {
  289. struct tifm_sd *host;
  290. unsigned int fifo_status = 0;
  291. spin_lock(&sock->lock);
  292. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  293. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  294. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  295. host->flags |= fifo_status & FIFO_RDY;
  296. if (host->req)
  297. tifm_sd_process_cmd(sock, host, 0);
  298. dev_dbg(&sock->dev, "fifo_status %x\n", fifo_status);
  299. spin_unlock(&sock->lock);
  300. }
  301. /* Called from interrupt handler */
  302. static void tifm_sd_card_event(struct tifm_dev *sock)
  303. {
  304. struct tifm_sd *host;
  305. unsigned int host_status = 0;
  306. int error_code = 0;
  307. spin_lock(&sock->lock);
  308. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  309. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  310. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  311. if (!host->req)
  312. goto done;
  313. if (host_status & TIFM_MMCSD_ERRMASK) {
  314. if (host_status & (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  315. error_code = MMC_ERR_TIMEOUT;
  316. else if (host_status
  317. & (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  318. error_code = MMC_ERR_BADCRC;
  319. writel(TIFM_FIFO_INT_SETALL,
  320. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  321. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  322. if (host->req->stop) {
  323. if (host->state == SCMD) {
  324. host->req->stop->error = error_code;
  325. } else if (host->state == BRS
  326. || host->state == CARD
  327. || host->state == FIFO) {
  328. host->req->cmd->error = error_code;
  329. tifm_sd_exec(host, host->req->stop);
  330. host->state = SCMD;
  331. goto done;
  332. } else {
  333. host->req->cmd->error = error_code;
  334. }
  335. } else {
  336. host->req->cmd->error = error_code;
  337. }
  338. host->state = READY;
  339. }
  340. if (host_status & TIFM_MMCSD_CB)
  341. host->flags |= CARD_BUSY;
  342. if ((host_status & TIFM_MMCSD_EOFB)
  343. && (host->flags & CARD_BUSY)) {
  344. host->written_blocks++;
  345. host->flags &= ~CARD_BUSY;
  346. }
  347. if (host->req)
  348. tifm_sd_process_cmd(sock, host, host_status);
  349. done:
  350. dev_dbg(&sock->dev, "host_status %x\n", host_status);
  351. spin_unlock(&sock->lock);
  352. }
  353. static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
  354. {
  355. struct tifm_dev *sock = host->dev;
  356. unsigned int dest_cnt;
  357. /* DMA style IO */
  358. dev_dbg(&sock->dev, "setting dma for %d blocks\n",
  359. cmd->data->blocks);
  360. writel(TIFM_FIFO_INT_SETALL,
  361. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  362. writel(ilog2(cmd->data->blksz) - 2,
  363. sock->addr + SOCK_FIFO_PAGE_SIZE);
  364. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  365. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  366. dest_cnt = (cmd->data->blocks) << 8;
  367. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  368. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  369. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  370. if (cmd->data->flags & MMC_DATA_WRITE) {
  371. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  372. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  373. sock->addr + SOCK_DMA_CONTROL);
  374. } else {
  375. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  376. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  377. }
  378. }
  379. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  380. struct mmc_data *data)
  381. {
  382. struct tifm_dev *sock = host->dev;
  383. unsigned int data_timeout = data->timeout_clks;
  384. if (fixed_timeout)
  385. return;
  386. data_timeout += data->timeout_ns /
  387. ((1000000000UL / host->clk_freq) * host->clk_div);
  388. if (data_timeout < 0xffff) {
  389. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  390. writel((~TIFM_MMCSD_DPE)
  391. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  392. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  393. } else {
  394. data_timeout = (data_timeout >> 10) + 1;
  395. if (data_timeout > 0xffff)
  396. data_timeout = 0; /* set to unlimited */
  397. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  398. writel(TIFM_MMCSD_DPE
  399. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  400. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  401. }
  402. }
  403. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  404. {
  405. struct tifm_sd *host = mmc_priv(mmc);
  406. struct tifm_dev *sock = host->dev;
  407. unsigned long flags;
  408. int sg_count = 0;
  409. struct mmc_data *r_data = mrq->cmd->data;
  410. spin_lock_irqsave(&sock->lock, flags);
  411. if (host->flags & EJECT) {
  412. spin_unlock_irqrestore(&sock->lock, flags);
  413. goto err_out;
  414. }
  415. if (host->req) {
  416. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  417. spin_unlock_irqrestore(&sock->lock, flags);
  418. goto err_out;
  419. }
  420. if (r_data) {
  421. tifm_sd_set_data_timeout(host, r_data);
  422. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  423. mrq->cmd->flags & MMC_DATA_WRITE
  424. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  425. if (sg_count != 1) {
  426. printk(KERN_ERR DRIVER_NAME
  427. ": scatterlist map failed\n");
  428. spin_unlock_irqrestore(&sock->lock, flags);
  429. goto err_out;
  430. }
  431. host->written_blocks = 0;
  432. host->flags &= ~CARD_BUSY;
  433. tifm_sd_prepare_data(host, mrq->cmd);
  434. }
  435. host->req = mrq;
  436. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  437. host->state = CMD;
  438. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  439. sock->addr + SOCK_CONTROL);
  440. tifm_sd_exec(host, mrq->cmd);
  441. spin_unlock_irqrestore(&sock->lock, flags);
  442. return;
  443. err_out:
  444. if (sg_count > 0)
  445. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  446. (r_data->flags & MMC_DATA_WRITE)
  447. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  448. mrq->cmd->error = MMC_ERR_TIMEOUT;
  449. mmc_request_done(mmc, mrq);
  450. }
  451. static void tifm_sd_end_cmd(unsigned long data)
  452. {
  453. struct tifm_sd *host = (struct tifm_sd*)data;
  454. struct tifm_dev *sock = host->dev;
  455. struct mmc_host *mmc = tifm_get_drvdata(sock);
  456. struct mmc_request *mrq;
  457. struct mmc_data *r_data = NULL;
  458. unsigned long flags;
  459. spin_lock_irqsave(&sock->lock, flags);
  460. del_timer(&host->timer);
  461. mrq = host->req;
  462. host->req = NULL;
  463. host->state = IDLE;
  464. if (!mrq) {
  465. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  466. spin_unlock_irqrestore(&sock->lock, flags);
  467. return;
  468. }
  469. r_data = mrq->cmd->data;
  470. if (r_data) {
  471. if (r_data->flags & MMC_DATA_WRITE) {
  472. r_data->bytes_xfered = host->written_blocks
  473. * r_data->blksz;
  474. } else {
  475. r_data->bytes_xfered = r_data->blocks -
  476. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  477. r_data->bytes_xfered *= r_data->blksz;
  478. r_data->bytes_xfered += r_data->blksz -
  479. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  480. }
  481. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  482. (r_data->flags & MMC_DATA_WRITE)
  483. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  484. }
  485. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  486. sock->addr + SOCK_CONTROL);
  487. spin_unlock_irqrestore(&sock->lock, flags);
  488. mmc_request_done(mmc, mrq);
  489. }
  490. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  491. {
  492. struct tifm_sd *host = mmc_priv(mmc);
  493. struct tifm_dev *sock = host->dev;
  494. unsigned long flags;
  495. struct mmc_data *r_data = mrq->cmd->data;
  496. spin_lock_irqsave(&sock->lock, flags);
  497. if (host->flags & EJECT) {
  498. spin_unlock_irqrestore(&sock->lock, flags);
  499. goto err_out;
  500. }
  501. if (host->req) {
  502. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  503. spin_unlock_irqrestore(&sock->lock, flags);
  504. goto err_out;
  505. }
  506. if (r_data) {
  507. tifm_sd_set_data_timeout(host, r_data);
  508. host->buffer_size = mrq->cmd->data->blocks
  509. * mrq->cmd->data->blksz;
  510. writel(TIFM_MMCSD_BUFINT
  511. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  512. sock->addr + SOCK_MMCSD_INT_ENABLE);
  513. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  514. | (TIFM_MMCSD_FIFO_SIZE - 1),
  515. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  516. host->written_blocks = 0;
  517. host->flags &= ~CARD_BUSY;
  518. host->buffer_pos = 0;
  519. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  520. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  521. }
  522. host->req = mrq;
  523. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  524. host->state = CMD;
  525. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  526. sock->addr + SOCK_CONTROL);
  527. tifm_sd_exec(host, mrq->cmd);
  528. spin_unlock_irqrestore(&sock->lock, flags);
  529. return;
  530. err_out:
  531. mrq->cmd->error = MMC_ERR_TIMEOUT;
  532. mmc_request_done(mmc, mrq);
  533. }
  534. static void tifm_sd_end_cmd_nodma(unsigned long data)
  535. {
  536. struct tifm_sd *host = (struct tifm_sd*)data;
  537. struct tifm_dev *sock = host->dev;
  538. struct mmc_host *mmc = tifm_get_drvdata(sock);
  539. struct mmc_request *mrq;
  540. struct mmc_data *r_data = NULL;
  541. unsigned long flags;
  542. spin_lock_irqsave(&sock->lock, flags);
  543. del_timer(&host->timer);
  544. mrq = host->req;
  545. host->req = NULL;
  546. host->state = IDLE;
  547. if (!mrq) {
  548. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  549. spin_unlock_irqrestore(&sock->lock, flags);
  550. return;
  551. }
  552. r_data = mrq->cmd->data;
  553. if (r_data) {
  554. writel((~TIFM_MMCSD_BUFINT) &
  555. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  556. sock->addr + SOCK_MMCSD_INT_ENABLE);
  557. if (r_data->flags & MMC_DATA_WRITE) {
  558. r_data->bytes_xfered = host->written_blocks
  559. * r_data->blksz;
  560. } else {
  561. r_data->bytes_xfered = r_data->blocks -
  562. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  563. r_data->bytes_xfered *= r_data->blksz;
  564. r_data->bytes_xfered += r_data->blksz -
  565. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  566. }
  567. host->buffer_pos = 0;
  568. host->buffer_size = 0;
  569. }
  570. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  571. sock->addr + SOCK_CONTROL);
  572. spin_unlock_irqrestore(&sock->lock, flags);
  573. mmc_request_done(mmc, mrq);
  574. }
  575. static void tifm_sd_terminate(struct tifm_sd *host)
  576. {
  577. struct tifm_dev *sock = host->dev;
  578. unsigned long flags;
  579. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  580. mmiowb();
  581. spin_lock_irqsave(&sock->lock, flags);
  582. host->flags |= EJECT;
  583. if (host->req) {
  584. writel(TIFM_FIFO_INT_SETALL,
  585. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  586. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  587. tasklet_schedule(&host->finish_tasklet);
  588. }
  589. spin_unlock_irqrestore(&sock->lock, flags);
  590. }
  591. static void tifm_sd_abort(unsigned long data)
  592. {
  593. struct tifm_sd *host = (struct tifm_sd*)data;
  594. printk(KERN_ERR DRIVER_NAME
  595. ": card failed to respond for a long period of time");
  596. tifm_sd_terminate(host);
  597. tifm_eject(host->dev);
  598. }
  599. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  600. {
  601. struct tifm_sd *host = mmc_priv(mmc);
  602. struct tifm_dev *sock = host->dev;
  603. unsigned int clk_div1, clk_div2;
  604. unsigned long flags;
  605. spin_lock_irqsave(&sock->lock, flags);
  606. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  607. ios->power_mode);
  608. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  609. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  610. sock->addr + SOCK_MMCSD_CONFIG);
  611. } else {
  612. writel((~TIFM_MMCSD_4BBUS)
  613. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  614. sock->addr + SOCK_MMCSD_CONFIG);
  615. }
  616. if (ios->clock) {
  617. clk_div1 = 20000000 / ios->clock;
  618. if (!clk_div1)
  619. clk_div1 = 1;
  620. clk_div2 = 24000000 / ios->clock;
  621. if (!clk_div2)
  622. clk_div2 = 1;
  623. if ((20000000 / clk_div1) > ios->clock)
  624. clk_div1++;
  625. if ((24000000 / clk_div2) > ios->clock)
  626. clk_div2++;
  627. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  628. host->clk_freq = 20000000;
  629. host->clk_div = clk_div1;
  630. writel((~TIFM_CTRL_FAST_CLK)
  631. & readl(sock->addr + SOCK_CONTROL),
  632. sock->addr + SOCK_CONTROL);
  633. } else {
  634. host->clk_freq = 24000000;
  635. host->clk_div = clk_div2;
  636. writel(TIFM_CTRL_FAST_CLK
  637. | readl(sock->addr + SOCK_CONTROL),
  638. sock->addr + SOCK_CONTROL);
  639. }
  640. } else {
  641. host->clk_div = 0;
  642. }
  643. host->clk_div &= TIFM_MMCSD_CLKMASK;
  644. writel(host->clk_div
  645. | ((~TIFM_MMCSD_CLKMASK)
  646. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  647. sock->addr + SOCK_MMCSD_CONFIG);
  648. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  649. host->flags |= OPENDRAIN;
  650. else
  651. host->flags &= ~OPENDRAIN;
  652. /* chip_select : maybe later */
  653. //vdd
  654. //power is set before probe / after remove
  655. //I believe, power_off when already marked for eject is sufficient to
  656. // allow removal.
  657. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  658. host->flags |= EJECT_DONE;
  659. wake_up_all(&host->notify);
  660. }
  661. spin_unlock_irqrestore(&sock->lock, flags);
  662. }
  663. static int tifm_sd_ro(struct mmc_host *mmc)
  664. {
  665. int rc;
  666. struct tifm_sd *host = mmc_priv(mmc);
  667. struct tifm_dev *sock = host->dev;
  668. unsigned long flags;
  669. spin_lock_irqsave(&sock->lock, flags);
  670. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  671. rc = (host->flags & CARD_RO) ? 1 : 0;
  672. spin_unlock_irqrestore(&sock->lock, flags);
  673. return rc;
  674. }
  675. static struct mmc_host_ops tifm_sd_ops = {
  676. .request = tifm_sd_request,
  677. .set_ios = tifm_sd_ios,
  678. .get_ro = tifm_sd_ro
  679. };
  680. static int tifm_sd_initialize_host(struct tifm_sd *host)
  681. {
  682. int rc;
  683. unsigned int host_status = 0;
  684. struct tifm_dev *sock = host->dev;
  685. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  686. mmiowb();
  687. host->clk_div = 61;
  688. host->clk_freq = 20000000;
  689. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  690. writel(host->clk_div | TIFM_MMCSD_POWER,
  691. sock->addr + SOCK_MMCSD_CONFIG);
  692. /* wait up to 0.51 sec for reset */
  693. for (rc = 2; rc <= 256; rc <<= 1) {
  694. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  695. rc = 0;
  696. break;
  697. }
  698. msleep(rc);
  699. }
  700. if (rc) {
  701. printk(KERN_ERR DRIVER_NAME
  702. ": controller failed to reset\n");
  703. return -ENODEV;
  704. }
  705. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  706. writel(host->clk_div | TIFM_MMCSD_POWER,
  707. sock->addr + SOCK_MMCSD_CONFIG);
  708. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  709. // command timeout fixed to 64 clocks for now
  710. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  711. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  712. /* INAB should take much less than reset */
  713. for (rc = 1; rc <= 16; rc <<= 1) {
  714. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  715. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  716. if (!(host_status & TIFM_MMCSD_ERRMASK)
  717. && (host_status & TIFM_MMCSD_EOC)) {
  718. rc = 0;
  719. break;
  720. }
  721. msleep(rc);
  722. }
  723. if (rc) {
  724. printk(KERN_ERR DRIVER_NAME
  725. ": card not ready - probe failed on initialization\n");
  726. return -ENODEV;
  727. }
  728. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  729. sock->addr + SOCK_MMCSD_INT_ENABLE);
  730. mmiowb();
  731. return 0;
  732. }
  733. static int tifm_sd_probe(struct tifm_dev *sock)
  734. {
  735. struct mmc_host *mmc;
  736. struct tifm_sd *host;
  737. int rc = -EIO;
  738. if (!(TIFM_SOCK_STATE_OCCUPIED
  739. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  740. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  741. return rc;
  742. }
  743. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  744. if (!mmc)
  745. return -ENOMEM;
  746. host = mmc_priv(mmc);
  747. tifm_set_drvdata(sock, mmc);
  748. host->dev = sock;
  749. host->timeout_jiffies = msecs_to_jiffies(1000);
  750. init_waitqueue_head(&host->notify);
  751. tasklet_init(&host->finish_tasklet,
  752. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
  753. (unsigned long)host);
  754. setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
  755. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  756. mmc->ops = &tifm_sd_ops;
  757. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  758. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
  759. mmc->f_min = 20000000 / 60;
  760. mmc->f_max = 24000000;
  761. mmc->max_hw_segs = 1;
  762. mmc->max_phys_segs = 1;
  763. // limited by DMA counter - it's safer to stick with
  764. // block counter has 11 bits though
  765. mmc->max_blk_count = 256;
  766. // 2k maximum hw block length
  767. mmc->max_blk_size = 2048;
  768. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  769. mmc->max_seg_size = mmc->max_req_size;
  770. sock->card_event = tifm_sd_card_event;
  771. sock->data_event = tifm_sd_data_event;
  772. rc = tifm_sd_initialize_host(host);
  773. if (!rc)
  774. rc = mmc_add_host(mmc);
  775. if (rc)
  776. goto out_free_mmc;
  777. return 0;
  778. out_free_mmc:
  779. mmc_free_host(mmc);
  780. return rc;
  781. }
  782. static void tifm_sd_remove(struct tifm_dev *sock)
  783. {
  784. struct mmc_host *mmc = tifm_get_drvdata(sock);
  785. struct tifm_sd *host = mmc_priv(mmc);
  786. del_timer_sync(&host->timer);
  787. tifm_sd_terminate(host);
  788. wait_event_timeout(host->notify, host->flags & EJECT_DONE,
  789. host->timeout_jiffies);
  790. tasklet_kill(&host->finish_tasklet);
  791. mmc_remove_host(mmc);
  792. /* The meaning of the bit majority in this constant is unknown. */
  793. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  794. sock->addr + SOCK_CONTROL);
  795. tifm_set_drvdata(sock, NULL);
  796. mmc_free_host(mmc);
  797. }
  798. #ifdef CONFIG_PM
  799. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  800. {
  801. struct mmc_host *mmc = tifm_get_drvdata(sock);
  802. int rc;
  803. rc = mmc_suspend_host(mmc, state);
  804. /* The meaning of the bit majority in this constant is unknown. */
  805. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  806. sock->addr + SOCK_CONTROL);
  807. return rc;
  808. }
  809. static int tifm_sd_resume(struct tifm_dev *sock)
  810. {
  811. struct mmc_host *mmc = tifm_get_drvdata(sock);
  812. struct tifm_sd *host = mmc_priv(mmc);
  813. if (sock->type != TIFM_TYPE_SD
  814. || tifm_sd_initialize_host(host)) {
  815. tifm_eject(sock);
  816. return 0;
  817. } else {
  818. return mmc_resume_host(mmc);
  819. }
  820. }
  821. #else
  822. #define tifm_sd_suspend NULL
  823. #define tifm_sd_resume NULL
  824. #endif /* CONFIG_PM */
  825. static struct tifm_device_id tifm_sd_id_tbl[] = {
  826. { TIFM_TYPE_SD }, { }
  827. };
  828. static struct tifm_driver tifm_sd_driver = {
  829. .driver = {
  830. .name = DRIVER_NAME,
  831. .owner = THIS_MODULE
  832. },
  833. .id_table = tifm_sd_id_tbl,
  834. .probe = tifm_sd_probe,
  835. .remove = tifm_sd_remove,
  836. .suspend = tifm_sd_suspend,
  837. .resume = tifm_sd_resume
  838. };
  839. static int __init tifm_sd_init(void)
  840. {
  841. return tifm_register_driver(&tifm_sd_driver);
  842. }
  843. static void __exit tifm_sd_exit(void)
  844. {
  845. tifm_unregister_driver(&tifm_sd_driver);
  846. }
  847. MODULE_AUTHOR("Alex Dubov");
  848. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  849. MODULE_LICENSE("GPL");
  850. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  851. MODULE_VERSION(DRIVER_VERSION);
  852. module_init(tifm_sd_init);
  853. module_exit(tifm_sd_exit);