icm.c 11 KB

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  1. /*
  2. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  3. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/errno.h>
  34. #include <linux/mm.h>
  35. #include <linux/scatterlist.h>
  36. #include <linux/slab.h>
  37. #include <linux/mlx4/cmd.h>
  38. #include "mlx4.h"
  39. #include "icm.h"
  40. #include "fw.h"
  41. /*
  42. * We allocate in as big chunks as we can, up to a maximum of 256 KB
  43. * per chunk.
  44. */
  45. enum {
  46. MLX4_ICM_ALLOC_SIZE = 1 << 18,
  47. MLX4_TABLE_CHUNK_SIZE = 1 << 18
  48. };
  49. static void mlx4_free_icm_pages(struct mlx4_dev *dev, struct mlx4_icm_chunk *chunk)
  50. {
  51. int i;
  52. if (chunk->nsg > 0)
  53. pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
  54. PCI_DMA_BIDIRECTIONAL);
  55. for (i = 0; i < chunk->npages; ++i)
  56. __free_pages(sg_page(&chunk->mem[i]),
  57. get_order(chunk->mem[i].length));
  58. }
  59. static void mlx4_free_icm_coherent(struct mlx4_dev *dev, struct mlx4_icm_chunk *chunk)
  60. {
  61. int i;
  62. for (i = 0; i < chunk->npages; ++i)
  63. dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
  64. lowmem_page_address(sg_page(&chunk->mem[i])),
  65. sg_dma_address(&chunk->mem[i]));
  66. }
  67. void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent)
  68. {
  69. struct mlx4_icm_chunk *chunk, *tmp;
  70. if (!icm)
  71. return;
  72. list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
  73. if (coherent)
  74. mlx4_free_icm_coherent(dev, chunk);
  75. else
  76. mlx4_free_icm_pages(dev, chunk);
  77. kfree(chunk);
  78. }
  79. kfree(icm);
  80. }
  81. static int mlx4_alloc_icm_pages(struct scatterlist *mem, int order,
  82. gfp_t gfp_mask, int node)
  83. {
  84. struct page *page;
  85. page = alloc_pages_node(node, gfp_mask, order);
  86. if (!page) {
  87. page = alloc_pages(gfp_mask, order);
  88. if (!page)
  89. return -ENOMEM;
  90. }
  91. sg_set_page(mem, page, PAGE_SIZE << order, 0);
  92. return 0;
  93. }
  94. static int mlx4_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
  95. int order, gfp_t gfp_mask)
  96. {
  97. void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order,
  98. &sg_dma_address(mem), gfp_mask);
  99. if (!buf)
  100. return -ENOMEM;
  101. sg_set_buf(mem, buf, PAGE_SIZE << order);
  102. BUG_ON(mem->offset);
  103. sg_dma_len(mem) = PAGE_SIZE << order;
  104. return 0;
  105. }
  106. struct mlx4_icm *mlx4_alloc_icm(struct mlx4_dev *dev, int npages,
  107. gfp_t gfp_mask, int coherent)
  108. {
  109. struct mlx4_icm *icm;
  110. struct mlx4_icm_chunk *chunk = NULL;
  111. int cur_order;
  112. int ret;
  113. /* We use sg_set_buf for coherent allocs, which assumes low memory */
  114. BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
  115. icm = kmalloc_node(sizeof(*icm),
  116. gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN),
  117. dev->numa_node);
  118. if (!icm) {
  119. icm = kmalloc(sizeof(*icm),
  120. gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  121. if (!icm)
  122. return NULL;
  123. }
  124. icm->refcount = 0;
  125. INIT_LIST_HEAD(&icm->chunk_list);
  126. cur_order = get_order(MLX4_ICM_ALLOC_SIZE);
  127. while (npages > 0) {
  128. if (!chunk) {
  129. chunk = kmalloc_node(sizeof(*chunk),
  130. gfp_mask & ~(__GFP_HIGHMEM |
  131. __GFP_NOWARN),
  132. dev->numa_node);
  133. if (!chunk) {
  134. chunk = kmalloc(sizeof(*chunk),
  135. gfp_mask & ~(__GFP_HIGHMEM |
  136. __GFP_NOWARN));
  137. if (!chunk)
  138. goto fail;
  139. }
  140. sg_init_table(chunk->mem, MLX4_ICM_CHUNK_LEN);
  141. chunk->npages = 0;
  142. chunk->nsg = 0;
  143. list_add_tail(&chunk->list, &icm->chunk_list);
  144. }
  145. while (1 << cur_order > npages)
  146. --cur_order;
  147. if (coherent)
  148. ret = mlx4_alloc_icm_coherent(&dev->pdev->dev,
  149. &chunk->mem[chunk->npages],
  150. cur_order, gfp_mask);
  151. else
  152. ret = mlx4_alloc_icm_pages(&chunk->mem[chunk->npages],
  153. cur_order, gfp_mask,
  154. dev->numa_node);
  155. if (ret) {
  156. if (--cur_order < 0)
  157. goto fail;
  158. else
  159. continue;
  160. }
  161. ++chunk->npages;
  162. if (coherent)
  163. ++chunk->nsg;
  164. else if (chunk->npages == MLX4_ICM_CHUNK_LEN) {
  165. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  166. chunk->npages,
  167. PCI_DMA_BIDIRECTIONAL);
  168. if (chunk->nsg <= 0)
  169. goto fail;
  170. }
  171. if (chunk->npages == MLX4_ICM_CHUNK_LEN)
  172. chunk = NULL;
  173. npages -= 1 << cur_order;
  174. }
  175. if (!coherent && chunk) {
  176. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  177. chunk->npages,
  178. PCI_DMA_BIDIRECTIONAL);
  179. if (chunk->nsg <= 0)
  180. goto fail;
  181. }
  182. return icm;
  183. fail:
  184. mlx4_free_icm(dev, icm, coherent);
  185. return NULL;
  186. }
  187. static int mlx4_MAP_ICM(struct mlx4_dev *dev, struct mlx4_icm *icm, u64 virt)
  188. {
  189. return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM, icm, virt);
  190. }
  191. static int mlx4_UNMAP_ICM(struct mlx4_dev *dev, u64 virt, u32 page_count)
  192. {
  193. return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM,
  194. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  195. }
  196. int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm)
  197. {
  198. return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM_AUX, icm, -1);
  199. }
  200. int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev)
  201. {
  202. return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX,
  203. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  204. }
  205. int mlx4_table_get(struct mlx4_dev *dev, struct mlx4_icm_table *table, u32 obj)
  206. {
  207. u32 i = (obj & (table->num_obj - 1)) /
  208. (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
  209. int ret = 0;
  210. mutex_lock(&table->mutex);
  211. if (table->icm[i]) {
  212. ++table->icm[i]->refcount;
  213. goto out;
  214. }
  215. table->icm[i] = mlx4_alloc_icm(dev, MLX4_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
  216. (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  217. __GFP_NOWARN, table->coherent);
  218. if (!table->icm[i]) {
  219. ret = -ENOMEM;
  220. goto out;
  221. }
  222. if (mlx4_MAP_ICM(dev, table->icm[i], table->virt +
  223. (u64) i * MLX4_TABLE_CHUNK_SIZE)) {
  224. mlx4_free_icm(dev, table->icm[i], table->coherent);
  225. table->icm[i] = NULL;
  226. ret = -ENOMEM;
  227. goto out;
  228. }
  229. ++table->icm[i]->refcount;
  230. out:
  231. mutex_unlock(&table->mutex);
  232. return ret;
  233. }
  234. void mlx4_table_put(struct mlx4_dev *dev, struct mlx4_icm_table *table, u32 obj)
  235. {
  236. u32 i;
  237. u64 offset;
  238. i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
  239. mutex_lock(&table->mutex);
  240. if (--table->icm[i]->refcount == 0) {
  241. offset = (u64) i * MLX4_TABLE_CHUNK_SIZE;
  242. mlx4_UNMAP_ICM(dev, table->virt + offset,
  243. MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
  244. mlx4_free_icm(dev, table->icm[i], table->coherent);
  245. table->icm[i] = NULL;
  246. }
  247. mutex_unlock(&table->mutex);
  248. }
  249. void *mlx4_table_find(struct mlx4_icm_table *table, u32 obj,
  250. dma_addr_t *dma_handle)
  251. {
  252. int offset, dma_offset, i;
  253. u64 idx;
  254. struct mlx4_icm_chunk *chunk;
  255. struct mlx4_icm *icm;
  256. struct page *page = NULL;
  257. if (!table->lowmem)
  258. return NULL;
  259. mutex_lock(&table->mutex);
  260. idx = (u64) (obj & (table->num_obj - 1)) * table->obj_size;
  261. icm = table->icm[idx / MLX4_TABLE_CHUNK_SIZE];
  262. dma_offset = offset = idx % MLX4_TABLE_CHUNK_SIZE;
  263. if (!icm)
  264. goto out;
  265. list_for_each_entry(chunk, &icm->chunk_list, list) {
  266. for (i = 0; i < chunk->npages; ++i) {
  267. if (dma_handle && dma_offset >= 0) {
  268. if (sg_dma_len(&chunk->mem[i]) > dma_offset)
  269. *dma_handle = sg_dma_address(&chunk->mem[i]) +
  270. dma_offset;
  271. dma_offset -= sg_dma_len(&chunk->mem[i]);
  272. }
  273. /*
  274. * DMA mapping can merge pages but not split them,
  275. * so if we found the page, dma_handle has already
  276. * been assigned to.
  277. */
  278. if (chunk->mem[i].length > offset) {
  279. page = sg_page(&chunk->mem[i]);
  280. goto out;
  281. }
  282. offset -= chunk->mem[i].length;
  283. }
  284. }
  285. out:
  286. mutex_unlock(&table->mutex);
  287. return page ? lowmem_page_address(page) + offset : NULL;
  288. }
  289. int mlx4_table_get_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
  290. u32 start, u32 end)
  291. {
  292. int inc = MLX4_TABLE_CHUNK_SIZE / table->obj_size;
  293. int err;
  294. u32 i;
  295. for (i = start; i <= end; i += inc) {
  296. err = mlx4_table_get(dev, table, i);
  297. if (err)
  298. goto fail;
  299. }
  300. return 0;
  301. fail:
  302. while (i > start) {
  303. i -= inc;
  304. mlx4_table_put(dev, table, i);
  305. }
  306. return err;
  307. }
  308. void mlx4_table_put_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
  309. u32 start, u32 end)
  310. {
  311. u32 i;
  312. for (i = start; i <= end; i += MLX4_TABLE_CHUNK_SIZE / table->obj_size)
  313. mlx4_table_put(dev, table, i);
  314. }
  315. int mlx4_init_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table,
  316. u64 virt, int obj_size, u32 nobj, int reserved,
  317. int use_lowmem, int use_coherent)
  318. {
  319. int obj_per_chunk;
  320. int num_icm;
  321. unsigned chunk_size;
  322. int i;
  323. u64 size;
  324. obj_per_chunk = MLX4_TABLE_CHUNK_SIZE / obj_size;
  325. num_icm = (nobj + obj_per_chunk - 1) / obj_per_chunk;
  326. table->icm = kcalloc(num_icm, sizeof *table->icm, GFP_KERNEL);
  327. if (!table->icm)
  328. return -ENOMEM;
  329. table->virt = virt;
  330. table->num_icm = num_icm;
  331. table->num_obj = nobj;
  332. table->obj_size = obj_size;
  333. table->lowmem = use_lowmem;
  334. table->coherent = use_coherent;
  335. mutex_init(&table->mutex);
  336. size = (u64) nobj * obj_size;
  337. for (i = 0; i * MLX4_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
  338. chunk_size = MLX4_TABLE_CHUNK_SIZE;
  339. if ((i + 1) * MLX4_TABLE_CHUNK_SIZE > size)
  340. chunk_size = PAGE_ALIGN(size -
  341. i * MLX4_TABLE_CHUNK_SIZE);
  342. table->icm[i] = mlx4_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
  343. (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  344. __GFP_NOWARN, use_coherent);
  345. if (!table->icm[i])
  346. goto err;
  347. if (mlx4_MAP_ICM(dev, table->icm[i], virt + i * MLX4_TABLE_CHUNK_SIZE)) {
  348. mlx4_free_icm(dev, table->icm[i], use_coherent);
  349. table->icm[i] = NULL;
  350. goto err;
  351. }
  352. /*
  353. * Add a reference to this ICM chunk so that it never
  354. * gets freed (since it contains reserved firmware objects).
  355. */
  356. ++table->icm[i]->refcount;
  357. }
  358. return 0;
  359. err:
  360. for (i = 0; i < num_icm; ++i)
  361. if (table->icm[i]) {
  362. mlx4_UNMAP_ICM(dev, virt + i * MLX4_TABLE_CHUNK_SIZE,
  363. MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
  364. mlx4_free_icm(dev, table->icm[i], use_coherent);
  365. }
  366. kfree(table->icm);
  367. return -ENOMEM;
  368. }
  369. void mlx4_cleanup_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table)
  370. {
  371. int i;
  372. for (i = 0; i < table->num_icm; ++i)
  373. if (table->icm[i]) {
  374. mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
  375. MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
  376. mlx4_free_icm(dev, table->icm[i], table->coherent);
  377. }
  378. kfree(table->icm);
  379. }