spear-cpufreq.c 6.6 KB

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  1. /*
  2. * drivers/cpufreq/spear-cpufreq.c
  3. *
  4. * CPU Frequency Scaling for SPEAr platform
  5. *
  6. * Copyright (C) 2012 ST Microelectronics
  7. * Deepak Sikri <deepak.sikri@st.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14. #include <linux/clk.h>
  15. #include <linux/cpufreq.h>
  16. #include <linux/err.h>
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/of_device.h>
  20. #include <linux/slab.h>
  21. #include <linux/types.h>
  22. /* SPEAr CPUFreq driver data structure */
  23. static struct {
  24. struct clk *clk;
  25. unsigned int transition_latency;
  26. struct cpufreq_frequency_table *freq_tbl;
  27. u32 cnt;
  28. } spear_cpufreq;
  29. static unsigned int spear_cpufreq_get(unsigned int cpu)
  30. {
  31. return clk_get_rate(spear_cpufreq.clk) / 1000;
  32. }
  33. static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq)
  34. {
  35. struct clk *sys_pclk;
  36. int pclk;
  37. /*
  38. * In SPEAr1340, cpu clk's parent sys clk can take input from
  39. * following sources
  40. */
  41. const char *sys_clk_src[] = {
  42. "sys_syn_clk",
  43. "pll1_clk",
  44. "pll2_clk",
  45. "pll3_clk",
  46. };
  47. /*
  48. * As sys clk can have multiple source with their own range
  49. * limitation so we choose possible sources accordingly
  50. */
  51. if (newfreq <= 300000000)
  52. pclk = 0; /* src is sys_syn_clk */
  53. else if (newfreq > 300000000 && newfreq <= 500000000)
  54. pclk = 3; /* src is pll3_clk */
  55. else if (newfreq == 600000000)
  56. pclk = 1; /* src is pll1_clk */
  57. else
  58. return ERR_PTR(-EINVAL);
  59. /* Get parent to sys clock */
  60. sys_pclk = clk_get(NULL, sys_clk_src[pclk]);
  61. if (IS_ERR(sys_pclk))
  62. pr_err("Failed to get %s clock\n", sys_clk_src[pclk]);
  63. return sys_pclk;
  64. }
  65. /*
  66. * In SPEAr1340, we cannot use newfreq directly because we need to actually
  67. * access a source clock (clk) which might not be ancestor of cpu at present.
  68. * Hence in SPEAr1340 we would operate on source clock directly before switching
  69. * cpu clock to it.
  70. */
  71. static int spear1340_set_cpu_rate(struct clk *sys_pclk, unsigned long newfreq)
  72. {
  73. struct clk *sys_clk;
  74. int ret = 0;
  75. sys_clk = clk_get_parent(spear_cpufreq.clk);
  76. if (IS_ERR(sys_clk)) {
  77. pr_err("failed to get cpu's parent (sys) clock\n");
  78. return PTR_ERR(sys_clk);
  79. }
  80. /* Set the rate of the source clock before changing the parent */
  81. ret = clk_set_rate(sys_pclk, newfreq);
  82. if (ret) {
  83. pr_err("Failed to set sys clk rate to %lu\n", newfreq);
  84. return ret;
  85. }
  86. ret = clk_set_parent(sys_clk, sys_pclk);
  87. if (ret) {
  88. pr_err("Failed to set sys clk parent\n");
  89. return ret;
  90. }
  91. return 0;
  92. }
  93. static int spear_cpufreq_target(struct cpufreq_policy *policy,
  94. unsigned int target_freq, unsigned int relation)
  95. {
  96. struct cpufreq_freqs freqs;
  97. unsigned long newfreq;
  98. struct clk *srcclk;
  99. int index, ret, mult = 1;
  100. if (cpufreq_frequency_table_target(policy, spear_cpufreq.freq_tbl,
  101. target_freq, relation, &index))
  102. return -EINVAL;
  103. freqs.old = spear_cpufreq_get(0);
  104. newfreq = spear_cpufreq.freq_tbl[index].frequency * 1000;
  105. if (of_machine_is_compatible("st,spear1340")) {
  106. /*
  107. * SPEAr1340 is special in the sense that due to the possibility
  108. * of multiple clock sources for cpu clk's parent we can have
  109. * different clock source for different frequency of cpu clk.
  110. * Hence we need to choose one from amongst these possible clock
  111. * sources.
  112. */
  113. srcclk = spear1340_cpu_get_possible_parent(newfreq);
  114. if (IS_ERR(srcclk)) {
  115. pr_err("Failed to get src clk\n");
  116. return PTR_ERR(srcclk);
  117. }
  118. /* SPEAr1340: src clk is always 2 * intended cpu clk */
  119. mult = 2;
  120. } else {
  121. /*
  122. * src clock to be altered is ancestor of cpu clock. Hence we
  123. * can directly work on cpu clk
  124. */
  125. srcclk = spear_cpufreq.clk;
  126. }
  127. newfreq = clk_round_rate(srcclk, newfreq * mult);
  128. if (newfreq < 0) {
  129. pr_err("clk_round_rate failed for cpu src clock\n");
  130. return newfreq;
  131. }
  132. freqs.new = newfreq / 1000;
  133. freqs.new /= mult;
  134. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  135. if (mult == 2)
  136. ret = spear1340_set_cpu_rate(srcclk, newfreq);
  137. else
  138. ret = clk_set_rate(spear_cpufreq.clk, newfreq);
  139. /* Get current rate after clk_set_rate, in case of failure */
  140. if (ret) {
  141. pr_err("CPU Freq: cpu clk_set_rate failed: %d\n", ret);
  142. freqs.new = clk_get_rate(spear_cpufreq.clk) / 1000;
  143. }
  144. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  145. return ret;
  146. }
  147. static int spear_cpufreq_init(struct cpufreq_policy *policy)
  148. {
  149. int ret;
  150. ret = cpufreq_table_validate_and_show(policy, spear_cpufreq.freq_tbl);
  151. if (ret) {
  152. pr_err("cpufreq_table_validate_and_show() failed");
  153. return ret;
  154. }
  155. policy->cpuinfo.transition_latency = spear_cpufreq.transition_latency;
  156. policy->cur = spear_cpufreq_get(0);
  157. cpumask_setall(policy->cpus);
  158. return 0;
  159. }
  160. static struct cpufreq_driver spear_cpufreq_driver = {
  161. .name = "cpufreq-spear",
  162. .flags = CPUFREQ_STICKY,
  163. .verify = cpufreq_generic_frequency_table_verify,
  164. .target = spear_cpufreq_target,
  165. .get = spear_cpufreq_get,
  166. .init = spear_cpufreq_init,
  167. .exit = cpufreq_generic_exit,
  168. .attr = cpufreq_generic_attr,
  169. };
  170. static int spear_cpufreq_driver_init(void)
  171. {
  172. struct device_node *np;
  173. const struct property *prop;
  174. struct cpufreq_frequency_table *freq_tbl;
  175. const __be32 *val;
  176. int cnt, i, ret;
  177. np = of_cpu_device_node_get(0);
  178. if (!np) {
  179. pr_err("No cpu node found");
  180. return -ENODEV;
  181. }
  182. if (of_property_read_u32(np, "clock-latency",
  183. &spear_cpufreq.transition_latency))
  184. spear_cpufreq.transition_latency = CPUFREQ_ETERNAL;
  185. prop = of_find_property(np, "cpufreq_tbl", NULL);
  186. if (!prop || !prop->value) {
  187. pr_err("Invalid cpufreq_tbl");
  188. ret = -ENODEV;
  189. goto out_put_node;
  190. }
  191. cnt = prop->length / sizeof(u32);
  192. val = prop->value;
  193. freq_tbl = kmalloc(sizeof(*freq_tbl) * (cnt + 1), GFP_KERNEL);
  194. if (!freq_tbl) {
  195. ret = -ENOMEM;
  196. goto out_put_node;
  197. }
  198. for (i = 0; i < cnt; i++) {
  199. freq_tbl[i].driver_data = i;
  200. freq_tbl[i].frequency = be32_to_cpup(val++);
  201. }
  202. freq_tbl[i].driver_data = i;
  203. freq_tbl[i].frequency = CPUFREQ_TABLE_END;
  204. spear_cpufreq.freq_tbl = freq_tbl;
  205. of_node_put(np);
  206. spear_cpufreq.clk = clk_get(NULL, "cpu_clk");
  207. if (IS_ERR(spear_cpufreq.clk)) {
  208. pr_err("Unable to get CPU clock\n");
  209. ret = PTR_ERR(spear_cpufreq.clk);
  210. goto out_put_mem;
  211. }
  212. ret = cpufreq_register_driver(&spear_cpufreq_driver);
  213. if (!ret)
  214. return 0;
  215. pr_err("failed register driver: %d\n", ret);
  216. clk_put(spear_cpufreq.clk);
  217. out_put_mem:
  218. kfree(freq_tbl);
  219. return ret;
  220. out_put_node:
  221. of_node_put(np);
  222. return ret;
  223. }
  224. late_initcall(spear_cpufreq_driver_init);
  225. MODULE_AUTHOR("Deepak Sikri <deepak.sikri@st.com>");
  226. MODULE_DESCRIPTION("SPEAr CPUFreq driver");
  227. MODULE_LICENSE("GPL");