tilcdc_drv.c 16 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include "tilcdc_drv.h"
  19. #include "tilcdc_regs.h"
  20. #include "tilcdc_tfp410.h"
  21. #include "tilcdc_slave.h"
  22. #include "tilcdc_panel.h"
  23. #include "drm_fb_helper.h"
  24. static LIST_HEAD(module_list);
  25. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  26. const struct tilcdc_module_ops *funcs)
  27. {
  28. mod->name = name;
  29. mod->funcs = funcs;
  30. INIT_LIST_HEAD(&mod->list);
  31. list_add(&mod->list, &module_list);
  32. }
  33. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  34. {
  35. list_del(&mod->list);
  36. }
  37. static struct of_device_id tilcdc_of_match[];
  38. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  39. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  40. {
  41. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  42. }
  43. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  44. {
  45. struct tilcdc_drm_private *priv = dev->dev_private;
  46. if (priv->fbdev)
  47. drm_fbdev_cma_hotplug_event(priv->fbdev);
  48. }
  49. static const struct drm_mode_config_funcs mode_config_funcs = {
  50. .fb_create = tilcdc_fb_create,
  51. .output_poll_changed = tilcdc_fb_output_poll_changed,
  52. };
  53. static int modeset_init(struct drm_device *dev)
  54. {
  55. struct tilcdc_drm_private *priv = dev->dev_private;
  56. struct tilcdc_module *mod;
  57. drm_mode_config_init(dev);
  58. priv->crtc = tilcdc_crtc_create(dev);
  59. list_for_each_entry(mod, &module_list, list) {
  60. DBG("loading module: %s", mod->name);
  61. mod->funcs->modeset_init(mod, dev);
  62. }
  63. if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
  64. /* oh nos! */
  65. dev_err(dev->dev, "no encoders/connectors found\n");
  66. return -ENXIO;
  67. }
  68. dev->mode_config.min_width = 0;
  69. dev->mode_config.min_height = 0;
  70. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  71. dev->mode_config.max_height = 2048;
  72. dev->mode_config.funcs = &mode_config_funcs;
  73. return 0;
  74. }
  75. #ifdef CONFIG_CPU_FREQ
  76. static int cpufreq_transition(struct notifier_block *nb,
  77. unsigned long val, void *data)
  78. {
  79. struct tilcdc_drm_private *priv = container_of(nb,
  80. struct tilcdc_drm_private, freq_transition);
  81. if (val == CPUFREQ_POSTCHANGE) {
  82. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  83. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  84. tilcdc_crtc_update_clk(priv->crtc);
  85. }
  86. }
  87. return 0;
  88. }
  89. #endif
  90. /*
  91. * DRM operations:
  92. */
  93. static int tilcdc_unload(struct drm_device *dev)
  94. {
  95. struct tilcdc_drm_private *priv = dev->dev_private;
  96. struct tilcdc_module *mod, *cur;
  97. drm_kms_helper_poll_fini(dev);
  98. drm_mode_config_cleanup(dev);
  99. drm_vblank_cleanup(dev);
  100. pm_runtime_get_sync(dev->dev);
  101. drm_irq_uninstall(dev);
  102. pm_runtime_put_sync(dev->dev);
  103. #ifdef CONFIG_CPU_FREQ
  104. cpufreq_unregister_notifier(&priv->freq_transition,
  105. CPUFREQ_TRANSITION_NOTIFIER);
  106. #endif
  107. if (priv->clk)
  108. clk_put(priv->clk);
  109. if (priv->mmio)
  110. iounmap(priv->mmio);
  111. flush_workqueue(priv->wq);
  112. destroy_workqueue(priv->wq);
  113. dev->dev_private = NULL;
  114. pm_runtime_disable(dev->dev);
  115. list_for_each_entry_safe(mod, cur, &module_list, list) {
  116. DBG("destroying module: %s", mod->name);
  117. mod->funcs->destroy(mod);
  118. }
  119. kfree(priv);
  120. return 0;
  121. }
  122. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  123. {
  124. struct platform_device *pdev = dev->platformdev;
  125. struct device_node *node = pdev->dev.of_node;
  126. struct tilcdc_drm_private *priv;
  127. struct tilcdc_module *mod;
  128. struct resource *res;
  129. u32 bpp = 0;
  130. int ret;
  131. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  132. if (!priv) {
  133. dev_err(dev->dev, "failed to allocate private data\n");
  134. return -ENOMEM;
  135. }
  136. dev->dev_private = priv;
  137. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  138. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  139. if (!res) {
  140. dev_err(dev->dev, "failed to get memory resource\n");
  141. ret = -EINVAL;
  142. goto fail;
  143. }
  144. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  145. if (!priv->mmio) {
  146. dev_err(dev->dev, "failed to ioremap\n");
  147. ret = -ENOMEM;
  148. goto fail;
  149. }
  150. priv->clk = clk_get(dev->dev, "fck");
  151. if (IS_ERR(priv->clk)) {
  152. dev_err(dev->dev, "failed to get functional clock\n");
  153. ret = -ENODEV;
  154. goto fail;
  155. }
  156. priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
  157. if (IS_ERR(priv->clk)) {
  158. dev_err(dev->dev, "failed to get display clock\n");
  159. ret = -ENODEV;
  160. goto fail;
  161. }
  162. #ifdef CONFIG_CPU_FREQ
  163. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  164. priv->freq_transition.notifier_call = cpufreq_transition;
  165. ret = cpufreq_register_notifier(&priv->freq_transition,
  166. CPUFREQ_TRANSITION_NOTIFIER);
  167. if (ret) {
  168. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  169. goto fail;
  170. }
  171. #endif
  172. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  173. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  174. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  175. if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
  176. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  177. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  178. if (of_property_read_u32(node, "ti,max-pixelclock",
  179. &priv->max_pixelclock))
  180. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  181. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  182. pm_runtime_enable(dev->dev);
  183. /* Determine LCD IP Version */
  184. pm_runtime_get_sync(dev->dev);
  185. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  186. case 0x4c100102:
  187. priv->rev = 1;
  188. break;
  189. case 0x4f200800:
  190. case 0x4f201000:
  191. priv->rev = 2;
  192. break;
  193. default:
  194. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  195. "defaulting to LCD revision 1\n",
  196. tilcdc_read(dev, LCDC_PID_REG));
  197. priv->rev = 1;
  198. break;
  199. }
  200. pm_runtime_put_sync(dev->dev);
  201. ret = modeset_init(dev);
  202. if (ret < 0) {
  203. dev_err(dev->dev, "failed to initialize mode setting\n");
  204. goto fail;
  205. }
  206. ret = drm_vblank_init(dev, 1);
  207. if (ret < 0) {
  208. dev_err(dev->dev, "failed to initialize vblank\n");
  209. goto fail;
  210. }
  211. pm_runtime_get_sync(dev->dev);
  212. ret = drm_irq_install(dev);
  213. pm_runtime_put_sync(dev->dev);
  214. if (ret < 0) {
  215. dev_err(dev->dev, "failed to install IRQ handler\n");
  216. goto fail;
  217. }
  218. platform_set_drvdata(pdev, dev);
  219. list_for_each_entry(mod, &module_list, list) {
  220. DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
  221. bpp = mod->preferred_bpp;
  222. if (bpp > 0)
  223. break;
  224. }
  225. priv->fbdev = drm_fbdev_cma_init(dev, bpp,
  226. dev->mode_config.num_crtc,
  227. dev->mode_config.num_connector);
  228. drm_kms_helper_poll_init(dev);
  229. return 0;
  230. fail:
  231. tilcdc_unload(dev);
  232. return ret;
  233. }
  234. static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file)
  235. {
  236. struct tilcdc_drm_private *priv = dev->dev_private;
  237. tilcdc_crtc_cancel_page_flip(priv->crtc, file);
  238. }
  239. static void tilcdc_lastclose(struct drm_device *dev)
  240. {
  241. struct tilcdc_drm_private *priv = dev->dev_private;
  242. drm_fbdev_cma_restore_mode(priv->fbdev);
  243. }
  244. static irqreturn_t tilcdc_irq(DRM_IRQ_ARGS)
  245. {
  246. struct drm_device *dev = arg;
  247. struct tilcdc_drm_private *priv = dev->dev_private;
  248. return tilcdc_crtc_irq(priv->crtc);
  249. }
  250. static void tilcdc_irq_preinstall(struct drm_device *dev)
  251. {
  252. tilcdc_clear_irqstatus(dev, 0xffffffff);
  253. }
  254. static int tilcdc_irq_postinstall(struct drm_device *dev)
  255. {
  256. struct tilcdc_drm_private *priv = dev->dev_private;
  257. /* enable FIFO underflow irq: */
  258. if (priv->rev == 1)
  259. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  260. else
  261. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  262. return 0;
  263. }
  264. static void tilcdc_irq_uninstall(struct drm_device *dev)
  265. {
  266. struct tilcdc_drm_private *priv = dev->dev_private;
  267. /* disable irqs that we might have enabled: */
  268. if (priv->rev == 1) {
  269. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  270. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  271. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  272. } else {
  273. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  274. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  275. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  276. LCDC_FRAME_DONE);
  277. }
  278. }
  279. static void enable_vblank(struct drm_device *dev, bool enable)
  280. {
  281. struct tilcdc_drm_private *priv = dev->dev_private;
  282. u32 reg, mask;
  283. if (priv->rev == 1) {
  284. reg = LCDC_DMA_CTRL_REG;
  285. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  286. } else {
  287. reg = LCDC_INT_ENABLE_SET_REG;
  288. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  289. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  290. }
  291. if (enable)
  292. tilcdc_set(dev, reg, mask);
  293. else
  294. tilcdc_clear(dev, reg, mask);
  295. }
  296. static int tilcdc_enable_vblank(struct drm_device *dev, int crtc)
  297. {
  298. enable_vblank(dev, true);
  299. return 0;
  300. }
  301. static void tilcdc_disable_vblank(struct drm_device *dev, int crtc)
  302. {
  303. enable_vblank(dev, false);
  304. }
  305. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  306. static const struct {
  307. const char *name;
  308. uint8_t rev;
  309. uint8_t save;
  310. uint32_t reg;
  311. } registers[] = {
  312. #define REG(rev, save, reg) { #reg, rev, save, reg }
  313. /* exists in revision 1: */
  314. REG(1, false, LCDC_PID_REG),
  315. REG(1, true, LCDC_CTRL_REG),
  316. REG(1, false, LCDC_STAT_REG),
  317. REG(1, true, LCDC_RASTER_CTRL_REG),
  318. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  319. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  320. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  321. REG(1, true, LCDC_DMA_CTRL_REG),
  322. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  323. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  324. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  325. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  326. /* new in revision 2: */
  327. REG(2, false, LCDC_RAW_STAT_REG),
  328. REG(2, false, LCDC_MASKED_STAT_REG),
  329. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  330. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  331. REG(2, false, LCDC_END_OF_INT_IND_REG),
  332. REG(2, true, LCDC_CLK_ENABLE_REG),
  333. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  334. #undef REG
  335. };
  336. #endif
  337. #ifdef CONFIG_DEBUG_FS
  338. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  339. {
  340. struct drm_info_node *node = (struct drm_info_node *) m->private;
  341. struct drm_device *dev = node->minor->dev;
  342. struct tilcdc_drm_private *priv = dev->dev_private;
  343. unsigned i;
  344. pm_runtime_get_sync(dev->dev);
  345. seq_printf(m, "revision: %d\n", priv->rev);
  346. for (i = 0; i < ARRAY_SIZE(registers); i++)
  347. if (priv->rev >= registers[i].rev)
  348. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  349. tilcdc_read(dev, registers[i].reg));
  350. pm_runtime_put_sync(dev->dev);
  351. return 0;
  352. }
  353. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  354. {
  355. struct drm_info_node *node = (struct drm_info_node *) m->private;
  356. struct drm_device *dev = node->minor->dev;
  357. return drm_mm_dump_table(m, dev->mm_private);
  358. }
  359. static struct drm_info_list tilcdc_debugfs_list[] = {
  360. { "regs", tilcdc_regs_show, 0 },
  361. { "mm", tilcdc_mm_show, 0 },
  362. { "fb", drm_fb_cma_debugfs_show, 0 },
  363. };
  364. static int tilcdc_debugfs_init(struct drm_minor *minor)
  365. {
  366. struct drm_device *dev = minor->dev;
  367. struct tilcdc_module *mod;
  368. int ret;
  369. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  370. ARRAY_SIZE(tilcdc_debugfs_list),
  371. minor->debugfs_root, minor);
  372. list_for_each_entry(mod, &module_list, list)
  373. if (mod->funcs->debugfs_init)
  374. mod->funcs->debugfs_init(mod, minor);
  375. if (ret) {
  376. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  377. return ret;
  378. }
  379. return ret;
  380. }
  381. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  382. {
  383. struct tilcdc_module *mod;
  384. drm_debugfs_remove_files(tilcdc_debugfs_list,
  385. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  386. list_for_each_entry(mod, &module_list, list)
  387. if (mod->funcs->debugfs_cleanup)
  388. mod->funcs->debugfs_cleanup(mod, minor);
  389. }
  390. #endif
  391. static const struct file_operations fops = {
  392. .owner = THIS_MODULE,
  393. .open = drm_open,
  394. .release = drm_release,
  395. .unlocked_ioctl = drm_ioctl,
  396. #ifdef CONFIG_COMPAT
  397. .compat_ioctl = drm_compat_ioctl,
  398. #endif
  399. .poll = drm_poll,
  400. .read = drm_read,
  401. .fasync = drm_fasync,
  402. .llseek = no_llseek,
  403. .mmap = drm_gem_cma_mmap,
  404. };
  405. static struct drm_driver tilcdc_driver = {
  406. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  407. .load = tilcdc_load,
  408. .unload = tilcdc_unload,
  409. .preclose = tilcdc_preclose,
  410. .lastclose = tilcdc_lastclose,
  411. .irq_handler = tilcdc_irq,
  412. .irq_preinstall = tilcdc_irq_preinstall,
  413. .irq_postinstall = tilcdc_irq_postinstall,
  414. .irq_uninstall = tilcdc_irq_uninstall,
  415. .get_vblank_counter = drm_vblank_count,
  416. .enable_vblank = tilcdc_enable_vblank,
  417. .disable_vblank = tilcdc_disable_vblank,
  418. .gem_free_object = drm_gem_cma_free_object,
  419. .gem_vm_ops = &drm_gem_cma_vm_ops,
  420. .dumb_create = drm_gem_cma_dumb_create,
  421. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  422. .dumb_destroy = drm_gem_cma_dumb_destroy,
  423. #ifdef CONFIG_DEBUG_FS
  424. .debugfs_init = tilcdc_debugfs_init,
  425. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  426. #endif
  427. .fops = &fops,
  428. .name = "tilcdc",
  429. .desc = "TI LCD Controller DRM",
  430. .date = "20121205",
  431. .major = 1,
  432. .minor = 0,
  433. };
  434. /*
  435. * Power management:
  436. */
  437. #ifdef CONFIG_PM_SLEEP
  438. static int tilcdc_pm_suspend(struct device *dev)
  439. {
  440. struct drm_device *ddev = dev_get_drvdata(dev);
  441. struct tilcdc_drm_private *priv = ddev->dev_private;
  442. unsigned i, n = 0;
  443. drm_kms_helper_poll_disable(ddev);
  444. /* Save register state: */
  445. for (i = 0; i < ARRAY_SIZE(registers); i++)
  446. if (registers[i].save && (priv->rev >= registers[i].rev))
  447. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  448. return 0;
  449. }
  450. static int tilcdc_pm_resume(struct device *dev)
  451. {
  452. struct drm_device *ddev = dev_get_drvdata(dev);
  453. struct tilcdc_drm_private *priv = ddev->dev_private;
  454. unsigned i, n = 0;
  455. /* Restore register state: */
  456. for (i = 0; i < ARRAY_SIZE(registers); i++)
  457. if (registers[i].save && (priv->rev >= registers[i].rev))
  458. tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]);
  459. drm_kms_helper_poll_enable(ddev);
  460. return 0;
  461. }
  462. #endif
  463. static const struct dev_pm_ops tilcdc_pm_ops = {
  464. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  465. };
  466. /*
  467. * Platform driver:
  468. */
  469. static int tilcdc_pdev_probe(struct platform_device *pdev)
  470. {
  471. /* bail out early if no DT data: */
  472. if (!pdev->dev.of_node) {
  473. dev_err(&pdev->dev, "device-tree data is missing\n");
  474. return -ENXIO;
  475. }
  476. return drm_platform_init(&tilcdc_driver, pdev);
  477. }
  478. static int tilcdc_pdev_remove(struct platform_device *pdev)
  479. {
  480. drm_platform_exit(&tilcdc_driver, pdev);
  481. return 0;
  482. }
  483. static struct of_device_id tilcdc_of_match[] = {
  484. { .compatible = "ti,am33xx-tilcdc", },
  485. { },
  486. };
  487. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  488. static struct platform_driver tilcdc_platform_driver = {
  489. .probe = tilcdc_pdev_probe,
  490. .remove = tilcdc_pdev_remove,
  491. .driver = {
  492. .owner = THIS_MODULE,
  493. .name = "tilcdc",
  494. .pm = &tilcdc_pm_ops,
  495. .of_match_table = tilcdc_of_match,
  496. },
  497. };
  498. static int __init tilcdc_drm_init(void)
  499. {
  500. DBG("init");
  501. tilcdc_tfp410_init();
  502. tilcdc_slave_init();
  503. tilcdc_panel_init();
  504. return platform_driver_register(&tilcdc_platform_driver);
  505. }
  506. static void __exit tilcdc_drm_fini(void)
  507. {
  508. DBG("fini");
  509. tilcdc_tfp410_fini();
  510. tilcdc_slave_fini();
  511. tilcdc_panel_fini();
  512. platform_driver_unregister(&tilcdc_platform_driver);
  513. }
  514. late_initcall(tilcdc_drm_init);
  515. module_exit(tilcdc_drm_fini);
  516. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  517. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  518. MODULE_LICENSE("GPL");