stx_gp3_8560.dts 6.7 KB

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  1. /*
  2. * STX GP3 - 8560 ADS Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "stx,gp3";
  14. compatible = "stx,gp3-8560", "stx,gp3";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8560@0 {
  27. device_type = "cpu";
  28. reg = <0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. next-level-cache = <&L2>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x10000000>;
  42. };
  43. soc@fdf00000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. device_type = "soc";
  47. ranges = <0 0xfdf00000 0x100000>;
  48. reg = <0xfdf00000 0x1000>;
  49. bus-frequency = <0>;
  50. compatible = "fsl,mpc8560-immr", "simple-bus";
  51. ecm-law@0 {
  52. compatible = "fsl,ecm-law";
  53. reg = <0x0 0x1000>;
  54. fsl,num-laws = <8>;
  55. };
  56. ecm@1000 {
  57. compatible = "fsl,mpc8560-ecm", "fsl,ecm";
  58. reg = <0x1000 0x1000>;
  59. interrupts = <17 2>;
  60. interrupt-parent = <&mpic>;
  61. };
  62. memory-controller@2000 {
  63. compatible = "fsl,mpc8540-memory-controller";
  64. reg = <0x2000 0x1000>;
  65. interrupt-parent = <&mpic>;
  66. interrupts = <18 2>;
  67. };
  68. L2: l2-cache-controller@20000 {
  69. compatible = "fsl,mpc8540-l2-cache-controller";
  70. reg = <0x20000 0x1000>;
  71. cache-line-size = <32>;
  72. cache-size = <0x40000>; // L2, 256K
  73. interrupt-parent = <&mpic>;
  74. interrupts = <16 2>;
  75. };
  76. i2c@3000 {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. cell-index = <0>;
  80. compatible = "fsl-i2c";
  81. reg = <0x3000 0x100>;
  82. interrupts = <43 2>;
  83. interrupt-parent = <&mpic>;
  84. dfsrr;
  85. };
  86. dma@21300 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
  90. reg = <0x21300 0x4>;
  91. ranges = <0x0 0x21100 0x200>;
  92. cell-index = <0>;
  93. dma-channel@0 {
  94. compatible = "fsl,mpc8560-dma-channel",
  95. "fsl,eloplus-dma-channel";
  96. reg = <0x0 0x80>;
  97. cell-index = <0>;
  98. interrupt-parent = <&mpic>;
  99. interrupts = <20 2>;
  100. };
  101. dma-channel@80 {
  102. compatible = "fsl,mpc8560-dma-channel",
  103. "fsl,eloplus-dma-channel";
  104. reg = <0x80 0x80>;
  105. cell-index = <1>;
  106. interrupt-parent = <&mpic>;
  107. interrupts = <21 2>;
  108. };
  109. dma-channel@100 {
  110. compatible = "fsl,mpc8560-dma-channel",
  111. "fsl,eloplus-dma-channel";
  112. reg = <0x100 0x80>;
  113. cell-index = <2>;
  114. interrupt-parent = <&mpic>;
  115. interrupts = <22 2>;
  116. };
  117. dma-channel@180 {
  118. compatible = "fsl,mpc8560-dma-channel",
  119. "fsl,eloplus-dma-channel";
  120. reg = <0x180 0x80>;
  121. cell-index = <3>;
  122. interrupt-parent = <&mpic>;
  123. interrupts = <23 2>;
  124. };
  125. };
  126. enet0: ethernet@24000 {
  127. #address-cells = <1>;
  128. #size-cells = <1>;
  129. cell-index = <0>;
  130. device_type = "network";
  131. model = "TSEC";
  132. compatible = "gianfar";
  133. reg = <0x24000 0x1000>;
  134. ranges = <0x0 0x24000 0x1000>;
  135. local-mac-address = [ 00 00 00 00 00 00 ];
  136. interrupts = <29 2 30 2 34 2>;
  137. interrupt-parent = <&mpic>;
  138. tbi-handle = <&tbi0>;
  139. phy-handle = <&phy2>;
  140. mdio@520 {
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. compatible = "fsl,gianfar-mdio";
  144. reg = <0x520 0x20>;
  145. phy2: ethernet-phy@2 {
  146. interrupt-parent = <&mpic>;
  147. interrupts = <5 4>;
  148. reg = <2>;
  149. device_type = "ethernet-phy";
  150. };
  151. phy4: ethernet-phy@4 {
  152. interrupt-parent = <&mpic>;
  153. interrupts = <5 4>;
  154. reg = <4>;
  155. device_type = "ethernet-phy";
  156. };
  157. tbi0: tbi-phy@11 {
  158. reg = <0x11>;
  159. device_type = "tbi-phy";
  160. };
  161. };
  162. };
  163. enet1: ethernet@25000 {
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. cell-index = <1>;
  167. device_type = "network";
  168. model = "TSEC";
  169. compatible = "gianfar";
  170. reg = <0x25000 0x1000>;
  171. ranges = <0x0 0x25000 0x1000>;
  172. local-mac-address = [ 00 00 00 00 00 00 ];
  173. interrupts = <35 2 36 2 40 2>;
  174. interrupt-parent = <&mpic>;
  175. tbi-handle = <&tbi1>;
  176. phy-handle = <&phy4>;
  177. mdio@520 {
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. compatible = "fsl,gianfar-tbi";
  181. reg = <0x520 0x20>;
  182. tbi1: tbi-phy@11 {
  183. reg = <0x11>;
  184. device_type = "tbi-phy";
  185. };
  186. };
  187. };
  188. mpic: pic@40000 {
  189. interrupt-controller;
  190. #address-cells = <0>;
  191. #interrupt-cells = <2>;
  192. reg = <0x40000 0x40000>;
  193. compatible = "chrp,open-pic";
  194. device_type = "open-pic";
  195. };
  196. cpm@919c0 {
  197. #address-cells = <1>;
  198. #size-cells = <1>;
  199. compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
  200. reg = <0x919c0 0x30>;
  201. ranges;
  202. muram@80000 {
  203. #address-cells = <1>;
  204. #size-cells = <1>;
  205. ranges = <0 0x80000 0x10000>;
  206. data@0 {
  207. compatible = "fsl,cpm-muram-data";
  208. reg = <0 0x4000 0x9000 0x2000>;
  209. };
  210. };
  211. brg@919f0 {
  212. compatible = "fsl,mpc8560-brg",
  213. "fsl,cpm2-brg",
  214. "fsl,cpm-brg";
  215. reg = <0x919f0 0x10 0x915f0 0x10>;
  216. clock-frequency = <0>;
  217. };
  218. cpmpic: pic@90c00 {
  219. interrupt-controller;
  220. #address-cells = <0>;
  221. #interrupt-cells = <2>;
  222. interrupts = <46 2>;
  223. interrupt-parent = <&mpic>;
  224. reg = <0x90c00 0x80>;
  225. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  226. };
  227. serial0: serial@91a20 {
  228. device_type = "serial";
  229. compatible = "fsl,mpc8560-scc-uart",
  230. "fsl,cpm2-scc-uart";
  231. reg = <0x91a20 0x20 0x88100 0x100>;
  232. fsl,cpm-brg = <2>;
  233. fsl,cpm-command = <0x4a00000>;
  234. interrupts = <41 8>;
  235. interrupt-parent = <&cpmpic>;
  236. };
  237. };
  238. };
  239. pci0: pci@fdf08000 {
  240. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  241. interrupt-map = <
  242. /* IDSEL 0x0c */
  243. 0x6000 0 0 1 &mpic 1 1
  244. 0x6000 0 0 2 &mpic 2 1
  245. 0x6000 0 0 3 &mpic 3 1
  246. 0x6000 0 0 4 &mpic 4 1
  247. /* IDSEL 0x0d */
  248. 0x6800 0 0 1 &mpic 4 1
  249. 0x6800 0 0 2 &mpic 1 1
  250. 0x6800 0 0 3 &mpic 2 1
  251. 0x6800 0 0 4 &mpic 3 1
  252. /* IDSEL 0x0e */
  253. 0x7000 0 0 1 &mpic 3 1
  254. 0x7000 0 0 2 &mpic 4 1
  255. 0x7000 0 0 3 &mpic 1 1
  256. 0x7000 0 0 4 &mpic 2 1
  257. /* IDSEL 0x0f */
  258. 0x7800 0 0 1 &mpic 2 1
  259. 0x7800 0 0 2 &mpic 3 1
  260. 0x7800 0 0 3 &mpic 4 1
  261. 0x7800 0 0 4 &mpic 1 1>;
  262. interrupt-parent = <&mpic>;
  263. interrupts = <24 2>;
  264. bus-range = <0 0>;
  265. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  266. 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
  267. clock-frequency = <66666666>;
  268. #interrupt-cells = <1>;
  269. #size-cells = <2>;
  270. #address-cells = <3>;
  271. reg = <0xfdf08000 0x1000>;
  272. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  273. device_type = "pci";
  274. };
  275. };