scan.c 13 KB

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  1. /*
  2. * Broadcom specific AMBA
  3. * Bus scanning
  4. *
  5. * Licensed under the GNU/GPL. See COPYING for details.
  6. */
  7. #include "scan.h"
  8. #include "bcma_private.h"
  9. #include <linux/bcma/bcma.h>
  10. #include <linux/bcma/bcma_regs.h>
  11. #include <linux/pci.h>
  12. #include <linux/io.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/slab.h>
  15. struct bcma_device_id_name {
  16. u16 id;
  17. const char *name;
  18. };
  19. struct bcma_device_id_name bcma_device_names[] = {
  20. { BCMA_CORE_OOB_ROUTER, "OOB Router" },
  21. { BCMA_CORE_INVALID, "Invalid" },
  22. { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
  23. { BCMA_CORE_ILINE20, "ILine 20" },
  24. { BCMA_CORE_SRAM, "SRAM" },
  25. { BCMA_CORE_SDRAM, "SDRAM" },
  26. { BCMA_CORE_PCI, "PCI" },
  27. { BCMA_CORE_MIPS, "MIPS" },
  28. { BCMA_CORE_ETHERNET, "Fast Ethernet" },
  29. { BCMA_CORE_V90, "V90" },
  30. { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
  31. { BCMA_CORE_ADSL, "ADSL" },
  32. { BCMA_CORE_ILINE100, "ILine 100" },
  33. { BCMA_CORE_IPSEC, "IPSEC" },
  34. { BCMA_CORE_UTOPIA, "UTOPIA" },
  35. { BCMA_CORE_PCMCIA, "PCMCIA" },
  36. { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
  37. { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
  38. { BCMA_CORE_OFDM, "OFDM" },
  39. { BCMA_CORE_EXTIF, "EXTIF" },
  40. { BCMA_CORE_80211, "IEEE 802.11" },
  41. { BCMA_CORE_PHY_A, "PHY A" },
  42. { BCMA_CORE_PHY_B, "PHY B" },
  43. { BCMA_CORE_PHY_G, "PHY G" },
  44. { BCMA_CORE_MIPS_3302, "MIPS 3302" },
  45. { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
  46. { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
  47. { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
  48. { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
  49. { BCMA_CORE_SDIO_HOST, "SDIO Host" },
  50. { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
  51. { BCMA_CORE_PARA_ATA, "PATA" },
  52. { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
  53. { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
  54. { BCMA_CORE_PCIE, "PCIe" },
  55. { BCMA_CORE_PHY_N, "PHY N" },
  56. { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
  57. { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
  58. { BCMA_CORE_ARM_1176, "ARM 1176" },
  59. { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
  60. { BCMA_CORE_PHY_LP, "PHY LP" },
  61. { BCMA_CORE_PMU, "PMU" },
  62. { BCMA_CORE_PHY_SSN, "PHY SSN" },
  63. { BCMA_CORE_SDIO_DEV, "SDIO Device" },
  64. { BCMA_CORE_ARM_CM3, "ARM CM3" },
  65. { BCMA_CORE_PHY_HT, "PHY HT" },
  66. { BCMA_CORE_MIPS_74K, "MIPS 74K" },
  67. { BCMA_CORE_MAC_GBIT, "GBit MAC" },
  68. { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
  69. { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
  70. { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
  71. { BCMA_CORE_SHARED_COMMON, "Common Shared" },
  72. { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
  73. { BCMA_CORE_SPI_HOST, "SPI Host" },
  74. { BCMA_CORE_I2S, "I2S" },
  75. { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
  76. { BCMA_CORE_SHIM, "SHIM" },
  77. { BCMA_CORE_DEFAULT, "Default" },
  78. };
  79. const char *bcma_device_name(struct bcma_device_id *id)
  80. {
  81. int i;
  82. if (id->manuf == BCMA_MANUF_BCM) {
  83. for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
  84. if (bcma_device_names[i].id == id->id)
  85. return bcma_device_names[i].name;
  86. }
  87. }
  88. return "UNKNOWN";
  89. }
  90. static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
  91. u16 offset)
  92. {
  93. return readl(bus->mmio + offset);
  94. }
  95. static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
  96. {
  97. if (bus->hosttype == BCMA_HOSTTYPE_PCI)
  98. pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
  99. addr);
  100. }
  101. static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
  102. {
  103. u32 ent = readl(*eromptr);
  104. (*eromptr)++;
  105. return ent;
  106. }
  107. static void bcma_erom_push_ent(u32 **eromptr)
  108. {
  109. (*eromptr)--;
  110. }
  111. static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
  112. {
  113. u32 ent = bcma_erom_get_ent(bus, eromptr);
  114. if (!(ent & SCAN_ER_VALID))
  115. return -ENOENT;
  116. if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
  117. return -ENOENT;
  118. return ent;
  119. }
  120. static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
  121. {
  122. u32 ent = bcma_erom_get_ent(bus, eromptr);
  123. bcma_erom_push_ent(eromptr);
  124. return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
  125. }
  126. static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
  127. {
  128. u32 ent = bcma_erom_get_ent(bus, eromptr);
  129. bcma_erom_push_ent(eromptr);
  130. return (((ent & SCAN_ER_VALID)) &&
  131. ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
  132. ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
  133. }
  134. static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
  135. {
  136. u32 ent;
  137. while (1) {
  138. ent = bcma_erom_get_ent(bus, eromptr);
  139. if ((ent & SCAN_ER_VALID) &&
  140. ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
  141. break;
  142. if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
  143. break;
  144. }
  145. bcma_erom_push_ent(eromptr);
  146. }
  147. static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
  148. {
  149. u32 ent = bcma_erom_get_ent(bus, eromptr);
  150. if (!(ent & SCAN_ER_VALID))
  151. return -ENOENT;
  152. if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
  153. return -ENOENT;
  154. return ent;
  155. }
  156. static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
  157. u32 type, u8 port)
  158. {
  159. u32 addrl, addrh, sizel, sizeh = 0;
  160. u32 size;
  161. u32 ent = bcma_erom_get_ent(bus, eromptr);
  162. if ((!(ent & SCAN_ER_VALID)) ||
  163. ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
  164. ((ent & SCAN_ADDR_TYPE) != type) ||
  165. (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
  166. bcma_erom_push_ent(eromptr);
  167. return -EINVAL;
  168. }
  169. addrl = ent & SCAN_ADDR_ADDR;
  170. if (ent & SCAN_ADDR_AG32)
  171. addrh = bcma_erom_get_ent(bus, eromptr);
  172. else
  173. addrh = 0;
  174. if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
  175. size = bcma_erom_get_ent(bus, eromptr);
  176. sizel = size & SCAN_SIZE_SZ;
  177. if (size & SCAN_SIZE_SG32)
  178. sizeh = bcma_erom_get_ent(bus, eromptr);
  179. } else
  180. sizel = SCAN_ADDR_SZ_BASE <<
  181. ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
  182. return addrl;
  183. }
  184. static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
  185. u16 index)
  186. {
  187. struct bcma_device *core;
  188. list_for_each_entry(core, &bus->cores, list) {
  189. if (core->core_index == index)
  190. return core;
  191. }
  192. return NULL;
  193. }
  194. static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
  195. {
  196. struct bcma_device *core;
  197. list_for_each_entry_reverse(core, &bus->cores, list) {
  198. if (core->id.id == coreid)
  199. return core;
  200. }
  201. return NULL;
  202. }
  203. static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
  204. struct bcma_device_id *match, int core_num,
  205. struct bcma_device *core)
  206. {
  207. s32 tmp;
  208. u8 i, j;
  209. s32 cia, cib;
  210. u8 ports[2], wrappers[2];
  211. /* get CIs */
  212. cia = bcma_erom_get_ci(bus, eromptr);
  213. if (cia < 0) {
  214. bcma_erom_push_ent(eromptr);
  215. if (bcma_erom_is_end(bus, eromptr))
  216. return -ESPIPE;
  217. return -EILSEQ;
  218. }
  219. cib = bcma_erom_get_ci(bus, eromptr);
  220. if (cib < 0)
  221. return -EILSEQ;
  222. /* parse CIs */
  223. core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
  224. core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
  225. core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
  226. ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
  227. ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
  228. wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
  229. wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
  230. core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
  231. if (((core->id.manuf == BCMA_MANUF_ARM) &&
  232. (core->id.id == 0xFFF)) ||
  233. (ports[1] == 0)) {
  234. bcma_erom_skip_component(bus, eromptr);
  235. return -ENXIO;
  236. }
  237. /* check if component is a core at all */
  238. if (wrappers[0] + wrappers[1] == 0) {
  239. /* we could save addrl of the router
  240. if (cid == BCMA_CORE_OOB_ROUTER)
  241. */
  242. bcma_erom_skip_component(bus, eromptr);
  243. return -ENXIO;
  244. }
  245. if (bcma_erom_is_bridge(bus, eromptr)) {
  246. bcma_erom_skip_component(bus, eromptr);
  247. return -ENXIO;
  248. }
  249. if (bcma_find_core_by_index(bus, core_num)) {
  250. bcma_erom_skip_component(bus, eromptr);
  251. return -ENODEV;
  252. }
  253. if (match && ((match->manuf != BCMA_ANY_MANUF &&
  254. match->manuf != core->id.manuf) ||
  255. (match->id != BCMA_ANY_ID && match->id != core->id.id) ||
  256. (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
  257. (match->class != BCMA_ANY_CLASS && match->class != core->id.class)
  258. )) {
  259. bcma_erom_skip_component(bus, eromptr);
  260. return -ENODEV;
  261. }
  262. /* get & parse master ports */
  263. for (i = 0; i < ports[0]; i++) {
  264. s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
  265. if (mst_port_d < 0)
  266. return -EILSEQ;
  267. }
  268. /* First Slave Address Descriptor should be port 0:
  269. * the main register space for the core
  270. */
  271. tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
  272. if (tmp <= 0) {
  273. /* Try again to see if it is a bridge */
  274. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  275. SCAN_ADDR_TYPE_BRIDGE, 0);
  276. if (tmp <= 0) {
  277. return -EILSEQ;
  278. } else {
  279. pr_info("Bridge found\n");
  280. return -ENXIO;
  281. }
  282. }
  283. core->addr = tmp;
  284. /* get & parse slave ports */
  285. for (i = 0; i < ports[1]; i++) {
  286. for (j = 0; ; j++) {
  287. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  288. SCAN_ADDR_TYPE_SLAVE, i);
  289. if (tmp < 0) {
  290. /* no more entries for port _i_ */
  291. /* pr_debug("erom: slave port %d "
  292. * "has %d descriptors\n", i, j); */
  293. break;
  294. } else {
  295. if (i == 0 && j == 0)
  296. core->addr1 = tmp;
  297. }
  298. }
  299. }
  300. /* get & parse master wrappers */
  301. for (i = 0; i < wrappers[0]; i++) {
  302. for (j = 0; ; j++) {
  303. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  304. SCAN_ADDR_TYPE_MWRAP, i);
  305. if (tmp < 0) {
  306. /* no more entries for port _i_ */
  307. /* pr_debug("erom: master wrapper %d "
  308. * "has %d descriptors\n", i, j); */
  309. break;
  310. } else {
  311. if (i == 0 && j == 0)
  312. core->wrap = tmp;
  313. }
  314. }
  315. }
  316. /* get & parse slave wrappers */
  317. for (i = 0; i < wrappers[1]; i++) {
  318. u8 hack = (ports[1] == 1) ? 0 : 1;
  319. for (j = 0; ; j++) {
  320. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  321. SCAN_ADDR_TYPE_SWRAP, i + hack);
  322. if (tmp < 0) {
  323. /* no more entries for port _i_ */
  324. /* pr_debug("erom: master wrapper %d "
  325. * has %d descriptors\n", i, j); */
  326. break;
  327. } else {
  328. if (wrappers[0] == 0 && !i && !j)
  329. core->wrap = tmp;
  330. }
  331. }
  332. }
  333. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  334. core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
  335. if (!core->io_addr)
  336. return -ENOMEM;
  337. core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
  338. if (!core->io_wrap) {
  339. iounmap(core->io_addr);
  340. return -ENOMEM;
  341. }
  342. }
  343. return 0;
  344. }
  345. void bcma_init_bus(struct bcma_bus *bus)
  346. {
  347. s32 tmp;
  348. struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
  349. if (bus->init_done)
  350. return;
  351. INIT_LIST_HEAD(&bus->cores);
  352. bus->nr_cores = 0;
  353. bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
  354. tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
  355. chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
  356. chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
  357. chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
  358. pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
  359. chipinfo->id, chipinfo->rev, chipinfo->pkg);
  360. bus->init_done = true;
  361. }
  362. int bcma_bus_scan(struct bcma_bus *bus)
  363. {
  364. u32 erombase;
  365. u32 __iomem *eromptr, *eromend;
  366. int err, core_num = 0;
  367. bcma_init_bus(bus);
  368. erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
  369. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  370. eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
  371. if (!eromptr)
  372. return -ENOMEM;
  373. } else {
  374. eromptr = bus->mmio;
  375. }
  376. eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
  377. bcma_scan_switch_core(bus, erombase);
  378. while (eromptr < eromend) {
  379. struct bcma_device *other_core;
  380. struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
  381. if (!core)
  382. return -ENOMEM;
  383. INIT_LIST_HEAD(&core->list);
  384. core->bus = bus;
  385. err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
  386. if (err < 0) {
  387. kfree(core);
  388. if (err == -ENODEV) {
  389. core_num++;
  390. continue;
  391. } else if (err == -ENXIO) {
  392. continue;
  393. } else if (err == -ESPIPE) {
  394. break;
  395. }
  396. return err;
  397. }
  398. core->core_index = core_num++;
  399. bus->nr_cores++;
  400. other_core = bcma_find_core_reverse(bus, core->id.id);
  401. core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
  402. pr_info("Core %d found: %s "
  403. "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
  404. core->core_index, bcma_device_name(&core->id),
  405. core->id.manuf, core->id.id, core->id.rev,
  406. core->id.class);
  407. list_add(&core->list, &bus->cores);
  408. }
  409. if (bus->hosttype == BCMA_HOSTTYPE_SOC)
  410. iounmap(eromptr);
  411. return 0;
  412. }
  413. int __init bcma_bus_scan_early(struct bcma_bus *bus,
  414. struct bcma_device_id *match,
  415. struct bcma_device *core)
  416. {
  417. u32 erombase;
  418. u32 __iomem *eromptr, *eromend;
  419. int err = -ENODEV;
  420. int core_num = 0;
  421. erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
  422. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  423. eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
  424. if (!eromptr)
  425. return -ENOMEM;
  426. } else {
  427. eromptr = bus->mmio;
  428. }
  429. eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
  430. bcma_scan_switch_core(bus, erombase);
  431. while (eromptr < eromend) {
  432. memset(core, 0, sizeof(*core));
  433. INIT_LIST_HEAD(&core->list);
  434. core->bus = bus;
  435. err = bcma_get_next_core(bus, &eromptr, match, core_num, core);
  436. if (err == -ENODEV) {
  437. core_num++;
  438. continue;
  439. } else if (err == -ENXIO)
  440. continue;
  441. else if (err == -ESPIPE)
  442. break;
  443. else if (err < 0)
  444. return err;
  445. core->core_index = core_num++;
  446. bus->nr_cores++;
  447. pr_info("Core %d found: %s "
  448. "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
  449. core->core_index, bcma_device_name(&core->id),
  450. core->id.manuf, core->id.id, core->id.rev,
  451. core->id.class);
  452. list_add(&core->list, &bus->cores);
  453. err = 0;
  454. break;
  455. }
  456. if (bus->hosttype == BCMA_HOSTTYPE_SOC)
  457. iounmap(eromptr);
  458. return err;
  459. }