sdhci.c 32 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #define DBG(f, x...) \
  27. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. /* handle any SD host controller */
  30. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  31. { /* end: all zeroes */ },
  32. };
  33. MODULE_DEVICE_TABLE(pci, pci_ids);
  34. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  35. static void sdhci_finish_data(struct sdhci_host *);
  36. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  37. static void sdhci_finish_command(struct sdhci_host *);
  38. static void sdhci_dumpregs(struct sdhci_host *host)
  39. {
  40. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  41. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  42. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  43. readw(host->ioaddr + SDHCI_HOST_VERSION));
  44. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  45. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  46. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  47. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  48. readl(host->ioaddr + SDHCI_ARGUMENT),
  49. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  50. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  51. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  52. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  53. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  54. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  55. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  56. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  57. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  58. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  59. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  60. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  61. readl(host->ioaddr + SDHCI_INT_STATUS));
  62. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  63. readl(host->ioaddr + SDHCI_INT_ENABLE),
  64. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  65. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  66. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  67. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  68. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_CAPABILITIES),
  70. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  71. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  72. }
  73. /*****************************************************************************\
  74. * *
  75. * Low level functions *
  76. * *
  77. \*****************************************************************************/
  78. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  79. {
  80. unsigned long timeout;
  81. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  82. if (mask & SDHCI_RESET_ALL)
  83. host->clock = 0;
  84. /* Wait max 100 ms */
  85. timeout = 100;
  86. /* hw clears the bit when it's done */
  87. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  88. if (timeout == 0) {
  89. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  90. "Please report this to " BUGMAIL ".\n",
  91. mmc_hostname(host->mmc), (int)mask);
  92. sdhci_dumpregs(host);
  93. return;
  94. }
  95. timeout--;
  96. mdelay(1);
  97. }
  98. }
  99. static void sdhci_init(struct sdhci_host *host)
  100. {
  101. u32 intmask;
  102. sdhci_reset(host, SDHCI_RESET_ALL);
  103. intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  104. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  105. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  106. /* This is unknown magic. */
  107. writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  108. }
  109. static void sdhci_activate_led(struct sdhci_host *host)
  110. {
  111. u8 ctrl;
  112. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  113. ctrl |= SDHCI_CTRL_LED;
  114. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  115. }
  116. static void sdhci_deactivate_led(struct sdhci_host *host)
  117. {
  118. u8 ctrl;
  119. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  120. ctrl &= ~SDHCI_CTRL_LED;
  121. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  122. }
  123. /*****************************************************************************\
  124. * *
  125. * Core functions *
  126. * *
  127. \*****************************************************************************/
  128. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  129. {
  130. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  131. return host->mapped_sg + host->cur_sg->offset;
  132. }
  133. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  134. {
  135. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  136. }
  137. static inline int sdhci_next_sg(struct sdhci_host* host)
  138. {
  139. /*
  140. * Skip to next SG entry.
  141. */
  142. host->cur_sg++;
  143. host->num_sg--;
  144. /*
  145. * Any entries left?
  146. */
  147. if (host->num_sg > 0) {
  148. host->offset = 0;
  149. host->remain = host->cur_sg->length;
  150. }
  151. return host->num_sg;
  152. }
  153. static void sdhci_transfer_pio(struct sdhci_host *host)
  154. {
  155. char *buffer;
  156. u32 mask;
  157. int bytes, size;
  158. unsigned long max_jiffies;
  159. BUG_ON(!host->data);
  160. if (host->num_sg == 0)
  161. return;
  162. bytes = 0;
  163. if (host->data->flags & MMC_DATA_READ)
  164. mask = SDHCI_DATA_AVAILABLE;
  165. else
  166. mask = SDHCI_SPACE_AVAILABLE;
  167. buffer = sdhci_kmap_sg(host) + host->offset;
  168. /* Transfer shouldn't take more than 5 s */
  169. max_jiffies = jiffies + HZ * 5;
  170. while (host->size > 0) {
  171. if (time_after(jiffies, max_jiffies)) {
  172. printk(KERN_ERR "%s: PIO transfer stalled. "
  173. "Please report this to "
  174. BUGMAIL ".\n", mmc_hostname(host->mmc));
  175. sdhci_dumpregs(host);
  176. sdhci_kunmap_sg(host);
  177. host->data->error = MMC_ERR_FAILED;
  178. sdhci_finish_data(host);
  179. return;
  180. }
  181. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  182. continue;
  183. size = min(host->size, host->remain);
  184. if (size >= 4) {
  185. if (host->data->flags & MMC_DATA_READ)
  186. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  187. else
  188. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  189. size = 4;
  190. } else if (size >= 2) {
  191. if (host->data->flags & MMC_DATA_READ)
  192. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  193. else
  194. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  195. size = 2;
  196. } else {
  197. if (host->data->flags & MMC_DATA_READ)
  198. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  199. else
  200. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  201. size = 1;
  202. }
  203. buffer += size;
  204. host->offset += size;
  205. host->remain -= size;
  206. bytes += size;
  207. host->size -= size;
  208. if (host->remain == 0) {
  209. sdhci_kunmap_sg(host);
  210. if (sdhci_next_sg(host) == 0) {
  211. DBG("PIO transfer: %d bytes\n", bytes);
  212. return;
  213. }
  214. buffer = sdhci_kmap_sg(host);
  215. }
  216. }
  217. sdhci_kunmap_sg(host);
  218. DBG("PIO transfer: %d bytes\n", bytes);
  219. }
  220. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  221. {
  222. u16 mode;
  223. WARN_ON(host->data);
  224. if (data == NULL) {
  225. writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
  226. return;
  227. }
  228. DBG("blksz %04x blks %04x flags %08x\n",
  229. data->blksz, data->blocks, data->flags);
  230. DBG("tsac %d ms nsac %d clk\n",
  231. data->timeout_ns / 1000000, data->timeout_clks);
  232. mode = SDHCI_TRNS_BLK_CNT_EN;
  233. if (data->blocks > 1)
  234. mode |= SDHCI_TRNS_MULTI;
  235. if (data->flags & MMC_DATA_READ)
  236. mode |= SDHCI_TRNS_READ;
  237. if (host->flags & SDHCI_USE_DMA)
  238. mode |= SDHCI_TRNS_DMA;
  239. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  240. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  241. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  242. if (host->flags & SDHCI_USE_DMA) {
  243. int count;
  244. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  245. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  246. BUG_ON(count != 1);
  247. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  248. } else {
  249. host->size = data->blksz * data->blocks;
  250. host->cur_sg = data->sg;
  251. host->num_sg = data->sg_len;
  252. host->offset = 0;
  253. host->remain = host->cur_sg->length;
  254. }
  255. }
  256. static void sdhci_finish_data(struct sdhci_host *host)
  257. {
  258. struct mmc_data *data;
  259. u32 intmask;
  260. u16 blocks;
  261. BUG_ON(!host->data);
  262. data = host->data;
  263. host->data = NULL;
  264. if (host->flags & SDHCI_USE_DMA) {
  265. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  266. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  267. } else {
  268. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  269. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  270. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  271. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  272. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  273. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  274. }
  275. /*
  276. * Controller doesn't count down when in single block mode.
  277. */
  278. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  279. blocks = 0;
  280. else
  281. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  282. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  283. if ((data->error == MMC_ERR_NONE) && blocks) {
  284. printk(KERN_ERR "%s: Controller signalled completion even "
  285. "though there were blocks left. Please report this "
  286. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  287. data->error = MMC_ERR_FAILED;
  288. }
  289. if (host->size != 0) {
  290. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  291. "Please report this to " BUGMAIL ".\n",
  292. mmc_hostname(host->mmc), host->size);
  293. data->error = MMC_ERR_FAILED;
  294. }
  295. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  296. if (data->stop) {
  297. /*
  298. * The controller needs a reset of internal state machines
  299. * upon error conditions.
  300. */
  301. if (data->error != MMC_ERR_NONE) {
  302. sdhci_reset(host, SDHCI_RESET_CMD);
  303. sdhci_reset(host, SDHCI_RESET_DATA);
  304. }
  305. sdhci_send_command(host, data->stop);
  306. } else
  307. tasklet_schedule(&host->finish_tasklet);
  308. }
  309. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  310. {
  311. int flags;
  312. unsigned long timeout;
  313. WARN_ON(host->cmd);
  314. DBG("Sending cmd (%x)\n", cmd->opcode);
  315. /* Wait max 10 ms */
  316. timeout = 10;
  317. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  318. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  319. if (timeout == 0) {
  320. printk(KERN_ERR "%s: Controller never released "
  321. "inhibit bits. Please report this to "
  322. BUGMAIL ".\n", mmc_hostname(host->mmc));
  323. sdhci_dumpregs(host);
  324. cmd->error = MMC_ERR_FAILED;
  325. tasklet_schedule(&host->finish_tasklet);
  326. return;
  327. }
  328. timeout--;
  329. mdelay(1);
  330. }
  331. mod_timer(&host->timer, jiffies + 10 * HZ);
  332. host->cmd = cmd;
  333. sdhci_prepare_data(host, cmd->data);
  334. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  335. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  336. printk(KERN_ERR "%s: Unsupported response type! "
  337. "Please report this to " BUGMAIL ".\n",
  338. mmc_hostname(host->mmc));
  339. cmd->error = MMC_ERR_INVALID;
  340. tasklet_schedule(&host->finish_tasklet);
  341. return;
  342. }
  343. if (!(cmd->flags & MMC_RSP_PRESENT))
  344. flags = SDHCI_CMD_RESP_NONE;
  345. else if (cmd->flags & MMC_RSP_136)
  346. flags = SDHCI_CMD_RESP_LONG;
  347. else if (cmd->flags & MMC_RSP_BUSY)
  348. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  349. else
  350. flags = SDHCI_CMD_RESP_SHORT;
  351. if (cmd->flags & MMC_RSP_CRC)
  352. flags |= SDHCI_CMD_CRC;
  353. if (cmd->flags & MMC_RSP_OPCODE)
  354. flags |= SDHCI_CMD_INDEX;
  355. if (cmd->data)
  356. flags |= SDHCI_CMD_DATA;
  357. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  358. host->ioaddr + SDHCI_COMMAND);
  359. }
  360. static void sdhci_finish_command(struct sdhci_host *host)
  361. {
  362. int i;
  363. BUG_ON(host->cmd == NULL);
  364. if (host->cmd->flags & MMC_RSP_PRESENT) {
  365. if (host->cmd->flags & MMC_RSP_136) {
  366. /* CRC is stripped so we need to do some shifting. */
  367. for (i = 0;i < 4;i++) {
  368. host->cmd->resp[i] = readl(host->ioaddr +
  369. SDHCI_RESPONSE + (3-i)*4) << 8;
  370. if (i != 3)
  371. host->cmd->resp[i] |=
  372. readb(host->ioaddr +
  373. SDHCI_RESPONSE + (3-i)*4-1);
  374. }
  375. } else {
  376. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  377. }
  378. }
  379. host->cmd->error = MMC_ERR_NONE;
  380. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  381. if (host->cmd->data) {
  382. u32 intmask;
  383. host->data = host->cmd->data;
  384. if (!(host->flags & SDHCI_USE_DMA)) {
  385. /*
  386. * Don't enable the interrupts until now to make sure we
  387. * get stable handling of the FIFO.
  388. */
  389. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  390. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  391. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  392. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  393. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  394. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  395. /*
  396. * The buffer interrupts are to unreliable so we
  397. * start the transfer immediatly.
  398. */
  399. sdhci_transfer_pio(host);
  400. }
  401. } else
  402. tasklet_schedule(&host->finish_tasklet);
  403. host->cmd = NULL;
  404. }
  405. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  406. {
  407. int div;
  408. u16 clk;
  409. unsigned long timeout;
  410. if (clock == host->clock)
  411. return;
  412. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  413. if (clock == 0)
  414. goto out;
  415. for (div = 1;div < 256;div *= 2) {
  416. if ((host->max_clk / div) <= clock)
  417. break;
  418. }
  419. div >>= 1;
  420. clk = div << SDHCI_DIVIDER_SHIFT;
  421. clk |= SDHCI_CLOCK_INT_EN;
  422. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  423. /* Wait max 10 ms */
  424. timeout = 10;
  425. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  426. & SDHCI_CLOCK_INT_STABLE)) {
  427. if (timeout == 0) {
  428. printk(KERN_ERR "%s: Internal clock never stabilised. "
  429. "Please report this to " BUGMAIL ".\n",
  430. mmc_hostname(host->mmc));
  431. sdhci_dumpregs(host);
  432. return;
  433. }
  434. timeout--;
  435. mdelay(1);
  436. }
  437. clk |= SDHCI_CLOCK_CARD_EN;
  438. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  439. out:
  440. host->clock = clock;
  441. }
  442. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  443. {
  444. u8 pwr;
  445. if (host->power == power)
  446. return;
  447. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  448. if (power == (unsigned short)-1)
  449. goto out;
  450. pwr = SDHCI_POWER_ON;
  451. switch (power) {
  452. case MMC_VDD_170:
  453. case MMC_VDD_180:
  454. case MMC_VDD_190:
  455. pwr |= SDHCI_POWER_180;
  456. break;
  457. case MMC_VDD_290:
  458. case MMC_VDD_300:
  459. case MMC_VDD_310:
  460. pwr |= SDHCI_POWER_300;
  461. break;
  462. case MMC_VDD_320:
  463. case MMC_VDD_330:
  464. case MMC_VDD_340:
  465. pwr |= SDHCI_POWER_330;
  466. break;
  467. default:
  468. BUG();
  469. }
  470. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  471. out:
  472. host->power = power;
  473. }
  474. /*****************************************************************************\
  475. * *
  476. * MMC callbacks *
  477. * *
  478. \*****************************************************************************/
  479. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  480. {
  481. struct sdhci_host *host;
  482. unsigned long flags;
  483. host = mmc_priv(mmc);
  484. spin_lock_irqsave(&host->lock, flags);
  485. WARN_ON(host->mrq != NULL);
  486. sdhci_activate_led(host);
  487. host->mrq = mrq;
  488. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  489. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  490. tasklet_schedule(&host->finish_tasklet);
  491. } else
  492. sdhci_send_command(host, mrq->cmd);
  493. spin_unlock_irqrestore(&host->lock, flags);
  494. }
  495. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  496. {
  497. struct sdhci_host *host;
  498. unsigned long flags;
  499. u8 ctrl;
  500. host = mmc_priv(mmc);
  501. spin_lock_irqsave(&host->lock, flags);
  502. /*
  503. * Reset the chip on each power off.
  504. * Should clear out any weird states.
  505. */
  506. if (ios->power_mode == MMC_POWER_OFF) {
  507. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  508. sdhci_init(host);
  509. }
  510. sdhci_set_clock(host, ios->clock);
  511. if (ios->power_mode == MMC_POWER_OFF)
  512. sdhci_set_power(host, -1);
  513. else
  514. sdhci_set_power(host, ios->vdd);
  515. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  516. if (ios->bus_width == MMC_BUS_WIDTH_4)
  517. ctrl |= SDHCI_CTRL_4BITBUS;
  518. else
  519. ctrl &= ~SDHCI_CTRL_4BITBUS;
  520. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  521. spin_unlock_irqrestore(&host->lock, flags);
  522. }
  523. static int sdhci_get_ro(struct mmc_host *mmc)
  524. {
  525. struct sdhci_host *host;
  526. unsigned long flags;
  527. int present;
  528. host = mmc_priv(mmc);
  529. spin_lock_irqsave(&host->lock, flags);
  530. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  531. spin_unlock_irqrestore(&host->lock, flags);
  532. return !(present & SDHCI_WRITE_PROTECT);
  533. }
  534. static struct mmc_host_ops sdhci_ops = {
  535. .request = sdhci_request,
  536. .set_ios = sdhci_set_ios,
  537. .get_ro = sdhci_get_ro,
  538. };
  539. /*****************************************************************************\
  540. * *
  541. * Tasklets *
  542. * *
  543. \*****************************************************************************/
  544. static void sdhci_tasklet_card(unsigned long param)
  545. {
  546. struct sdhci_host *host;
  547. unsigned long flags;
  548. host = (struct sdhci_host*)param;
  549. spin_lock_irqsave(&host->lock, flags);
  550. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  551. if (host->mrq) {
  552. printk(KERN_ERR "%s: Card removed during transfer!\n",
  553. mmc_hostname(host->mmc));
  554. printk(KERN_ERR "%s: Resetting controller.\n",
  555. mmc_hostname(host->mmc));
  556. sdhci_reset(host, SDHCI_RESET_CMD);
  557. sdhci_reset(host, SDHCI_RESET_DATA);
  558. host->mrq->cmd->error = MMC_ERR_FAILED;
  559. tasklet_schedule(&host->finish_tasklet);
  560. }
  561. }
  562. spin_unlock_irqrestore(&host->lock, flags);
  563. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  564. }
  565. static void sdhci_tasklet_finish(unsigned long param)
  566. {
  567. struct sdhci_host *host;
  568. unsigned long flags;
  569. struct mmc_request *mrq;
  570. host = (struct sdhci_host*)param;
  571. spin_lock_irqsave(&host->lock, flags);
  572. del_timer(&host->timer);
  573. mrq = host->mrq;
  574. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  575. /*
  576. * The controller needs a reset of internal state machines
  577. * upon error conditions.
  578. */
  579. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  580. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  581. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  582. sdhci_reset(host, SDHCI_RESET_CMD);
  583. sdhci_reset(host, SDHCI_RESET_DATA);
  584. }
  585. host->mrq = NULL;
  586. host->cmd = NULL;
  587. host->data = NULL;
  588. sdhci_deactivate_led(host);
  589. spin_unlock_irqrestore(&host->lock, flags);
  590. mmc_request_done(host->mmc, mrq);
  591. }
  592. static void sdhci_timeout_timer(unsigned long data)
  593. {
  594. struct sdhci_host *host;
  595. unsigned long flags;
  596. host = (struct sdhci_host*)data;
  597. spin_lock_irqsave(&host->lock, flags);
  598. if (host->mrq) {
  599. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  600. "Please report this to " BUGMAIL ".\n",
  601. mmc_hostname(host->mmc));
  602. sdhci_dumpregs(host);
  603. if (host->data) {
  604. host->data->error = MMC_ERR_TIMEOUT;
  605. sdhci_finish_data(host);
  606. } else {
  607. if (host->cmd)
  608. host->cmd->error = MMC_ERR_TIMEOUT;
  609. else
  610. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  611. tasklet_schedule(&host->finish_tasklet);
  612. }
  613. }
  614. spin_unlock_irqrestore(&host->lock, flags);
  615. }
  616. /*****************************************************************************\
  617. * *
  618. * Interrupt handling *
  619. * *
  620. \*****************************************************************************/
  621. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  622. {
  623. BUG_ON(intmask == 0);
  624. if (!host->cmd) {
  625. printk(KERN_ERR "%s: Got command interrupt even though no "
  626. "command operation was in progress.\n",
  627. mmc_hostname(host->mmc));
  628. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  629. mmc_hostname(host->mmc));
  630. sdhci_dumpregs(host);
  631. return;
  632. }
  633. if (intmask & SDHCI_INT_RESPONSE)
  634. sdhci_finish_command(host);
  635. else {
  636. if (intmask & SDHCI_INT_TIMEOUT)
  637. host->cmd->error = MMC_ERR_TIMEOUT;
  638. else if (intmask & SDHCI_INT_CRC)
  639. host->cmd->error = MMC_ERR_BADCRC;
  640. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  641. host->cmd->error = MMC_ERR_FAILED;
  642. else
  643. host->cmd->error = MMC_ERR_INVALID;
  644. tasklet_schedule(&host->finish_tasklet);
  645. }
  646. }
  647. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  648. {
  649. BUG_ON(intmask == 0);
  650. if (!host->data) {
  651. /*
  652. * A data end interrupt is sent together with the response
  653. * for the stop command.
  654. */
  655. if (intmask & SDHCI_INT_DATA_END)
  656. return;
  657. printk(KERN_ERR "%s: Got data interrupt even though no "
  658. "data operation was in progress.\n",
  659. mmc_hostname(host->mmc));
  660. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  661. mmc_hostname(host->mmc));
  662. sdhci_dumpregs(host);
  663. return;
  664. }
  665. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  666. host->data->error = MMC_ERR_TIMEOUT;
  667. else if (intmask & SDHCI_INT_DATA_CRC)
  668. host->data->error = MMC_ERR_BADCRC;
  669. else if (intmask & SDHCI_INT_DATA_END_BIT)
  670. host->data->error = MMC_ERR_FAILED;
  671. if (host->data->error != MMC_ERR_NONE)
  672. sdhci_finish_data(host);
  673. else {
  674. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  675. sdhci_transfer_pio(host);
  676. if (intmask & SDHCI_INT_DATA_END)
  677. sdhci_finish_data(host);
  678. }
  679. }
  680. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  681. {
  682. irqreturn_t result;
  683. struct sdhci_host* host = dev_id;
  684. u32 intmask;
  685. spin_lock(&host->lock);
  686. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  687. if (!intmask) {
  688. result = IRQ_NONE;
  689. goto out;
  690. }
  691. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  692. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  693. tasklet_schedule(&host->card_tasklet);
  694. if (intmask & SDHCI_INT_CMD_MASK) {
  695. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  696. writel(intmask & SDHCI_INT_CMD_MASK,
  697. host->ioaddr + SDHCI_INT_STATUS);
  698. }
  699. if (intmask & SDHCI_INT_DATA_MASK) {
  700. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  701. writel(intmask & SDHCI_INT_DATA_MASK,
  702. host->ioaddr + SDHCI_INT_STATUS);
  703. }
  704. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  705. if (intmask & SDHCI_INT_CARD_INT) {
  706. printk(KERN_ERR "%s: Unexpected card interrupt. Please "
  707. "report this to " BUGMAIL ".\n",
  708. mmc_hostname(host->mmc));
  709. sdhci_dumpregs(host);
  710. }
  711. if (intmask & SDHCI_INT_BUS_POWER) {
  712. printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
  713. "report this to " BUGMAIL ".\n",
  714. mmc_hostname(host->mmc));
  715. sdhci_dumpregs(host);
  716. }
  717. if (intmask & SDHCI_INT_ACMD12ERR) {
  718. printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
  719. "report this to " BUGMAIL ".\n",
  720. mmc_hostname(host->mmc));
  721. sdhci_dumpregs(host);
  722. writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
  723. }
  724. if (intmask)
  725. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  726. result = IRQ_HANDLED;
  727. out:
  728. spin_unlock(&host->lock);
  729. return result;
  730. }
  731. /*****************************************************************************\
  732. * *
  733. * Suspend/resume *
  734. * *
  735. \*****************************************************************************/
  736. #ifdef CONFIG_PM
  737. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  738. {
  739. struct sdhci_chip *chip;
  740. int i, ret;
  741. chip = pci_get_drvdata(pdev);
  742. if (!chip)
  743. return 0;
  744. DBG("Suspending...\n");
  745. for (i = 0;i < chip->num_slots;i++) {
  746. if (!chip->hosts[i])
  747. continue;
  748. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  749. if (ret) {
  750. for (i--;i >= 0;i--)
  751. mmc_resume_host(chip->hosts[i]->mmc);
  752. return ret;
  753. }
  754. }
  755. pci_save_state(pdev);
  756. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  757. pci_disable_device(pdev);
  758. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  759. return 0;
  760. }
  761. static int sdhci_resume (struct pci_dev *pdev)
  762. {
  763. struct sdhci_chip *chip;
  764. int i, ret;
  765. chip = pci_get_drvdata(pdev);
  766. if (!chip)
  767. return 0;
  768. DBG("Resuming...\n");
  769. pci_set_power_state(pdev, PCI_D0);
  770. pci_restore_state(pdev);
  771. pci_enable_device(pdev);
  772. for (i = 0;i < chip->num_slots;i++) {
  773. if (!chip->hosts[i])
  774. continue;
  775. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  776. pci_set_master(pdev);
  777. sdhci_init(chip->hosts[i]);
  778. ret = mmc_resume_host(chip->hosts[i]->mmc);
  779. if (ret)
  780. return ret;
  781. }
  782. return 0;
  783. }
  784. #else /* CONFIG_PM */
  785. #define sdhci_suspend NULL
  786. #define sdhci_resume NULL
  787. #endif /* CONFIG_PM */
  788. /*****************************************************************************\
  789. * *
  790. * Device probing/removal *
  791. * *
  792. \*****************************************************************************/
  793. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  794. {
  795. int ret;
  796. struct sdhci_chip *chip;
  797. struct mmc_host *mmc;
  798. struct sdhci_host *host;
  799. u8 first_bar;
  800. unsigned int caps;
  801. chip = pci_get_drvdata(pdev);
  802. BUG_ON(!chip);
  803. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  804. if (ret)
  805. return ret;
  806. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  807. if (first_bar > 5) {
  808. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  809. return -ENODEV;
  810. }
  811. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  812. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  813. return -ENODEV;
  814. }
  815. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  816. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  817. return -ENODEV;
  818. }
  819. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  820. if (!mmc)
  821. return -ENOMEM;
  822. host = mmc_priv(mmc);
  823. host->mmc = mmc;
  824. host->bar = first_bar + slot;
  825. host->addr = pci_resource_start(pdev, host->bar);
  826. host->irq = pdev->irq;
  827. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  828. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  829. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  830. if (ret)
  831. goto free;
  832. host->ioaddr = ioremap_nocache(host->addr,
  833. pci_resource_len(pdev, host->bar));
  834. if (!host->ioaddr) {
  835. ret = -ENOMEM;
  836. goto release;
  837. }
  838. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  839. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  840. host->flags |= SDHCI_USE_DMA;
  841. if (host->flags & SDHCI_USE_DMA) {
  842. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  843. printk(KERN_WARNING "%s: No suitable DMA available. "
  844. "Falling back to PIO.\n", host->slot_descr);
  845. host->flags &= ~SDHCI_USE_DMA;
  846. }
  847. }
  848. if (host->flags & SDHCI_USE_DMA)
  849. pci_set_master(pdev);
  850. else /* XXX: Hack to get MMC layer to avoid highmem */
  851. pdev->dma_mask = 0;
  852. host->max_clk =
  853. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  854. if (host->max_clk == 0) {
  855. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  856. "frequency.\n", host->slot_descr);
  857. ret = -ENODEV;
  858. goto unmap;
  859. }
  860. host->max_clk *= 1000000;
  861. /*
  862. * Set host parameters.
  863. */
  864. mmc->ops = &sdhci_ops;
  865. mmc->f_min = host->max_clk / 256;
  866. mmc->f_max = host->max_clk;
  867. mmc->caps = MMC_CAP_4_BIT_DATA;
  868. mmc->ocr_avail = 0;
  869. if (caps & SDHCI_CAN_VDD_330)
  870. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  871. else if (caps & SDHCI_CAN_VDD_300)
  872. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  873. else if (caps & SDHCI_CAN_VDD_180)
  874. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  875. if (mmc->ocr_avail == 0) {
  876. printk(KERN_ERR "%s: Hardware doesn't report any "
  877. "support voltages.\n", host->slot_descr);
  878. ret = -ENODEV;
  879. goto unmap;
  880. }
  881. spin_lock_init(&host->lock);
  882. /*
  883. * Maximum number of segments. Hardware cannot do scatter lists.
  884. */
  885. if (host->flags & SDHCI_USE_DMA)
  886. mmc->max_hw_segs = 1;
  887. else
  888. mmc->max_hw_segs = 16;
  889. mmc->max_phys_segs = 16;
  890. /*
  891. * Maximum number of sectors in one transfer. Limited by sector
  892. * count register.
  893. */
  894. mmc->max_sectors = 0x3FFF;
  895. /*
  896. * Maximum segment size. Could be one segment with the maximum number
  897. * of sectors.
  898. */
  899. mmc->max_seg_size = mmc->max_sectors * 512;
  900. /*
  901. * Init tasklets.
  902. */
  903. tasklet_init(&host->card_tasklet,
  904. sdhci_tasklet_card, (unsigned long)host);
  905. tasklet_init(&host->finish_tasklet,
  906. sdhci_tasklet_finish, (unsigned long)host);
  907. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  908. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  909. host->slot_descr, host);
  910. if (ret)
  911. goto untasklet;
  912. sdhci_init(host);
  913. #ifdef CONFIG_MMC_DEBUG
  914. sdhci_dumpregs(host);
  915. #endif
  916. host->chip = chip;
  917. chip->hosts[slot] = host;
  918. mmc_add_host(mmc);
  919. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  920. host->addr, host->irq,
  921. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  922. return 0;
  923. untasklet:
  924. tasklet_kill(&host->card_tasklet);
  925. tasklet_kill(&host->finish_tasklet);
  926. unmap:
  927. iounmap(host->ioaddr);
  928. release:
  929. pci_release_region(pdev, host->bar);
  930. free:
  931. mmc_free_host(mmc);
  932. return ret;
  933. }
  934. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  935. {
  936. struct sdhci_chip *chip;
  937. struct mmc_host *mmc;
  938. struct sdhci_host *host;
  939. chip = pci_get_drvdata(pdev);
  940. host = chip->hosts[slot];
  941. mmc = host->mmc;
  942. chip->hosts[slot] = NULL;
  943. mmc_remove_host(mmc);
  944. sdhci_reset(host, SDHCI_RESET_ALL);
  945. free_irq(host->irq, host);
  946. del_timer_sync(&host->timer);
  947. tasklet_kill(&host->card_tasklet);
  948. tasklet_kill(&host->finish_tasklet);
  949. iounmap(host->ioaddr);
  950. pci_release_region(pdev, host->bar);
  951. mmc_free_host(mmc);
  952. }
  953. static int __devinit sdhci_probe(struct pci_dev *pdev,
  954. const struct pci_device_id *ent)
  955. {
  956. int ret, i;
  957. u8 slots, rev;
  958. struct sdhci_chip *chip;
  959. BUG_ON(pdev == NULL);
  960. BUG_ON(ent == NULL);
  961. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  962. printk(KERN_INFO DRIVER_NAME
  963. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  964. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  965. (int)rev);
  966. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  967. if (ret)
  968. return ret;
  969. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  970. DBG("found %d slot(s)\n", slots);
  971. if (slots == 0)
  972. return -ENODEV;
  973. ret = pci_enable_device(pdev);
  974. if (ret)
  975. return ret;
  976. chip = kzalloc(sizeof(struct sdhci_chip) +
  977. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  978. if (!chip) {
  979. ret = -ENOMEM;
  980. goto err;
  981. }
  982. chip->pdev = pdev;
  983. chip->num_slots = slots;
  984. pci_set_drvdata(pdev, chip);
  985. for (i = 0;i < slots;i++) {
  986. ret = sdhci_probe_slot(pdev, i);
  987. if (ret) {
  988. for (i--;i >= 0;i--)
  989. sdhci_remove_slot(pdev, i);
  990. goto free;
  991. }
  992. }
  993. return 0;
  994. free:
  995. pci_set_drvdata(pdev, NULL);
  996. kfree(chip);
  997. err:
  998. pci_disable_device(pdev);
  999. return ret;
  1000. }
  1001. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1002. {
  1003. int i;
  1004. struct sdhci_chip *chip;
  1005. chip = pci_get_drvdata(pdev);
  1006. if (chip) {
  1007. for (i = 0;i < chip->num_slots;i++)
  1008. sdhci_remove_slot(pdev, i);
  1009. pci_set_drvdata(pdev, NULL);
  1010. kfree(chip);
  1011. }
  1012. pci_disable_device(pdev);
  1013. }
  1014. static struct pci_driver sdhci_driver = {
  1015. .name = DRIVER_NAME,
  1016. .id_table = pci_ids,
  1017. .probe = sdhci_probe,
  1018. .remove = __devexit_p(sdhci_remove),
  1019. .suspend = sdhci_suspend,
  1020. .resume = sdhci_resume,
  1021. };
  1022. /*****************************************************************************\
  1023. * *
  1024. * Driver init/exit *
  1025. * *
  1026. \*****************************************************************************/
  1027. static int __init sdhci_drv_init(void)
  1028. {
  1029. printk(KERN_INFO DRIVER_NAME
  1030. ": Secure Digital Host Controller Interface driver, "
  1031. DRIVER_VERSION "\n");
  1032. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1033. return pci_register_driver(&sdhci_driver);
  1034. }
  1035. static void __exit sdhci_drv_exit(void)
  1036. {
  1037. DBG("Exiting\n");
  1038. pci_unregister_driver(&sdhci_driver);
  1039. }
  1040. module_init(sdhci_drv_init);
  1041. module_exit(sdhci_drv_exit);
  1042. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1043. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1044. MODULE_VERSION(DRIVER_VERSION);
  1045. MODULE_LICENSE("GPL");