iwl-trans-int-pcie.h 7.5 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #ifndef __iwl_trans_int_pcie_h__
  30. #define __iwl_trans_int_pcie_h__
  31. #include <linux/spinlock.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/skbuff.h>
  34. #include "iwl-fh.h"
  35. #include "iwl-csr.h"
  36. #include "iwl-shared.h"
  37. #include "iwl-trans.h"
  38. #include "iwl-debug.h"
  39. #include "iwl-io.h"
  40. struct iwl_tx_queue;
  41. struct iwl_queue;
  42. struct iwl_host_cmd;
  43. /*This file includes the declaration that are internal to the
  44. * trans_pcie layer */
  45. /**
  46. * struct isr_statistics - interrupt statistics
  47. *
  48. */
  49. struct isr_statistics {
  50. u32 hw;
  51. u32 sw;
  52. u32 err_code;
  53. u32 sch;
  54. u32 alive;
  55. u32 rfkill;
  56. u32 ctkill;
  57. u32 wakeup;
  58. u32 rx;
  59. u32 tx;
  60. u32 unhandled;
  61. };
  62. /**
  63. * struct iwl_rx_queue - Rx queue
  64. * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
  65. * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
  66. * @pool:
  67. * @queue:
  68. * @read: Shared index to newest available Rx buffer
  69. * @write: Shared index to oldest written Rx packet
  70. * @free_count: Number of pre-allocated buffers in rx_free
  71. * @write_actual:
  72. * @rx_free: list of free SKBs for use
  73. * @rx_used: List of Rx buffers with no SKB
  74. * @need_update: flag to indicate we need to update read/write index
  75. * @rb_stts: driver's pointer to receive buffer status
  76. * @rb_stts_dma: bus address of receive buffer status
  77. * @lock:
  78. *
  79. * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
  80. */
  81. struct iwl_rx_queue {
  82. __le32 *bd;
  83. dma_addr_t bd_dma;
  84. struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
  85. struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
  86. u32 read;
  87. u32 write;
  88. u32 free_count;
  89. u32 write_actual;
  90. struct list_head rx_free;
  91. struct list_head rx_used;
  92. int need_update;
  93. struct iwl_rb_status *rb_stts;
  94. dma_addr_t rb_stts_dma;
  95. spinlock_t lock;
  96. };
  97. struct iwl_dma_ptr {
  98. dma_addr_t dma;
  99. void *addr;
  100. size_t size;
  101. };
  102. /*
  103. * This queue number is required for proper operation
  104. * because the ucode will stop/start the scheduler as
  105. * required.
  106. */
  107. #define IWL_IPAN_MCAST_QUEUE 8
  108. /**
  109. * struct iwl_trans_pcie - PCIe transport specific data
  110. * @rxq: all the RX queue data
  111. * @rx_replenish: work that will be called when buffers need to be allocated
  112. * @trans: pointer to the generic transport area
  113. * @scd_base_addr: scheduler sram base address in SRAM
  114. * @scd_bc_tbls: pointer to the byte count table of the scheduler
  115. * @kw: keep warm address
  116. * @ac_to_fifo: to what fifo is a specifc AC mapped ?
  117. * @ac_to_queue: to what tx queue is a specifc AC mapped ?
  118. * @mcast_queue:
  119. */
  120. struct iwl_trans_pcie {
  121. struct iwl_rx_queue rxq;
  122. struct work_struct rx_replenish;
  123. struct iwl_trans *trans;
  124. /* INT ICT Table */
  125. __le32 *ict_tbl;
  126. void *ict_tbl_vir;
  127. dma_addr_t ict_tbl_dma;
  128. dma_addr_t aligned_ict_tbl_dma;
  129. int ict_index;
  130. u32 inta;
  131. bool use_ict;
  132. struct tasklet_struct irq_tasklet;
  133. struct isr_statistics isr_stats;
  134. u32 inta_mask;
  135. u32 scd_base_addr;
  136. struct iwl_dma_ptr scd_bc_tbls;
  137. struct iwl_dma_ptr kw;
  138. const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
  139. const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
  140. u8 mcast_queue[NUM_IWL_RXON_CTX];
  141. };
  142. #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
  143. ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
  144. /*****************************************************
  145. * RX
  146. ******************************************************/
  147. void iwl_bg_rx_replenish(struct work_struct *data);
  148. void iwl_irq_tasklet(struct iwl_trans *trans);
  149. void iwlagn_rx_replenish(struct iwl_trans *trans);
  150. void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
  151. struct iwl_rx_queue *q);
  152. /*****************************************************
  153. * ICT
  154. ******************************************************/
  155. int iwl_reset_ict(struct iwl_trans *trans);
  156. void iwl_disable_ict(struct iwl_trans *trans);
  157. int iwl_alloc_isr_ict(struct iwl_trans *trans);
  158. void iwl_free_isr_ict(struct iwl_trans *trans);
  159. irqreturn_t iwl_isr_ict(int irq, void *data);
  160. /*****************************************************
  161. * TX / HCMD
  162. ******************************************************/
  163. void iwl_txq_update_write_ptr(struct iwl_trans *trans,
  164. struct iwl_tx_queue *txq);
  165. int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
  166. struct iwl_tx_queue *txq,
  167. dma_addr_t addr, u16 len, u8 reset);
  168. int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
  169. int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
  170. int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
  171. u32 flags, u16 len, const void *data);
  172. void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
  173. void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
  174. struct iwl_tx_queue *txq,
  175. u16 byte_cnt);
  176. int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id);
  177. void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
  178. void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
  179. struct iwl_tx_queue *txq,
  180. int tx_fifo_id, int scd_retry);
  181. void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
  182. enum iwl_rxon_context_id ctx,
  183. int sta_id, int tid, int frame_limit);
  184. void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
  185. int index);
  186. void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
  187. struct sk_buff_head *skbs);
  188. /*****************************************************
  189. * Error handling
  190. ******************************************************/
  191. int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
  192. char **buf, bool display);
  193. int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
  194. void iwl_dump_csr(struct iwl_trans *trans);
  195. static inline void iwl_disable_interrupts(struct iwl_trans *trans)
  196. {
  197. clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
  198. /* disable interrupts from uCode/NIC to host */
  199. iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
  200. /* acknowledge/clear/reset any interrupts still pending
  201. * from uCode or flow handler (Rx/Tx DMA) */
  202. iwl_write32(bus(trans), CSR_INT, 0xffffffff);
  203. iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
  204. IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
  205. }
  206. static inline void iwl_enable_interrupts(struct iwl_trans *trans)
  207. {
  208. struct iwl_trans_pcie *trans_pcie =
  209. IWL_TRANS_GET_PCIE_TRANS(trans);
  210. IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
  211. set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
  212. iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
  213. }
  214. #endif /* __iwl_trans_int_pcie_h__ */