netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static inline void
  50. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  51. unsigned long off, int *data)
  52. {
  53. void __iomem *addr = pci_base_offset(adapter, off);
  54. writel(*data, addr);
  55. }
  56. static void crb_addr_transform_setup(void)
  57. {
  58. crb_addr_transform(XDMA);
  59. crb_addr_transform(TIMR);
  60. crb_addr_transform(SRE);
  61. crb_addr_transform(SQN3);
  62. crb_addr_transform(SQN2);
  63. crb_addr_transform(SQN1);
  64. crb_addr_transform(SQN0);
  65. crb_addr_transform(SQS3);
  66. crb_addr_transform(SQS2);
  67. crb_addr_transform(SQS1);
  68. crb_addr_transform(SQS0);
  69. crb_addr_transform(RPMX7);
  70. crb_addr_transform(RPMX6);
  71. crb_addr_transform(RPMX5);
  72. crb_addr_transform(RPMX4);
  73. crb_addr_transform(RPMX3);
  74. crb_addr_transform(RPMX2);
  75. crb_addr_transform(RPMX1);
  76. crb_addr_transform(RPMX0);
  77. crb_addr_transform(ROMUSB);
  78. crb_addr_transform(SN);
  79. crb_addr_transform(QMN);
  80. crb_addr_transform(QMS);
  81. crb_addr_transform(PGNI);
  82. crb_addr_transform(PGND);
  83. crb_addr_transform(PGN3);
  84. crb_addr_transform(PGN2);
  85. crb_addr_transform(PGN1);
  86. crb_addr_transform(PGN0);
  87. crb_addr_transform(PGSI);
  88. crb_addr_transform(PGSD);
  89. crb_addr_transform(PGS3);
  90. crb_addr_transform(PGS2);
  91. crb_addr_transform(PGS1);
  92. crb_addr_transform(PGS0);
  93. crb_addr_transform(PS);
  94. crb_addr_transform(PH);
  95. crb_addr_transform(NIU);
  96. crb_addr_transform(I2Q);
  97. crb_addr_transform(EG);
  98. crb_addr_transform(MN);
  99. crb_addr_transform(MS);
  100. crb_addr_transform(CAS2);
  101. crb_addr_transform(CAS1);
  102. crb_addr_transform(CAS0);
  103. crb_addr_transform(CAM);
  104. crb_addr_transform(C2C1);
  105. crb_addr_transform(C2C0);
  106. crb_addr_transform(SMB);
  107. }
  108. int netxen_init_firmware(struct netxen_adapter *adapter)
  109. {
  110. u32 state = 0, loops = 0, err = 0;
  111. /* Window 1 call */
  112. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  113. if (state == PHAN_INITIALIZE_ACK)
  114. return 0;
  115. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  116. udelay(100);
  117. /* Window 1 call */
  118. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  119. loops++;
  120. }
  121. if (loops >= 2000) {
  122. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  123. state);
  124. err = -EIO;
  125. return err;
  126. }
  127. /* Window 1 call */
  128. writel(MPORT_SINGLE_FUNCTION_MODE,
  129. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  130. writel(PHAN_INITIALIZE_ACK,
  131. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  132. return err;
  133. }
  134. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  135. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  136. struct pci_dev **used_dev)
  137. {
  138. void *addr;
  139. addr = pci_alloc_consistent(pdev, sz, ptr);
  140. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  141. *used_dev = pdev;
  142. return addr;
  143. }
  144. pci_free_consistent(pdev, sz, addr, *ptr);
  145. addr = pci_alloc_consistent(NULL, sz, ptr);
  146. *used_dev = NULL;
  147. return addr;
  148. }
  149. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  150. {
  151. int ctxid, ring;
  152. u32 i;
  153. u32 num_rx_bufs = 0;
  154. struct netxen_rcv_desc_ctx *rcv_desc;
  155. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  156. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  157. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  158. struct netxen_rx_buffer *rx_buf;
  159. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  160. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  161. rcv_desc->begin_alloc = 0;
  162. rx_buf = rcv_desc->rx_buf_arr;
  163. num_rx_bufs = rcv_desc->max_rx_desc_count;
  164. /*
  165. * Now go through all of them, set reference handles
  166. * and put them in the queues.
  167. */
  168. for (i = 0; i < num_rx_bufs; i++) {
  169. rx_buf->ref_handle = i;
  170. rx_buf->state = NETXEN_BUFFER_FREE;
  171. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  172. "%p\n", ctxid, i, rx_buf);
  173. rx_buf++;
  174. }
  175. }
  176. }
  177. }
  178. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  179. {
  180. int ports = 0;
  181. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  182. if (netxen_nic_get_board_info(adapter) != 0)
  183. printk("%s: Error getting board config info.\n",
  184. netxen_nic_driver_name);
  185. get_brd_port_by_type(board_info->board_type, &ports);
  186. if (ports == 0)
  187. printk(KERN_ERR "%s: Unknown board type\n",
  188. netxen_nic_driver_name);
  189. adapter->ahw.max_ports = ports;
  190. }
  191. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  192. {
  193. switch (adapter->ahw.board_type) {
  194. case NETXEN_NIC_GBE:
  195. adapter->enable_phy_interrupts =
  196. netxen_niu_gbe_enable_phy_interrupts;
  197. adapter->disable_phy_interrupts =
  198. netxen_niu_gbe_disable_phy_interrupts;
  199. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  200. adapter->macaddr_set = netxen_niu_macaddr_set;
  201. adapter->set_mtu = netxen_nic_set_mtu_gb;
  202. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  203. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  204. adapter->phy_read = netxen_niu_gbe_phy_read;
  205. adapter->phy_write = netxen_niu_gbe_phy_write;
  206. adapter->init_port = netxen_niu_gbe_init_port;
  207. adapter->init_niu = netxen_nic_init_niu_gb;
  208. adapter->stop_port = netxen_niu_disable_gbe_port;
  209. break;
  210. case NETXEN_NIC_XGBE:
  211. adapter->enable_phy_interrupts =
  212. netxen_niu_xgbe_enable_phy_interrupts;
  213. adapter->disable_phy_interrupts =
  214. netxen_niu_xgbe_disable_phy_interrupts;
  215. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  216. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  217. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  218. adapter->init_port = netxen_niu_xg_init_port;
  219. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  220. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  221. adapter->stop_port = netxen_niu_disable_xg_port;
  222. break;
  223. default:
  224. break;
  225. }
  226. }
  227. /*
  228. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  229. * address to external PCI CRB address.
  230. */
  231. u32 netxen_decode_crb_addr(u32 addr)
  232. {
  233. int i;
  234. u32 base_addr, offset, pci_base;
  235. crb_addr_transform_setup();
  236. pci_base = NETXEN_ADDR_ERROR;
  237. base_addr = addr & 0xfff00000;
  238. offset = addr & 0x000fffff;
  239. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  240. if (crb_addr_xform[i] == base_addr) {
  241. pci_base = i << 20;
  242. break;
  243. }
  244. }
  245. if (pci_base == NETXEN_ADDR_ERROR)
  246. return pci_base;
  247. else
  248. return (pci_base + offset);
  249. }
  250. static long rom_max_timeout = 10000;
  251. static long rom_lock_timeout = 1000000;
  252. static long rom_write_timeout = 700;
  253. static inline int rom_lock(struct netxen_adapter *adapter)
  254. {
  255. int iter;
  256. u32 done = 0;
  257. int timeout = 0;
  258. while (!done) {
  259. /* acquire semaphore2 from PCI HW block */
  260. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  261. &done);
  262. if (done == 1)
  263. break;
  264. if (timeout >= rom_lock_timeout)
  265. return -EIO;
  266. timeout++;
  267. /*
  268. * Yield CPU
  269. */
  270. if (!in_atomic())
  271. schedule();
  272. else {
  273. for (iter = 0; iter < 20; iter++)
  274. cpu_relax(); /*This a nop instr on i386 */
  275. }
  276. }
  277. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  278. return 0;
  279. }
  280. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  281. {
  282. long timeout = 0;
  283. long done = 0;
  284. while (done == 0) {
  285. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  286. done &= 2;
  287. timeout++;
  288. if (timeout >= rom_max_timeout) {
  289. printk("Timeout reached waiting for rom done");
  290. return -EIO;
  291. }
  292. }
  293. return 0;
  294. }
  295. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  296. {
  297. /* Set write enable latch in ROM status register */
  298. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  299. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  300. M25P_INSTR_WREN);
  301. if (netxen_wait_rom_done(adapter)) {
  302. return -1;
  303. }
  304. return 0;
  305. }
  306. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  307. unsigned int addr)
  308. {
  309. unsigned int data = 0xdeaddead;
  310. data = netxen_nic_reg_read(adapter, addr);
  311. return data;
  312. }
  313. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  314. {
  315. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  316. M25P_INSTR_RDSR);
  317. if (netxen_wait_rom_done(adapter)) {
  318. return -1;
  319. }
  320. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  321. }
  322. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  323. {
  324. u32 val;
  325. /* release semaphore2 */
  326. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  327. }
  328. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  329. {
  330. long timeout = 0;
  331. long wip = 1;
  332. int val;
  333. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  334. while (wip != 0) {
  335. val = netxen_do_rom_rdsr(adapter);
  336. wip = val & 1;
  337. timeout++;
  338. if (timeout > rom_max_timeout) {
  339. return -1;
  340. }
  341. }
  342. return 0;
  343. }
  344. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  345. int data)
  346. {
  347. if (netxen_rom_wren(adapter)) {
  348. return -1;
  349. }
  350. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  351. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  354. M25P_INSTR_PP);
  355. if (netxen_wait_rom_done(adapter)) {
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  357. return -1;
  358. }
  359. return netxen_rom_wip_poll(adapter);
  360. }
  361. static inline int
  362. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  363. {
  364. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  365. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  366. udelay(70); /* prevent bursting on CRB */
  367. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  369. if (netxen_wait_rom_done(adapter)) {
  370. printk("Error waiting for rom done\n");
  371. return -EIO;
  372. }
  373. /* reset abyte_cnt and dummy_byte_cnt */
  374. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  375. udelay(70); /* prevent bursting on CRB */
  376. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  377. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  378. return 0;
  379. }
  380. static inline int
  381. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  382. u8 *bytes, size_t size)
  383. {
  384. int addridx;
  385. int ret = 0;
  386. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  387. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  388. if (ret != 0)
  389. break;
  390. bytes += 4;
  391. }
  392. return ret;
  393. }
  394. int
  395. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  396. u8 *bytes, size_t size)
  397. {
  398. int ret;
  399. ret = rom_lock(adapter);
  400. if (ret < 0)
  401. return ret;
  402. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  403. netxen_rom_unlock(adapter);
  404. return ret;
  405. }
  406. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  407. {
  408. int ret;
  409. if (rom_lock(adapter) != 0)
  410. return -EIO;
  411. ret = do_rom_fast_read(adapter, addr, valp);
  412. netxen_rom_unlock(adapter);
  413. return ret;
  414. }
  415. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  416. {
  417. int ret = 0;
  418. if (rom_lock(adapter) != 0) {
  419. return -1;
  420. }
  421. ret = do_rom_fast_write(adapter, addr, data);
  422. netxen_rom_unlock(adapter);
  423. return ret;
  424. }
  425. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  426. int addr, u8 *bytes, size_t size)
  427. {
  428. int addridx = addr;
  429. int ret = 0;
  430. while (addridx < (addr + size)) {
  431. int last_attempt = 0;
  432. int timeout = 0;
  433. int data;
  434. data = *(u32*)bytes;
  435. ret = do_rom_fast_write(adapter, addridx, data);
  436. if (ret < 0)
  437. return ret;
  438. while(1) {
  439. int data1;
  440. ret = do_rom_fast_read(adapter, addridx, &data1);
  441. if (ret < 0)
  442. return ret;
  443. if (data1 == data)
  444. break;
  445. if (timeout++ >= rom_write_timeout) {
  446. if (last_attempt++ < 4) {
  447. ret = do_rom_fast_write(adapter,
  448. addridx, data);
  449. if (ret < 0)
  450. return ret;
  451. }
  452. else {
  453. printk(KERN_INFO "Data write did not "
  454. "succeed at address 0x%x\n", addridx);
  455. break;
  456. }
  457. }
  458. }
  459. bytes += 4;
  460. addridx += 4;
  461. }
  462. return ret;
  463. }
  464. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  465. u8 *bytes, size_t size)
  466. {
  467. int ret = 0;
  468. ret = rom_lock(adapter);
  469. if (ret < 0)
  470. return ret;
  471. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  472. netxen_rom_unlock(adapter);
  473. return ret;
  474. }
  475. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  476. {
  477. int ret;
  478. ret = netxen_rom_wren(adapter);
  479. if (ret < 0)
  480. return ret;
  481. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  482. netxen_crb_writelit_adapter(adapter,
  483. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  484. ret = netxen_wait_rom_done(adapter);
  485. if (ret < 0)
  486. return ret;
  487. return netxen_rom_wip_poll(adapter);
  488. }
  489. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  490. {
  491. int ret;
  492. ret = rom_lock(adapter);
  493. if (ret < 0)
  494. return ret;
  495. ret = netxen_do_rom_rdsr(adapter);
  496. netxen_rom_unlock(adapter);
  497. return ret;
  498. }
  499. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  500. {
  501. int ret = FLASH_SUCCESS;
  502. int val;
  503. char *buffer = kmalloc(FLASH_SECTOR_SIZE, GFP_KERNEL);
  504. if (!buffer)
  505. return -ENOMEM;
  506. /* unlock sector 63 */
  507. val = netxen_rom_rdsr(adapter);
  508. val = val & 0xe3;
  509. ret = netxen_rom_wrsr(adapter, val);
  510. if (ret != FLASH_SUCCESS)
  511. goto out_kfree;
  512. ret = netxen_rom_wip_poll(adapter);
  513. if (ret != FLASH_SUCCESS)
  514. goto out_kfree;
  515. /* copy sector 0 to sector 63 */
  516. ret = netxen_rom_fast_read_words(adapter, CRBINIT_START,
  517. buffer, FLASH_SECTOR_SIZE);
  518. if (ret != FLASH_SUCCESS)
  519. goto out_kfree;
  520. ret = netxen_rom_fast_write_words(adapter, FIXED_START,
  521. buffer, FLASH_SECTOR_SIZE);
  522. if (ret != FLASH_SUCCESS)
  523. goto out_kfree;
  524. /* lock sector 63 */
  525. val = netxen_rom_rdsr(adapter);
  526. if (!(val & 0x8)) {
  527. val |= (0x1 << 2);
  528. /* lock sector 63 */
  529. if (netxen_rom_wrsr(adapter, val) == 0) {
  530. ret = netxen_rom_wip_poll(adapter);
  531. if (ret != FLASH_SUCCESS)
  532. goto out_kfree;
  533. /* lock SR writes */
  534. ret = netxen_rom_wip_poll(adapter);
  535. if (ret != FLASH_SUCCESS)
  536. goto out_kfree;
  537. }
  538. }
  539. out_kfree:
  540. kfree(buffer);
  541. return ret;
  542. }
  543. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  544. {
  545. netxen_rom_wren(adapter);
  546. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  547. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  548. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  549. M25P_INSTR_SE);
  550. if (netxen_wait_rom_done(adapter)) {
  551. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  552. return -1;
  553. }
  554. return netxen_rom_wip_poll(adapter);
  555. }
  556. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  557. {
  558. int i;
  559. int val;
  560. int count = 0, erased_errors = 0;
  561. int range;
  562. range = (addr == USER_START) ? FIXED_START : addr + FLASH_SECTOR_SIZE;
  563. for (i = addr; i < range; i += 4) {
  564. netxen_rom_fast_read(adapter, i, &val);
  565. if (val != 0xffffffff)
  566. erased_errors++;
  567. count++;
  568. }
  569. if (erased_errors)
  570. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  571. "for sector address: %x\n", erased_errors, count, addr);
  572. }
  573. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  574. {
  575. int ret = 0;
  576. if (rom_lock(adapter) != 0) {
  577. return -1;
  578. }
  579. ret = netxen_do_rom_se(adapter, addr);
  580. netxen_rom_unlock(adapter);
  581. msleep(30);
  582. check_erased_flash(adapter, addr);
  583. return ret;
  584. }
  585. int
  586. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  587. {
  588. int ret = FLASH_SUCCESS;
  589. int i;
  590. for (i = start; i < end; i++) {
  591. ret = netxen_rom_se(adapter, i * FLASH_SECTOR_SIZE);
  592. if (ret)
  593. break;
  594. ret = netxen_rom_wip_poll(adapter);
  595. if (ret < 0)
  596. return ret;
  597. }
  598. return ret;
  599. }
  600. int
  601. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  602. {
  603. int ret = FLASH_SUCCESS;
  604. int start, end;
  605. start = SECONDARY_START / FLASH_SECTOR_SIZE;
  606. end = USER_START / FLASH_SECTOR_SIZE;
  607. ret = netxen_flash_erase_sections(adapter, start, end);
  608. return ret;
  609. }
  610. int
  611. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  612. {
  613. int ret = FLASH_SUCCESS;
  614. int start, end;
  615. start = PRIMARY_START / FLASH_SECTOR_SIZE;
  616. end = SECONDARY_START / FLASH_SECTOR_SIZE;
  617. ret = netxen_flash_erase_sections(adapter, start, end);
  618. return ret;
  619. }
  620. void netxen_halt_pegs(struct netxen_adapter *adapter)
  621. {
  622. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  623. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  624. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  625. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  626. }
  627. int netxen_flash_unlock(struct netxen_adapter *adapter)
  628. {
  629. int ret = 0;
  630. ret = netxen_rom_wrsr(adapter, 0);
  631. if (ret < 0)
  632. return ret;
  633. ret = netxen_rom_wren(adapter);
  634. if (ret < 0)
  635. return ret;
  636. return ret;
  637. }
  638. #define NETXEN_BOARDTYPE 0x4008
  639. #define NETXEN_BOARDNUM 0x400c
  640. #define NETXEN_CHIPNUM 0x4010
  641. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  642. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  643. #define NETXEN_ROM_FOUND_INIT 0x400
  644. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  645. {
  646. int addr, val, status;
  647. int n, i;
  648. int init_delay = 0;
  649. struct crb_addr_pair *buf;
  650. u32 off;
  651. /* resetall */
  652. status = netxen_nic_get_board_info(adapter);
  653. if (status)
  654. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  655. netxen_nic_driver_name);
  656. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  657. NETXEN_ROMBUS_RESET);
  658. if (verbose) {
  659. int val;
  660. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  661. printk("P2 ROM board type: 0x%08x\n", val);
  662. else
  663. printk("Could not read board type\n");
  664. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  665. printk("P2 ROM board num: 0x%08x\n", val);
  666. else
  667. printk("Could not read board number\n");
  668. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  669. printk("P2 ROM chip num: 0x%08x\n", val);
  670. else
  671. printk("Could not read chip number\n");
  672. }
  673. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  674. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  675. n &= ~NETXEN_ROM_ROUNDUP;
  676. if (n < NETXEN_ROM_FOUND_INIT) {
  677. if (verbose)
  678. printk("%s: %d CRB init values found"
  679. " in ROM.\n", netxen_nic_driver_name, n);
  680. } else {
  681. printk("%s:n=0x%x Error! NetXen card flash not"
  682. " initialized.\n", __FUNCTION__, n);
  683. return -EIO;
  684. }
  685. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  686. if (buf == NULL) {
  687. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  688. "memory.\n", netxen_nic_driver_name);
  689. return -ENOMEM;
  690. }
  691. for (i = 0; i < n; i++) {
  692. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  693. || netxen_rom_fast_read(adapter, 8 * i + 8,
  694. &addr) != 0)
  695. return -EIO;
  696. buf[i].addr = addr;
  697. buf[i].data = val;
  698. if (verbose)
  699. printk("%s: PCI: 0x%08x == 0x%08x\n",
  700. netxen_nic_driver_name, (unsigned int)
  701. netxen_decode_crb_addr(addr), val);
  702. }
  703. for (i = 0; i < n; i++) {
  704. off = netxen_decode_crb_addr(buf[i].addr);
  705. if (off == NETXEN_ADDR_ERROR) {
  706. printk(KERN_ERR"CRB init value out of range %x\n",
  707. buf[i].addr);
  708. continue;
  709. }
  710. off += NETXEN_PCI_CRBSPACE;
  711. /* skipping cold reboot MAGIC */
  712. if (off == NETXEN_CAM_RAM(0x1fc))
  713. continue;
  714. /* After writing this register, HW needs time for CRB */
  715. /* to quiet down (else crb_window returns 0xffffffff) */
  716. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  717. init_delay = 1;
  718. /* hold xdma in reset also */
  719. buf[i].data = NETXEN_NIC_XDMA_RESET;
  720. }
  721. if (ADDR_IN_WINDOW1(off)) {
  722. writel(buf[i].data,
  723. NETXEN_CRB_NORMALIZE(adapter, off));
  724. } else {
  725. netxen_nic_pci_change_crbwindow(adapter, 0);
  726. writel(buf[i].data,
  727. pci_base_offset(adapter, off));
  728. netxen_nic_pci_change_crbwindow(adapter, 1);
  729. }
  730. if (init_delay == 1) {
  731. ssleep(1);
  732. init_delay = 0;
  733. }
  734. msleep(1);
  735. }
  736. kfree(buf);
  737. /* disable_peg_cache_all */
  738. /* unreset_net_cache */
  739. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  740. 4);
  741. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  742. (val & 0xffffff0f));
  743. /* p2dn replyCount */
  744. netxen_crb_writelit_adapter(adapter,
  745. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  746. /* disable_peg_cache 0 */
  747. netxen_crb_writelit_adapter(adapter,
  748. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  749. /* disable_peg_cache 1 */
  750. netxen_crb_writelit_adapter(adapter,
  751. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  752. /* peg_clr_all */
  753. /* peg_clr 0 */
  754. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  755. 0);
  756. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  757. 0);
  758. /* peg_clr 1 */
  759. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  760. 0);
  761. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  762. 0);
  763. /* peg_clr 2 */
  764. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  765. 0);
  766. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  767. 0);
  768. /* peg_clr 3 */
  769. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  770. 0);
  771. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  772. 0);
  773. }
  774. return 0;
  775. }
  776. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  777. {
  778. uint64_t addr;
  779. uint32_t hi;
  780. uint32_t lo;
  781. adapter->dummy_dma.addr =
  782. pci_alloc_consistent(adapter->ahw.pdev,
  783. NETXEN_HOST_DUMMY_DMA_SIZE,
  784. &adapter->dummy_dma.phys_addr);
  785. if (adapter->dummy_dma.addr == NULL) {
  786. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  787. __FUNCTION__);
  788. return -ENOMEM;
  789. }
  790. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  791. hi = (addr >> 32) & 0xffffffff;
  792. lo = addr & 0xffffffff;
  793. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  794. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  795. return 0;
  796. }
  797. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  798. {
  799. if (adapter->dummy_dma.addr) {
  800. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  801. CRB_HOST_DUMMY_BUF_ADDR_HI));
  802. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  803. CRB_HOST_DUMMY_BUF_ADDR_LO));
  804. pci_free_consistent(adapter->ahw.pdev,
  805. NETXEN_HOST_DUMMY_DMA_SIZE,
  806. adapter->dummy_dma.addr,
  807. adapter->dummy_dma.phys_addr);
  808. adapter->dummy_dma.addr = NULL;
  809. }
  810. }
  811. void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  812. {
  813. u32 val = 0;
  814. int loops = 0;
  815. if (!pegtune_val) {
  816. val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  817. while (val != PHAN_INITIALIZE_COMPLETE && loops < 200000) {
  818. udelay(100);
  819. schedule();
  820. val =
  821. readl(NETXEN_CRB_NORMALIZE
  822. (adapter, CRB_CMDPEG_STATE));
  823. loops++;
  824. }
  825. if (val != PHAN_INITIALIZE_COMPLETE)
  826. printk("WARNING: Initial boot wait loop failed...\n");
  827. }
  828. }
  829. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  830. {
  831. int ctx;
  832. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  833. struct netxen_recv_context *recv_ctx =
  834. &(adapter->recv_ctx[ctx]);
  835. u32 consumer;
  836. struct status_desc *desc_head;
  837. struct status_desc *desc;
  838. consumer = recv_ctx->status_rx_consumer;
  839. desc_head = recv_ctx->rcv_status_desc_head;
  840. desc = &desc_head[consumer];
  841. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  842. return 1;
  843. }
  844. return 0;
  845. }
  846. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  847. {
  848. int port_num;
  849. struct netxen_port *port;
  850. struct net_device *netdev;
  851. uint32_t temp, temp_state, temp_val;
  852. int rv = 0;
  853. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  854. temp_state = nx_get_temp_state(temp);
  855. temp_val = nx_get_temp_val(temp);
  856. if (temp_state == NX_TEMP_PANIC) {
  857. printk(KERN_ALERT
  858. "%s: Device temperature %d degrees C exceeds"
  859. " maximum allowed. Hardware has been shut down.\n",
  860. netxen_nic_driver_name, temp_val);
  861. for (port_num = 0; port_num < adapter->ahw.max_ports;
  862. port_num++) {
  863. port = adapter->port[port_num];
  864. netdev = port->netdev;
  865. netif_carrier_off(netdev);
  866. netif_stop_queue(netdev);
  867. }
  868. rv = 1;
  869. } else if (temp_state == NX_TEMP_WARN) {
  870. if (adapter->temp == NX_TEMP_NORMAL) {
  871. printk(KERN_ALERT
  872. "%s: Device temperature %d degrees C "
  873. "exceeds operating range."
  874. " Immediate action needed.\n",
  875. netxen_nic_driver_name, temp_val);
  876. }
  877. } else {
  878. if (adapter->temp == NX_TEMP_WARN) {
  879. printk(KERN_INFO
  880. "%s: Device temperature is now %d degrees C"
  881. " in normal range.\n", netxen_nic_driver_name,
  882. temp_val);
  883. }
  884. }
  885. adapter->temp = temp_state;
  886. return rv;
  887. }
  888. void netxen_watchdog_task(struct work_struct *work)
  889. {
  890. int port_num;
  891. struct netxen_port *port;
  892. struct net_device *netdev;
  893. struct netxen_adapter *adapter =
  894. container_of(work, struct netxen_adapter, watchdog_task);
  895. if (netxen_nic_check_temp(adapter))
  896. return;
  897. for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
  898. port = adapter->port[port_num];
  899. netdev = port->netdev;
  900. if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
  901. printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
  902. netxen_nic_driver_name, port_num, netdev->name);
  903. netif_carrier_on(netdev);
  904. }
  905. if (netif_queue_stopped(netdev))
  906. netif_wake_queue(netdev);
  907. }
  908. if (adapter->handle_phy_intr)
  909. adapter->handle_phy_intr(adapter);
  910. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  911. }
  912. /*
  913. * netxen_process_rcv() send the received packet to the protocol stack.
  914. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  915. * invoke the routine to send more rx buffers to the Phantom...
  916. */
  917. void
  918. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  919. struct status_desc *desc)
  920. {
  921. struct netxen_port *port = adapter->port[netxen_get_sts_port(desc)];
  922. struct pci_dev *pdev = port->pdev;
  923. struct net_device *netdev = port->netdev;
  924. int index = netxen_get_sts_refhandle(desc);
  925. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  926. struct netxen_rx_buffer *buffer;
  927. struct sk_buff *skb;
  928. u32 length = netxen_get_sts_totallength(desc);
  929. u32 desc_ctx;
  930. struct netxen_rcv_desc_ctx *rcv_desc;
  931. int ret;
  932. desc_ctx = netxen_get_sts_type(desc);
  933. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  934. printk("%s: %s Bad Rcv descriptor ring\n",
  935. netxen_nic_driver_name, netdev->name);
  936. return;
  937. }
  938. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  939. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  940. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  941. index, rcv_desc->max_rx_desc_count);
  942. return;
  943. }
  944. buffer = &rcv_desc->rx_buf_arr[index];
  945. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  946. buffer->lro_current_frags++;
  947. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  948. buffer->lro_expected_frags =
  949. netxen_get_sts_desc_lro_cnt(desc);
  950. buffer->lro_length = length;
  951. }
  952. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  953. if (buffer->lro_expected_frags != 0) {
  954. printk("LRO: (refhandle:%x) recv frag."
  955. "wait for last. flags: %x expected:%d"
  956. "have:%d\n", index,
  957. netxen_get_sts_desc_lro_last_frag(desc),
  958. buffer->lro_expected_frags,
  959. buffer->lro_current_frags);
  960. }
  961. return;
  962. }
  963. }
  964. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  965. PCI_DMA_FROMDEVICE);
  966. skb = (struct sk_buff *)buffer->skb;
  967. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  968. port->stats.csummed++;
  969. skb->ip_summed = CHECKSUM_UNNECESSARY;
  970. }
  971. skb->dev = netdev;
  972. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  973. /* True length was only available on the last pkt */
  974. skb_put(skb, buffer->lro_length);
  975. } else {
  976. skb_put(skb, length);
  977. }
  978. skb->protocol = eth_type_trans(skb, netdev);
  979. ret = netif_receive_skb(skb);
  980. /*
  981. * RH: Do we need these stats on a regular basis. Can we get it from
  982. * Linux stats.
  983. */
  984. switch (ret) {
  985. case NET_RX_SUCCESS:
  986. port->stats.uphappy++;
  987. break;
  988. case NET_RX_CN_LOW:
  989. port->stats.uplcong++;
  990. break;
  991. case NET_RX_CN_MOD:
  992. port->stats.upmcong++;
  993. break;
  994. case NET_RX_CN_HIGH:
  995. port->stats.uphcong++;
  996. break;
  997. case NET_RX_DROP:
  998. port->stats.updropped++;
  999. break;
  1000. default:
  1001. port->stats.updunno++;
  1002. break;
  1003. }
  1004. netdev->last_rx = jiffies;
  1005. rcv_desc->rcv_free++;
  1006. rcv_desc->rcv_pending--;
  1007. /*
  1008. * We just consumed one buffer so post a buffer.
  1009. */
  1010. adapter->stats.post_called++;
  1011. buffer->skb = NULL;
  1012. buffer->state = NETXEN_BUFFER_FREE;
  1013. buffer->lro_current_frags = 0;
  1014. buffer->lro_expected_frags = 0;
  1015. port->stats.no_rcv++;
  1016. port->stats.rxbytes += length;
  1017. }
  1018. /* Process Receive status ring */
  1019. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1020. {
  1021. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1022. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1023. struct status_desc *desc; /* used to read status desc here */
  1024. u32 consumer = recv_ctx->status_rx_consumer;
  1025. u32 producer = 0;
  1026. int count = 0, ring;
  1027. DPRINTK(INFO, "procesing receive\n");
  1028. /*
  1029. * we assume in this case that there is only one port and that is
  1030. * port #1...changes need to be done in firmware to indicate port
  1031. * number as part of the descriptor. This way we will be able to get
  1032. * the netdev which is associated with that device.
  1033. */
  1034. while (count < max) {
  1035. desc = &desc_head[consumer];
  1036. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1037. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1038. netxen_get_sts_owner(desc));
  1039. break;
  1040. }
  1041. netxen_process_rcv(adapter, ctxid, desc);
  1042. netxen_clear_sts_owner(desc);
  1043. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1044. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1045. count++;
  1046. }
  1047. if (count) {
  1048. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1049. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1050. }
  1051. }
  1052. /* update the consumer index in phantom */
  1053. if (count) {
  1054. adapter->stats.process_rcv++;
  1055. recv_ctx->status_rx_consumer = consumer;
  1056. recv_ctx->status_rx_producer = producer;
  1057. /* Window = 1 */
  1058. writel(consumer,
  1059. NETXEN_CRB_NORMALIZE(adapter,
  1060. recv_crb_registers[ctxid].
  1061. crb_rcv_status_consumer));
  1062. }
  1063. return count;
  1064. }
  1065. /* Process Command status ring */
  1066. int netxen_process_cmd_ring(unsigned long data)
  1067. {
  1068. u32 last_consumer;
  1069. u32 consumer;
  1070. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1071. int count1 = 0;
  1072. int count2 = 0;
  1073. struct netxen_cmd_buffer *buffer;
  1074. struct netxen_port *port; /* port #1 */
  1075. struct netxen_port *nport;
  1076. struct pci_dev *pdev;
  1077. struct netxen_skb_frag *frag;
  1078. u32 i;
  1079. struct sk_buff *skb = NULL;
  1080. int p;
  1081. int done;
  1082. spin_lock(&adapter->tx_lock);
  1083. last_consumer = adapter->last_cmd_consumer;
  1084. DPRINTK(INFO, "procesing xmit complete\n");
  1085. /* we assume in this case that there is only one port and that is
  1086. * port #1...changes need to be done in firmware to indicate port
  1087. * number as part of the descriptor. This way we will be able to get
  1088. * the netdev which is associated with that device.
  1089. */
  1090. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1091. if (last_consumer == consumer) { /* Ring is empty */
  1092. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1093. last_consumer, consumer);
  1094. spin_unlock(&adapter->tx_lock);
  1095. return 1;
  1096. }
  1097. adapter->proc_cmd_buf_counter++;
  1098. adapter->stats.process_xmit++;
  1099. /*
  1100. * Not needed - does not seem to be used anywhere.
  1101. * adapter->cmd_consumer = consumer;
  1102. */
  1103. spin_unlock(&adapter->tx_lock);
  1104. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1105. buffer = &adapter->cmd_buf_arr[last_consumer];
  1106. port = adapter->port[buffer->port];
  1107. pdev = port->pdev;
  1108. frag = &buffer->frag_array[0];
  1109. skb = buffer->skb;
  1110. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1111. pci_unmap_single(pdev, frag->dma, frag->length,
  1112. PCI_DMA_TODEVICE);
  1113. for (i = 1; i < buffer->frag_count; i++) {
  1114. DPRINTK(INFO, "getting fragment no %d\n", i);
  1115. frag++; /* Get the next frag */
  1116. pci_unmap_page(pdev, frag->dma, frag->length,
  1117. PCI_DMA_TODEVICE);
  1118. }
  1119. port->stats.skbfreed++;
  1120. dev_kfree_skb_any(skb);
  1121. skb = NULL;
  1122. } else if (adapter->proc_cmd_buf_counter == 1) {
  1123. port->stats.txnullskb++;
  1124. }
  1125. if (unlikely(netif_queue_stopped(port->netdev)
  1126. && netif_carrier_ok(port->netdev))
  1127. && ((jiffies - port->netdev->trans_start) >
  1128. port->netdev->watchdog_timeo)) {
  1129. SCHEDULE_WORK(&port->tx_timeout_task);
  1130. }
  1131. last_consumer = get_next_index(last_consumer,
  1132. adapter->max_tx_desc_count);
  1133. count1++;
  1134. }
  1135. adapter->stats.noxmitdone += count1;
  1136. count2 = 0;
  1137. spin_lock(&adapter->tx_lock);
  1138. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1139. adapter->last_cmd_consumer = last_consumer;
  1140. while ((adapter->last_cmd_consumer != consumer)
  1141. && (count2 < MAX_STATUS_HANDLE)) {
  1142. buffer =
  1143. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1144. count2++;
  1145. if (buffer->skb)
  1146. break;
  1147. else
  1148. adapter->last_cmd_consumer =
  1149. get_next_index(adapter->last_cmd_consumer,
  1150. adapter->max_tx_desc_count);
  1151. }
  1152. }
  1153. if (count1 || count2) {
  1154. for (p = 0; p < adapter->ahw.max_ports; p++) {
  1155. nport = adapter->port[p];
  1156. if (netif_queue_stopped(nport->netdev)
  1157. && (nport->flags & NETXEN_NETDEV_STATUS)) {
  1158. netif_wake_queue(nport->netdev);
  1159. nport->flags &= ~NETXEN_NETDEV_STATUS;
  1160. }
  1161. }
  1162. }
  1163. /*
  1164. * If everything is freed up to consumer then check if the ring is full
  1165. * If the ring is full then check if more needs to be freed and
  1166. * schedule the call back again.
  1167. *
  1168. * This happens when there are 2 CPUs. One could be freeing and the
  1169. * other filling it. If the ring is full when we get out of here and
  1170. * the card has already interrupted the host then the host can miss the
  1171. * interrupt.
  1172. *
  1173. * There is still a possible race condition and the host could miss an
  1174. * interrupt. The card has to take care of this.
  1175. */
  1176. if (adapter->last_cmd_consumer == consumer &&
  1177. (((adapter->cmd_producer + 1) %
  1178. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1179. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1180. }
  1181. done = (adapter->last_cmd_consumer == consumer);
  1182. spin_unlock(&adapter->tx_lock);
  1183. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1184. __FUNCTION__);
  1185. return (done);
  1186. }
  1187. /*
  1188. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1189. */
  1190. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1191. {
  1192. struct pci_dev *pdev = adapter->ahw.pdev;
  1193. struct sk_buff *skb;
  1194. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1195. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1196. uint producer;
  1197. struct rcv_desc *pdesc;
  1198. struct netxen_rx_buffer *buffer;
  1199. int count = 0;
  1200. int index = 0;
  1201. netxen_ctx_msg msg = 0;
  1202. dma_addr_t dma;
  1203. adapter->stats.post_called++;
  1204. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1205. producer = rcv_desc->producer;
  1206. index = rcv_desc->begin_alloc;
  1207. buffer = &rcv_desc->rx_buf_arr[index];
  1208. /* We can start writing rx descriptors into the phantom memory. */
  1209. while (buffer->state == NETXEN_BUFFER_FREE) {
  1210. skb = dev_alloc_skb(rcv_desc->skb_size);
  1211. if (unlikely(!skb)) {
  1212. /*
  1213. * TODO
  1214. * We need to schedule the posting of buffers to the pegs.
  1215. */
  1216. rcv_desc->begin_alloc = index;
  1217. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1218. " allocated only %d buffers\n", count);
  1219. break;
  1220. }
  1221. count++; /* now there should be no failure */
  1222. pdesc = &rcv_desc->desc_head[producer];
  1223. #if defined(XGB_DEBUG)
  1224. *(unsigned long *)(skb->head) = 0xc0debabe;
  1225. if (skb_is_nonlinear(skb)) {
  1226. printk("Allocated SKB @%p is nonlinear\n");
  1227. }
  1228. #endif
  1229. skb_reserve(skb, 2);
  1230. /* This will be setup when we receive the
  1231. * buffer after it has been filled FSL TBD TBD
  1232. * skb->dev = netdev;
  1233. */
  1234. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1235. PCI_DMA_FROMDEVICE);
  1236. pdesc->addr_buffer = cpu_to_le64(dma);
  1237. buffer->skb = skb;
  1238. buffer->state = NETXEN_BUFFER_BUSY;
  1239. buffer->dma = dma;
  1240. /* make a rcv descriptor */
  1241. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1242. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1243. DPRINTK(INFO, "done writing descripter\n");
  1244. producer =
  1245. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1246. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1247. buffer = &rcv_desc->rx_buf_arr[index];
  1248. }
  1249. /* if we did allocate buffers, then write the count to Phantom */
  1250. if (count) {
  1251. rcv_desc->begin_alloc = index;
  1252. rcv_desc->rcv_pending += count;
  1253. adapter->stats.lastposted = count;
  1254. adapter->stats.posted += count;
  1255. rcv_desc->producer = producer;
  1256. if (rcv_desc->rcv_free >= 32) {
  1257. rcv_desc->rcv_free = 0;
  1258. /* Window = 1 */
  1259. writel((producer - 1) &
  1260. (rcv_desc->max_rx_desc_count - 1),
  1261. NETXEN_CRB_NORMALIZE(adapter,
  1262. recv_crb_registers[0].
  1263. rcv_desc_crb[ringid].
  1264. crb_rcv_producer_offset));
  1265. /*
  1266. * Write a doorbell msg to tell phanmon of change in
  1267. * receive ring producer
  1268. */
  1269. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1270. netxen_set_msg_privid(msg);
  1271. netxen_set_msg_count(msg,
  1272. ((producer -
  1273. 1) & (rcv_desc->
  1274. max_rx_desc_count - 1)));
  1275. netxen_set_msg_ctxid(msg, 0);
  1276. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1277. writel(msg,
  1278. DB_NORMALIZE(adapter,
  1279. NETXEN_RCV_PRODUCER_OFFSET));
  1280. }
  1281. }
  1282. }
  1283. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1284. uint32_t ringid)
  1285. {
  1286. struct pci_dev *pdev = adapter->ahw.pdev;
  1287. struct sk_buff *skb;
  1288. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1289. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1290. u32 producer;
  1291. struct rcv_desc *pdesc;
  1292. struct netxen_rx_buffer *buffer;
  1293. int count = 0;
  1294. int index = 0;
  1295. adapter->stats.post_called++;
  1296. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1297. producer = rcv_desc->producer;
  1298. index = rcv_desc->begin_alloc;
  1299. buffer = &rcv_desc->rx_buf_arr[index];
  1300. /* We can start writing rx descriptors into the phantom memory. */
  1301. while (buffer->state == NETXEN_BUFFER_FREE) {
  1302. skb = dev_alloc_skb(rcv_desc->skb_size);
  1303. if (unlikely(!skb)) {
  1304. /*
  1305. * We need to schedule the posting of buffers to the pegs.
  1306. */
  1307. rcv_desc->begin_alloc = index;
  1308. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1309. " allocated only %d buffers\n", count);
  1310. break;
  1311. }
  1312. count++; /* now there should be no failure */
  1313. pdesc = &rcv_desc->desc_head[producer];
  1314. skb_reserve(skb, 2);
  1315. /*
  1316. * This will be setup when we receive the
  1317. * buffer after it has been filled
  1318. * skb->dev = netdev;
  1319. */
  1320. buffer->skb = skb;
  1321. buffer->state = NETXEN_BUFFER_BUSY;
  1322. buffer->dma = pci_map_single(pdev, skb->data,
  1323. rcv_desc->dma_size,
  1324. PCI_DMA_FROMDEVICE);
  1325. /* make a rcv descriptor */
  1326. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1327. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1328. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1329. DPRINTK(INFO, "done writing descripter\n");
  1330. producer =
  1331. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1332. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1333. buffer = &rcv_desc->rx_buf_arr[index];
  1334. }
  1335. /* if we did allocate buffers, then write the count to Phantom */
  1336. if (count) {
  1337. rcv_desc->begin_alloc = index;
  1338. rcv_desc->rcv_pending += count;
  1339. adapter->stats.lastposted = count;
  1340. adapter->stats.posted += count;
  1341. rcv_desc->producer = producer;
  1342. if (rcv_desc->rcv_free >= 32) {
  1343. rcv_desc->rcv_free = 0;
  1344. /* Window = 1 */
  1345. writel((producer - 1) &
  1346. (rcv_desc->max_rx_desc_count - 1),
  1347. NETXEN_CRB_NORMALIZE(adapter,
  1348. recv_crb_registers[0].
  1349. rcv_desc_crb[ringid].
  1350. crb_rcv_producer_offset));
  1351. wmb();
  1352. }
  1353. }
  1354. }
  1355. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1356. {
  1357. if (find_diff_among(adapter->last_cmd_consumer,
  1358. adapter->cmd_producer,
  1359. adapter->max_tx_desc_count) > 0)
  1360. return 1;
  1361. return 0;
  1362. }
  1363. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1364. {
  1365. struct netxen_port *port;
  1366. int port_num;
  1367. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1368. for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
  1369. port = adapter->port[port_num];
  1370. memset(&port->stats, 0, sizeof(port->stats));
  1371. }
  1372. }