mantis_hif.c 6.6 KB

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  1. /*
  2. Mantis PCI bridge driver
  3. Copyright (C) 2005, 2006 Manu Abraham (abraham.manu@gmail.com)
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. */
  16. #include "mantis_common.h"
  17. #include "mantis_hif.h"
  18. #include "mantis_link.h" /* temporary due to physical layer stuff */
  19. static int mantis_hif_data_available(struct mantis_ca *ca)
  20. {
  21. struct mantis_pci *mantis = ca->ca_priv;
  22. int rc = 0;
  23. if (wait_event_interruptible_timeout(ca->hif_data_wq,
  24. ca->sbuf_status & MANTIS_SBUF_DATA_AVAIL,
  25. msecs_to_jiffies(500)) == -ERESTARTSYS) {
  26. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Read wait event timeout !", mantis->num);
  27. rc = -EREMOTEIO;
  28. }
  29. ca->sbuf_status &= ~MANTIS_SBUF_DATA_AVAIL;
  30. udelay(2);
  31. return rc;
  32. }
  33. static int mantis_hif_sbuf_opdone_wait(struct mantis_ca *ca)
  34. {
  35. struct mantis_pci *mantis = ca->ca_priv;
  36. int rc = 0;
  37. if (wait_event_timeout(ca->hif_opdone_wq,
  38. ca->hif_event & MANTIS_SBUF_OPDONE,
  39. msecs_to_jiffies(500)) == -ERESTARTSYS) {
  40. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Smart buffer operation timeout !", mantis->num);
  41. rc = -EREMOTEIO;
  42. }
  43. dprintk(verbose, MANTIS_DEBUG, 1, "Smart Buffer Operation complete");
  44. ca->hif_event &= ~MANTIS_SBUF_OPDONE;
  45. udelay(5);
  46. return rc;
  47. }
  48. static int mantis_hif_write_wait(struct mantis_ca *ca)
  49. {
  50. struct mantis_pci *mantis = ca->ca_priv;
  51. u32 opdone = 0, timeout = 0;
  52. int rc = 0;
  53. if (wait_event_timeout(ca->hif_write_wq,
  54. mantis->gpif_status & MANTIS_GPIF_WRACK,
  55. msecs_to_jiffies(500)) == -ERESTARTSYS) {
  56. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write ACK timed out !", mantis->num);
  57. rc = -EREMOTEIO;
  58. }
  59. dprintk(verbose, MANTIS_DEBUG, 1, "Write Acknowledged");
  60. mantis->gpif_status &= ~MANTIS_GPIF_WRACK;
  61. while (!opdone) {
  62. opdone = (mmread(MANTIS_GPIF_STATUS) & MANTIS_SBUF_OPDONE);
  63. udelay(500);
  64. timeout++;
  65. if (timeout > 100) {
  66. dprintk(verbose, MANTIS_ERROR, 1, "Adater(%d) Slot(0): Write operation timed out!", mantis->num);
  67. rc = -ETIMEDOUT;
  68. break;
  69. }
  70. }
  71. dprintk(verbose, MANTIS_DEBUG, 1, "HIF Write success");
  72. return rc;
  73. }
  74. int mantis_hif_read_mem(struct mantis_ca *ca, u32 addr)
  75. {
  76. struct mantis_pci *mantis = ca->ca_priv;
  77. u32 hif_addr = 0, data, count = 4;
  78. dprintk(verbose, MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Read", mantis->num);
  79. hif_addr |= MANTIS_GPIF_HIFRDWRN;
  80. hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
  81. hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
  82. hif_addr |= addr;
  83. mmwrite(hif_addr | MANTIS_HIF_STATUS, MANTIS_GPIF_BRADDR);
  84. mmwrite(count, MANTIS_GPIF_BRBYTES);
  85. udelay(20);
  86. mmwrite(hif_addr, MANTIS_GPIF_ADDR);
  87. if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
  88. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): GPIF Smart Buffer operation failed", mantis->num);
  89. return -EREMOTEIO;
  90. }
  91. data = mmread(MANTIS_GPIF_DIN);
  92. dprintk(verbose, MANTIS_DEBUG, 1, "Mem Read: 0x%02x", data);
  93. return (data >> 24) & 0xff;
  94. }
  95. int mantis_hif_write_mem(struct mantis_ca *ca, u32 addr, u8 data)
  96. {
  97. struct mantis_slot *slot = ca->slot;
  98. struct mantis_pci *mantis = ca->ca_priv;
  99. u32 hif_addr = 0;
  100. dprintk(verbose, MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Write", mantis->num);
  101. hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
  102. hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
  103. hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
  104. hif_addr |= addr;
  105. mmwrite(slot->slave_cfg, MANTIS_GPIF_CFGSLA); /* Slot0 alone for now */
  106. mmwrite(hif_addr | MANTIS_HIF_STATUS, MANTIS_GPIF_ADDR);
  107. mmwrite(data, MANTIS_GPIF_DOUT);
  108. if (mantis_hif_write_wait(ca) != 0) {
  109. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
  110. return -EREMOTEIO;
  111. }
  112. dprintk(verbose, MANTIS_DEBUG, 1, "Mem Write: (0x%02x to 0x%02x)", data, addr);
  113. return 0;
  114. }
  115. int mantis_hif_read_iom(struct mantis_ca *ca, u32 addr)
  116. {
  117. struct mantis_pci *mantis = ca->ca_priv;
  118. u32 data, hif_addr = 0;
  119. dprintk(verbose, MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Read", mantis->num);
  120. hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
  121. hif_addr |= MANTIS_GPIF_HIFRDWRN;
  122. hif_addr |= MANTIS_GPIF_PCMCIAIOM;
  123. hif_addr |= addr;
  124. mmwrite(hif_addr | MANTIS_HIF_STATUS, MANTIS_GPIF_ADDR);
  125. if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
  126. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
  127. return -EREMOTEIO;
  128. }
  129. data = mmread(MANTIS_GPIF_DIN);
  130. dprintk(verbose, MANTIS_DEBUG, 1, "I/O Read: 0x%02x", data);
  131. udelay(50);
  132. return (u8) data;
  133. }
  134. int mantis_hif_write_iom(struct mantis_ca *ca, u32 addr, u8 data)
  135. {
  136. struct mantis_pci *mantis = ca->ca_priv;
  137. u32 hif_addr = 0;
  138. dprintk(verbose, MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Write", mantis->num);
  139. hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
  140. hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
  141. hif_addr |= MANTIS_GPIF_PCMCIAIOM;
  142. hif_addr |= addr;
  143. mmwrite(hif_addr | MANTIS_HIF_STATUS, MANTIS_GPIF_ADDR);
  144. mmwrite(data, MANTIS_GPIF_DOUT);
  145. if (mantis_hif_write_wait(ca) != 0) {
  146. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
  147. return -EREMOTEIO;
  148. }
  149. dprintk(verbose, MANTIS_DEBUG, 1, "I/O Write: (0x%02x to 0x%02x)", data, addr);
  150. udelay(50);
  151. return 0;
  152. }
  153. int mantis_hif_init(struct mantis_ca *ca)
  154. {
  155. struct mantis_slot *slot = ca->slot;
  156. struct mantis_pci *mantis = ca->ca_priv;
  157. u32 irqcfg;
  158. slot[0].slave_cfg = 0x70773028;
  159. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Initializing Mantis Host Interface", mantis->num);
  160. init_waitqueue_head(&ca->hif_data_wq);
  161. init_waitqueue_head(&ca->hif_opdone_wq);
  162. init_waitqueue_head(&ca->hif_write_wq);
  163. irqcfg = mmread(MANTIS_GPIF_IRQCFG);
  164. irqcfg = MANTIS_MASK_BRRDY |
  165. MANTIS_MASK_WRACK |
  166. MANTIS_MASK_EXTIRQ |
  167. MANTIS_MASK_WSTO |
  168. MANTIS_MASK_OTHERR |
  169. MANTIS_MASK_OVFLW;
  170. mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
  171. return 0;
  172. }
  173. void mantis_hif_exit(struct mantis_ca *ca)
  174. {
  175. struct mantis_pci *mantis = ca->ca_priv;
  176. u32 irqcfg;
  177. dprintk(verbose, MANTIS_ERROR, 1, "Adapter(%d) Exiting Mantis Host Interface", mantis->num);
  178. irqcfg = mmread(MANTIS_GPIF_IRQCFG);
  179. irqcfg &= ~MANTIS_MASK_BRRDY;
  180. mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
  181. }