tegra20-tamonten.dtsi 11 KB

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  1. #include "tegra20.dtsi"
  2. / {
  3. model = "Avionic Design Tamonten SOM";
  4. compatible = "ad,tamonten", "nvidia,tegra20";
  5. memory {
  6. reg = <0x00000000 0x20000000>;
  7. };
  8. host1x {
  9. hdmi {
  10. vdd-supply = <&hdmi_vdd_reg>;
  11. pll-supply = <&hdmi_pll_reg>;
  12. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  13. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  14. GPIO_ACTIVE_HIGH>;
  15. };
  16. };
  17. pinmux {
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&state_default>;
  20. state_default: pinmux {
  21. ata {
  22. nvidia,pins = "ata";
  23. nvidia,function = "ide";
  24. };
  25. atb {
  26. nvidia,pins = "atb", "gma", "gme";
  27. nvidia,function = "sdio4";
  28. };
  29. atc {
  30. nvidia,pins = "atc";
  31. nvidia,function = "nand";
  32. };
  33. atd {
  34. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  35. "spia", "spib", "spic";
  36. nvidia,function = "gmi";
  37. };
  38. cdev1 {
  39. nvidia,pins = "cdev1";
  40. nvidia,function = "plla_out";
  41. };
  42. cdev2 {
  43. nvidia,pins = "cdev2";
  44. nvidia,function = "pllp_out4";
  45. };
  46. crtp {
  47. nvidia,pins = "crtp";
  48. nvidia,function = "crt";
  49. };
  50. csus {
  51. nvidia,pins = "csus";
  52. nvidia,function = "vi_sensor_clk";
  53. };
  54. dap1 {
  55. nvidia,pins = "dap1";
  56. nvidia,function = "dap1";
  57. };
  58. dap2 {
  59. nvidia,pins = "dap2";
  60. nvidia,function = "dap2";
  61. };
  62. dap3 {
  63. nvidia,pins = "dap3";
  64. nvidia,function = "dap3";
  65. };
  66. dap4 {
  67. nvidia,pins = "dap4";
  68. nvidia,function = "dap4";
  69. };
  70. dta {
  71. nvidia,pins = "dta", "dtd";
  72. nvidia,function = "sdio2";
  73. };
  74. dtb {
  75. nvidia,pins = "dtb", "dtc", "dte";
  76. nvidia,function = "rsvd1";
  77. };
  78. dtf {
  79. nvidia,pins = "dtf";
  80. nvidia,function = "i2c3";
  81. };
  82. gmc {
  83. nvidia,pins = "gmc";
  84. nvidia,function = "uartd";
  85. };
  86. gpu7 {
  87. nvidia,pins = "gpu7";
  88. nvidia,function = "rtck";
  89. };
  90. gpv {
  91. nvidia,pins = "gpv", "slxa", "slxk";
  92. nvidia,function = "pcie";
  93. };
  94. hdint {
  95. nvidia,pins = "hdint";
  96. nvidia,function = "hdmi";
  97. };
  98. i2cp {
  99. nvidia,pins = "i2cp";
  100. nvidia,function = "i2cp";
  101. };
  102. irrx {
  103. nvidia,pins = "irrx", "irtx";
  104. nvidia,function = "uarta";
  105. };
  106. kbca {
  107. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  108. "kbce", "kbcf";
  109. nvidia,function = "kbc";
  110. };
  111. lcsn {
  112. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  113. "ld3", "ld4", "ld5", "ld6", "ld7",
  114. "ld8", "ld9", "ld10", "ld11", "ld12",
  115. "ld13", "ld14", "ld15", "ld16", "ld17",
  116. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  117. "lhs", "lm0", "lm1", "lpp", "lpw0",
  118. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  119. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  120. "lvs";
  121. nvidia,function = "displaya";
  122. };
  123. owc {
  124. nvidia,pins = "owc", "spdi", "spdo", "uac";
  125. nvidia,function = "rsvd2";
  126. };
  127. pmc {
  128. nvidia,pins = "pmc";
  129. nvidia,function = "pwr_on";
  130. };
  131. rm {
  132. nvidia,pins = "rm";
  133. nvidia,function = "i2c1";
  134. };
  135. sdb {
  136. nvidia,pins = "sdb", "sdc", "sdd";
  137. nvidia,function = "pwm";
  138. };
  139. sdio1 {
  140. nvidia,pins = "sdio1";
  141. nvidia,function = "sdio1";
  142. };
  143. slxc {
  144. nvidia,pins = "slxc", "slxd";
  145. nvidia,function = "spdif";
  146. };
  147. spid {
  148. nvidia,pins = "spid", "spie", "spif";
  149. nvidia,function = "spi1";
  150. };
  151. spig {
  152. nvidia,pins = "spig", "spih";
  153. nvidia,function = "spi2_alt";
  154. };
  155. uaa {
  156. nvidia,pins = "uaa", "uab", "uda";
  157. nvidia,function = "ulpi";
  158. };
  159. uad {
  160. nvidia,pins = "uad";
  161. nvidia,function = "irda";
  162. };
  163. uca {
  164. nvidia,pins = "uca", "ucb";
  165. nvidia,function = "uartc";
  166. };
  167. conf_ata {
  168. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  169. "cdev1", "cdev2", "dap1", "dtb", "gma",
  170. "gmb", "gmc", "gmd", "gme", "gpu7",
  171. "gpv", "i2cp", "pta", "rm", "slxa",
  172. "slxk", "spia", "spib", "uac";
  173. nvidia,pull = <0>;
  174. nvidia,tristate = <0>;
  175. };
  176. conf_ck32 {
  177. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  178. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  179. nvidia,pull = <0>;
  180. };
  181. conf_csus {
  182. nvidia,pins = "csus", "spid", "spif";
  183. nvidia,pull = <1>;
  184. nvidia,tristate = <1>;
  185. };
  186. conf_crtp {
  187. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  188. "dtc", "dte", "dtf", "gpu", "sdio1",
  189. "slxc", "slxd", "spdi", "spdo", "spig",
  190. "uda";
  191. nvidia,pull = <0>;
  192. nvidia,tristate = <1>;
  193. };
  194. conf_ddc {
  195. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  196. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  197. "sdc";
  198. nvidia,pull = <2>;
  199. nvidia,tristate = <0>;
  200. };
  201. conf_hdint {
  202. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  203. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  204. "lvp0", "owc", "sdb";
  205. nvidia,tristate = <1>;
  206. };
  207. conf_irrx {
  208. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  209. "spie", "spih", "uaa", "uab", "uad",
  210. "uca", "ucb";
  211. nvidia,pull = <2>;
  212. nvidia,tristate = <1>;
  213. };
  214. conf_lc {
  215. nvidia,pins = "lc", "ls";
  216. nvidia,pull = <2>;
  217. };
  218. conf_ld0 {
  219. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  220. "ld5", "ld6", "ld7", "ld8", "ld9",
  221. "ld10", "ld11", "ld12", "ld13", "ld14",
  222. "ld15", "ld16", "ld17", "ldi", "lhp0",
  223. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  224. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  225. "lvs", "pmc";
  226. nvidia,tristate = <0>;
  227. };
  228. conf_ld17_0 {
  229. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  230. "ld23_22";
  231. nvidia,pull = <1>;
  232. };
  233. };
  234. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  235. ddc {
  236. nvidia,pins = "ddc";
  237. nvidia,function = "i2c2";
  238. };
  239. pta {
  240. nvidia,pins = "pta";
  241. nvidia,function = "rsvd4";
  242. };
  243. };
  244. state_i2cmux_pta: pinmux_i2cmux_pta {
  245. ddc {
  246. nvidia,pins = "ddc";
  247. nvidia,function = "rsvd4";
  248. };
  249. pta {
  250. nvidia,pins = "pta";
  251. nvidia,function = "i2c2";
  252. };
  253. };
  254. state_i2cmux_idle: pinmux_i2cmux_idle {
  255. ddc {
  256. nvidia,pins = "ddc";
  257. nvidia,function = "rsvd4";
  258. };
  259. pta {
  260. nvidia,pins = "pta";
  261. nvidia,function = "rsvd4";
  262. };
  263. };
  264. };
  265. i2s@70002800 {
  266. status = "okay";
  267. };
  268. serial@70006300 {
  269. status = "okay";
  270. };
  271. i2c@7000c000 {
  272. clock-frequency = <400000>;
  273. status = "okay";
  274. };
  275. i2c@7000c400 {
  276. clock-frequency = <100000>;
  277. status = "okay";
  278. };
  279. i2cmux {
  280. compatible = "i2c-mux-pinctrl";
  281. #address-cells = <1>;
  282. #size-cells = <0>;
  283. i2c-parent = <&{/i2c@7000c400}>;
  284. pinctrl-names = "ddc", "pta", "idle";
  285. pinctrl-0 = <&state_i2cmux_ddc>;
  286. pinctrl-1 = <&state_i2cmux_pta>;
  287. pinctrl-2 = <&state_i2cmux_idle>;
  288. hdmi_ddc: i2c@0 {
  289. reg = <0>;
  290. #address-cells = <1>;
  291. #size-cells = <0>;
  292. };
  293. i2c@1 {
  294. reg = <1>;
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. };
  298. };
  299. i2c@7000d000 {
  300. clock-frequency = <400000>;
  301. status = "okay";
  302. pmic: tps6586x@34 {
  303. compatible = "ti,tps6586x";
  304. reg = <0x34>;
  305. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  306. ti,system-power-controller;
  307. #gpio-cells = <2>;
  308. gpio-controller;
  309. sys-supply = <&vdd_5v0_reg>;
  310. vin-sm0-supply = <&sys_reg>;
  311. vin-sm1-supply = <&sys_reg>;
  312. vin-sm2-supply = <&sys_reg>;
  313. vinldo01-supply = <&sm2_reg>;
  314. vinldo23-supply = <&sm2_reg>;
  315. vinldo4-supply = <&sm2_reg>;
  316. vinldo678-supply = <&sm2_reg>;
  317. vinldo9-supply = <&sm2_reg>;
  318. regulators {
  319. sys_reg: sys {
  320. regulator-name = "vdd_sys";
  321. regulator-always-on;
  322. };
  323. sm0 {
  324. regulator-name = "vdd_sys_sm0,vdd_core";
  325. regulator-min-microvolt = <1200000>;
  326. regulator-max-microvolt = <1200000>;
  327. regulator-always-on;
  328. };
  329. sm1 {
  330. regulator-name = "vdd_sys_sm1,vdd_cpu";
  331. regulator-min-microvolt = <1000000>;
  332. regulator-max-microvolt = <1000000>;
  333. regulator-always-on;
  334. };
  335. sm2_reg: sm2 {
  336. regulator-name = "vdd_sys_sm2,vin_ldo*";
  337. regulator-min-microvolt = <3700000>;
  338. regulator-max-microvolt = <3700000>;
  339. regulator-always-on;
  340. };
  341. pci_clk_reg: ldo0 {
  342. regulator-name = "vdd_ldo0,vddio_pex_clk";
  343. regulator-min-microvolt = <3300000>;
  344. regulator-max-microvolt = <3300000>;
  345. };
  346. ldo1 {
  347. regulator-name = "vdd_ldo1,avdd_pll*";
  348. regulator-min-microvolt = <1100000>;
  349. regulator-max-microvolt = <1100000>;
  350. regulator-always-on;
  351. };
  352. ldo2 {
  353. regulator-name = "vdd_ldo2,vdd_rtc";
  354. regulator-min-microvolt = <1200000>;
  355. regulator-max-microvolt = <1200000>;
  356. };
  357. ldo3 {
  358. regulator-name = "vdd_ldo3,avdd_usb*";
  359. regulator-min-microvolt = <3300000>;
  360. regulator-max-microvolt = <3300000>;
  361. regulator-always-on;
  362. };
  363. ldo4 {
  364. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  365. regulator-min-microvolt = <1800000>;
  366. regulator-max-microvolt = <1800000>;
  367. regulator-always-on;
  368. };
  369. ldo5 {
  370. regulator-name = "vdd_ldo5,vcore_mmc";
  371. regulator-min-microvolt = <2850000>;
  372. regulator-max-microvolt = <2850000>;
  373. };
  374. ldo6 {
  375. regulator-name = "vdd_ldo6,avdd_vdac";
  376. /*
  377. * According to the Tegra 2 Automotive
  378. * DataSheet, a typical value for this
  379. * would be 2.8V, but the PMIC only
  380. * supports 2.85V.
  381. */
  382. regulator-min-microvolt = <2850000>;
  383. regulator-max-microvolt = <2850000>;
  384. };
  385. hdmi_vdd_reg: ldo7 {
  386. regulator-name = "vdd_ldo7,avdd_hdmi";
  387. regulator-min-microvolt = <3300000>;
  388. regulator-max-microvolt = <3300000>;
  389. };
  390. hdmi_pll_reg: ldo8 {
  391. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  392. regulator-min-microvolt = <1800000>;
  393. regulator-max-microvolt = <1800000>;
  394. };
  395. ldo9 {
  396. regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
  397. /*
  398. * According to the Tegra 2 Automotive
  399. * DataSheet, a typical value for this
  400. * would be 2.8V, but the PMIC only
  401. * supports 2.85V.
  402. */
  403. regulator-min-microvolt = <2850000>;
  404. regulator-max-microvolt = <2850000>;
  405. regulator-always-on;
  406. };
  407. ldo_rtc {
  408. regulator-name = "vdd_rtc_out";
  409. regulator-min-microvolt = <3300000>;
  410. regulator-max-microvolt = <3300000>;
  411. regulator-always-on;
  412. };
  413. };
  414. };
  415. temperature-sensor@4c {
  416. compatible = "onnn,nct1008";
  417. reg = <0x4c>;
  418. };
  419. };
  420. pmc {
  421. nvidia,invert-interrupt;
  422. nvidia,suspend-mode = <1>;
  423. nvidia,cpu-pwr-good-time = <5000>;
  424. nvidia,cpu-pwr-off-time = <5000>;
  425. nvidia,core-pwr-good-time = <3845 3845>;
  426. nvidia,core-pwr-off-time = <3875>;
  427. nvidia,sys-clock-req-active-high;
  428. };
  429. pcie-controller {
  430. pex-clk-supply = <&pci_clk_reg>;
  431. vdd-supply = <&pci_vdd_reg>;
  432. };
  433. usb@c5008000 {
  434. status = "okay";
  435. };
  436. usb-phy@c5008000 {
  437. status = "okay";
  438. };
  439. sdhci@c8000600 {
  440. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  441. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  442. bus-width = <4>;
  443. status = "okay";
  444. };
  445. clocks {
  446. compatible = "simple-bus";
  447. #address-cells = <1>;
  448. #size-cells = <0>;
  449. clk32k_in: clock {
  450. compatible = "fixed-clock";
  451. reg=<0>;
  452. #clock-cells = <0>;
  453. clock-frequency = <32768>;
  454. };
  455. };
  456. regulators {
  457. compatible = "simple-bus";
  458. #address-cells = <1>;
  459. #size-cells = <0>;
  460. vdd_5v0_reg: regulator@0 {
  461. compatible = "regulator-fixed";
  462. reg = <0>;
  463. regulator-name = "vdd_5v0";
  464. regulator-min-microvolt = <5000000>;
  465. regulator-max-microvolt = <5000000>;
  466. regulator-always-on;
  467. };
  468. pci_vdd_reg: regulator@1 {
  469. compatible = "regulator-fixed";
  470. reg = <1>;
  471. regulator-name = "vdd_1v05";
  472. regulator-min-microvolt = <1050000>;
  473. regulator-max-microvolt = <1050000>;
  474. gpio = <&pmic 2 0>;
  475. enable-active-high;
  476. };
  477. };
  478. };