zynq-7000.dtsi 1.4 KB

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  1. /*
  2. * Copyright (C) 2011 Xilinx
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. /include/ "skeleton.dtsi"
  14. / {
  15. compatible = "xlnx,zynq-7000";
  16. amba {
  17. compatible = "simple-bus";
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. interrupt-parent = <&intc>;
  21. ranges;
  22. intc: interrupt-controller@f8f01000 {
  23. compatible = "arm,cortex-a9-gic";
  24. #interrupt-cells = <3>;
  25. #address-cells = <1>;
  26. interrupt-controller;
  27. reg = <0xF8F01000 0x1000>,
  28. <0xF8F00100 0x100>;
  29. };
  30. L2: cache-controller {
  31. compatible = "arm,pl310-cache";
  32. reg = <0xF8F02000 0x1000>;
  33. arm,data-latency = <2 3 2>;
  34. arm,tag-latency = <2 3 2>;
  35. cache-unified;
  36. cache-level = <2>;
  37. };
  38. uart0: uart@e0000000 {
  39. compatible = "xlnx,xuartps";
  40. reg = <0xE0000000 0x1000>;
  41. interrupts = <0 27 4>;
  42. clock = <50000000>;
  43. };
  44. uart1: uart@e0001000 {
  45. compatible = "xlnx,xuartps";
  46. reg = <0xE0001000 0x1000>;
  47. interrupts = <0 50 4>;
  48. clock = <50000000>;
  49. };
  50. };
  51. };