tifm_sd.c 25 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #define DRIVER_NAME "tifm_sd"
  16. #define DRIVER_VERSION "0.6"
  17. static int no_dma = 0;
  18. static int fixed_timeout = 0;
  19. module_param(no_dma, bool, 0644);
  20. module_param(fixed_timeout, bool, 0644);
  21. /* Constants here are mostly from OMAP5912 datasheet */
  22. #define TIFM_MMCSD_RESET 0x0002
  23. #define TIFM_MMCSD_CLKMASK 0x03ff
  24. #define TIFM_MMCSD_POWER 0x0800
  25. #define TIFM_MMCSD_4BBUS 0x8000
  26. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  27. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  28. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  29. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  30. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  31. #define TIFM_MMCSD_READ 0x8000
  32. #define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
  33. #define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
  34. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  35. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  36. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  37. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  38. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  39. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  40. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  41. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  42. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  43. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  44. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  45. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  46. #define TIFM_MMCSD_RSP_R0 0x0000
  47. #define TIFM_MMCSD_RSP_R1 0x0100
  48. #define TIFM_MMCSD_RSP_R2 0x0200
  49. #define TIFM_MMCSD_RSP_R3 0x0300
  50. #define TIFM_MMCSD_RSP_R4 0x0400
  51. #define TIFM_MMCSD_RSP_R5 0x0500
  52. #define TIFM_MMCSD_RSP_R6 0x0600
  53. #define TIFM_MMCSD_RSP_BUSY 0x0800
  54. #define TIFM_MMCSD_CMD_BC 0x0000
  55. #define TIFM_MMCSD_CMD_BCR 0x1000
  56. #define TIFM_MMCSD_CMD_AC 0x2000
  57. #define TIFM_MMCSD_CMD_ADTC 0x3000
  58. typedef enum {
  59. IDLE = 0,
  60. CMD, /* main command ended */
  61. BRS, /* block transfer finished */
  62. SCMD, /* stop command ended */
  63. CARD, /* card left busy state */
  64. FIFO, /* FIFO operation completed (uncertain) */
  65. READY
  66. } card_state_t;
  67. enum {
  68. FIFO_RDY = 0x0001, /* hardware dependent value */
  69. HOST_REG = 0x0002,
  70. EJECT = 0x0004,
  71. EJECT_DONE = 0x0008,
  72. CARD_BUSY = 0x0010,
  73. OPENDRAIN = 0x0040, /* hardware dependent value */
  74. CARD_EVENT = 0x0100, /* hardware dependent value */
  75. CARD_RO = 0x0200, /* hardware dependent value */
  76. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  77. struct tifm_sd {
  78. struct tifm_dev *dev;
  79. unsigned int flags;
  80. card_state_t state;
  81. unsigned int clk_freq;
  82. unsigned int clk_div;
  83. unsigned long timeout_jiffies; // software timeout - 2 sec
  84. struct mmc_request *req;
  85. struct work_struct cmd_handler;
  86. struct work_struct abort_handler;
  87. wait_queue_head_t can_eject;
  88. size_t written_blocks;
  89. char *buffer;
  90. size_t buffer_size;
  91. size_t buffer_pos;
  92. };
  93. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  94. unsigned int host_status)
  95. {
  96. struct mmc_command *cmd = host->req->cmd;
  97. unsigned int t_val = 0, cnt = 0;
  98. if (host_status & TIFM_MMCSD_BRS) {
  99. /* in non-dma rx mode BRS fires when fifo is still not empty */
  100. if (host->buffer && (cmd->data->flags & MMC_DATA_READ)) {
  101. while (host->buffer_size > host->buffer_pos) {
  102. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  103. host->buffer[host->buffer_pos++] = t_val & 0xff;
  104. host->buffer[host->buffer_pos++] =
  105. (t_val >> 8) & 0xff;
  106. }
  107. }
  108. return 1;
  109. } else if (host->buffer) {
  110. if ((cmd->data->flags & MMC_DATA_READ) &&
  111. (host_status & TIFM_MMCSD_AF)) {
  112. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  113. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  114. if (host->buffer_size > host->buffer_pos) {
  115. host->buffer[host->buffer_pos++] =
  116. t_val & 0xff;
  117. host->buffer[host->buffer_pos++] =
  118. (t_val >> 8) & 0xff;
  119. }
  120. }
  121. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  122. && (host_status & TIFM_MMCSD_AE)) {
  123. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  124. if (host->buffer_size > host->buffer_pos) {
  125. t_val = host->buffer[host->buffer_pos++] & 0x00ff;
  126. t_val |= ((host->buffer[host->buffer_pos++]) << 8)
  127. & 0xff00;
  128. writel(t_val,
  129. sock->addr + SOCK_MMCSD_DATA);
  130. }
  131. }
  132. }
  133. }
  134. return 0;
  135. }
  136. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  137. {
  138. unsigned int rc = 0;
  139. switch (mmc_resp_type(cmd)) {
  140. case MMC_RSP_NONE:
  141. rc |= TIFM_MMCSD_RSP_R0;
  142. break;
  143. case MMC_RSP_R1B:
  144. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  145. case MMC_RSP_R1:
  146. rc |= TIFM_MMCSD_RSP_R1;
  147. break;
  148. case MMC_RSP_R2:
  149. rc |= TIFM_MMCSD_RSP_R2;
  150. break;
  151. case MMC_RSP_R3:
  152. rc |= TIFM_MMCSD_RSP_R3;
  153. break;
  154. case MMC_RSP_R6:
  155. rc |= TIFM_MMCSD_RSP_R6;
  156. break;
  157. default:
  158. BUG();
  159. }
  160. switch (mmc_cmd_type(cmd)) {
  161. case MMC_CMD_BC:
  162. rc |= TIFM_MMCSD_CMD_BC;
  163. break;
  164. case MMC_CMD_BCR:
  165. rc |= TIFM_MMCSD_CMD_BCR;
  166. break;
  167. case MMC_CMD_AC:
  168. rc |= TIFM_MMCSD_CMD_AC;
  169. break;
  170. case MMC_CMD_ADTC:
  171. rc |= TIFM_MMCSD_CMD_ADTC;
  172. break;
  173. default:
  174. BUG();
  175. }
  176. return rc;
  177. }
  178. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  179. {
  180. struct tifm_dev *sock = host->dev;
  181. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  182. (host->flags & OPENDRAIN);
  183. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  184. cmd_mask |= TIFM_MMCSD_READ;
  185. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  186. cmd->opcode, cmd->arg, cmd_mask);
  187. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  188. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  189. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  190. }
  191. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  192. {
  193. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  194. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  195. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  196. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  197. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  198. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  199. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  200. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  201. }
  202. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  203. unsigned int host_status)
  204. {
  205. struct mmc_command *cmd = host->req->cmd;
  206. change_state:
  207. switch (host->state) {
  208. case IDLE:
  209. return;
  210. case CMD:
  211. if (host_status & TIFM_MMCSD_EOC) {
  212. tifm_sd_fetch_resp(cmd, sock);
  213. if (cmd->data) {
  214. host->state = BRS;
  215. } else
  216. host->state = READY;
  217. goto change_state;
  218. }
  219. break;
  220. case BRS:
  221. if (tifm_sd_transfer_data(sock, host, host_status)) {
  222. if (!host->req->stop) {
  223. if (cmd->data->flags & MMC_DATA_WRITE) {
  224. host->state = CARD;
  225. } else {
  226. host->state =
  227. host->buffer ? READY : FIFO;
  228. }
  229. goto change_state;
  230. }
  231. tifm_sd_exec(host, host->req->stop);
  232. host->state = SCMD;
  233. }
  234. break;
  235. case SCMD:
  236. if (host_status & TIFM_MMCSD_EOC) {
  237. tifm_sd_fetch_resp(host->req->stop, sock);
  238. if (cmd->error) {
  239. host->state = READY;
  240. } else if (cmd->data->flags & MMC_DATA_WRITE) {
  241. host->state = CARD;
  242. } else {
  243. host->state = host->buffer ? READY : FIFO;
  244. }
  245. goto change_state;
  246. }
  247. break;
  248. case CARD:
  249. if (!(host->flags & CARD_BUSY)
  250. && (host->written_blocks == cmd->data->blocks)) {
  251. host->state = host->buffer ? READY : FIFO;
  252. goto change_state;
  253. }
  254. break;
  255. case FIFO:
  256. if (host->flags & FIFO_RDY) {
  257. host->state = READY;
  258. host->flags &= ~FIFO_RDY;
  259. goto change_state;
  260. }
  261. break;
  262. case READY:
  263. queue_work(sock->wq, &host->cmd_handler);
  264. return;
  265. }
  266. queue_delayed_work(sock->wq, &host->abort_handler,
  267. host->timeout_jiffies);
  268. }
  269. /* Called from interrupt handler */
  270. static unsigned int tifm_sd_signal_irq(struct tifm_dev *sock,
  271. unsigned int sock_irq_status)
  272. {
  273. struct tifm_sd *host;
  274. unsigned int host_status = 0, fifo_status = 0;
  275. int error_code = 0;
  276. spin_lock(&sock->lock);
  277. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  278. cancel_delayed_work(&host->abort_handler);
  279. if (sock_irq_status & FIFO_EVENT) {
  280. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  281. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  282. host->flags |= fifo_status & FIFO_RDY;
  283. }
  284. if (sock_irq_status & CARD_EVENT) {
  285. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  286. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  287. if (!(host->flags & HOST_REG))
  288. queue_work(sock->wq, &host->cmd_handler);
  289. if (!host->req)
  290. goto done;
  291. if (host_status & TIFM_MMCSD_ERRMASK) {
  292. if (host_status & TIFM_MMCSD_CERR)
  293. error_code = MMC_ERR_FAILED;
  294. else if (host_status &
  295. (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  296. error_code = MMC_ERR_TIMEOUT;
  297. else if (host_status &
  298. (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  299. error_code = MMC_ERR_BADCRC;
  300. writel(TIFM_FIFO_INT_SETALL,
  301. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  302. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  303. if (host->req->stop) {
  304. if (host->state == SCMD) {
  305. host->req->stop->error = error_code;
  306. } else if(host->state == BRS) {
  307. host->req->cmd->error = error_code;
  308. tifm_sd_exec(host, host->req->stop);
  309. queue_delayed_work(sock->wq,
  310. &host->abort_handler,
  311. host->timeout_jiffies);
  312. host->state = SCMD;
  313. goto done;
  314. } else {
  315. host->req->cmd->error = error_code;
  316. }
  317. } else {
  318. host->req->cmd->error = error_code;
  319. }
  320. host->state = READY;
  321. }
  322. if (host_status & TIFM_MMCSD_CB)
  323. host->flags |= CARD_BUSY;
  324. if ((host_status & TIFM_MMCSD_EOFB) &&
  325. (host->flags & CARD_BUSY)) {
  326. host->written_blocks++;
  327. host->flags &= ~CARD_BUSY;
  328. }
  329. }
  330. if (host->req)
  331. tifm_sd_process_cmd(sock, host, host_status);
  332. done:
  333. dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
  334. host_status, fifo_status);
  335. spin_unlock(&sock->lock);
  336. return sock_irq_status;
  337. }
  338. static void tifm_sd_prepare_data(struct tifm_sd *card, struct mmc_command *cmd)
  339. {
  340. struct tifm_dev *sock = card->dev;
  341. unsigned int dest_cnt;
  342. /* DMA style IO */
  343. writel(TIFM_FIFO_INT_SETALL,
  344. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  345. writel(long_log2(cmd->data->blksz) - 2,
  346. sock->addr + SOCK_FIFO_PAGE_SIZE);
  347. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  348. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  349. dest_cnt = (cmd->data->blocks) << 8;
  350. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  351. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  352. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  353. if (cmd->data->flags & MMC_DATA_WRITE) {
  354. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  355. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  356. sock->addr + SOCK_DMA_CONTROL);
  357. } else {
  358. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  359. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  360. }
  361. }
  362. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  363. struct mmc_data *data)
  364. {
  365. struct tifm_dev *sock = host->dev;
  366. unsigned int data_timeout = data->timeout_clks;
  367. if (fixed_timeout)
  368. return;
  369. data_timeout += data->timeout_ns /
  370. ((1000000000 / host->clk_freq) * host->clk_div);
  371. data_timeout *= 10; // call it fudge factor for now
  372. if (data_timeout < 0xffff) {
  373. writel((~TIFM_MMCSD_DPE) &
  374. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  375. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  376. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  377. } else {
  378. writel(TIFM_MMCSD_DPE |
  379. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  380. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  381. data_timeout = (data_timeout >> 10) + 1;
  382. if(data_timeout > 0xffff)
  383. data_timeout = 0; /* set to unlimited */
  384. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  385. }
  386. }
  387. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  388. {
  389. struct tifm_sd *host = mmc_priv(mmc);
  390. struct tifm_dev *sock = host->dev;
  391. unsigned long flags;
  392. int sg_count = 0;
  393. struct mmc_data *r_data = mrq->cmd->data;
  394. spin_lock_irqsave(&sock->lock, flags);
  395. if (host->flags & EJECT) {
  396. spin_unlock_irqrestore(&sock->lock, flags);
  397. goto err_out;
  398. }
  399. if (host->req) {
  400. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  401. spin_unlock_irqrestore(&sock->lock, flags);
  402. goto err_out;
  403. }
  404. if (r_data) {
  405. tifm_sd_set_data_timeout(host, r_data);
  406. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  407. mrq->cmd->flags & MMC_DATA_WRITE
  408. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  409. if (sg_count != 1) {
  410. printk(KERN_ERR DRIVER_NAME
  411. ": scatterlist map failed\n");
  412. spin_unlock_irqrestore(&sock->lock, flags);
  413. goto err_out;
  414. }
  415. host->written_blocks = 0;
  416. host->flags &= ~CARD_BUSY;
  417. tifm_sd_prepare_data(host, mrq->cmd);
  418. }
  419. host->req = mrq;
  420. host->state = CMD;
  421. queue_delayed_work(sock->wq, &host->abort_handler,
  422. host->timeout_jiffies);
  423. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  424. sock->addr + SOCK_CONTROL);
  425. tifm_sd_exec(host, mrq->cmd);
  426. spin_unlock_irqrestore(&sock->lock, flags);
  427. return;
  428. err_out:
  429. if (sg_count > 0)
  430. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  431. (r_data->flags & MMC_DATA_WRITE)
  432. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  433. mrq->cmd->error = MMC_ERR_TIMEOUT;
  434. mmc_request_done(mmc, mrq);
  435. }
  436. static void tifm_sd_end_cmd(void *data)
  437. {
  438. struct tifm_sd *host = data;
  439. struct tifm_dev *sock = host->dev;
  440. struct mmc_host *mmc = tifm_get_drvdata(sock);
  441. struct mmc_request *mrq;
  442. struct mmc_data *r_data = NULL;
  443. unsigned long flags;
  444. spin_lock_irqsave(&sock->lock, flags);
  445. mrq = host->req;
  446. host->req = NULL;
  447. host->state = IDLE;
  448. if (!mrq) {
  449. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  450. spin_unlock_irqrestore(&sock->lock, flags);
  451. return;
  452. }
  453. r_data = mrq->cmd->data;
  454. if (r_data) {
  455. if (r_data->flags & MMC_DATA_WRITE) {
  456. r_data->bytes_xfered = host->written_blocks *
  457. r_data->blksz;
  458. } else {
  459. r_data->bytes_xfered = r_data->blocks -
  460. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  461. r_data->bytes_xfered *= r_data->blksz;
  462. r_data->bytes_xfered += r_data->blksz -
  463. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  464. }
  465. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  466. (r_data->flags & MMC_DATA_WRITE)
  467. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  468. }
  469. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  470. sock->addr + SOCK_CONTROL);
  471. spin_unlock_irqrestore(&sock->lock, flags);
  472. mmc_request_done(mmc, mrq);
  473. }
  474. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  475. {
  476. struct tifm_sd *host = mmc_priv(mmc);
  477. struct tifm_dev *sock = host->dev;
  478. unsigned long flags;
  479. struct mmc_data *r_data = mrq->cmd->data;
  480. char *t_buffer = NULL;
  481. if (r_data) {
  482. t_buffer = kmap(r_data->sg->page);
  483. if (!t_buffer) {
  484. printk(KERN_ERR DRIVER_NAME ": kmap failed\n");
  485. goto err_out;
  486. }
  487. }
  488. spin_lock_irqsave(&sock->lock, flags);
  489. if (host->flags & EJECT) {
  490. spin_unlock_irqrestore(&sock->lock, flags);
  491. goto err_out;
  492. }
  493. if (host->req) {
  494. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  495. spin_unlock_irqrestore(&sock->lock, flags);
  496. goto err_out;
  497. }
  498. if (r_data) {
  499. tifm_sd_set_data_timeout(host, r_data);
  500. host->buffer = t_buffer + r_data->sg->offset;
  501. host->buffer_size = mrq->cmd->data->blocks *
  502. mrq->cmd->data->blksz;
  503. writel(TIFM_MMCSD_BUFINT |
  504. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  505. sock->addr + SOCK_MMCSD_INT_ENABLE);
  506. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) |
  507. (TIFM_MMCSD_FIFO_SIZE - 1),
  508. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  509. host->written_blocks = 0;
  510. host->flags &= ~CARD_BUSY;
  511. host->buffer_pos = 0;
  512. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  513. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  514. }
  515. host->req = mrq;
  516. host->state = CMD;
  517. queue_delayed_work(sock->wq, &host->abort_handler,
  518. host->timeout_jiffies);
  519. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  520. sock->addr + SOCK_CONTROL);
  521. tifm_sd_exec(host, mrq->cmd);
  522. spin_unlock_irqrestore(&sock->lock, flags);
  523. return;
  524. err_out:
  525. if (t_buffer)
  526. kunmap(r_data->sg->page);
  527. mrq->cmd->error = MMC_ERR_TIMEOUT;
  528. mmc_request_done(mmc, mrq);
  529. }
  530. static void tifm_sd_end_cmd_nodma(void *data)
  531. {
  532. struct tifm_sd *host = (struct tifm_sd*)data;
  533. struct tifm_dev *sock = host->dev;
  534. struct mmc_host *mmc = tifm_get_drvdata(sock);
  535. struct mmc_request *mrq;
  536. struct mmc_data *r_data = NULL;
  537. unsigned long flags;
  538. spin_lock_irqsave(&sock->lock, flags);
  539. mrq = host->req;
  540. host->req = NULL;
  541. host->state = IDLE;
  542. if (!mrq) {
  543. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  544. spin_unlock_irqrestore(&sock->lock, flags);
  545. return;
  546. }
  547. r_data = mrq->cmd->data;
  548. if (r_data) {
  549. writel((~TIFM_MMCSD_BUFINT) &
  550. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  551. sock->addr + SOCK_MMCSD_INT_ENABLE);
  552. if (r_data->flags & MMC_DATA_WRITE) {
  553. r_data->bytes_xfered = host->written_blocks *
  554. r_data->blksz;
  555. } else {
  556. r_data->bytes_xfered = r_data->blocks -
  557. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  558. r_data->bytes_xfered *= r_data->blksz;
  559. r_data->bytes_xfered += r_data->blksz -
  560. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  561. }
  562. host->buffer = NULL;
  563. host->buffer_pos = 0;
  564. host->buffer_size = 0;
  565. }
  566. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  567. sock->addr + SOCK_CONTROL);
  568. spin_unlock_irqrestore(&sock->lock, flags);
  569. if (r_data)
  570. kunmap(r_data->sg->page);
  571. mmc_request_done(mmc, mrq);
  572. }
  573. static void tifm_sd_abort(void *data)
  574. {
  575. printk(KERN_ERR DRIVER_NAME
  576. ": card failed to respond for a long period of time");
  577. tifm_eject(((struct tifm_sd*)data)->dev);
  578. }
  579. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  580. {
  581. struct tifm_sd *host = mmc_priv(mmc);
  582. struct tifm_dev *sock = host->dev;
  583. unsigned int clk_div1, clk_div2;
  584. unsigned long flags;
  585. spin_lock_irqsave(&sock->lock, flags);
  586. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  587. ios->power_mode);
  588. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  589. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  590. sock->addr + SOCK_MMCSD_CONFIG);
  591. } else {
  592. writel((~TIFM_MMCSD_4BBUS) &
  593. readl(sock->addr + SOCK_MMCSD_CONFIG),
  594. sock->addr + SOCK_MMCSD_CONFIG);
  595. }
  596. if (ios->clock) {
  597. clk_div1 = 20000000 / ios->clock;
  598. if (!clk_div1)
  599. clk_div1 = 1;
  600. clk_div2 = 24000000 / ios->clock;
  601. if (!clk_div2)
  602. clk_div2 = 1;
  603. if ((20000000 / clk_div1) > ios->clock)
  604. clk_div1++;
  605. if ((24000000 / clk_div2) > ios->clock)
  606. clk_div2++;
  607. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  608. host->clk_freq = 20000000;
  609. host->clk_div = clk_div1;
  610. writel((~TIFM_CTRL_FAST_CLK) &
  611. readl(sock->addr + SOCK_CONTROL),
  612. sock->addr + SOCK_CONTROL);
  613. } else {
  614. host->clk_freq = 24000000;
  615. host->clk_div = clk_div2;
  616. writel(TIFM_CTRL_FAST_CLK |
  617. readl(sock->addr + SOCK_CONTROL),
  618. sock->addr + SOCK_CONTROL);
  619. }
  620. } else {
  621. host->clk_div = 0;
  622. }
  623. host->clk_div &= TIFM_MMCSD_CLKMASK;
  624. writel(host->clk_div | ((~TIFM_MMCSD_CLKMASK) &
  625. readl(sock->addr + SOCK_MMCSD_CONFIG)),
  626. sock->addr + SOCK_MMCSD_CONFIG);
  627. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  628. host->flags |= OPENDRAIN;
  629. else
  630. host->flags &= ~OPENDRAIN;
  631. /* chip_select : maybe later */
  632. //vdd
  633. //power is set before probe / after remove
  634. //I believe, power_off when already marked for eject is sufficient to
  635. // allow removal.
  636. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  637. host->flags |= EJECT_DONE;
  638. wake_up_all(&host->can_eject);
  639. }
  640. spin_unlock_irqrestore(&sock->lock, flags);
  641. }
  642. static int tifm_sd_ro(struct mmc_host *mmc)
  643. {
  644. int rc;
  645. struct tifm_sd *host = mmc_priv(mmc);
  646. struct tifm_dev *sock = host->dev;
  647. unsigned long flags;
  648. spin_lock_irqsave(&sock->lock, flags);
  649. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  650. rc = (host->flags & CARD_RO) ? 1 : 0;
  651. spin_unlock_irqrestore(&sock->lock, flags);
  652. return rc;
  653. }
  654. static struct mmc_host_ops tifm_sd_ops = {
  655. .request = tifm_sd_request,
  656. .set_ios = tifm_sd_ios,
  657. .get_ro = tifm_sd_ro
  658. };
  659. static void tifm_sd_register_host(void *data)
  660. {
  661. struct tifm_sd *host = (struct tifm_sd*)data;
  662. struct tifm_dev *sock = host->dev;
  663. struct mmc_host *mmc = tifm_get_drvdata(sock);
  664. unsigned long flags;
  665. spin_lock_irqsave(&sock->lock, flags);
  666. host->flags |= HOST_REG;
  667. PREPARE_WORK(&host->cmd_handler,
  668. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
  669. data);
  670. spin_unlock_irqrestore(&sock->lock, flags);
  671. dev_dbg(&sock->dev, "adding host\n");
  672. mmc_add_host(mmc);
  673. }
  674. static int tifm_sd_probe(struct tifm_dev *sock)
  675. {
  676. struct mmc_host *mmc;
  677. struct tifm_sd *host;
  678. int rc = -EIO;
  679. if (!(TIFM_SOCK_STATE_OCCUPIED &
  680. readl(sock->addr + SOCK_PRESENT_STATE))) {
  681. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  682. return rc;
  683. }
  684. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  685. if (!mmc)
  686. return -ENOMEM;
  687. host = mmc_priv(mmc);
  688. host->dev = sock;
  689. host->clk_div = 61;
  690. init_waitqueue_head(&host->can_eject);
  691. INIT_WORK(&host->cmd_handler, tifm_sd_register_host, host);
  692. INIT_WORK(&host->abort_handler, tifm_sd_abort, host);
  693. tifm_set_drvdata(sock, mmc);
  694. sock->signal_irq = tifm_sd_signal_irq;
  695. host->clk_freq = 20000000;
  696. host->timeout_jiffies = msecs_to_jiffies(1000);
  697. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  698. mmc->ops = &tifm_sd_ops;
  699. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  700. mmc->caps = MMC_CAP_4_BIT_DATA;
  701. mmc->f_min = 20000000 / 60;
  702. mmc->f_max = 24000000;
  703. mmc->max_hw_segs = 1;
  704. mmc->max_phys_segs = 1;
  705. mmc->max_sectors = 127;
  706. mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
  707. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  708. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  709. writel(host->clk_div | TIFM_MMCSD_POWER,
  710. sock->addr + SOCK_MMCSD_CONFIG);
  711. for (rc = 0; rc < 50; rc++) {
  712. /* Wait for reset ack */
  713. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  714. rc = 0;
  715. break;
  716. }
  717. msleep(10);
  718. }
  719. if (rc) {
  720. printk(KERN_ERR DRIVER_NAME
  721. ": card not ready - probe failed\n");
  722. mmc_free_host(mmc);
  723. return -ENODEV;
  724. }
  725. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  726. writel(host->clk_div | TIFM_MMCSD_POWER,
  727. sock->addr + SOCK_MMCSD_CONFIG);
  728. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  729. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  730. sock->addr + SOCK_MMCSD_INT_ENABLE);
  731. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); // command timeout 64 clocks for now
  732. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  733. writel(host->clk_div | TIFM_MMCSD_POWER,
  734. sock->addr + SOCK_MMCSD_CONFIG);
  735. queue_delayed_work(sock->wq, &host->abort_handler,
  736. host->timeout_jiffies);
  737. return 0;
  738. }
  739. static int tifm_sd_host_is_down(struct tifm_dev *sock)
  740. {
  741. struct mmc_host *mmc = tifm_get_drvdata(sock);
  742. struct tifm_sd *host = mmc_priv(mmc);
  743. unsigned long flags;
  744. int rc = 0;
  745. spin_lock_irqsave(&sock->lock, flags);
  746. rc = (host->flags & EJECT_DONE);
  747. spin_unlock_irqrestore(&sock->lock, flags);
  748. return rc;
  749. }
  750. static void tifm_sd_remove(struct tifm_dev *sock)
  751. {
  752. struct mmc_host *mmc = tifm_get_drvdata(sock);
  753. struct tifm_sd *host = mmc_priv(mmc);
  754. unsigned long flags;
  755. spin_lock_irqsave(&sock->lock, flags);
  756. host->flags |= EJECT;
  757. if (host->req)
  758. queue_work(sock->wq, &host->cmd_handler);
  759. spin_unlock_irqrestore(&sock->lock, flags);
  760. wait_event_timeout(host->can_eject, tifm_sd_host_is_down(sock),
  761. host->timeout_jiffies);
  762. if (host->flags & HOST_REG)
  763. mmc_remove_host(mmc);
  764. /* The meaning of the bit majority in this constant is unknown. */
  765. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  766. sock->addr + SOCK_CONTROL);
  767. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  768. writel(TIFM_FIFO_INT_SETALL,
  769. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  770. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  771. tifm_set_drvdata(sock, NULL);
  772. mmc_free_host(mmc);
  773. }
  774. static tifm_media_id tifm_sd_id_tbl[] = {
  775. FM_SD, 0
  776. };
  777. static struct tifm_driver tifm_sd_driver = {
  778. .driver = {
  779. .name = DRIVER_NAME,
  780. .owner = THIS_MODULE
  781. },
  782. .id_table = tifm_sd_id_tbl,
  783. .probe = tifm_sd_probe,
  784. .remove = tifm_sd_remove
  785. };
  786. static int __init tifm_sd_init(void)
  787. {
  788. return tifm_register_driver(&tifm_sd_driver);
  789. }
  790. static void __exit tifm_sd_exit(void)
  791. {
  792. tifm_unregister_driver(&tifm_sd_driver);
  793. }
  794. MODULE_AUTHOR("Alex Dubov");
  795. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  796. MODULE_LICENSE("GPL");
  797. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  798. MODULE_VERSION(DRIVER_VERSION);
  799. module_init(tifm_sd_init);
  800. module_exit(tifm_sd_exit);