fsl_rio.c 29 KB

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  1. /*
  2. * Freescale MPC85xx/MPC86xx RapidIO support
  3. *
  4. * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
  5. * Zhang Wei <wei.zhang@freescale.com>
  6. *
  7. * Copyright 2005 MontaVista Software, Inc.
  8. * Matt Porter <mporter@kernel.crashing.org>
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/types.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/rio.h>
  21. #include <linux/rio_drv.h>
  22. #include <linux/of_platform.h>
  23. #include <asm/io.h>
  24. /* RapidIO definition irq, which read from OF-tree */
  25. #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
  26. #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
  27. #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
  28. #define RIO_ATMU_REGS_OFFSET 0x10c00
  29. #define RIO_MSG_REGS_OFFSET 0x11000
  30. #define RIO_MAINT_WIN_SIZE 0x400000
  31. #define RIO_DBELL_WIN_SIZE 0x1000
  32. #define RIO_MSG_OMR_MUI 0x00000002
  33. #define RIO_MSG_OSR_TE 0x00000080
  34. #define RIO_MSG_OSR_QOI 0x00000020
  35. #define RIO_MSG_OSR_QFI 0x00000010
  36. #define RIO_MSG_OSR_MUB 0x00000004
  37. #define RIO_MSG_OSR_EOMI 0x00000002
  38. #define RIO_MSG_OSR_QEI 0x00000001
  39. #define RIO_MSG_IMR_MI 0x00000002
  40. #define RIO_MSG_ISR_TE 0x00000080
  41. #define RIO_MSG_ISR_QFI 0x00000010
  42. #define RIO_MSG_ISR_DIQI 0x00000001
  43. #define RIO_MSG_DESC_SIZE 32
  44. #define RIO_MSG_BUFFER_SIZE 4096
  45. #define RIO_MIN_TX_RING_SIZE 2
  46. #define RIO_MAX_TX_RING_SIZE 2048
  47. #define RIO_MIN_RX_RING_SIZE 2
  48. #define RIO_MAX_RX_RING_SIZE 2048
  49. #define DOORBELL_DMR_DI 0x00000002
  50. #define DOORBELL_DSR_TE 0x00000080
  51. #define DOORBELL_DSR_QFI 0x00000010
  52. #define DOORBELL_DSR_DIQI 0x00000001
  53. #define DOORBELL_TID_OFFSET 0x03
  54. #define DOORBELL_SID_OFFSET 0x05
  55. #define DOORBELL_INFO_OFFSET 0x06
  56. #define DOORBELL_MESSAGE_SIZE 0x08
  57. #define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
  58. #define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
  59. #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
  60. struct rio_atmu_regs {
  61. u32 rowtar;
  62. u32 pad1;
  63. u32 rowbar;
  64. u32 pad2;
  65. u32 rowar;
  66. u32 pad3[3];
  67. };
  68. struct rio_msg_regs {
  69. u32 omr;
  70. u32 osr;
  71. u32 pad1;
  72. u32 odqdpar;
  73. u32 pad2;
  74. u32 osar;
  75. u32 odpr;
  76. u32 odatr;
  77. u32 odcr;
  78. u32 pad3;
  79. u32 odqepar;
  80. u32 pad4[13];
  81. u32 imr;
  82. u32 isr;
  83. u32 pad5;
  84. u32 ifqdpar;
  85. u32 pad6;
  86. u32 ifqepar;
  87. u32 pad7[250];
  88. u32 dmr;
  89. u32 dsr;
  90. u32 pad8;
  91. u32 dqdpar;
  92. u32 pad9;
  93. u32 dqepar;
  94. u32 pad10[26];
  95. u32 pwmr;
  96. u32 pwsr;
  97. u32 pad11;
  98. u32 pwqbar;
  99. };
  100. struct rio_tx_desc {
  101. u32 res1;
  102. u32 saddr;
  103. u32 dport;
  104. u32 dattr;
  105. u32 res2;
  106. u32 res3;
  107. u32 dwcnt;
  108. u32 res4;
  109. };
  110. struct rio_dbell_ring {
  111. void *virt;
  112. dma_addr_t phys;
  113. };
  114. struct rio_msg_tx_ring {
  115. void *virt;
  116. dma_addr_t phys;
  117. void *virt_buffer[RIO_MAX_TX_RING_SIZE];
  118. dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
  119. int tx_slot;
  120. int size;
  121. void *dev_id;
  122. };
  123. struct rio_msg_rx_ring {
  124. void *virt;
  125. dma_addr_t phys;
  126. void *virt_buffer[RIO_MAX_RX_RING_SIZE];
  127. int rx_slot;
  128. int size;
  129. void *dev_id;
  130. };
  131. struct rio_priv {
  132. void __iomem *regs_win;
  133. struct rio_atmu_regs __iomem *atmu_regs;
  134. struct rio_atmu_regs __iomem *maint_atmu_regs;
  135. struct rio_atmu_regs __iomem *dbell_atmu_regs;
  136. void __iomem *dbell_win;
  137. void __iomem *maint_win;
  138. struct rio_msg_regs __iomem *msg_regs;
  139. struct rio_dbell_ring dbell_ring;
  140. struct rio_msg_tx_ring msg_tx_ring;
  141. struct rio_msg_rx_ring msg_rx_ring;
  142. int bellirq;
  143. int txirq;
  144. int rxirq;
  145. };
  146. /**
  147. * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
  148. * @index: ID of RapidIO interface
  149. * @destid: Destination ID of target device
  150. * @data: 16-bit info field of RapidIO doorbell message
  151. *
  152. * Sends a MPC85xx doorbell message. Returns %0 on success or
  153. * %-EINVAL on failure.
  154. */
  155. static int fsl_rio_doorbell_send(struct rio_mport *mport,
  156. int index, u16 destid, u16 data)
  157. {
  158. struct rio_priv *priv = mport->priv;
  159. pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
  160. index, destid, data);
  161. out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
  162. out_be16(priv->dbell_win, data);
  163. return 0;
  164. }
  165. /**
  166. * fsl_local_config_read - Generate a MPC85xx local config space read
  167. * @index: ID of RapdiIO interface
  168. * @offset: Offset into configuration space
  169. * @len: Length (in bytes) of the maintenance transaction
  170. * @data: Value to be read into
  171. *
  172. * Generates a MPC85xx local configuration space read. Returns %0 on
  173. * success or %-EINVAL on failure.
  174. */
  175. static int fsl_local_config_read(struct rio_mport *mport,
  176. int index, u32 offset, int len, u32 *data)
  177. {
  178. struct rio_priv *priv = mport->priv;
  179. pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
  180. offset);
  181. *data = in_be32(priv->regs_win + offset);
  182. return 0;
  183. }
  184. /**
  185. * fsl_local_config_write - Generate a MPC85xx local config space write
  186. * @index: ID of RapdiIO interface
  187. * @offset: Offset into configuration space
  188. * @len: Length (in bytes) of the maintenance transaction
  189. * @data: Value to be written
  190. *
  191. * Generates a MPC85xx local configuration space write. Returns %0 on
  192. * success or %-EINVAL on failure.
  193. */
  194. static int fsl_local_config_write(struct rio_mport *mport,
  195. int index, u32 offset, int len, u32 data)
  196. {
  197. struct rio_priv *priv = mport->priv;
  198. pr_debug
  199. ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
  200. index, offset, data);
  201. out_be32(priv->regs_win + offset, data);
  202. return 0;
  203. }
  204. /**
  205. * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
  206. * @index: ID of RapdiIO interface
  207. * @destid: Destination ID of transaction
  208. * @hopcount: Number of hops to target device
  209. * @offset: Offset into configuration space
  210. * @len: Length (in bytes) of the maintenance transaction
  211. * @val: Location to be read into
  212. *
  213. * Generates a MPC85xx read maintenance transaction. Returns %0 on
  214. * success or %-EINVAL on failure.
  215. */
  216. static int
  217. fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
  218. u8 hopcount, u32 offset, int len, u32 *val)
  219. {
  220. struct rio_priv *priv = mport->priv;
  221. u8 *data;
  222. pr_debug
  223. ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
  224. index, destid, hopcount, offset, len);
  225. out_be32(&priv->maint_atmu_regs->rowtar,
  226. (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
  227. data = (u8 *) priv->maint_win + offset;
  228. switch (len) {
  229. case 1:
  230. *val = in_8((u8 *) data);
  231. break;
  232. case 2:
  233. *val = in_be16((u16 *) data);
  234. break;
  235. default:
  236. *val = in_be32((u32 *) data);
  237. break;
  238. }
  239. return 0;
  240. }
  241. /**
  242. * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
  243. * @index: ID of RapdiIO interface
  244. * @destid: Destination ID of transaction
  245. * @hopcount: Number of hops to target device
  246. * @offset: Offset into configuration space
  247. * @len: Length (in bytes) of the maintenance transaction
  248. * @val: Value to be written
  249. *
  250. * Generates an MPC85xx write maintenance transaction. Returns %0 on
  251. * success or %-EINVAL on failure.
  252. */
  253. static int
  254. fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
  255. u8 hopcount, u32 offset, int len, u32 val)
  256. {
  257. struct rio_priv *priv = mport->priv;
  258. u8 *data;
  259. pr_debug
  260. ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
  261. index, destid, hopcount, offset, len, val);
  262. out_be32(&priv->maint_atmu_regs->rowtar,
  263. (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
  264. data = (u8 *) priv->maint_win + offset;
  265. switch (len) {
  266. case 1:
  267. out_8((u8 *) data, val);
  268. break;
  269. case 2:
  270. out_be16((u16 *) data, val);
  271. break;
  272. default:
  273. out_be32((u32 *) data, val);
  274. break;
  275. }
  276. return 0;
  277. }
  278. /**
  279. * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
  280. * @mport: Master port with outbound message queue
  281. * @rdev: Target of outbound message
  282. * @mbox: Outbound mailbox
  283. * @buffer: Message to add to outbound queue
  284. * @len: Length of message
  285. *
  286. * Adds the @buffer message to the MPC85xx outbound message queue. Returns
  287. * %0 on success or %-EINVAL on failure.
  288. */
  289. int
  290. rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
  291. void *buffer, size_t len)
  292. {
  293. struct rio_priv *priv = mport->priv;
  294. u32 omr;
  295. struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
  296. + priv->msg_tx_ring.tx_slot;
  297. int ret = 0;
  298. pr_debug
  299. ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
  300. rdev->destid, mbox, (int)buffer, len);
  301. if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
  302. ret = -EINVAL;
  303. goto out;
  304. }
  305. /* Copy and clear rest of buffer */
  306. memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
  307. len);
  308. if (len < (RIO_MAX_MSG_SIZE - 4))
  309. memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
  310. + len, 0, RIO_MAX_MSG_SIZE - len);
  311. /* Set mbox field for message */
  312. desc->dport = mbox & 0x3;
  313. /* Enable EOMI interrupt, set priority, and set destid */
  314. desc->dattr = 0x28000000 | (rdev->destid << 2);
  315. /* Set transfer size aligned to next power of 2 (in double words) */
  316. desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
  317. /* Set snooping and source buffer address */
  318. desc->saddr = 0x00000004
  319. | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
  320. /* Increment enqueue pointer */
  321. omr = in_be32(&priv->msg_regs->omr);
  322. out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
  323. /* Go to next descriptor */
  324. if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
  325. priv->msg_tx_ring.tx_slot = 0;
  326. out:
  327. return ret;
  328. }
  329. EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
  330. /**
  331. * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
  332. * @irq: Linux interrupt number
  333. * @dev_instance: Pointer to interrupt-specific data
  334. *
  335. * Handles outbound message interrupts. Executes a register outbound
  336. * mailbox event handler and acks the interrupt occurrence.
  337. */
  338. static irqreturn_t
  339. fsl_rio_tx_handler(int irq, void *dev_instance)
  340. {
  341. int osr;
  342. struct rio_mport *port = (struct rio_mport *)dev_instance;
  343. struct rio_priv *priv = port->priv;
  344. osr = in_be32(&priv->msg_regs->osr);
  345. if (osr & RIO_MSG_OSR_TE) {
  346. pr_info("RIO: outbound message transmission error\n");
  347. out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
  348. goto out;
  349. }
  350. if (osr & RIO_MSG_OSR_QOI) {
  351. pr_info("RIO: outbound message queue overflow\n");
  352. out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
  353. goto out;
  354. }
  355. if (osr & RIO_MSG_OSR_EOMI) {
  356. u32 dqp = in_be32(&priv->msg_regs->odqdpar);
  357. int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
  358. port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
  359. slot);
  360. /* Ack the end-of-message interrupt */
  361. out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
  362. }
  363. out:
  364. return IRQ_HANDLED;
  365. }
  366. /**
  367. * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
  368. * @mport: Master port implementing the outbound message unit
  369. * @dev_id: Device specific pointer to pass on event
  370. * @mbox: Mailbox to open
  371. * @entries: Number of entries in the outbound mailbox ring
  372. *
  373. * Initializes buffer ring, request the outbound message interrupt,
  374. * and enables the outbound message unit. Returns %0 on success and
  375. * %-EINVAL or %-ENOMEM on failure.
  376. */
  377. int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
  378. {
  379. int i, j, rc = 0;
  380. struct rio_priv *priv = mport->priv;
  381. if ((entries < RIO_MIN_TX_RING_SIZE) ||
  382. (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
  383. rc = -EINVAL;
  384. goto out;
  385. }
  386. /* Initialize shadow copy ring */
  387. priv->msg_tx_ring.dev_id = dev_id;
  388. priv->msg_tx_ring.size = entries;
  389. for (i = 0; i < priv->msg_tx_ring.size; i++) {
  390. priv->msg_tx_ring.virt_buffer[i] =
  391. dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
  392. &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
  393. if (!priv->msg_tx_ring.virt_buffer[i]) {
  394. rc = -ENOMEM;
  395. for (j = 0; j < priv->msg_tx_ring.size; j++)
  396. if (priv->msg_tx_ring.virt_buffer[j])
  397. dma_free_coherent(NULL,
  398. RIO_MSG_BUFFER_SIZE,
  399. priv->msg_tx_ring.
  400. virt_buffer[j],
  401. priv->msg_tx_ring.
  402. phys_buffer[j]);
  403. goto out;
  404. }
  405. }
  406. /* Initialize outbound message descriptor ring */
  407. priv->msg_tx_ring.virt = dma_alloc_coherent(NULL,
  408. priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
  409. &priv->msg_tx_ring.phys, GFP_KERNEL);
  410. if (!priv->msg_tx_ring.virt) {
  411. rc = -ENOMEM;
  412. goto out_dma;
  413. }
  414. memset(priv->msg_tx_ring.virt, 0,
  415. priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
  416. priv->msg_tx_ring.tx_slot = 0;
  417. /* Point dequeue/enqueue pointers at first entry in ring */
  418. out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
  419. out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
  420. /* Configure for snooping */
  421. out_be32(&priv->msg_regs->osar, 0x00000004);
  422. /* Clear interrupt status */
  423. out_be32(&priv->msg_regs->osr, 0x000000b3);
  424. /* Hook up outbound message handler */
  425. rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
  426. "msg_tx", (void *)mport);
  427. if (rc < 0)
  428. goto out_irq;
  429. /*
  430. * Configure outbound message unit
  431. * Snooping
  432. * Interrupts (all enabled, except QEIE)
  433. * Chaining mode
  434. * Disable
  435. */
  436. out_be32(&priv->msg_regs->omr, 0x00100220);
  437. /* Set number of entries */
  438. out_be32(&priv->msg_regs->omr,
  439. in_be32(&priv->msg_regs->omr) |
  440. ((get_bitmask_order(entries) - 2) << 12));
  441. /* Now enable the unit */
  442. out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
  443. out:
  444. return rc;
  445. out_irq:
  446. dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
  447. priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
  448. out_dma:
  449. for (i = 0; i < priv->msg_tx_ring.size; i++)
  450. dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
  451. priv->msg_tx_ring.virt_buffer[i],
  452. priv->msg_tx_ring.phys_buffer[i]);
  453. return rc;
  454. }
  455. /**
  456. * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
  457. * @mport: Master port implementing the outbound message unit
  458. * @mbox: Mailbox to close
  459. *
  460. * Disables the outbound message unit, free all buffers, and
  461. * frees the outbound message interrupt.
  462. */
  463. void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
  464. {
  465. struct rio_priv *priv = mport->priv;
  466. /* Disable inbound message unit */
  467. out_be32(&priv->msg_regs->omr, 0);
  468. /* Free ring */
  469. dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
  470. priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
  471. /* Free interrupt */
  472. free_irq(IRQ_RIO_TX(mport), (void *)mport);
  473. }
  474. /**
  475. * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
  476. * @irq: Linux interrupt number
  477. * @dev_instance: Pointer to interrupt-specific data
  478. *
  479. * Handles inbound message interrupts. Executes a registered inbound
  480. * mailbox event handler and acks the interrupt occurrence.
  481. */
  482. static irqreturn_t
  483. fsl_rio_rx_handler(int irq, void *dev_instance)
  484. {
  485. int isr;
  486. struct rio_mport *port = (struct rio_mport *)dev_instance;
  487. struct rio_priv *priv = port->priv;
  488. isr = in_be32(&priv->msg_regs->isr);
  489. if (isr & RIO_MSG_ISR_TE) {
  490. pr_info("RIO: inbound message reception error\n");
  491. out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
  492. goto out;
  493. }
  494. /* XXX Need to check/dispatch until queue empty */
  495. if (isr & RIO_MSG_ISR_DIQI) {
  496. /*
  497. * We implement *only* mailbox 0, but can receive messages
  498. * for any mailbox/letter to that mailbox destination. So,
  499. * make the callback with an unknown/invalid mailbox number
  500. * argument.
  501. */
  502. port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
  503. /* Ack the queueing interrupt */
  504. out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
  505. }
  506. out:
  507. return IRQ_HANDLED;
  508. }
  509. /**
  510. * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
  511. * @mport: Master port implementing the inbound message unit
  512. * @dev_id: Device specific pointer to pass on event
  513. * @mbox: Mailbox to open
  514. * @entries: Number of entries in the inbound mailbox ring
  515. *
  516. * Initializes buffer ring, request the inbound message interrupt,
  517. * and enables the inbound message unit. Returns %0 on success
  518. * and %-EINVAL or %-ENOMEM on failure.
  519. */
  520. int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
  521. {
  522. int i, rc = 0;
  523. struct rio_priv *priv = mport->priv;
  524. if ((entries < RIO_MIN_RX_RING_SIZE) ||
  525. (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
  526. rc = -EINVAL;
  527. goto out;
  528. }
  529. /* Initialize client buffer ring */
  530. priv->msg_rx_ring.dev_id = dev_id;
  531. priv->msg_rx_ring.size = entries;
  532. priv->msg_rx_ring.rx_slot = 0;
  533. for (i = 0; i < priv->msg_rx_ring.size; i++)
  534. priv->msg_rx_ring.virt_buffer[i] = NULL;
  535. /* Initialize inbound message ring */
  536. priv->msg_rx_ring.virt = dma_alloc_coherent(NULL,
  537. priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
  538. &priv->msg_rx_ring.phys, GFP_KERNEL);
  539. if (!priv->msg_rx_ring.virt) {
  540. rc = -ENOMEM;
  541. goto out;
  542. }
  543. /* Point dequeue/enqueue pointers at first entry in ring */
  544. out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
  545. out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
  546. /* Clear interrupt status */
  547. out_be32(&priv->msg_regs->isr, 0x00000091);
  548. /* Hook up inbound message handler */
  549. rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
  550. "msg_rx", (void *)mport);
  551. if (rc < 0) {
  552. dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
  553. priv->msg_tx_ring.virt_buffer[i],
  554. priv->msg_tx_ring.phys_buffer[i]);
  555. goto out;
  556. }
  557. /*
  558. * Configure inbound message unit:
  559. * Snooping
  560. * 4KB max message size
  561. * Unmask all interrupt sources
  562. * Disable
  563. */
  564. out_be32(&priv->msg_regs->imr, 0x001b0060);
  565. /* Set number of queue entries */
  566. setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
  567. /* Now enable the unit */
  568. setbits32(&priv->msg_regs->imr, 0x1);
  569. out:
  570. return rc;
  571. }
  572. /**
  573. * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
  574. * @mport: Master port implementing the inbound message unit
  575. * @mbox: Mailbox to close
  576. *
  577. * Disables the inbound message unit, free all buffers, and
  578. * frees the inbound message interrupt.
  579. */
  580. void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
  581. {
  582. struct rio_priv *priv = mport->priv;
  583. /* Disable inbound message unit */
  584. out_be32(&priv->msg_regs->imr, 0);
  585. /* Free ring */
  586. dma_free_coherent(NULL, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
  587. priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
  588. /* Free interrupt */
  589. free_irq(IRQ_RIO_RX(mport), (void *)mport);
  590. }
  591. /**
  592. * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
  593. * @mport: Master port implementing the inbound message unit
  594. * @mbox: Inbound mailbox number
  595. * @buf: Buffer to add to inbound queue
  596. *
  597. * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
  598. * %0 on success or %-EINVAL on failure.
  599. */
  600. int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
  601. {
  602. int rc = 0;
  603. struct rio_priv *priv = mport->priv;
  604. pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
  605. priv->msg_rx_ring.rx_slot);
  606. if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
  607. printk(KERN_ERR
  608. "RIO: error adding inbound buffer %d, buffer exists\n",
  609. priv->msg_rx_ring.rx_slot);
  610. rc = -EINVAL;
  611. goto out;
  612. }
  613. priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
  614. if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
  615. priv->msg_rx_ring.rx_slot = 0;
  616. out:
  617. return rc;
  618. }
  619. EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
  620. /**
  621. * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
  622. * @mport: Master port implementing the inbound message unit
  623. * @mbox: Inbound mailbox number
  624. *
  625. * Gets the next available inbound message from the inbound message queue.
  626. * A pointer to the message is returned on success or NULL on failure.
  627. */
  628. void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
  629. {
  630. struct rio_priv *priv = mport->priv;
  631. u32 phys_buf, virt_buf;
  632. void *buf = NULL;
  633. int buf_idx;
  634. phys_buf = in_be32(&priv->msg_regs->ifqdpar);
  635. /* If no more messages, then bail out */
  636. if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
  637. goto out2;
  638. virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
  639. - priv->msg_rx_ring.phys);
  640. buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
  641. buf = priv->msg_rx_ring.virt_buffer[buf_idx];
  642. if (!buf) {
  643. printk(KERN_ERR
  644. "RIO: inbound message copy failed, no buffers\n");
  645. goto out1;
  646. }
  647. /* Copy max message size, caller is expected to allocate that big */
  648. memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
  649. /* Clear the available buffer */
  650. priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
  651. out1:
  652. setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
  653. out2:
  654. return buf;
  655. }
  656. EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
  657. /**
  658. * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
  659. * @irq: Linux interrupt number
  660. * @dev_instance: Pointer to interrupt-specific data
  661. *
  662. * Handles doorbell interrupts. Parses a list of registered
  663. * doorbell event handlers and executes a matching event handler.
  664. */
  665. static irqreturn_t
  666. fsl_rio_dbell_handler(int irq, void *dev_instance)
  667. {
  668. int dsr;
  669. struct rio_mport *port = (struct rio_mport *)dev_instance;
  670. struct rio_priv *priv = port->priv;
  671. dsr = in_be32(&priv->msg_regs->dsr);
  672. if (dsr & DOORBELL_DSR_TE) {
  673. pr_info("RIO: doorbell reception error\n");
  674. out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
  675. goto out;
  676. }
  677. if (dsr & DOORBELL_DSR_QFI) {
  678. pr_info("RIO: doorbell queue full\n");
  679. out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
  680. goto out;
  681. }
  682. /* XXX Need to check/dispatch until queue empty */
  683. if (dsr & DOORBELL_DSR_DIQI) {
  684. u32 dmsg =
  685. (u32) priv->dbell_ring.virt +
  686. (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
  687. struct rio_dbell *dbell;
  688. int found = 0;
  689. pr_debug
  690. ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
  691. DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
  692. list_for_each_entry(dbell, &port->dbells, node) {
  693. if ((dbell->res->start <= DBELL_INF(dmsg)) &&
  694. (dbell->res->end >= DBELL_INF(dmsg))) {
  695. found = 1;
  696. break;
  697. }
  698. }
  699. if (found) {
  700. dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
  701. DBELL_INF(dmsg));
  702. } else {
  703. pr_debug
  704. ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
  705. DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
  706. }
  707. setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
  708. out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
  709. }
  710. out:
  711. return IRQ_HANDLED;
  712. }
  713. /**
  714. * fsl_rio_doorbell_init - MPC85xx doorbell interface init
  715. * @mport: Master port implementing the inbound doorbell unit
  716. *
  717. * Initializes doorbell unit hardware and inbound DMA buffer
  718. * ring. Called from fsl_rio_setup(). Returns %0 on success
  719. * or %-ENOMEM on failure.
  720. */
  721. static int fsl_rio_doorbell_init(struct rio_mport *mport)
  722. {
  723. struct rio_priv *priv = mport->priv;
  724. int rc = 0;
  725. /* Map outbound doorbell window immediately after maintenance window */
  726. priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
  727. RIO_DBELL_WIN_SIZE);
  728. if (!priv->dbell_win) {
  729. printk(KERN_ERR
  730. "RIO: unable to map outbound doorbell window\n");
  731. rc = -ENOMEM;
  732. goto out;
  733. }
  734. /* Initialize inbound doorbells */
  735. priv->dbell_ring.virt = dma_alloc_coherent(NULL, 512 *
  736. DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
  737. if (!priv->dbell_ring.virt) {
  738. printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
  739. rc = -ENOMEM;
  740. iounmap(priv->dbell_win);
  741. goto out;
  742. }
  743. /* Point dequeue/enqueue pointers at first entry in ring */
  744. out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
  745. out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
  746. /* Clear interrupt status */
  747. out_be32(&priv->msg_regs->dsr, 0x00000091);
  748. /* Hook up doorbell handler */
  749. rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
  750. "dbell_rx", (void *)mport);
  751. if (rc < 0) {
  752. iounmap(priv->dbell_win);
  753. dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
  754. priv->dbell_ring.virt, priv->dbell_ring.phys);
  755. printk(KERN_ERR
  756. "MPC85xx RIO: unable to request inbound doorbell irq");
  757. goto out;
  758. }
  759. /* Configure doorbells for snooping, 512 entries, and enable */
  760. out_be32(&priv->msg_regs->dmr, 0x00108161);
  761. out:
  762. return rc;
  763. }
  764. static char *cmdline = NULL;
  765. static int fsl_rio_get_hdid(int index)
  766. {
  767. /* XXX Need to parse multiple entries in some format */
  768. if (!cmdline)
  769. return -1;
  770. return simple_strtol(cmdline, NULL, 0);
  771. }
  772. static int fsl_rio_get_cmdline(char *s)
  773. {
  774. if (!s)
  775. return 0;
  776. cmdline = s;
  777. return 1;
  778. }
  779. __setup("riohdid=", fsl_rio_get_cmdline);
  780. /**
  781. * fsl_rio_setup - Setup MPC85xx RapidIO interface
  782. * @fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
  783. *
  784. * Initializes MPC85xx RapidIO hardware interface, configures
  785. * master port with system-specific info, and registers the
  786. * master port with the RapidIO subsystem.
  787. */
  788. int fsl_rio_setup(struct of_device *dev)
  789. {
  790. struct rio_ops *ops;
  791. struct rio_mport *port;
  792. struct rio_priv *priv;
  793. int rc = 0;
  794. const u32 *dt_range, *cell;
  795. struct resource regs;
  796. int rlen;
  797. u64 law_start, law_size;
  798. int paw, aw, sw;
  799. if (!dev->node) {
  800. dev_err(&dev->dev, "Device OF-Node is NULL");
  801. return -EFAULT;
  802. }
  803. rc = of_address_to_resource(dev->node, 0, &regs);
  804. if (rc) {
  805. dev_err(&dev->dev, "Can't get %s property 'reg'\n",
  806. dev->node->full_name);
  807. return -EFAULT;
  808. }
  809. dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name);
  810. dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n", regs.start,
  811. regs.end - regs.start + 1);
  812. dt_range = of_get_property(dev->node, "ranges", &rlen);
  813. if (!dt_range) {
  814. dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
  815. dev->node->full_name);
  816. return -EFAULT;
  817. }
  818. /* Get node address wide */
  819. cell = of_get_property(dev->node, "#address-cells", NULL);
  820. if (cell)
  821. aw = *cell;
  822. else
  823. aw = of_n_addr_cells(dev->node);
  824. /* Get node size wide */
  825. cell = of_get_property(dev->node, "#size-cells", NULL);
  826. if (cell)
  827. sw = *cell;
  828. else
  829. sw = of_n_size_cells(dev->node);
  830. /* Get parent address wide wide */
  831. paw = of_n_addr_cells(dev->node);
  832. law_start = of_read_number(dt_range + aw, paw);
  833. law_size = of_read_number(dt_range + aw + paw, sw);
  834. dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
  835. law_start, law_size);
  836. ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
  837. ops->lcread = fsl_local_config_read;
  838. ops->lcwrite = fsl_local_config_write;
  839. ops->cread = fsl_rio_config_read;
  840. ops->cwrite = fsl_rio_config_write;
  841. ops->dsend = fsl_rio_doorbell_send;
  842. port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
  843. port->id = 0;
  844. port->index = 0;
  845. priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
  846. if (!priv) {
  847. printk(KERN_ERR "Can't alloc memory for 'priv'\n");
  848. rc = -ENOMEM;
  849. goto err;
  850. }
  851. INIT_LIST_HEAD(&port->dbells);
  852. port->iores.start = law_start;
  853. port->iores.end = law_start + law_size;
  854. port->iores.flags = IORESOURCE_MEM;
  855. priv->bellirq = irq_of_parse_and_map(dev->node, 2);
  856. priv->txirq = irq_of_parse_and_map(dev->node, 3);
  857. priv->rxirq = irq_of_parse_and_map(dev->node, 4);
  858. dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq,
  859. priv->txirq, priv->rxirq);
  860. rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
  861. rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
  862. rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
  863. strcpy(port->name, "RIO0 mport");
  864. port->ops = ops;
  865. port->host_deviceid = fsl_rio_get_hdid(port->id);
  866. port->priv = priv;
  867. rio_register_mport(port);
  868. priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
  869. port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
  870. & RIO_PEF_CTLS) >> 4;
  871. dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
  872. port->sys_size ? 65536 : 256);
  873. priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
  874. + RIO_ATMU_REGS_OFFSET);
  875. priv->maint_atmu_regs = priv->atmu_regs + 1;
  876. priv->dbell_atmu_regs = priv->atmu_regs + 2;
  877. priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win
  878. + RIO_MSG_REGS_OFFSET);
  879. /* Configure maintenance transaction window */
  880. out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000);
  881. out_be32(&priv->maint_atmu_regs->rowar, 0x80077015);
  882. priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
  883. /* Configure outbound doorbell window */
  884. out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400);
  885. out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);
  886. fsl_rio_doorbell_init(port);
  887. return 0;
  888. err:
  889. if (priv)
  890. iounmap(priv->regs_win);
  891. kfree(ops);
  892. kfree(priv);
  893. kfree(port);
  894. return rc;
  895. }
  896. /* The probe function for RapidIO peer-to-peer network.
  897. */
  898. static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
  899. const struct of_device_id *match)
  900. {
  901. int rc;
  902. printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
  903. dev->node->full_name);
  904. rc = fsl_rio_setup(dev);
  905. if (rc)
  906. goto out;
  907. /* Enumerate all registered ports */
  908. rc = rio_init_mports();
  909. out:
  910. return rc;
  911. };
  912. static const struct of_device_id fsl_of_rio_rpn_ids[] = {
  913. {
  914. .compatible = "fsl,rapidio-delta",
  915. },
  916. {},
  917. };
  918. static struct of_platform_driver fsl_of_rio_rpn_driver = {
  919. .name = "fsl-of-rio",
  920. .match_table = fsl_of_rio_rpn_ids,
  921. .probe = fsl_of_rio_rpn_probe,
  922. };
  923. static __init int fsl_of_rio_rpn_init(void)
  924. {
  925. return of_register_platform_driver(&fsl_of_rio_rpn_driver);
  926. }
  927. subsys_initcall(fsl_of_rio_rpn_init);