gdth.c 203 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-04 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-04 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.2.x, 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.73 2004/03/31 13:33:03 achim
  34. * Special command 0xfd implemented to detect 64-bit DMA support
  35. *
  36. * Revision 1.72 2004/03/17 08:56:04 achim
  37. * 64-bit DMA only enabled if FW >= x.43
  38. *
  39. * Revision 1.71 2004/03/05 15:51:29 achim
  40. * Screen service: separate message buffer, bugfixes
  41. *
  42. * Revision 1.70 2004/02/27 12:19:07 achim
  43. * Bugfix: Reset bit in config (0xfe) call removed
  44. *
  45. * Revision 1.69 2004/02/20 09:50:24 achim
  46. * Compatibility changes for kernels < 2.4.20
  47. * Bugfix screen service command size
  48. * pci_set_dma_mask() error handling added
  49. *
  50. * Revision 1.68 2004/02/19 15:46:54 achim
  51. * 64-bit DMA bugfixes
  52. * Drive size bugfix for drives > 1TB
  53. *
  54. * Revision 1.67 2004/01/14 13:11:57 achim
  55. * Tool access over /proc no longer supported
  56. * Bugfixes IOCTLs
  57. *
  58. * Revision 1.66 2003/12/19 15:04:06 achim
  59. * Bugfixes support for drives > 2TB
  60. *
  61. * Revision 1.65 2003/12/15 11:21:56 achim
  62. * 64-bit DMA support added
  63. * Support for drives > 2 TB implemented
  64. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  65. *
  66. * Revision 1.64 2003/09/17 08:30:26 achim
  67. * EISA/ISA controller scan disabled
  68. * Command line switch probe_eisa_isa added
  69. *
  70. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  71. * Minor cleanups in gdth_ioctl.
  72. *
  73. * Revision 1.62 2003/02/27 15:01:59 achim
  74. * Dynamic DMA mapping implemented
  75. * New (character device) IOCTL interface added
  76. * Other controller related changes made
  77. *
  78. * Revision 1.61 2002/11/08 13:09:52 boji
  79. * Added support for XSCALE based RAID Controllers
  80. * Fixed SCREENSERVICE initialization in SMP cases
  81. * Added checks for gdth_polling before GDTH_HA_LOCK
  82. *
  83. * Revision 1.60 2002/02/05 09:35:22 achim
  84. * MODULE_LICENSE only if kernel >= 2.4.11
  85. *
  86. * Revision 1.59 2002/01/30 09:46:33 achim
  87. * Small changes
  88. *
  89. * Revision 1.58 2002/01/29 15:30:02 achim
  90. * Set default value of shared_access to Y
  91. * New status S_CACHE_RESERV for clustering added
  92. *
  93. * Revision 1.57 2001/08/21 11:16:35 achim
  94. * Bugfix free_irq()
  95. *
  96. * Revision 1.56 2001/08/09 11:19:39 achim
  97. * struct scsi_host_template changes
  98. *
  99. * Revision 1.55 2001/08/09 10:11:28 achim
  100. * Command HOST_UNFREEZE_IO before cache service init.
  101. *
  102. * Revision 1.54 2001/07/20 13:48:12 achim
  103. * Expand: gdth_analyse_hdrive() removed
  104. *
  105. * Revision 1.53 2001/07/17 09:52:49 achim
  106. * Small OEM related change
  107. *
  108. * Revision 1.52 2001/06/19 15:06:20 achim
  109. * New host command GDT_UNFREEZE_IO added
  110. *
  111. * Revision 1.51 2001/05/22 06:42:37 achim
  112. * PCI: Subdevice ID added
  113. *
  114. * Revision 1.50 2001/05/17 13:42:16 achim
  115. * Support for Intel Storage RAID Controllers added
  116. *
  117. * Revision 1.50 2001/05/17 12:12:34 achim
  118. * Support for Intel Storage RAID Controllers added
  119. *
  120. * Revision 1.49 2001/03/15 15:07:17 achim
  121. * New __setup interface for boot command line options added
  122. *
  123. * Revision 1.48 2001/02/06 12:36:28 achim
  124. * Bugfix Cluster protocol
  125. *
  126. * Revision 1.47 2001/01/10 14:42:06 achim
  127. * New switch shared_access added
  128. *
  129. * Revision 1.46 2001/01/09 08:11:35 achim
  130. * gdth_command() removed
  131. * meaning of Scsi_Pointer members changed
  132. *
  133. * Revision 1.45 2000/11/16 12:02:24 achim
  134. * Changes for kernel 2.4
  135. *
  136. * Revision 1.44 2000/10/11 08:44:10 achim
  137. * Clustering changes: New flag media_changed added
  138. *
  139. * Revision 1.43 2000/09/20 12:59:01 achim
  140. * DPMEM remap functions for all PCI controller types implemented
  141. * Small changes for ia64 platform
  142. *
  143. * Revision 1.42 2000/07/20 09:04:50 achim
  144. * Small changes for kernel 2.4
  145. *
  146. * Revision 1.41 2000/07/04 14:11:11 achim
  147. * gdth_analyse_hdrive() added to rescan drives after online expansion
  148. *
  149. * Revision 1.40 2000/06/27 11:24:16 achim
  150. * Changes Clustering, Screenservice
  151. *
  152. * Revision 1.39 2000/06/15 13:09:04 achim
  153. * Changes for gdth_do_cmd()
  154. *
  155. * Revision 1.38 2000/06/15 12:08:43 achim
  156. * Bugfix gdth_sync_event(), service SCREENSERVICE
  157. * Data direction for command 0xc2 changed to DOU
  158. *
  159. * Revision 1.37 2000/05/25 13:50:10 achim
  160. * New driver parameter virt_ctr added
  161. *
  162. * Revision 1.36 2000/05/04 08:50:46 achim
  163. * Event buffer now in gdth_ha_str
  164. *
  165. * Revision 1.35 2000/03/03 10:44:08 achim
  166. * New event_string only valid for the RP controller family
  167. *
  168. * Revision 1.34 2000/03/02 14:55:29 achim
  169. * New mechanism for async. event handling implemented
  170. *
  171. * Revision 1.33 2000/02/21 15:37:37 achim
  172. * Bugfix Alpha platform + DPMEM above 4GB
  173. *
  174. * Revision 1.32 2000/02/14 16:17:37 achim
  175. * Bugfix sense_buffer[] + raw devices
  176. *
  177. * Revision 1.31 2000/02/10 10:29:00 achim
  178. * Delete sense_buffer[0], if command OK
  179. *
  180. * Revision 1.30 1999/11/02 13:42:39 achim
  181. * ARRAY_DRV_LIST2 implemented
  182. * Now 255 log. and 100 host drives supported
  183. *
  184. * Revision 1.29 1999/10/05 13:28:47 achim
  185. * GDT_CLUST_RESET added
  186. *
  187. * Revision 1.28 1999/08/12 13:44:54 achim
  188. * MOUNTALL removed
  189. * Cluster drives -> removeable drives
  190. *
  191. * Revision 1.27 1999/06/22 07:22:38 achim
  192. * Small changes
  193. *
  194. * Revision 1.26 1999/06/10 16:09:12 achim
  195. * Cluster Host Drive support: Bugfixes
  196. *
  197. * Revision 1.25 1999/06/01 16:03:56 achim
  198. * gdth_init_pci(): Manipulate config. space to start RP controller
  199. *
  200. * Revision 1.24 1999/05/26 11:53:06 achim
  201. * Cluster Host Drive support added
  202. *
  203. * Revision 1.23 1999/03/26 09:12:31 achim
  204. * Default value for hdr_channel set to 0
  205. *
  206. * Revision 1.22 1999/03/22 16:27:16 achim
  207. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  208. *
  209. * Revision 1.21 1999/03/16 13:40:34 achim
  210. * Problems with reserved drives solved
  211. * gdth_eh_bus_reset() implemented
  212. *
  213. * Revision 1.20 1999/03/10 09:08:13 achim
  214. * Bugfix: Corrections in gdth_direction_tab[] made
  215. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  216. *
  217. * Revision 1.19 1999/03/05 14:38:16 achim
  218. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  219. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  220. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  221. * with BIOS disabled and memory test set to Intensive
  222. * Enhanced /proc support
  223. *
  224. * Revision 1.18 1999/02/24 09:54:33 achim
  225. * Command line parameter hdr_channel implemented
  226. * Bugfix for EISA controllers + Linux 2.2.x
  227. *
  228. * Revision 1.17 1998/12/17 15:58:11 achim
  229. * Command line parameters implemented
  230. * Changes for Alpha platforms
  231. * PCI controller scan changed
  232. * SMP support improved (spin_lock_irqsave(),...)
  233. * New async. events, new scan/reserve commands included
  234. *
  235. * Revision 1.16 1998/09/28 16:08:46 achim
  236. * GDT_PCIMPR: DPMEM remapping, if required
  237. * mdelay() added
  238. *
  239. * Revision 1.15 1998/06/03 14:54:06 achim
  240. * gdth_delay(), gdth_flush() implemented
  241. * Bugfix: gdth_release() changed
  242. *
  243. * Revision 1.14 1998/05/22 10:01:17 achim
  244. * mj: pcibios_strerror() removed
  245. * Improved SMP support (if version >= 2.1.95)
  246. * gdth_halt(): halt_called flag added (if version < 2.1)
  247. *
  248. * Revision 1.13 1998/04/16 09:14:57 achim
  249. * Reserve drives (for raw service) implemented
  250. * New error handling code enabled
  251. * Get controller name from board_info() IOCTL
  252. * Final round of PCI device driver patches by Martin Mares
  253. *
  254. * Revision 1.12 1998/03/03 09:32:37 achim
  255. * Fibre channel controller support added
  256. *
  257. * Revision 1.11 1998/01/27 16:19:14 achim
  258. * SA_SHIRQ added
  259. * add_timer()/del_timer() instead of GDTH_TIMER
  260. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  261. * New error handling included
  262. *
  263. * Revision 1.10 1997/10/31 12:29:57 achim
  264. * Read heads/sectors from host drive
  265. *
  266. * Revision 1.9 1997/09/04 10:07:25 achim
  267. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  268. * register_reboot_notifier() to get a notify on shutown used
  269. *
  270. * Revision 1.8 1997/04/02 12:14:30 achim
  271. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  272. *
  273. * Revision 1.7 1997/03/12 13:33:37 achim
  274. * gdth_reset() changed, new async. events
  275. *
  276. * Revision 1.6 1997/03/04 14:01:11 achim
  277. * Shutdown routine gdth_halt() implemented
  278. *
  279. * Revision 1.5 1997/02/21 09:08:36 achim
  280. * New controller included (RP, RP1, RP2 series)
  281. * IOCTL interface implemented
  282. *
  283. * Revision 1.4 1996/07/05 12:48:55 achim
  284. * Function gdth_bios_param() implemented
  285. * New constant GDTH_MAXC_P_L inserted
  286. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  287. * Function gdth_reset() changed
  288. *
  289. * Revision 1.3 1996/05/10 09:04:41 achim
  290. * Small changes for Linux 1.2.13
  291. *
  292. * Revision 1.2 1996/05/09 12:45:27 achim
  293. * Loadable module support implemented
  294. * /proc support corrections made
  295. *
  296. * Revision 1.1 1996/04/11 07:35:57 achim
  297. * Initial revision
  298. *
  299. ************************************************************************/
  300. /* All GDT Disk Array Controllers are fully supported by this driver.
  301. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  302. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  303. * list of all controller types.
  304. *
  305. * If you have one or more GDT3000/3020 EISA controllers with
  306. * controller BIOS disabled, you have to set the IRQ values with the
  307. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  308. * the IRQ values for the EISA controllers.
  309. *
  310. * After the optional list of IRQ values, other possible
  311. * command line options are:
  312. * disable:Y disable driver
  313. * disable:N enable driver
  314. * reserve_mode:0 reserve no drives for the raw service
  315. * reserve_mode:1 reserve all not init., removable drives
  316. * reserve_mode:2 reserve all not init. drives
  317. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  318. * h- controller no., b- channel no.,
  319. * t- target ID, l- LUN
  320. * reverse_scan:Y reverse scan order for PCI controllers
  321. * reverse_scan:N scan PCI controllers like BIOS
  322. * max_ids:x x - target ID count per channel (1..MAXID)
  323. * rescan:Y rescan all channels/IDs
  324. * rescan:N use all devices found until now
  325. * virt_ctr:Y map every channel to a virtual controller
  326. * virt_ctr:N use multi channel support
  327. * hdr_channel:x x - number of virtual bus for host drives
  328. * shared_access:Y disable driver reserve/release protocol to
  329. * access a shared resource from several nodes,
  330. * appropriate controller firmware required
  331. * shared_access:N enable driver reserve/release protocol
  332. * probe_eisa_isa:Y scan for EISA/ISA controllers
  333. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  334. * force_dma32:Y use only 32 bit DMA mode
  335. * force_dma32:N use 64 bit DMA mode, if supported
  336. *
  337. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  338. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  339. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  340. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  341. *
  342. * When loading the gdth driver as a module, the same options are available.
  343. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  344. * options changes slightly. You must replace all ',' between options
  345. * with ' ' and all ':' with '=' and you must use
  346. * '1' in place of 'Y' and '0' in place of 'N'.
  347. *
  348. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  349. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  350. * probe_eisa_isa=0 force_dma32=0"
  351. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  352. */
  353. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  354. * ptr: Chaining
  355. * this_residual: Command priority
  356. * buffer: phys. DMA sense buffer
  357. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  358. * buffers_residual: Timeout value
  359. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  360. * Message: Additional info (gdth_do_cmd()), DMA direction
  361. * have_data_in: Flag for gdth_wait_completion()
  362. * sent_command: Opcode special command
  363. * phase: Service/parameter/return code special command
  364. */
  365. /* interrupt coalescing */
  366. /* #define INT_COAL */
  367. /* statistics */
  368. #define GDTH_STATISTICS
  369. #include <linux/module.h>
  370. #include <linux/version.h>
  371. #include <linux/kernel.h>
  372. #include <linux/types.h>
  373. #include <linux/pci.h>
  374. #include <linux/string.h>
  375. #include <linux/ctype.h>
  376. #include <linux/ioport.h>
  377. #include <linux/delay.h>
  378. #include <linux/sched.h>
  379. #include <linux/interrupt.h>
  380. #include <linux/in.h>
  381. #include <linux/proc_fs.h>
  382. #include <linux/time.h>
  383. #include <linux/timer.h>
  384. #ifdef GDTH_RTC
  385. #include <linux/mc146818rtc.h>
  386. #endif
  387. #include <linux/reboot.h>
  388. #include <asm/dma.h>
  389. #include <asm/system.h>
  390. #include <asm/io.h>
  391. #include <asm/uaccess.h>
  392. #include <linux/spinlock.h>
  393. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  394. #include <linux/blkdev.h>
  395. #else
  396. #include <linux/blk.h>
  397. #include "sd.h"
  398. #endif
  399. #include "scsi.h"
  400. #include <scsi/scsi_host.h>
  401. #include "gdth.h"
  402. #include "gdth_kcompat.h"
  403. static void gdth_delay(int milliseconds);
  404. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  405. static irqreturn_t gdth_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  406. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  407. static int gdth_async_event(int hanum);
  408. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  409. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  410. static void gdth_next(int hanum);
  411. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  412. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  413. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  414. ushort idx, gdth_evt_data *evt);
  415. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  416. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  417. gdth_evt_str *estr);
  418. static void gdth_clear_events(void);
  419. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  420. char *buffer,ushort count);
  421. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  422. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  423. static int gdth_search_eisa(ushort eisa_adr);
  424. static int gdth_search_isa(ulong32 bios_adr);
  425. static int gdth_search_pci(gdth_pci_str *pcistr);
  426. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  427. ushort vendor, ushort dev);
  428. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  429. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  430. static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
  431. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  432. static void gdth_enable_int(int hanum);
  433. static int gdth_get_status(unchar *pIStatus,int irq);
  434. static int gdth_test_busy(int hanum);
  435. static int gdth_get_cmd_index(int hanum);
  436. static void gdth_release_event(int hanum);
  437. static int gdth_wait(int hanum,int index,ulong32 time);
  438. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  439. ulong64 p2,ulong64 p3);
  440. static int gdth_search_drives(int hanum);
  441. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  442. static const char *gdth_ctr_name(int hanum);
  443. static int gdth_open(struct inode *inode, struct file *filep);
  444. static int gdth_close(struct inode *inode, struct file *filep);
  445. static int gdth_ioctl(struct inode *inode, struct file *filep,
  446. unsigned int cmd, unsigned long arg);
  447. static void gdth_flush(int hanum);
  448. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  449. #ifdef DEBUG_GDTH
  450. static unchar DebugState = DEBUG_GDTH;
  451. #ifdef __SERIAL__
  452. #define MAX_SERBUF 160
  453. static void ser_init(void);
  454. static void ser_puts(char *str);
  455. static void ser_putc(char c);
  456. static int ser_printk(const char *fmt, ...);
  457. static char strbuf[MAX_SERBUF+1];
  458. #ifdef __COM2__
  459. #define COM_BASE 0x2f8
  460. #else
  461. #define COM_BASE 0x3f8
  462. #endif
  463. static void ser_init()
  464. {
  465. unsigned port=COM_BASE;
  466. outb(0x80,port+3);
  467. outb(0,port+1);
  468. /* 19200 Baud, if 9600: outb(12,port) */
  469. outb(6, port);
  470. outb(3,port+3);
  471. outb(0,port+1);
  472. /*
  473. ser_putc('I');
  474. ser_putc(' ');
  475. */
  476. }
  477. static void ser_puts(char *str)
  478. {
  479. char *ptr;
  480. ser_init();
  481. for (ptr=str;*ptr;++ptr)
  482. ser_putc(*ptr);
  483. }
  484. static void ser_putc(char c)
  485. {
  486. unsigned port=COM_BASE;
  487. while ((inb(port+5) & 0x20)==0);
  488. outb(c,port);
  489. if (c==0x0a)
  490. {
  491. while ((inb(port+5) & 0x20)==0);
  492. outb(0x0d,port);
  493. }
  494. }
  495. static int ser_printk(const char *fmt, ...)
  496. {
  497. va_list args;
  498. int i;
  499. va_start(args,fmt);
  500. i = vsprintf(strbuf,fmt,args);
  501. ser_puts(strbuf);
  502. va_end(args);
  503. return i;
  504. }
  505. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  506. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  507. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  508. #else /* !__SERIAL__ */
  509. #define TRACE(a) {if (DebugState==1) {printk a;}}
  510. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  511. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  512. #endif
  513. #else /* !DEBUG */
  514. #define TRACE(a)
  515. #define TRACE2(a)
  516. #define TRACE3(a)
  517. #endif
  518. #ifdef GDTH_STATISTICS
  519. static ulong32 max_rq=0, max_index=0, max_sg=0;
  520. #ifdef INT_COAL
  521. static ulong32 max_int_coal=0;
  522. #endif
  523. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  524. static struct timer_list gdth_timer;
  525. #endif
  526. #define PTR2USHORT(a) (ushort)(ulong)(a)
  527. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  528. #define INDEX_OK(i,t) ((i)<sizeof(t)/sizeof((t)[0]))
  529. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  530. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  531. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  532. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  533. #define gdth_readb(addr) readb(addr)
  534. #define gdth_readw(addr) readw(addr)
  535. #define gdth_readl(addr) readl(addr)
  536. #define gdth_writeb(b,addr) writeb((b),(addr))
  537. #define gdth_writew(b,addr) writew((b),(addr))
  538. #define gdth_writel(b,addr) writel((b),(addr))
  539. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  540. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  541. static unchar gdth_polling; /* polling if TRUE */
  542. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  543. static int wait_index,wait_hanum; /* gdth_wait() */
  544. static int gdth_ctr_count = 0; /* controller count */
  545. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  546. static int gdth_ctr_released = 0; /* gdth_release() */
  547. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  548. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  549. static unchar gdth_write_through = FALSE; /* write through */
  550. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  551. static int elastidx;
  552. static int eoldidx;
  553. static int major;
  554. #define DIN 1 /* IN data direction */
  555. #define DOU 2 /* OUT data direction */
  556. #define DNO DIN /* no data transfer */
  557. #define DUN DIN /* unknown data direction */
  558. static unchar gdth_direction_tab[0x100] = {
  559. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  560. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  561. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  562. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  563. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  564. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  565. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  566. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  567. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  568. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  569. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  570. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  571. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  572. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  573. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  574. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  575. };
  576. /* LILO and modprobe/insmod parameters */
  577. /* IRQ list for GDT3000/3020 EISA controllers */
  578. static int irq[MAXHA] __initdata =
  579. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  580. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  581. /* disable driver flag */
  582. static int disable __initdata = 0;
  583. /* reserve flag */
  584. static int reserve_mode = 1;
  585. /* reserve list */
  586. static int reserve_list[MAX_RES_ARGS] =
  587. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  588. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  589. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  590. /* scan order for PCI controllers */
  591. static int reverse_scan = 0;
  592. /* virtual channel for the host drives */
  593. static int hdr_channel = 0;
  594. /* max. IDs per channel */
  595. static int max_ids = MAXID;
  596. /* rescan all IDs */
  597. static int rescan = 0;
  598. /* map channels to virtual controllers */
  599. static int virt_ctr = 0;
  600. /* shared access */
  601. static int shared_access = 1;
  602. /* enable support for EISA and ISA controllers */
  603. static int probe_eisa_isa = 0;
  604. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  605. static int force_dma32 = 0;
  606. /* parameters for modprobe/insmod */
  607. module_param_array(irq, int, NULL, 0);
  608. module_param(disable, int, 0);
  609. module_param(reserve_mode, int, 0);
  610. module_param_array(reserve_list, int, NULL, 0);
  611. module_param(reverse_scan, int, 0);
  612. module_param(hdr_channel, int, 0);
  613. module_param(max_ids, int, 0);
  614. module_param(rescan, int, 0);
  615. module_param(virt_ctr, int, 0);
  616. module_param(shared_access, int, 0);
  617. module_param(probe_eisa_isa, int, 0);
  618. module_param(force_dma32, int, 0);
  619. MODULE_AUTHOR("Achim Leubner");
  620. MODULE_LICENSE("GPL");
  621. /* ioctl interface */
  622. static struct file_operations gdth_fops = {
  623. .ioctl = gdth_ioctl,
  624. .open = gdth_open,
  625. .release = gdth_close,
  626. };
  627. #include "gdth_proc.h"
  628. #include "gdth_proc.c"
  629. /* notifier block to get a notify on system shutdown/halt/reboot */
  630. static struct notifier_block gdth_notifier = {
  631. gdth_halt, NULL, 0
  632. };
  633. static int notifier_disabled = 0;
  634. static void gdth_delay(int milliseconds)
  635. {
  636. if (milliseconds == 0) {
  637. udelay(1);
  638. } else {
  639. mdelay(milliseconds);
  640. }
  641. }
  642. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  643. {
  644. *cyls = size /HEADS/SECS;
  645. if (*cyls <= MAXCYLS) {
  646. *heads = HEADS;
  647. *secs = SECS;
  648. } else { /* too high for 64*32 */
  649. *cyls = size /MEDHEADS/MEDSECS;
  650. if (*cyls <= MAXCYLS) {
  651. *heads = MEDHEADS;
  652. *secs = MEDSECS;
  653. } else { /* too high for 127*63 */
  654. *cyls = size /BIGHEADS/BIGSECS;
  655. *heads = BIGHEADS;
  656. *secs = BIGSECS;
  657. }
  658. }
  659. }
  660. /* controller search and initialization functions */
  661. static int __init gdth_search_eisa(ushort eisa_adr)
  662. {
  663. ulong32 id;
  664. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  665. id = inl(eisa_adr+ID0REG);
  666. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  667. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  668. return 0; /* not EISA configured */
  669. return 1;
  670. }
  671. if (id == GDT3_ID) /* GDT3000 */
  672. return 1;
  673. return 0;
  674. }
  675. static int __init gdth_search_isa(ulong32 bios_adr)
  676. {
  677. void __iomem *addr;
  678. ulong32 id;
  679. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  680. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  681. id = gdth_readl(addr);
  682. iounmap(addr);
  683. if (id == GDT2_ID) /* GDT2000 */
  684. return 1;
  685. }
  686. return 0;
  687. }
  688. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  689. {
  690. ushort device, cnt;
  691. TRACE(("gdth_search_pci()\n"));
  692. cnt = 0;
  693. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  694. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  695. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  696. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  697. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  698. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  699. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  700. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  701. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  702. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  703. PCI_DEVICE_ID_INTEL_SRC);
  704. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  705. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  706. return cnt;
  707. }
  708. /* Vortex only makes RAID controllers.
  709. * We do not really want to specify all 550 ids here, so wildcard match.
  710. */
  711. static struct pci_device_id gdthtable[] __attribute_used__ = {
  712. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  713. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  714. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  715. {0}
  716. };
  717. MODULE_DEVICE_TABLE(pci,gdthtable);
  718. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  719. ushort vendor, ushort device)
  720. {
  721. ulong base0, base1, base2;
  722. struct pci_dev *pdev;
  723. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  724. *cnt, vendor, device));
  725. pdev = NULL;
  726. while ((pdev = pci_find_device(vendor, device, pdev))
  727. != NULL) {
  728. if (pci_enable_device(pdev))
  729. continue;
  730. if (*cnt >= MAXHA)
  731. return;
  732. /* GDT PCI controller found, resources are already in pdev */
  733. pcistr[*cnt].pdev = pdev;
  734. pcistr[*cnt].vendor_id = vendor;
  735. pcistr[*cnt].device_id = device;
  736. pcistr[*cnt].subdevice_id = pdev->subsystem_device;
  737. pcistr[*cnt].bus = pdev->bus->number;
  738. pcistr[*cnt].device_fn = pdev->devfn;
  739. pcistr[*cnt].irq = pdev->irq;
  740. base0 = pci_resource_flags(pdev, 0);
  741. base1 = pci_resource_flags(pdev, 1);
  742. base2 = pci_resource_flags(pdev, 2);
  743. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  744. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  745. if (!(base0 & IORESOURCE_MEM))
  746. continue;
  747. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  748. } else { /* GDT6110, GDT6120, .. */
  749. if (!(base0 & IORESOURCE_MEM) ||
  750. !(base2 & IORESOURCE_MEM) ||
  751. !(base1 & IORESOURCE_IO))
  752. continue;
  753. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  754. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  755. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  756. }
  757. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  758. pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
  759. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  760. (*cnt)++;
  761. }
  762. }
  763. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  764. {
  765. gdth_pci_str temp;
  766. int i, changed;
  767. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  768. if (cnt == 0)
  769. return;
  770. do {
  771. changed = FALSE;
  772. for (i = 0; i < cnt-1; ++i) {
  773. if (!reverse_scan) {
  774. if ((pcistr[i].bus > pcistr[i+1].bus) ||
  775. (pcistr[i].bus == pcistr[i+1].bus &&
  776. PCI_SLOT(pcistr[i].device_fn) >
  777. PCI_SLOT(pcistr[i+1].device_fn))) {
  778. temp = pcistr[i];
  779. pcistr[i] = pcistr[i+1];
  780. pcistr[i+1] = temp;
  781. changed = TRUE;
  782. }
  783. } else {
  784. if ((pcistr[i].bus < pcistr[i+1].bus) ||
  785. (pcistr[i].bus == pcistr[i+1].bus &&
  786. PCI_SLOT(pcistr[i].device_fn) <
  787. PCI_SLOT(pcistr[i+1].device_fn))) {
  788. temp = pcistr[i];
  789. pcistr[i] = pcistr[i+1];
  790. pcistr[i+1] = temp;
  791. changed = TRUE;
  792. }
  793. }
  794. }
  795. } while (changed);
  796. }
  797. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  798. {
  799. ulong32 retries,id;
  800. unchar prot_ver,eisacf,i,irq_found;
  801. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  802. /* disable board interrupts, deinitialize services */
  803. outb(0xff,eisa_adr+EDOORREG);
  804. outb(0x00,eisa_adr+EDENABREG);
  805. outb(0x00,eisa_adr+EINTENABREG);
  806. outb(0xff,eisa_adr+LDOORREG);
  807. retries = INIT_RETRIES;
  808. gdth_delay(20);
  809. while (inb(eisa_adr+EDOORREG) != 0xff) {
  810. if (--retries == 0) {
  811. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  812. return 0;
  813. }
  814. gdth_delay(1);
  815. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  816. }
  817. prot_ver = inb(eisa_adr+MAILBOXREG);
  818. outb(0xff,eisa_adr+EDOORREG);
  819. if (prot_ver != PROTOCOL_VERSION) {
  820. printk("GDT-EISA: Illegal protocol version\n");
  821. return 0;
  822. }
  823. ha->bmic = eisa_adr;
  824. ha->brd_phys = (ulong32)eisa_adr >> 12;
  825. outl(0,eisa_adr+MAILBOXREG);
  826. outl(0,eisa_adr+MAILBOXREG+4);
  827. outl(0,eisa_adr+MAILBOXREG+8);
  828. outl(0,eisa_adr+MAILBOXREG+12);
  829. /* detect IRQ */
  830. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  831. ha->oem_id = OEM_ID_ICP;
  832. ha->type = GDT_EISA;
  833. ha->stype = id;
  834. outl(1,eisa_adr+MAILBOXREG+8);
  835. outb(0xfe,eisa_adr+LDOORREG);
  836. retries = INIT_RETRIES;
  837. gdth_delay(20);
  838. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  839. if (--retries == 0) {
  840. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  841. return 0;
  842. }
  843. gdth_delay(1);
  844. }
  845. ha->irq = inb(eisa_adr+MAILBOXREG);
  846. outb(0xff,eisa_adr+EDOORREG);
  847. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  848. /* check the result */
  849. if (ha->irq == 0) {
  850. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  851. for (i = 0, irq_found = FALSE;
  852. i < MAXHA && irq[i] != 0xff; ++i) {
  853. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  854. irq_found = TRUE;
  855. break;
  856. }
  857. }
  858. if (irq_found) {
  859. ha->irq = irq[i];
  860. irq[i] = 0;
  861. printk("GDT-EISA: Can not detect controller IRQ,\n");
  862. printk("Use IRQ setting from command line (IRQ = %d)\n",
  863. ha->irq);
  864. } else {
  865. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  866. printk("the controller BIOS or use command line parameters\n");
  867. return 0;
  868. }
  869. }
  870. } else {
  871. eisacf = inb(eisa_adr+EISAREG) & 7;
  872. if (eisacf > 4) /* level triggered */
  873. eisacf -= 4;
  874. ha->irq = gdth_irq_tab[eisacf];
  875. ha->oem_id = OEM_ID_ICP;
  876. ha->type = GDT_EISA;
  877. ha->stype = id;
  878. }
  879. ha->dma64_support = 0;
  880. return 1;
  881. }
  882. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  883. {
  884. register gdt2_dpram_str __iomem *dp2_ptr;
  885. int i;
  886. unchar irq_drq,prot_ver;
  887. ulong32 retries;
  888. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  889. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  890. if (ha->brd == NULL) {
  891. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  892. return 0;
  893. }
  894. dp2_ptr = ha->brd;
  895. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  896. /* reset interface area */
  897. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  898. if (gdth_readl(&dp2_ptr->u) != 0) {
  899. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  900. iounmap(ha->brd);
  901. return 0;
  902. }
  903. /* disable board interrupts, read DRQ and IRQ */
  904. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  905. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  906. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  907. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  908. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  909. for (i=0; i<3; ++i) {
  910. if ((irq_drq & 1)==0)
  911. break;
  912. irq_drq >>= 1;
  913. }
  914. ha->drq = gdth_drq_tab[i];
  915. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  916. for (i=1; i<5; ++i) {
  917. if ((irq_drq & 1)==0)
  918. break;
  919. irq_drq >>= 1;
  920. }
  921. ha->irq = gdth_irq_tab[i];
  922. /* deinitialize services */
  923. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  924. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  925. gdth_writeb(0, &dp2_ptr->io.event);
  926. retries = INIT_RETRIES;
  927. gdth_delay(20);
  928. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  929. if (--retries == 0) {
  930. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  931. iounmap(ha->brd);
  932. return 0;
  933. }
  934. gdth_delay(1);
  935. }
  936. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  937. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  938. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  939. if (prot_ver != PROTOCOL_VERSION) {
  940. printk("GDT-ISA: Illegal protocol version\n");
  941. iounmap(ha->brd);
  942. return 0;
  943. }
  944. ha->oem_id = OEM_ID_ICP;
  945. ha->type = GDT_ISA;
  946. ha->ic_all_size = sizeof(dp2_ptr->u);
  947. ha->stype= GDT2_ID;
  948. ha->brd_phys = bios_adr >> 4;
  949. /* special request to controller BIOS */
  950. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  951. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  952. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  953. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  954. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  955. gdth_writeb(0, &dp2_ptr->io.event);
  956. retries = INIT_RETRIES;
  957. gdth_delay(20);
  958. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  959. if (--retries == 0) {
  960. printk("GDT-ISA: Initialization error\n");
  961. iounmap(ha->brd);
  962. return 0;
  963. }
  964. gdth_delay(1);
  965. }
  966. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  967. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  968. ha->dma64_support = 0;
  969. return 1;
  970. }
  971. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  972. {
  973. register gdt6_dpram_str __iomem *dp6_ptr;
  974. register gdt6c_dpram_str __iomem *dp6c_ptr;
  975. register gdt6m_dpram_str __iomem *dp6m_ptr;
  976. ulong32 retries;
  977. unchar prot_ver;
  978. ushort command;
  979. int i, found = FALSE;
  980. TRACE(("gdth_init_pci()\n"));
  981. if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
  982. ha->oem_id = OEM_ID_INTEL;
  983. else
  984. ha->oem_id = OEM_ID_ICP;
  985. ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
  986. ha->stype = (ulong32)pcistr->device_id;
  987. ha->subdevice_id = pcistr->subdevice_id;
  988. ha->irq = pcistr->irq;
  989. ha->pdev = pcistr->pdev;
  990. if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  991. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  992. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  993. if (ha->brd == NULL) {
  994. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  995. return 0;
  996. }
  997. /* check and reset interface area */
  998. dp6_ptr = ha->brd;
  999. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1000. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1001. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1002. pcistr->dpmem);
  1003. found = FALSE;
  1004. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1005. iounmap(ha->brd);
  1006. ha->brd = ioremap(i, sizeof(ushort));
  1007. if (ha->brd == NULL) {
  1008. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1009. return 0;
  1010. }
  1011. if (gdth_readw(ha->brd) != 0xffff) {
  1012. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1013. continue;
  1014. }
  1015. iounmap(ha->brd);
  1016. pci_write_config_dword(pcistr->pdev,
  1017. PCI_BASE_ADDRESS_0, i);
  1018. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1019. if (ha->brd == NULL) {
  1020. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1021. return 0;
  1022. }
  1023. dp6_ptr = ha->brd;
  1024. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1025. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1026. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1027. found = TRUE;
  1028. break;
  1029. }
  1030. }
  1031. if (!found) {
  1032. printk("GDT-PCI: No free address found!\n");
  1033. iounmap(ha->brd);
  1034. return 0;
  1035. }
  1036. }
  1037. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1038. if (gdth_readl(&dp6_ptr->u) != 0) {
  1039. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1040. iounmap(ha->brd);
  1041. return 0;
  1042. }
  1043. /* disable board interrupts, deinit services */
  1044. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1045. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1046. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1047. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1048. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1049. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1050. gdth_writeb(0, &dp6_ptr->io.event);
  1051. retries = INIT_RETRIES;
  1052. gdth_delay(20);
  1053. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1054. if (--retries == 0) {
  1055. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1056. iounmap(ha->brd);
  1057. return 0;
  1058. }
  1059. gdth_delay(1);
  1060. }
  1061. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1062. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1063. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1064. if (prot_ver != PROTOCOL_VERSION) {
  1065. printk("GDT-PCI: Illegal protocol version\n");
  1066. iounmap(ha->brd);
  1067. return 0;
  1068. }
  1069. ha->type = GDT_PCI;
  1070. ha->ic_all_size = sizeof(dp6_ptr->u);
  1071. /* special command to controller BIOS */
  1072. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1073. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1074. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1075. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1076. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1077. gdth_writeb(0, &dp6_ptr->io.event);
  1078. retries = INIT_RETRIES;
  1079. gdth_delay(20);
  1080. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1081. if (--retries == 0) {
  1082. printk("GDT-PCI: Initialization error\n");
  1083. iounmap(ha->brd);
  1084. return 0;
  1085. }
  1086. gdth_delay(1);
  1087. }
  1088. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1089. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1090. ha->dma64_support = 0;
  1091. } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1092. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1093. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1094. pcistr->dpmem,ha->irq));
  1095. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1096. if (ha->brd == NULL) {
  1097. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1098. iounmap(ha->brd);
  1099. return 0;
  1100. }
  1101. /* check and reset interface area */
  1102. dp6c_ptr = ha->brd;
  1103. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1104. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1105. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1106. pcistr->dpmem);
  1107. found = FALSE;
  1108. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1109. iounmap(ha->brd);
  1110. ha->brd = ioremap(i, sizeof(ushort));
  1111. if (ha->brd == NULL) {
  1112. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1113. return 0;
  1114. }
  1115. if (gdth_readw(ha->brd) != 0xffff) {
  1116. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1117. continue;
  1118. }
  1119. iounmap(ha->brd);
  1120. pci_write_config_dword(pcistr->pdev,
  1121. PCI_BASE_ADDRESS_2, i);
  1122. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1123. if (ha->brd == NULL) {
  1124. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1125. return 0;
  1126. }
  1127. dp6c_ptr = ha->brd;
  1128. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1129. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1130. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1131. found = TRUE;
  1132. break;
  1133. }
  1134. }
  1135. if (!found) {
  1136. printk("GDT-PCI: No free address found!\n");
  1137. iounmap(ha->brd);
  1138. return 0;
  1139. }
  1140. }
  1141. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1142. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1143. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1144. iounmap(ha->brd);
  1145. return 0;
  1146. }
  1147. /* disable board interrupts, deinit services */
  1148. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1149. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1150. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1151. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1152. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1153. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1154. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1155. retries = INIT_RETRIES;
  1156. gdth_delay(20);
  1157. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1158. if (--retries == 0) {
  1159. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1160. iounmap(ha->brd);
  1161. return 0;
  1162. }
  1163. gdth_delay(1);
  1164. }
  1165. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1166. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1167. if (prot_ver != PROTOCOL_VERSION) {
  1168. printk("GDT-PCI: Illegal protocol version\n");
  1169. iounmap(ha->brd);
  1170. return 0;
  1171. }
  1172. ha->type = GDT_PCINEW;
  1173. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1174. /* special command to controller BIOS */
  1175. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1176. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1177. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1178. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1179. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1180. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1181. retries = INIT_RETRIES;
  1182. gdth_delay(20);
  1183. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1184. if (--retries == 0) {
  1185. printk("GDT-PCI: Initialization error\n");
  1186. iounmap(ha->brd);
  1187. return 0;
  1188. }
  1189. gdth_delay(1);
  1190. }
  1191. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1192. ha->dma64_support = 0;
  1193. } else { /* MPR */
  1194. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1195. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1196. if (ha->brd == NULL) {
  1197. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1198. return 0;
  1199. }
  1200. /* manipulate config. space to enable DPMEM, start RP controller */
  1201. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1202. command |= 6;
  1203. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1204. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1205. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1206. i = 0xFEFF0001UL;
  1207. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1208. gdth_delay(1);
  1209. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1210. pci_resource_start(pcistr->pdev, 8));
  1211. dp6m_ptr = ha->brd;
  1212. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1213. * Aditional check needed for Xscale based RAID controllers */
  1214. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1215. gdth_delay(1);
  1216. /* check and reset interface area */
  1217. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1218. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1219. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1220. pcistr->dpmem);
  1221. found = FALSE;
  1222. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1223. iounmap(ha->brd);
  1224. ha->brd = ioremap(i, sizeof(ushort));
  1225. if (ha->brd == NULL) {
  1226. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1227. return 0;
  1228. }
  1229. if (gdth_readw(ha->brd) != 0xffff) {
  1230. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1231. continue;
  1232. }
  1233. iounmap(ha->brd);
  1234. pci_write_config_dword(pcistr->pdev,
  1235. PCI_BASE_ADDRESS_0, i);
  1236. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1237. if (ha->brd == NULL) {
  1238. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1239. return 0;
  1240. }
  1241. dp6m_ptr = ha->brd;
  1242. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1243. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1244. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1245. found = TRUE;
  1246. break;
  1247. }
  1248. }
  1249. if (!found) {
  1250. printk("GDT-PCI: No free address found!\n");
  1251. iounmap(ha->brd);
  1252. return 0;
  1253. }
  1254. }
  1255. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1256. /* disable board interrupts, deinit services */
  1257. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1258. &dp6m_ptr->i960r.edoor_en_reg);
  1259. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1260. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1261. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1262. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1263. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1264. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1265. retries = INIT_RETRIES;
  1266. gdth_delay(20);
  1267. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1268. if (--retries == 0) {
  1269. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1270. iounmap(ha->brd);
  1271. return 0;
  1272. }
  1273. gdth_delay(1);
  1274. }
  1275. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1276. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1277. if (prot_ver != PROTOCOL_VERSION) {
  1278. printk("GDT-PCI: Illegal protocol version\n");
  1279. iounmap(ha->brd);
  1280. return 0;
  1281. }
  1282. ha->type = GDT_PCIMPR;
  1283. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1284. /* special command to controller BIOS */
  1285. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1286. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1287. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1288. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1289. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1290. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1291. retries = INIT_RETRIES;
  1292. gdth_delay(20);
  1293. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1294. if (--retries == 0) {
  1295. printk("GDT-PCI: Initialization error\n");
  1296. iounmap(ha->brd);
  1297. return 0;
  1298. }
  1299. gdth_delay(1);
  1300. }
  1301. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1302. /* read FW version to detect 64-bit DMA support */
  1303. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1304. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1305. retries = INIT_RETRIES;
  1306. gdth_delay(20);
  1307. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1308. if (--retries == 0) {
  1309. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1310. iounmap(ha->brd);
  1311. return 0;
  1312. }
  1313. gdth_delay(1);
  1314. }
  1315. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1316. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1317. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1318. ha->dma64_support = 0;
  1319. else
  1320. ha->dma64_support = 1;
  1321. }
  1322. return 1;
  1323. }
  1324. /* controller protocol functions */
  1325. static void __init gdth_enable_int(int hanum)
  1326. {
  1327. gdth_ha_str *ha;
  1328. ulong flags;
  1329. gdt2_dpram_str __iomem *dp2_ptr;
  1330. gdt6_dpram_str __iomem *dp6_ptr;
  1331. gdt6m_dpram_str __iomem *dp6m_ptr;
  1332. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1333. ha = HADATA(gdth_ctr_tab[hanum]);
  1334. spin_lock_irqsave(&ha->smp_lock, flags);
  1335. if (ha->type == GDT_EISA) {
  1336. outb(0xff, ha->bmic + EDOORREG);
  1337. outb(0xff, ha->bmic + EDENABREG);
  1338. outb(0x01, ha->bmic + EINTENABREG);
  1339. } else if (ha->type == GDT_ISA) {
  1340. dp2_ptr = ha->brd;
  1341. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1342. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1343. gdth_writeb(1, &dp2_ptr->io.irqen);
  1344. } else if (ha->type == GDT_PCI) {
  1345. dp6_ptr = ha->brd;
  1346. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1347. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1348. gdth_writeb(1, &dp6_ptr->io.irqen);
  1349. } else if (ha->type == GDT_PCINEW) {
  1350. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1351. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1352. } else if (ha->type == GDT_PCIMPR) {
  1353. dp6m_ptr = ha->brd;
  1354. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1355. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1356. &dp6m_ptr->i960r.edoor_en_reg);
  1357. }
  1358. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1359. }
  1360. static int gdth_get_status(unchar *pIStatus,int irq)
  1361. {
  1362. register gdth_ha_str *ha;
  1363. int i;
  1364. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1365. irq,gdth_ctr_count));
  1366. *pIStatus = 0;
  1367. for (i=0; i<gdth_ctr_count; ++i) {
  1368. ha = HADATA(gdth_ctr_tab[i]);
  1369. if (ha->irq != (unchar)irq) /* check IRQ */
  1370. continue;
  1371. if (ha->type == GDT_EISA)
  1372. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1373. else if (ha->type == GDT_ISA)
  1374. *pIStatus =
  1375. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1376. else if (ha->type == GDT_PCI)
  1377. *pIStatus =
  1378. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1379. else if (ha->type == GDT_PCINEW)
  1380. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1381. else if (ha->type == GDT_PCIMPR)
  1382. *pIStatus =
  1383. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1384. if (*pIStatus)
  1385. return i; /* board found */
  1386. }
  1387. return -1;
  1388. }
  1389. static int gdth_test_busy(int hanum)
  1390. {
  1391. register gdth_ha_str *ha;
  1392. register int gdtsema0 = 0;
  1393. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1394. ha = HADATA(gdth_ctr_tab[hanum]);
  1395. if (ha->type == GDT_EISA)
  1396. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1397. else if (ha->type == GDT_ISA)
  1398. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1399. else if (ha->type == GDT_PCI)
  1400. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1401. else if (ha->type == GDT_PCINEW)
  1402. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1403. else if (ha->type == GDT_PCIMPR)
  1404. gdtsema0 =
  1405. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1406. return (gdtsema0 & 1);
  1407. }
  1408. static int gdth_get_cmd_index(int hanum)
  1409. {
  1410. register gdth_ha_str *ha;
  1411. int i;
  1412. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1413. ha = HADATA(gdth_ctr_tab[hanum]);
  1414. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1415. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1416. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1417. ha->cmd_tab[i].service = ha->pccb->Service;
  1418. ha->pccb->CommandIndex = (ulong32)i+2;
  1419. return (i+2);
  1420. }
  1421. }
  1422. return 0;
  1423. }
  1424. static void gdth_set_sema0(int hanum)
  1425. {
  1426. register gdth_ha_str *ha;
  1427. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1428. ha = HADATA(gdth_ctr_tab[hanum]);
  1429. if (ha->type == GDT_EISA) {
  1430. outb(1, ha->bmic + SEMA0REG);
  1431. } else if (ha->type == GDT_ISA) {
  1432. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1433. } else if (ha->type == GDT_PCI) {
  1434. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1435. } else if (ha->type == GDT_PCINEW) {
  1436. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1437. } else if (ha->type == GDT_PCIMPR) {
  1438. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1439. }
  1440. }
  1441. static void gdth_copy_command(int hanum)
  1442. {
  1443. register gdth_ha_str *ha;
  1444. register gdth_cmd_str *cmd_ptr;
  1445. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1446. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1447. gdt6_dpram_str __iomem *dp6_ptr;
  1448. gdt2_dpram_str __iomem *dp2_ptr;
  1449. ushort cp_count,dp_offset,cmd_no;
  1450. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1451. ha = HADATA(gdth_ctr_tab[hanum]);
  1452. cp_count = ha->cmd_len;
  1453. dp_offset= ha->cmd_offs_dpmem;
  1454. cmd_no = ha->cmd_cnt;
  1455. cmd_ptr = ha->pccb;
  1456. ++ha->cmd_cnt;
  1457. if (ha->type == GDT_EISA)
  1458. return; /* no DPMEM, no copy */
  1459. /* set cpcount dword aligned */
  1460. if (cp_count & 3)
  1461. cp_count += (4 - (cp_count & 3));
  1462. ha->cmd_offs_dpmem += cp_count;
  1463. /* set offset and service, copy command to DPMEM */
  1464. if (ha->type == GDT_ISA) {
  1465. dp2_ptr = ha->brd;
  1466. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1467. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1468. gdth_writew((ushort)cmd_ptr->Service,
  1469. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1470. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1471. } else if (ha->type == GDT_PCI) {
  1472. dp6_ptr = ha->brd;
  1473. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1474. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1475. gdth_writew((ushort)cmd_ptr->Service,
  1476. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1477. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1478. } else if (ha->type == GDT_PCINEW) {
  1479. dp6c_ptr = ha->brd;
  1480. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1481. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1482. gdth_writew((ushort)cmd_ptr->Service,
  1483. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1484. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1485. } else if (ha->type == GDT_PCIMPR) {
  1486. dp6m_ptr = ha->brd;
  1487. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1488. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1489. gdth_writew((ushort)cmd_ptr->Service,
  1490. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1491. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1492. }
  1493. }
  1494. static void gdth_release_event(int hanum)
  1495. {
  1496. register gdth_ha_str *ha;
  1497. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1498. ha = HADATA(gdth_ctr_tab[hanum]);
  1499. #ifdef GDTH_STATISTICS
  1500. {
  1501. ulong32 i,j;
  1502. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1503. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1504. ++i;
  1505. }
  1506. if (max_index < i) {
  1507. max_index = i;
  1508. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1509. }
  1510. }
  1511. #endif
  1512. if (ha->pccb->OpCode == GDT_INIT)
  1513. ha->pccb->Service |= 0x80;
  1514. if (ha->type == GDT_EISA) {
  1515. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1516. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1517. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1518. } else if (ha->type == GDT_ISA) {
  1519. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1520. } else if (ha->type == GDT_PCI) {
  1521. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1522. } else if (ha->type == GDT_PCINEW) {
  1523. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1524. } else if (ha->type == GDT_PCIMPR) {
  1525. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1526. }
  1527. }
  1528. static int gdth_wait(int hanum,int index,ulong32 time)
  1529. {
  1530. gdth_ha_str *ha;
  1531. int answer_found = FALSE;
  1532. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1533. ha = HADATA(gdth_ctr_tab[hanum]);
  1534. if (index == 0)
  1535. return 1; /* no wait required */
  1536. gdth_from_wait = TRUE;
  1537. do {
  1538. gdth_interrupt((int)ha->irq,ha,NULL);
  1539. if (wait_hanum==hanum && wait_index==index) {
  1540. answer_found = TRUE;
  1541. break;
  1542. }
  1543. gdth_delay(1);
  1544. } while (--time);
  1545. gdth_from_wait = FALSE;
  1546. while (gdth_test_busy(hanum))
  1547. gdth_delay(0);
  1548. return (answer_found);
  1549. }
  1550. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1551. ulong64 p2,ulong64 p3)
  1552. {
  1553. register gdth_ha_str *ha;
  1554. register gdth_cmd_str *cmd_ptr;
  1555. int retries,index;
  1556. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1557. ha = HADATA(gdth_ctr_tab[hanum]);
  1558. cmd_ptr = ha->pccb;
  1559. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1560. /* make command */
  1561. for (retries = INIT_RETRIES;;) {
  1562. cmd_ptr->Service = service;
  1563. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1564. if (!(index=gdth_get_cmd_index(hanum))) {
  1565. TRACE(("GDT: No free command index found\n"));
  1566. return 0;
  1567. }
  1568. gdth_set_sema0(hanum);
  1569. cmd_ptr->OpCode = opcode;
  1570. cmd_ptr->BoardNode = LOCALBOARD;
  1571. if (service == CACHESERVICE) {
  1572. if (opcode == GDT_IOCTL) {
  1573. cmd_ptr->u.ioctl.subfunc = p1;
  1574. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1575. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1576. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1577. } else {
  1578. if (ha->cache_feat & GDT_64BIT) {
  1579. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1580. cmd_ptr->u.cache64.BlockNo = p2;
  1581. } else {
  1582. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1583. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1584. }
  1585. }
  1586. } else if (service == SCSIRAWSERVICE) {
  1587. if (ha->raw_feat & GDT_64BIT) {
  1588. cmd_ptr->u.raw64.direction = p1;
  1589. cmd_ptr->u.raw64.bus = (unchar)p2;
  1590. cmd_ptr->u.raw64.target = (unchar)p3;
  1591. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1592. } else {
  1593. cmd_ptr->u.raw.direction = p1;
  1594. cmd_ptr->u.raw.bus = (unchar)p2;
  1595. cmd_ptr->u.raw.target = (unchar)p3;
  1596. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1597. }
  1598. } else if (service == SCREENSERVICE) {
  1599. if (opcode == GDT_REALTIME) {
  1600. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1601. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1602. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1603. }
  1604. }
  1605. ha->cmd_len = sizeof(gdth_cmd_str);
  1606. ha->cmd_offs_dpmem = 0;
  1607. ha->cmd_cnt = 0;
  1608. gdth_copy_command(hanum);
  1609. gdth_release_event(hanum);
  1610. gdth_delay(20);
  1611. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1612. printk("GDT: Initialization error (timeout service %d)\n",service);
  1613. return 0;
  1614. }
  1615. if (ha->status != S_BSY || --retries == 0)
  1616. break;
  1617. gdth_delay(1);
  1618. }
  1619. return (ha->status != S_OK ? 0:1);
  1620. }
  1621. /* search for devices */
  1622. static int __init gdth_search_drives(int hanum)
  1623. {
  1624. register gdth_ha_str *ha;
  1625. ushort cdev_cnt, i;
  1626. int ok;
  1627. ulong32 bus_no, drv_cnt, drv_no, j;
  1628. gdth_getch_str *chn;
  1629. gdth_drlist_str *drl;
  1630. gdth_iochan_str *ioc;
  1631. gdth_raw_iochan_str *iocr;
  1632. gdth_arcdl_str *alst;
  1633. gdth_alist_str *alst2;
  1634. gdth_oem_str_ioctl *oemstr;
  1635. #ifdef INT_COAL
  1636. gdth_perf_modes *pmod;
  1637. #endif
  1638. #ifdef GDTH_RTC
  1639. unchar rtc[12];
  1640. ulong flags;
  1641. #endif
  1642. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1643. ha = HADATA(gdth_ctr_tab[hanum]);
  1644. ok = 0;
  1645. /* initialize controller services, at first: screen service */
  1646. ha->screen_feat = 0;
  1647. if (!force_dma32) {
  1648. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1649. if (ok)
  1650. ha->screen_feat = GDT_64BIT;
  1651. }
  1652. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1653. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1654. if (!ok) {
  1655. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1656. hanum, ha->status);
  1657. return 0;
  1658. }
  1659. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1660. #ifdef GDTH_RTC
  1661. /* read realtime clock info, send to controller */
  1662. /* 1. wait for the falling edge of update flag */
  1663. spin_lock_irqsave(&rtc_lock, flags);
  1664. for (j = 0; j < 1000000; ++j)
  1665. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1666. break;
  1667. for (j = 0; j < 1000000; ++j)
  1668. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1669. break;
  1670. /* 2. read info */
  1671. do {
  1672. for (j = 0; j < 12; ++j)
  1673. rtc[j] = CMOS_READ(j);
  1674. } while (rtc[0] != CMOS_READ(0));
  1675. spin_lock_irqrestore(&rtc_lock, flags);
  1676. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1677. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1678. /* 3. send to controller firmware */
  1679. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1680. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1681. #endif
  1682. /* unfreeze all IOs */
  1683. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1684. /* initialize cache service */
  1685. ha->cache_feat = 0;
  1686. if (!force_dma32) {
  1687. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1688. if (ok)
  1689. ha->cache_feat = GDT_64BIT;
  1690. }
  1691. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1692. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1693. if (!ok) {
  1694. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1695. hanum, ha->status);
  1696. return 0;
  1697. }
  1698. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1699. cdev_cnt = (ushort)ha->info;
  1700. ha->fw_vers = ha->service;
  1701. #ifdef INT_COAL
  1702. if (ha->type == GDT_PCIMPR) {
  1703. /* set perf. modes */
  1704. pmod = (gdth_perf_modes *)ha->pscratch;
  1705. pmod->version = 1;
  1706. pmod->st_mode = 1; /* enable one status buffer */
  1707. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1708. pmod->st_buff_indx1 = COALINDEX;
  1709. pmod->st_buff_addr2 = 0;
  1710. pmod->st_buff_u_addr2 = 0;
  1711. pmod->st_buff_indx2 = 0;
  1712. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1713. pmod->cmd_mode = 0; // disable all cmd buffers
  1714. pmod->cmd_buff_addr1 = 0;
  1715. pmod->cmd_buff_u_addr1 = 0;
  1716. pmod->cmd_buff_indx1 = 0;
  1717. pmod->cmd_buff_addr2 = 0;
  1718. pmod->cmd_buff_u_addr2 = 0;
  1719. pmod->cmd_buff_indx2 = 0;
  1720. pmod->cmd_buff_size = 0;
  1721. pmod->reserved1 = 0;
  1722. pmod->reserved2 = 0;
  1723. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1724. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1725. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1726. }
  1727. }
  1728. #endif
  1729. /* detect number of buses - try new IOCTL */
  1730. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1731. iocr->hdr.version = 0xffffffff;
  1732. iocr->hdr.list_entries = MAXBUS;
  1733. iocr->hdr.first_chan = 0;
  1734. iocr->hdr.last_chan = MAXBUS-1;
  1735. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1736. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1737. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1738. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1739. ha->bus_cnt = iocr->hdr.chan_count;
  1740. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1741. if (iocr->list[bus_no].proc_id < MAXID)
  1742. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1743. else
  1744. ha->bus_id[bus_no] = 0xff;
  1745. }
  1746. } else {
  1747. /* old method */
  1748. chn = (gdth_getch_str *)ha->pscratch;
  1749. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1750. chn->channel_no = bus_no;
  1751. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1752. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1753. IO_CHANNEL | INVALID_CHANNEL,
  1754. sizeof(gdth_getch_str))) {
  1755. if (bus_no == 0) {
  1756. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1757. hanum, ha->status);
  1758. return 0;
  1759. }
  1760. break;
  1761. }
  1762. if (chn->siop_id < MAXID)
  1763. ha->bus_id[bus_no] = chn->siop_id;
  1764. else
  1765. ha->bus_id[bus_no] = 0xff;
  1766. }
  1767. ha->bus_cnt = (unchar)bus_no;
  1768. }
  1769. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1770. /* read cache configuration */
  1771. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1772. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1773. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1774. hanum, ha->status);
  1775. return 0;
  1776. }
  1777. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1778. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1779. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1780. ha->cpar.write_back,ha->cpar.block_size));
  1781. /* read board info and features */
  1782. ha->more_proc = FALSE;
  1783. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1784. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1785. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1786. sizeof(gdth_binfo_str));
  1787. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1788. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1789. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1790. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1791. ha->more_proc = TRUE;
  1792. }
  1793. } else {
  1794. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1795. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1796. }
  1797. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1798. /* read more informations */
  1799. if (ha->more_proc) {
  1800. /* physical drives, channel addresses */
  1801. ioc = (gdth_iochan_str *)ha->pscratch;
  1802. ioc->hdr.version = 0xffffffff;
  1803. ioc->hdr.list_entries = MAXBUS;
  1804. ioc->hdr.first_chan = 0;
  1805. ioc->hdr.last_chan = MAXBUS-1;
  1806. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1807. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1808. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1809. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1810. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1811. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1812. }
  1813. } else {
  1814. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1815. ha->raw[bus_no].address = IO_CHANNEL;
  1816. ha->raw[bus_no].local_no = bus_no;
  1817. }
  1818. }
  1819. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1820. chn = (gdth_getch_str *)ha->pscratch;
  1821. chn->channel_no = ha->raw[bus_no].local_no;
  1822. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1823. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1824. ha->raw[bus_no].address | INVALID_CHANNEL,
  1825. sizeof(gdth_getch_str))) {
  1826. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1827. TRACE2(("Channel %d: %d phys. drives\n",
  1828. bus_no,chn->drive_cnt));
  1829. }
  1830. if (ha->raw[bus_no].pdev_cnt > 0) {
  1831. drl = (gdth_drlist_str *)ha->pscratch;
  1832. drl->sc_no = ha->raw[bus_no].local_no;
  1833. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1834. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1835. SCSI_DR_LIST | L_CTRL_PATTERN,
  1836. ha->raw[bus_no].address | INVALID_CHANNEL,
  1837. sizeof(gdth_drlist_str))) {
  1838. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1839. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1840. } else {
  1841. ha->raw[bus_no].pdev_cnt = 0;
  1842. }
  1843. }
  1844. }
  1845. /* logical drives */
  1846. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1847. INVALID_CHANNEL,sizeof(ulong32))) {
  1848. drv_cnt = *(ulong32 *)ha->pscratch;
  1849. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1850. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1851. for (j = 0; j < drv_cnt; ++j) {
  1852. drv_no = ((ulong32 *)ha->pscratch)[j];
  1853. if (drv_no < MAX_LDRIVES) {
  1854. ha->hdr[drv_no].is_logdrv = TRUE;
  1855. TRACE2(("Drive %d is log. drive\n",drv_no));
  1856. }
  1857. }
  1858. }
  1859. alst = (gdth_arcdl_str *)ha->pscratch;
  1860. alst->entries_avail = MAX_LDRIVES;
  1861. alst->first_entry = 0;
  1862. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1863. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1864. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1865. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1866. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1867. for (j = 0; j < alst->entries_init; ++j) {
  1868. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1869. ha->hdr[j].is_master = alst->list[j].is_master;
  1870. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1871. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1872. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1873. }
  1874. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1875. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1876. 0, 35 * sizeof(gdth_alist_str))) {
  1877. for (j = 0; j < 35; ++j) {
  1878. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1879. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1880. ha->hdr[j].is_master = alst2->is_master;
  1881. ha->hdr[j].is_parity = alst2->is_parity;
  1882. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1883. ha->hdr[j].master_no = alst2->cd_handle;
  1884. }
  1885. }
  1886. }
  1887. }
  1888. /* initialize raw service */
  1889. ha->raw_feat = 0;
  1890. if (!force_dma32) {
  1891. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1892. if (ok)
  1893. ha->raw_feat = GDT_64BIT;
  1894. }
  1895. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1896. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1897. if (!ok) {
  1898. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1899. hanum, ha->status);
  1900. return 0;
  1901. }
  1902. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1903. /* set/get features raw service (scatter/gather) */
  1904. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  1905. 0,0)) {
  1906. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1907. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  1908. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1909. ha->info));
  1910. ha->raw_feat |= (ushort)ha->info;
  1911. }
  1912. }
  1913. /* set/get features cache service (equal to raw service) */
  1914. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  1915. SCATTER_GATHER,0)) {
  1916. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1917. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  1918. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1919. ha->info));
  1920. ha->cache_feat |= (ushort)ha->info;
  1921. }
  1922. }
  1923. /* reserve drives for raw service */
  1924. if (reserve_mode != 0) {
  1925. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  1926. reserve_mode == 1 ? 1 : 3, 0, 0);
  1927. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1928. ha->status));
  1929. }
  1930. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1931. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  1932. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1933. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1934. reserve_list[i], reserve_list[i+1],
  1935. reserve_list[i+2], reserve_list[i+3]));
  1936. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  1937. reserve_list[i+1], reserve_list[i+2] |
  1938. (reserve_list[i+3] << 8))) {
  1939. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1940. hanum, ha->status);
  1941. }
  1942. }
  1943. }
  1944. /* Determine OEM string using IOCTL */
  1945. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1946. oemstr->params.ctl_version = 0x01;
  1947. oemstr->params.buffer_size = sizeof(oemstr->text);
  1948. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1949. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1950. sizeof(gdth_oem_str_ioctl))) {
  1951. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1952. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1953. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  1954. /* Save the Host Drive inquiry data */
  1955. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  1956. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1957. sizeof(ha->oem_name));
  1958. #else
  1959. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  1960. ha->oem_name[7] = '\0';
  1961. #endif
  1962. } else {
  1963. /* Old method, based on PCI ID */
  1964. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1965. printk("GDT-HA %d: Name: %s\n",
  1966. hanum,ha->binfo.type_string);
  1967. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  1968. if (ha->oem_id == OEM_ID_INTEL)
  1969. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1970. else
  1971. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1972. #else
  1973. if (ha->oem_id == OEM_ID_INTEL)
  1974. strcpy(ha->oem_name,"Intel ");
  1975. else
  1976. strcpy(ha->oem_name,"ICP ");
  1977. #endif
  1978. }
  1979. /* scanning for host drives */
  1980. for (i = 0; i < cdev_cnt; ++i)
  1981. gdth_analyse_hdrive(hanum,i);
  1982. TRACE(("gdth_search_drives() OK\n"));
  1983. return 1;
  1984. }
  1985. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  1986. {
  1987. register gdth_ha_str *ha;
  1988. ulong32 drv_cyls;
  1989. int drv_hds, drv_secs;
  1990. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  1991. if (hdrive >= MAX_HDRIVES)
  1992. return 0;
  1993. ha = HADATA(gdth_ctr_tab[hanum]);
  1994. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  1995. return 0;
  1996. ha->hdr[hdrive].present = TRUE;
  1997. ha->hdr[hdrive].size = ha->info;
  1998. /* evaluate mapping (sectors per head, heads per cylinder) */
  1999. ha->hdr[hdrive].size &= ~SECS32;
  2000. if (ha->info2 == 0) {
  2001. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2002. } else {
  2003. drv_hds = ha->info2 & 0xff;
  2004. drv_secs = (ha->info2 >> 8) & 0xff;
  2005. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2006. }
  2007. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2008. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2009. /* round size */
  2010. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2011. if (ha->cache_feat & GDT_64BIT) {
  2012. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2013. && ha->info2 != 0) {
  2014. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2015. }
  2016. }
  2017. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2018. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2019. /* get informations about device */
  2020. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2021. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2022. hdrive,ha->info));
  2023. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2024. }
  2025. /* cluster info */
  2026. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2027. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2028. hdrive,ha->info));
  2029. if (!shared_access)
  2030. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2031. }
  2032. /* R/W attributes */
  2033. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2034. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2035. hdrive,ha->info));
  2036. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2037. }
  2038. return 1;
  2039. }
  2040. /* command queueing/sending functions */
  2041. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2042. {
  2043. register gdth_ha_str *ha;
  2044. register Scsi_Cmnd *pscp;
  2045. register Scsi_Cmnd *nscp;
  2046. ulong flags;
  2047. unchar b, t;
  2048. TRACE(("gdth_putq() priority %d\n",priority));
  2049. ha = HADATA(gdth_ctr_tab[hanum]);
  2050. spin_lock_irqsave(&ha->smp_lock, flags);
  2051. scp->SCp.this_residual = (int)priority;
  2052. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  2053. t = scp->device->id;
  2054. if (priority >= DEFAULT_PRI) {
  2055. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2056. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  2057. TRACE2(("gdth_putq(): locked IO -> update_timeout()\n"));
  2058. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2059. }
  2060. }
  2061. if (ha->req_first==NULL) {
  2062. ha->req_first = scp; /* queue was empty */
  2063. scp->SCp.ptr = NULL;
  2064. } else { /* queue not empty */
  2065. pscp = ha->req_first;
  2066. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2067. /* priority: 0-highest,..,0xff-lowest */
  2068. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2069. pscp = nscp;
  2070. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2071. }
  2072. pscp->SCp.ptr = (char *)scp;
  2073. scp->SCp.ptr = (char *)nscp;
  2074. }
  2075. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2076. #ifdef GDTH_STATISTICS
  2077. flags = 0;
  2078. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2079. ++flags;
  2080. if (max_rq < flags) {
  2081. max_rq = flags;
  2082. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2083. }
  2084. #endif
  2085. }
  2086. static void gdth_next(int hanum)
  2087. {
  2088. register gdth_ha_str *ha;
  2089. register Scsi_Cmnd *pscp;
  2090. register Scsi_Cmnd *nscp;
  2091. unchar b, t, l, firsttime;
  2092. unchar this_cmd, next_cmd;
  2093. ulong flags = 0;
  2094. int cmd_index;
  2095. TRACE(("gdth_next() hanum %d\n",hanum));
  2096. ha = HADATA(gdth_ctr_tab[hanum]);
  2097. if (!gdth_polling)
  2098. spin_lock_irqsave(&ha->smp_lock, flags);
  2099. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2100. this_cmd = firsttime = TRUE;
  2101. next_cmd = gdth_polling ? FALSE:TRUE;
  2102. cmd_index = 0;
  2103. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2104. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2105. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2106. b = virt_ctr ? NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2107. t = nscp->device->id;
  2108. l = nscp->device->lun;
  2109. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2110. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2111. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2112. continue;
  2113. }
  2114. if (firsttime) {
  2115. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2116. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2117. if (!gdth_polling) {
  2118. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2119. return;
  2120. }
  2121. while (gdth_test_busy(hanum))
  2122. gdth_delay(1);
  2123. }
  2124. firsttime = FALSE;
  2125. }
  2126. if (nscp->done != gdth_scsi_done || nscp->cmnd[0] != 0xff) {
  2127. if (nscp->SCp.phase == -1) {
  2128. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2129. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2130. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2131. b, t, l));
  2132. /* TEST_UNIT_READY -> set scan mode */
  2133. if ((ha->scan_mode & 0x0f) == 0) {
  2134. if (b == 0 && t == 0 && l == 0) {
  2135. ha->scan_mode |= 1;
  2136. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2137. }
  2138. } else if ((ha->scan_mode & 0x0f) == 1) {
  2139. if (b == 0 && ((t == 0 && l == 1) ||
  2140. (t == 1 && l == 0))) {
  2141. nscp->SCp.sent_command = GDT_SCAN_START;
  2142. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2143. | SCSIRAWSERVICE;
  2144. ha->scan_mode = 0x12;
  2145. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2146. ha->scan_mode));
  2147. } else {
  2148. ha->scan_mode &= 0x10;
  2149. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2150. }
  2151. } else if (ha->scan_mode == 0x12) {
  2152. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2153. nscp->SCp.phase = SCSIRAWSERVICE;
  2154. nscp->SCp.sent_command = GDT_SCAN_END;
  2155. ha->scan_mode &= 0x10;
  2156. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2157. ha->scan_mode));
  2158. }
  2159. }
  2160. }
  2161. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2162. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2163. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2164. /* always GDT_CLUST_INFO! */
  2165. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2166. }
  2167. }
  2168. }
  2169. if (nscp->SCp.sent_command != -1) {
  2170. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2171. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2172. this_cmd = FALSE;
  2173. next_cmd = FALSE;
  2174. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2175. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2176. this_cmd = FALSE;
  2177. next_cmd = FALSE;
  2178. } else {
  2179. memset((char*)nscp->sense_buffer,0,16);
  2180. nscp->sense_buffer[0] = 0x70;
  2181. nscp->sense_buffer[2] = NOT_READY;
  2182. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2183. if (!nscp->SCp.have_data_in)
  2184. nscp->SCp.have_data_in++;
  2185. else
  2186. nscp->scsi_done(nscp);
  2187. }
  2188. } else if (nscp->done == gdth_scsi_done && nscp->cmnd[0] == 0xff) {
  2189. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2190. this_cmd = FALSE;
  2191. next_cmd = FALSE;
  2192. } else if (b != ha->virt_bus) {
  2193. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2194. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2195. this_cmd = FALSE;
  2196. else
  2197. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2198. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2199. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2200. nscp->cmnd[0], b, t, l));
  2201. nscp->result = DID_BAD_TARGET << 16;
  2202. if (!nscp->SCp.have_data_in)
  2203. nscp->SCp.have_data_in++;
  2204. else
  2205. nscp->scsi_done(nscp);
  2206. } else {
  2207. switch (nscp->cmnd[0]) {
  2208. case TEST_UNIT_READY:
  2209. case INQUIRY:
  2210. case REQUEST_SENSE:
  2211. case READ_CAPACITY:
  2212. case VERIFY:
  2213. case START_STOP:
  2214. case MODE_SENSE:
  2215. case SERVICE_ACTION_IN:
  2216. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2217. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2218. nscp->cmnd[4],nscp->cmnd[5]));
  2219. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2220. /* return UNIT_ATTENTION */
  2221. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2222. nscp->cmnd[0], t));
  2223. ha->hdr[t].media_changed = FALSE;
  2224. memset((char*)nscp->sense_buffer,0,16);
  2225. nscp->sense_buffer[0] = 0x70;
  2226. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2227. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2228. if (!nscp->SCp.have_data_in)
  2229. nscp->SCp.have_data_in++;
  2230. else
  2231. nscp->scsi_done(nscp);
  2232. } else if (gdth_internal_cache_cmd(hanum,nscp))
  2233. nscp->scsi_done(nscp);
  2234. break;
  2235. case ALLOW_MEDIUM_REMOVAL:
  2236. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2237. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2238. nscp->cmnd[4],nscp->cmnd[5]));
  2239. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2240. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2241. nscp->result = DID_OK << 16;
  2242. nscp->sense_buffer[0] = 0;
  2243. if (!nscp->SCp.have_data_in)
  2244. nscp->SCp.have_data_in++;
  2245. else
  2246. nscp->scsi_done(nscp);
  2247. } else {
  2248. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2249. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2250. nscp->cmnd[4],nscp->cmnd[3]));
  2251. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2252. this_cmd = FALSE;
  2253. }
  2254. break;
  2255. case RESERVE:
  2256. case RELEASE:
  2257. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2258. "RESERVE" : "RELEASE"));
  2259. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2260. this_cmd = FALSE;
  2261. break;
  2262. case READ_6:
  2263. case WRITE_6:
  2264. case READ_10:
  2265. case WRITE_10:
  2266. case READ_16:
  2267. case WRITE_16:
  2268. if (ha->hdr[t].media_changed) {
  2269. /* return UNIT_ATTENTION */
  2270. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2271. nscp->cmnd[0], t));
  2272. ha->hdr[t].media_changed = FALSE;
  2273. memset((char*)nscp->sense_buffer,0,16);
  2274. nscp->sense_buffer[0] = 0x70;
  2275. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2276. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2277. if (!nscp->SCp.have_data_in)
  2278. nscp->SCp.have_data_in++;
  2279. else
  2280. nscp->scsi_done(nscp);
  2281. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2282. this_cmd = FALSE;
  2283. break;
  2284. default:
  2285. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2286. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2287. nscp->cmnd[4],nscp->cmnd[5]));
  2288. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2289. hanum, nscp->cmnd[0]);
  2290. nscp->result = DID_ABORT << 16;
  2291. if (!nscp->SCp.have_data_in)
  2292. nscp->SCp.have_data_in++;
  2293. else
  2294. nscp->scsi_done(nscp);
  2295. break;
  2296. }
  2297. }
  2298. if (!this_cmd)
  2299. break;
  2300. if (nscp == ha->req_first)
  2301. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2302. else
  2303. pscp->SCp.ptr = nscp->SCp.ptr;
  2304. if (!next_cmd)
  2305. break;
  2306. }
  2307. if (ha->cmd_cnt > 0) {
  2308. gdth_release_event(hanum);
  2309. }
  2310. if (!gdth_polling)
  2311. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2312. if (gdth_polling && ha->cmd_cnt > 0) {
  2313. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2314. printk("GDT-HA %d: Command %d timed out !\n",
  2315. hanum,cmd_index);
  2316. }
  2317. }
  2318. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2319. char *buffer,ushort count)
  2320. {
  2321. ushort cpcount,i;
  2322. ushort cpsum,cpnow;
  2323. struct scatterlist *sl;
  2324. gdth_ha_str *ha;
  2325. char *address;
  2326. cpcount = count<=(ushort)scp->bufflen ? count:(ushort)scp->bufflen;
  2327. ha = HADATA(gdth_ctr_tab[hanum]);
  2328. if (scp->use_sg) {
  2329. sl = (struct scatterlist *)scp->request_buffer;
  2330. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2331. unsigned long flags;
  2332. cpnow = (ushort)sl->length;
  2333. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2334. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2335. if (cpsum+cpnow > cpcount)
  2336. cpnow = cpcount - cpsum;
  2337. cpsum += cpnow;
  2338. if (!sl->page) {
  2339. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2340. hanum);
  2341. return;
  2342. }
  2343. local_irq_save(flags);
  2344. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2345. memcpy(address,buffer,cpnow);
  2346. flush_dcache_page(sl->page);
  2347. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2348. local_irq_restore(flags);
  2349. if (cpsum == cpcount)
  2350. break;
  2351. buffer += cpnow;
  2352. }
  2353. } else {
  2354. TRACE(("copy_internal() count %d\n",cpcount));
  2355. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2356. }
  2357. }
  2358. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2359. {
  2360. register gdth_ha_str *ha;
  2361. unchar t;
  2362. gdth_inq_data inq;
  2363. gdth_rdcap_data rdc;
  2364. gdth_sense_data sd;
  2365. gdth_modep_data mpd;
  2366. ha = HADATA(gdth_ctr_tab[hanum]);
  2367. t = scp->device->id;
  2368. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2369. scp->cmnd[0],t));
  2370. scp->result = DID_OK << 16;
  2371. scp->sense_buffer[0] = 0;
  2372. switch (scp->cmnd[0]) {
  2373. case TEST_UNIT_READY:
  2374. case VERIFY:
  2375. case START_STOP:
  2376. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2377. break;
  2378. case INQUIRY:
  2379. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2380. t,ha->hdr[t].devtype));
  2381. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2382. /* you can here set all disks to removable, if you want to do
  2383. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2384. inq.modif_rmb = 0x00;
  2385. if ((ha->hdr[t].devtype & 1) ||
  2386. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2387. inq.modif_rmb = 0x80;
  2388. inq.version = 2;
  2389. inq.resp_aenc = 2;
  2390. inq.add_length= 32;
  2391. strcpy(inq.vendor,ha->oem_name);
  2392. sprintf(inq.product,"Host Drive #%02d",t);
  2393. strcpy(inq.revision," ");
  2394. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2395. break;
  2396. case REQUEST_SENSE:
  2397. TRACE2(("Request sense hdrive %d\n",t));
  2398. sd.errorcode = 0x70;
  2399. sd.segno = 0x00;
  2400. sd.key = NO_SENSE;
  2401. sd.info = 0;
  2402. sd.add_length= 0;
  2403. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2404. break;
  2405. case MODE_SENSE:
  2406. TRACE2(("Mode sense hdrive %d\n",t));
  2407. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2408. mpd.hd.data_length = sizeof(gdth_modep_data);
  2409. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2410. mpd.hd.bd_length = sizeof(mpd.bd);
  2411. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2412. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2413. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2414. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2415. break;
  2416. case READ_CAPACITY:
  2417. TRACE2(("Read capacity hdrive %d\n",t));
  2418. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2419. rdc.last_block_no = 0xffffffff;
  2420. else
  2421. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2422. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2423. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2424. break;
  2425. case SERVICE_ACTION_IN:
  2426. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2427. (ha->cache_feat & GDT_64BIT)) {
  2428. gdth_rdcap16_data rdc16;
  2429. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2430. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2431. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2432. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2433. } else {
  2434. scp->result = DID_ABORT << 16;
  2435. }
  2436. break;
  2437. default:
  2438. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2439. break;
  2440. }
  2441. if (!scp->SCp.have_data_in)
  2442. scp->SCp.have_data_in++;
  2443. else
  2444. return 1;
  2445. return 0;
  2446. }
  2447. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2448. {
  2449. register gdth_ha_str *ha;
  2450. register gdth_cmd_str *cmdp;
  2451. struct scatterlist *sl;
  2452. ulong32 cnt, blockcnt;
  2453. ulong64 no, blockno;
  2454. dma_addr_t phys_addr;
  2455. int i, cmd_index, read_write, sgcnt, mode64;
  2456. struct page *page;
  2457. ulong offset;
  2458. ha = HADATA(gdth_ctr_tab[hanum]);
  2459. cmdp = ha->pccb;
  2460. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2461. scp->cmnd[0],scp->cmd_len,hdrive));
  2462. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2463. return 0;
  2464. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2465. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2466. not required, should not occur due to error return on
  2467. READ_CAPACITY_16 */
  2468. cmdp->Service = CACHESERVICE;
  2469. cmdp->RequestBuffer = scp;
  2470. /* search free command index */
  2471. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2472. TRACE(("GDT: No free command index found\n"));
  2473. return 0;
  2474. }
  2475. /* if it's the first command, set command semaphore */
  2476. if (ha->cmd_cnt == 0)
  2477. gdth_set_sema0(hanum);
  2478. /* fill command */
  2479. read_write = 0;
  2480. if (scp->SCp.sent_command != -1)
  2481. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2482. else if (scp->cmnd[0] == RESERVE)
  2483. cmdp->OpCode = GDT_RESERVE_DRV;
  2484. else if (scp->cmnd[0] == RELEASE)
  2485. cmdp->OpCode = GDT_RELEASE_DRV;
  2486. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2487. if (scp->cmnd[4] & 1) /* prevent ? */
  2488. cmdp->OpCode = GDT_MOUNT;
  2489. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2490. cmdp->OpCode = GDT_UNMOUNT;
  2491. else
  2492. cmdp->OpCode = GDT_FLUSH;
  2493. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2494. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2495. ) {
  2496. read_write = 1;
  2497. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2498. (ha->cache_feat & GDT_WR_THROUGH)))
  2499. cmdp->OpCode = GDT_WRITE_THR;
  2500. else
  2501. cmdp->OpCode = GDT_WRITE;
  2502. } else {
  2503. read_write = 2;
  2504. cmdp->OpCode = GDT_READ;
  2505. }
  2506. cmdp->BoardNode = LOCALBOARD;
  2507. if (mode64) {
  2508. cmdp->u.cache64.DeviceNo = hdrive;
  2509. cmdp->u.cache64.BlockNo = 1;
  2510. cmdp->u.cache64.sg_canz = 0;
  2511. } else {
  2512. cmdp->u.cache.DeviceNo = hdrive;
  2513. cmdp->u.cache.BlockNo = 1;
  2514. cmdp->u.cache.sg_canz = 0;
  2515. }
  2516. if (read_write) {
  2517. if (scp->cmd_len == 16) {
  2518. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2519. blockno = be64_to_cpu(no);
  2520. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2521. blockcnt = be32_to_cpu(cnt);
  2522. } else if (scp->cmd_len == 10) {
  2523. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2524. blockno = be32_to_cpu(no);
  2525. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2526. blockcnt = be16_to_cpu(cnt);
  2527. } else {
  2528. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2529. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2530. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2531. }
  2532. if (mode64) {
  2533. cmdp->u.cache64.BlockNo = blockno;
  2534. cmdp->u.cache64.BlockCnt = blockcnt;
  2535. } else {
  2536. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2537. cmdp->u.cache.BlockCnt = blockcnt;
  2538. }
  2539. if (scp->use_sg) {
  2540. sl = (struct scatterlist *)scp->request_buffer;
  2541. sgcnt = scp->use_sg;
  2542. scp->SCp.Status = GDTH_MAP_SG;
  2543. scp->SCp.Message = (read_write == 1 ?
  2544. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2545. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2546. if (mode64) {
  2547. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2548. cmdp->u.cache64.sg_canz = sgcnt;
  2549. for (i=0; i<sgcnt; ++i,++sl) {
  2550. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2551. #ifdef GDTH_DMA_STATISTICS
  2552. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2553. ha->dma64_cnt++;
  2554. else
  2555. ha->dma32_cnt++;
  2556. #endif
  2557. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2558. }
  2559. } else {
  2560. cmdp->u.cache.DestAddr= 0xffffffff;
  2561. cmdp->u.cache.sg_canz = sgcnt;
  2562. for (i=0; i<sgcnt; ++i,++sl) {
  2563. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2564. #ifdef GDTH_DMA_STATISTICS
  2565. ha->dma32_cnt++;
  2566. #endif
  2567. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2568. }
  2569. }
  2570. #ifdef GDTH_STATISTICS
  2571. if (max_sg < (ulong32)sgcnt) {
  2572. max_sg = (ulong32)sgcnt;
  2573. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2574. }
  2575. #endif
  2576. } else if (scp->request_bufflen) {
  2577. scp->SCp.Status = GDTH_MAP_SINGLE;
  2578. scp->SCp.Message = (read_write == 1 ?
  2579. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2580. page = virt_to_page(scp->request_buffer);
  2581. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2582. phys_addr = pci_map_page(ha->pdev,page,offset,
  2583. scp->request_bufflen,scp->SCp.Message);
  2584. scp->SCp.dma_handle = phys_addr;
  2585. if (mode64) {
  2586. if (ha->cache_feat & SCATTER_GATHER) {
  2587. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2588. cmdp->u.cache64.sg_canz = 1;
  2589. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2590. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2591. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2592. } else {
  2593. cmdp->u.cache64.DestAddr = phys_addr;
  2594. cmdp->u.cache64.sg_canz= 0;
  2595. }
  2596. } else {
  2597. if (ha->cache_feat & SCATTER_GATHER) {
  2598. cmdp->u.cache.DestAddr = 0xffffffff;
  2599. cmdp->u.cache.sg_canz = 1;
  2600. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2601. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2602. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2603. } else {
  2604. cmdp->u.cache.DestAddr = phys_addr;
  2605. cmdp->u.cache.sg_canz= 0;
  2606. }
  2607. }
  2608. }
  2609. }
  2610. /* evaluate command size, check space */
  2611. if (mode64) {
  2612. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2613. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2614. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2615. cmdp->u.cache64.sg_lst[0].sg_len));
  2616. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2617. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2618. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2619. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2620. } else {
  2621. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2622. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2623. cmdp->u.cache.sg_lst[0].sg_ptr,
  2624. cmdp->u.cache.sg_lst[0].sg_len));
  2625. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2626. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2627. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2628. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2629. }
  2630. if (ha->cmd_len & 3)
  2631. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2632. if (ha->cmd_cnt > 0) {
  2633. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2634. ha->ic_all_size) {
  2635. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2636. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2637. return 0;
  2638. }
  2639. }
  2640. /* copy command */
  2641. gdth_copy_command(hanum);
  2642. return cmd_index;
  2643. }
  2644. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2645. {
  2646. register gdth_ha_str *ha;
  2647. register gdth_cmd_str *cmdp;
  2648. struct scatterlist *sl;
  2649. ushort i;
  2650. dma_addr_t phys_addr, sense_paddr;
  2651. int cmd_index, sgcnt, mode64;
  2652. unchar t,l;
  2653. struct page *page;
  2654. ulong offset;
  2655. ha = HADATA(gdth_ctr_tab[hanum]);
  2656. t = scp->device->id;
  2657. l = scp->device->lun;
  2658. cmdp = ha->pccb;
  2659. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2660. scp->cmnd[0],b,t,l));
  2661. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2662. return 0;
  2663. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2664. cmdp->Service = SCSIRAWSERVICE;
  2665. cmdp->RequestBuffer = scp;
  2666. /* search free command index */
  2667. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2668. TRACE(("GDT: No free command index found\n"));
  2669. return 0;
  2670. }
  2671. /* if it's the first command, set command semaphore */
  2672. if (ha->cmd_cnt == 0)
  2673. gdth_set_sema0(hanum);
  2674. /* fill command */
  2675. if (scp->SCp.sent_command != -1) {
  2676. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2677. cmdp->BoardNode = LOCALBOARD;
  2678. if (mode64) {
  2679. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2680. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2681. cmdp->OpCode, cmdp->u.raw64.direction));
  2682. /* evaluate command size */
  2683. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2684. } else {
  2685. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2686. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2687. cmdp->OpCode, cmdp->u.raw.direction));
  2688. /* evaluate command size */
  2689. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2690. }
  2691. } else {
  2692. page = virt_to_page(scp->sense_buffer);
  2693. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2694. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2695. 16,PCI_DMA_FROMDEVICE);
  2696. scp->SCp.buffer = (struct scatterlist *)((ulong32)sense_paddr);
  2697. /* high part, if 64bit */
  2698. scp->host_scribble = (char *)(ulong32)((ulong64)sense_paddr >> 32);
  2699. cmdp->OpCode = GDT_WRITE; /* always */
  2700. cmdp->BoardNode = LOCALBOARD;
  2701. if (mode64) {
  2702. cmdp->u.raw64.reserved = 0;
  2703. cmdp->u.raw64.mdisc_time = 0;
  2704. cmdp->u.raw64.mcon_time = 0;
  2705. cmdp->u.raw64.clen = scp->cmd_len;
  2706. cmdp->u.raw64.target = t;
  2707. cmdp->u.raw64.lun = l;
  2708. cmdp->u.raw64.bus = b;
  2709. cmdp->u.raw64.priority = 0;
  2710. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2711. cmdp->u.raw64.sense_len = 16;
  2712. cmdp->u.raw64.sense_data = sense_paddr;
  2713. cmdp->u.raw64.direction =
  2714. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2715. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2716. } else {
  2717. cmdp->u.raw.reserved = 0;
  2718. cmdp->u.raw.mdisc_time = 0;
  2719. cmdp->u.raw.mcon_time = 0;
  2720. cmdp->u.raw.clen = scp->cmd_len;
  2721. cmdp->u.raw.target = t;
  2722. cmdp->u.raw.lun = l;
  2723. cmdp->u.raw.bus = b;
  2724. cmdp->u.raw.priority = 0;
  2725. cmdp->u.raw.link_p = 0;
  2726. cmdp->u.raw.sdlen = scp->request_bufflen;
  2727. cmdp->u.raw.sense_len = 16;
  2728. cmdp->u.raw.sense_data = sense_paddr;
  2729. cmdp->u.raw.direction =
  2730. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2731. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2732. }
  2733. if (scp->use_sg) {
  2734. sl = (struct scatterlist *)scp->request_buffer;
  2735. sgcnt = scp->use_sg;
  2736. scp->SCp.Status = GDTH_MAP_SG;
  2737. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2738. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2739. if (mode64) {
  2740. cmdp->u.raw64.sdata = (ulong64)-1;
  2741. cmdp->u.raw64.sg_ranz = sgcnt;
  2742. for (i=0; i<sgcnt; ++i,++sl) {
  2743. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2744. #ifdef GDTH_DMA_STATISTICS
  2745. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2746. ha->dma64_cnt++;
  2747. else
  2748. ha->dma32_cnt++;
  2749. #endif
  2750. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2751. }
  2752. } else {
  2753. cmdp->u.raw.sdata = 0xffffffff;
  2754. cmdp->u.raw.sg_ranz = sgcnt;
  2755. for (i=0; i<sgcnt; ++i,++sl) {
  2756. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2757. #ifdef GDTH_DMA_STATISTICS
  2758. ha->dma32_cnt++;
  2759. #endif
  2760. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2761. }
  2762. }
  2763. #ifdef GDTH_STATISTICS
  2764. if (max_sg < sgcnt) {
  2765. max_sg = sgcnt;
  2766. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2767. }
  2768. #endif
  2769. } else {
  2770. scp->SCp.Status = GDTH_MAP_SINGLE;
  2771. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2772. page = virt_to_page(scp->request_buffer);
  2773. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2774. phys_addr = pci_map_page(ha->pdev,page,offset,
  2775. scp->request_bufflen,scp->SCp.Message);
  2776. scp->SCp.dma_handle = phys_addr;
  2777. if (mode64) {
  2778. if (ha->raw_feat & SCATTER_GATHER) {
  2779. cmdp->u.raw64.sdata = (ulong64)-1;
  2780. cmdp->u.raw64.sg_ranz= 1;
  2781. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2782. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2783. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2784. } else {
  2785. cmdp->u.raw64.sdata = phys_addr;
  2786. cmdp->u.raw64.sg_ranz= 0;
  2787. }
  2788. } else {
  2789. if (ha->raw_feat & SCATTER_GATHER) {
  2790. cmdp->u.raw.sdata = 0xffffffff;
  2791. cmdp->u.raw.sg_ranz= 1;
  2792. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2793. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2794. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2795. } else {
  2796. cmdp->u.raw.sdata = phys_addr;
  2797. cmdp->u.raw.sg_ranz= 0;
  2798. }
  2799. }
  2800. }
  2801. if (mode64) {
  2802. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2803. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2804. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2805. cmdp->u.raw64.sg_lst[0].sg_len));
  2806. /* evaluate command size */
  2807. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2808. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2809. } else {
  2810. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2811. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2812. cmdp->u.raw.sg_lst[0].sg_ptr,
  2813. cmdp->u.raw.sg_lst[0].sg_len));
  2814. /* evaluate command size */
  2815. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2816. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2817. }
  2818. }
  2819. /* check space */
  2820. if (ha->cmd_len & 3)
  2821. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2822. if (ha->cmd_cnt > 0) {
  2823. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2824. ha->ic_all_size) {
  2825. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2826. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2827. return 0;
  2828. }
  2829. }
  2830. /* copy command */
  2831. gdth_copy_command(hanum);
  2832. return cmd_index;
  2833. }
  2834. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2835. {
  2836. register gdth_ha_str *ha;
  2837. register gdth_cmd_str *cmdp;
  2838. int cmd_index;
  2839. ha = HADATA(gdth_ctr_tab[hanum]);
  2840. cmdp= ha->pccb;
  2841. TRACE2(("gdth_special_cmd(): "));
  2842. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2843. return 0;
  2844. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2845. cmdp->RequestBuffer = scp;
  2846. /* search free command index */
  2847. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2848. TRACE(("GDT: No free command index found\n"));
  2849. return 0;
  2850. }
  2851. /* if it's the first command, set command semaphore */
  2852. if (ha->cmd_cnt == 0)
  2853. gdth_set_sema0(hanum);
  2854. /* evaluate command size, check space */
  2855. if (cmdp->OpCode == GDT_IOCTL) {
  2856. TRACE2(("IOCTL\n"));
  2857. ha->cmd_len =
  2858. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2859. } else if (cmdp->Service == CACHESERVICE) {
  2860. TRACE2(("cache command %d\n",cmdp->OpCode));
  2861. if (ha->cache_feat & GDT_64BIT)
  2862. ha->cmd_len =
  2863. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2864. else
  2865. ha->cmd_len =
  2866. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2867. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2868. TRACE2(("raw command %d\n",cmdp->OpCode));
  2869. if (ha->raw_feat & GDT_64BIT)
  2870. ha->cmd_len =
  2871. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2872. else
  2873. ha->cmd_len =
  2874. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2875. }
  2876. if (ha->cmd_len & 3)
  2877. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2878. if (ha->cmd_cnt > 0) {
  2879. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2880. ha->ic_all_size) {
  2881. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2882. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2883. return 0;
  2884. }
  2885. }
  2886. /* copy command */
  2887. gdth_copy_command(hanum);
  2888. return cmd_index;
  2889. }
  2890. /* Controller event handling functions */
  2891. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2892. ushort idx, gdth_evt_data *evt)
  2893. {
  2894. gdth_evt_str *e;
  2895. struct timeval tv;
  2896. /* no GDTH_LOCK_HA() ! */
  2897. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2898. if (source == 0) /* no source -> no event */
  2899. return NULL;
  2900. if (ebuffer[elastidx].event_source == source &&
  2901. ebuffer[elastidx].event_idx == idx &&
  2902. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2903. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2904. (char *)&evt->eu, evt->size)) ||
  2905. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2906. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2907. (char *)&evt->event_string)))) {
  2908. e = &ebuffer[elastidx];
  2909. do_gettimeofday(&tv);
  2910. e->last_stamp = tv.tv_sec;
  2911. ++e->same_count;
  2912. } else {
  2913. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2914. ++elastidx;
  2915. if (elastidx == MAX_EVENTS)
  2916. elastidx = 0;
  2917. if (elastidx == eoldidx) { /* reached mark ? */
  2918. ++eoldidx;
  2919. if (eoldidx == MAX_EVENTS)
  2920. eoldidx = 0;
  2921. }
  2922. }
  2923. e = &ebuffer[elastidx];
  2924. e->event_source = source;
  2925. e->event_idx = idx;
  2926. do_gettimeofday(&tv);
  2927. e->first_stamp = e->last_stamp = tv.tv_sec;
  2928. e->same_count = 1;
  2929. e->event_data = *evt;
  2930. e->application = 0;
  2931. }
  2932. return e;
  2933. }
  2934. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2935. {
  2936. gdth_evt_str *e;
  2937. int eindex;
  2938. ulong flags;
  2939. TRACE2(("gdth_read_event() handle %d\n", handle));
  2940. spin_lock_irqsave(&ha->smp_lock, flags);
  2941. if (handle == -1)
  2942. eindex = eoldidx;
  2943. else
  2944. eindex = handle;
  2945. estr->event_source = 0;
  2946. if (eindex >= MAX_EVENTS) {
  2947. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2948. return eindex;
  2949. }
  2950. e = &ebuffer[eindex];
  2951. if (e->event_source != 0) {
  2952. if (eindex != elastidx) {
  2953. if (++eindex == MAX_EVENTS)
  2954. eindex = 0;
  2955. } else {
  2956. eindex = -1;
  2957. }
  2958. memcpy(estr, e, sizeof(gdth_evt_str));
  2959. }
  2960. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2961. return eindex;
  2962. }
  2963. static void gdth_readapp_event(gdth_ha_str *ha,
  2964. unchar application, gdth_evt_str *estr)
  2965. {
  2966. gdth_evt_str *e;
  2967. int eindex;
  2968. ulong flags;
  2969. unchar found = FALSE;
  2970. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2971. spin_lock_irqsave(&ha->smp_lock, flags);
  2972. eindex = eoldidx;
  2973. for (;;) {
  2974. e = &ebuffer[eindex];
  2975. if (e->event_source == 0)
  2976. break;
  2977. if ((e->application & application) == 0) {
  2978. e->application |= application;
  2979. found = TRUE;
  2980. break;
  2981. }
  2982. if (eindex == elastidx)
  2983. break;
  2984. if (++eindex == MAX_EVENTS)
  2985. eindex = 0;
  2986. }
  2987. if (found)
  2988. memcpy(estr, e, sizeof(gdth_evt_str));
  2989. else
  2990. estr->event_source = 0;
  2991. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2992. }
  2993. static void gdth_clear_events(void)
  2994. {
  2995. TRACE(("gdth_clear_events()"));
  2996. eoldidx = elastidx = 0;
  2997. ebuffer[0].event_source = 0;
  2998. }
  2999. /* SCSI interface functions */
  3000. static irqreturn_t gdth_interrupt(int irq,void *dev_id,struct pt_regs *regs)
  3001. {
  3002. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3003. register gdth_ha_str *ha;
  3004. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3005. gdt6_dpram_str __iomem *dp6_ptr;
  3006. gdt2_dpram_str __iomem *dp2_ptr;
  3007. Scsi_Cmnd *scp;
  3008. int hanum, rval, i;
  3009. unchar IStatus;
  3010. ushort Service;
  3011. ulong flags = 0;
  3012. #ifdef INT_COAL
  3013. int coalesced = FALSE;
  3014. int next = FALSE;
  3015. gdth_coal_status *pcs = NULL;
  3016. int act_int_coal = 0;
  3017. #endif
  3018. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3019. /* if polling and not from gdth_wait() -> return */
  3020. if (gdth_polling) {
  3021. if (!gdth_from_wait) {
  3022. return IRQ_HANDLED;
  3023. }
  3024. }
  3025. if (!gdth_polling)
  3026. spin_lock_irqsave(&ha2->smp_lock, flags);
  3027. wait_index = 0;
  3028. /* search controller */
  3029. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3030. /* spurious interrupt */
  3031. if (!gdth_polling)
  3032. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3033. return IRQ_HANDLED;
  3034. }
  3035. ha = HADATA(gdth_ctr_tab[hanum]);
  3036. #ifdef GDTH_STATISTICS
  3037. ++act_ints;
  3038. #endif
  3039. #ifdef INT_COAL
  3040. /* See if the fw is returning coalesced status */
  3041. if (IStatus == COALINDEX) {
  3042. /* Coalesced status. Setup the initial status
  3043. buffer pointer and flags */
  3044. pcs = ha->coal_stat;
  3045. coalesced = TRUE;
  3046. next = TRUE;
  3047. }
  3048. do {
  3049. if (coalesced) {
  3050. /* For coalesced requests all status
  3051. information is found in the status buffer */
  3052. IStatus = (unchar)(pcs->status & 0xff);
  3053. }
  3054. #endif
  3055. if (ha->type == GDT_EISA) {
  3056. if (IStatus & 0x80) { /* error flag */
  3057. IStatus &= ~0x80;
  3058. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3059. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3060. } else /* no error */
  3061. ha->status = S_OK;
  3062. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3063. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3064. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3065. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3066. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3067. } else if (ha->type == GDT_ISA) {
  3068. dp2_ptr = ha->brd;
  3069. if (IStatus & 0x80) { /* error flag */
  3070. IStatus &= ~0x80;
  3071. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3072. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3073. } else /* no error */
  3074. ha->status = S_OK;
  3075. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3076. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3077. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3078. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3079. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3080. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3081. } else if (ha->type == GDT_PCI) {
  3082. dp6_ptr = ha->brd;
  3083. if (IStatus & 0x80) { /* error flag */
  3084. IStatus &= ~0x80;
  3085. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3086. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3087. } else /* no error */
  3088. ha->status = S_OK;
  3089. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3090. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3091. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3092. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3093. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3094. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3095. } else if (ha->type == GDT_PCINEW) {
  3096. if (IStatus & 0x80) { /* error flag */
  3097. IStatus &= ~0x80;
  3098. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3099. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3100. } else
  3101. ha->status = S_OK;
  3102. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3103. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3104. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3105. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3106. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3107. } else if (ha->type == GDT_PCIMPR) {
  3108. dp6m_ptr = ha->brd;
  3109. if (IStatus & 0x80) { /* error flag */
  3110. IStatus &= ~0x80;
  3111. #ifdef INT_COAL
  3112. if (coalesced)
  3113. ha->status = pcs->ext_status && 0xffff;
  3114. else
  3115. #endif
  3116. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3117. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3118. } else /* no error */
  3119. ha->status = S_OK;
  3120. #ifdef INT_COAL
  3121. /* get information */
  3122. if (coalesced) {
  3123. ha->info = pcs->info0;
  3124. ha->info2 = pcs->info1;
  3125. ha->service = (pcs->ext_status >> 16) && 0xffff;
  3126. } else
  3127. #endif
  3128. {
  3129. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3130. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3131. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3132. }
  3133. /* event string */
  3134. if (IStatus == ASYNCINDEX) {
  3135. if (ha->service != SCREENSERVICE &&
  3136. (ha->fw_vers & 0xff) >= 0x1a) {
  3137. ha->dvr.severity = gdth_readb
  3138. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3139. for (i = 0; i < 256; ++i) {
  3140. ha->dvr.event_string[i] = gdth_readb
  3141. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3142. if (ha->dvr.event_string[i] == 0)
  3143. break;
  3144. }
  3145. }
  3146. }
  3147. #ifdef INT_COAL
  3148. /* Make sure that non coalesced interrupts get cleared
  3149. before being handled by gdth_async_event/gdth_sync_event */
  3150. if (!coalesced)
  3151. #endif
  3152. {
  3153. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3154. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3155. }
  3156. } else {
  3157. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3158. if (!gdth_polling)
  3159. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3160. return IRQ_HANDLED;
  3161. }
  3162. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3163. IStatus,ha->status,ha->info));
  3164. if (gdth_from_wait) {
  3165. wait_hanum = hanum;
  3166. wait_index = (int)IStatus;
  3167. }
  3168. if (IStatus == ASYNCINDEX) {
  3169. TRACE2(("gdth_interrupt() async. event\n"));
  3170. gdth_async_event(hanum);
  3171. if (!gdth_polling)
  3172. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3173. gdth_next(hanum);
  3174. return IRQ_HANDLED;
  3175. }
  3176. if (IStatus == SPEZINDEX) {
  3177. TRACE2(("Service unknown or not initialized !\n"));
  3178. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3179. ha->dvr.eu.driver.ionode = hanum;
  3180. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3181. if (!gdth_polling)
  3182. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3183. return IRQ_HANDLED;
  3184. }
  3185. scp = ha->cmd_tab[IStatus-2].cmnd;
  3186. Service = ha->cmd_tab[IStatus-2].service;
  3187. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3188. if (scp == UNUSED_CMND) {
  3189. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3190. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3191. ha->dvr.eu.driver.ionode = hanum;
  3192. ha->dvr.eu.driver.index = IStatus;
  3193. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3194. if (!gdth_polling)
  3195. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3196. return IRQ_HANDLED;
  3197. }
  3198. if (scp == INTERNAL_CMND) {
  3199. TRACE(("gdth_interrupt() answer to internal command\n"));
  3200. if (!gdth_polling)
  3201. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3202. return IRQ_HANDLED;
  3203. }
  3204. TRACE(("gdth_interrupt() sync. status\n"));
  3205. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3206. if (!gdth_polling)
  3207. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3208. if (rval == 2) {
  3209. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3210. } else if (rval == 1) {
  3211. scp->scsi_done(scp);
  3212. }
  3213. #ifdef INT_COAL
  3214. if (coalesced) {
  3215. /* go to the next status in the status buffer */
  3216. ++pcs;
  3217. #ifdef GDTH_STATISTICS
  3218. ++act_int_coal;
  3219. if (act_int_coal > max_int_coal) {
  3220. max_int_coal = act_int_coal;
  3221. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3222. }
  3223. #endif
  3224. /* see if there is another status */
  3225. if (pcs->status == 0)
  3226. /* Stop the coalesce loop */
  3227. next = FALSE;
  3228. }
  3229. } while (next);
  3230. /* coalescing only for new GDT_PCIMPR controllers available */
  3231. if (ha->type == GDT_PCIMPR && coalesced) {
  3232. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3233. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3234. }
  3235. #endif
  3236. gdth_next(hanum);
  3237. return IRQ_HANDLED;
  3238. }
  3239. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3240. {
  3241. register gdth_ha_str *ha;
  3242. gdth_msg_str *msg;
  3243. gdth_cmd_str *cmdp;
  3244. unchar b, t;
  3245. ha = HADATA(gdth_ctr_tab[hanum]);
  3246. cmdp = ha->pccb;
  3247. TRACE(("gdth_sync_event() serv %d status %d\n",
  3248. service,ha->status));
  3249. if (service == SCREENSERVICE) {
  3250. msg = ha->pmsg;
  3251. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3252. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3253. if (msg->msg_len > MSGLEN+1)
  3254. msg->msg_len = MSGLEN+1;
  3255. if (msg->msg_len)
  3256. if (!(msg->msg_answer && msg->msg_ext)) {
  3257. msg->msg_text[msg->msg_len] = '\0';
  3258. printk("%s",msg->msg_text);
  3259. }
  3260. if (msg->msg_ext && !msg->msg_answer) {
  3261. while (gdth_test_busy(hanum))
  3262. gdth_delay(0);
  3263. cmdp->Service = SCREENSERVICE;
  3264. cmdp->RequestBuffer = SCREEN_CMND;
  3265. gdth_get_cmd_index(hanum);
  3266. gdth_set_sema0(hanum);
  3267. cmdp->OpCode = GDT_READ;
  3268. cmdp->BoardNode = LOCALBOARD;
  3269. cmdp->u.screen.reserved = 0;
  3270. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3271. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3272. ha->cmd_offs_dpmem = 0;
  3273. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3274. + sizeof(ulong64);
  3275. ha->cmd_cnt = 0;
  3276. gdth_copy_command(hanum);
  3277. gdth_release_event(hanum);
  3278. return 0;
  3279. }
  3280. if (msg->msg_answer && msg->msg_alen) {
  3281. /* default answers (getchar() not possible) */
  3282. if (msg->msg_alen == 1) {
  3283. msg->msg_alen = 0;
  3284. msg->msg_len = 1;
  3285. msg->msg_text[0] = 0;
  3286. } else {
  3287. msg->msg_alen -= 2;
  3288. msg->msg_len = 2;
  3289. msg->msg_text[0] = 1;
  3290. msg->msg_text[1] = 0;
  3291. }
  3292. msg->msg_ext = 0;
  3293. msg->msg_answer = 0;
  3294. while (gdth_test_busy(hanum))
  3295. gdth_delay(0);
  3296. cmdp->Service = SCREENSERVICE;
  3297. cmdp->RequestBuffer = SCREEN_CMND;
  3298. gdth_get_cmd_index(hanum);
  3299. gdth_set_sema0(hanum);
  3300. cmdp->OpCode = GDT_WRITE;
  3301. cmdp->BoardNode = LOCALBOARD;
  3302. cmdp->u.screen.reserved = 0;
  3303. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3304. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3305. ha->cmd_offs_dpmem = 0;
  3306. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3307. + sizeof(ulong64);
  3308. ha->cmd_cnt = 0;
  3309. gdth_copy_command(hanum);
  3310. gdth_release_event(hanum);
  3311. return 0;
  3312. }
  3313. printk("\n");
  3314. } else {
  3315. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3316. t = scp->device->id;
  3317. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3318. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3319. }
  3320. /* cache or raw service */
  3321. if (ha->status == S_BSY) {
  3322. TRACE2(("Controller busy -> retry !\n"));
  3323. if (scp->SCp.sent_command == GDT_MOUNT)
  3324. scp->SCp.sent_command = GDT_CLUST_INFO;
  3325. /* retry */
  3326. return 2;
  3327. }
  3328. if (scp->SCp.Status == GDTH_MAP_SG)
  3329. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3330. scp->use_sg,scp->SCp.Message);
  3331. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3332. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3333. scp->request_bufflen,scp->SCp.Message);
  3334. if (scp->SCp.buffer) {
  3335. dma_addr_t addr;
  3336. addr = (dma_addr_t)(ulong32)scp->SCp.buffer;
  3337. if (scp->host_scribble)
  3338. addr += (dma_addr_t)((ulong64)(ulong32)scp->host_scribble << 32);
  3339. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3340. }
  3341. if (ha->status == S_OK) {
  3342. scp->SCp.Status = S_OK;
  3343. scp->SCp.Message = ha->info;
  3344. if (scp->SCp.sent_command != -1) {
  3345. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3346. scp->SCp.sent_command));
  3347. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3348. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3349. ha->hdr[t].cluster_type = (unchar)ha->info;
  3350. if (!(ha->hdr[t].cluster_type &
  3351. CLUSTER_MOUNTED)) {
  3352. /* NOT MOUNTED -> MOUNT */
  3353. scp->SCp.sent_command = GDT_MOUNT;
  3354. if (ha->hdr[t].cluster_type &
  3355. CLUSTER_RESERVED) {
  3356. /* cluster drive RESERVED (on the other node) */
  3357. scp->SCp.phase = -2; /* reservation conflict */
  3358. }
  3359. } else {
  3360. scp->SCp.sent_command = -1;
  3361. }
  3362. } else {
  3363. if (scp->SCp.sent_command == GDT_MOUNT) {
  3364. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3365. ha->hdr[t].media_changed = TRUE;
  3366. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3367. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3368. ha->hdr[t].media_changed = TRUE;
  3369. }
  3370. scp->SCp.sent_command = -1;
  3371. }
  3372. /* retry */
  3373. scp->SCp.this_residual = HIGH_PRI;
  3374. return 2;
  3375. } else {
  3376. /* RESERVE/RELEASE ? */
  3377. if (scp->cmnd[0] == RESERVE) {
  3378. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3379. } else if (scp->cmnd[0] == RELEASE) {
  3380. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3381. }
  3382. scp->result = DID_OK << 16;
  3383. scp->sense_buffer[0] = 0;
  3384. }
  3385. } else {
  3386. scp->SCp.Status = ha->status;
  3387. scp->SCp.Message = ha->info;
  3388. if (scp->SCp.sent_command != -1) {
  3389. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3390. scp->SCp.sent_command, ha->status));
  3391. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3392. scp->SCp.sent_command == GDT_SCAN_END) {
  3393. scp->SCp.sent_command = -1;
  3394. /* retry */
  3395. scp->SCp.this_residual = HIGH_PRI;
  3396. return 2;
  3397. }
  3398. memset((char*)scp->sense_buffer,0,16);
  3399. scp->sense_buffer[0] = 0x70;
  3400. scp->sense_buffer[2] = NOT_READY;
  3401. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3402. } else if (service == CACHESERVICE) {
  3403. if (ha->status == S_CACHE_UNKNOWN &&
  3404. (ha->hdr[t].cluster_type &
  3405. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3406. /* bus reset -> force GDT_CLUST_INFO */
  3407. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3408. }
  3409. memset((char*)scp->sense_buffer,0,16);
  3410. if (ha->status == (ushort)S_CACHE_RESERV) {
  3411. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3412. } else {
  3413. scp->sense_buffer[0] = 0x70;
  3414. scp->sense_buffer[2] = NOT_READY;
  3415. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3416. }
  3417. if (scp->done != gdth_scsi_done) {
  3418. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3419. ha->dvr.eu.sync.ionode = hanum;
  3420. ha->dvr.eu.sync.service = service;
  3421. ha->dvr.eu.sync.status = ha->status;
  3422. ha->dvr.eu.sync.info = ha->info;
  3423. ha->dvr.eu.sync.hostdrive = t;
  3424. if (ha->status >= 0x8000)
  3425. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3426. else
  3427. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3428. }
  3429. } else {
  3430. /* sense buffer filled from controller firmware (DMA) */
  3431. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3432. scp->result = DID_BAD_TARGET << 16;
  3433. } else {
  3434. scp->result = (DID_OK << 16) | ha->info;
  3435. }
  3436. }
  3437. }
  3438. if (!scp->SCp.have_data_in)
  3439. scp->SCp.have_data_in++;
  3440. else
  3441. return 1;
  3442. }
  3443. return 0;
  3444. }
  3445. static char *async_cache_tab[] = {
  3446. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3447. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3448. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3449. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3450. /* 2*/ "\005\000\002\006\004"
  3451. "GDT HA %u, Host Drive %lu not ready",
  3452. /* 3*/ "\005\000\002\006\004"
  3453. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3454. /* 4*/ "\005\000\002\006\004"
  3455. "GDT HA %u, mirror update on Host Drive %lu failed",
  3456. /* 5*/ "\005\000\002\006\004"
  3457. "GDT HA %u, Mirror Drive %lu failed",
  3458. /* 6*/ "\005\000\002\006\004"
  3459. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3460. /* 7*/ "\005\000\002\006\004"
  3461. "GDT HA %u, Host Drive %lu write protected",
  3462. /* 8*/ "\005\000\002\006\004"
  3463. "GDT HA %u, media changed in Host Drive %lu",
  3464. /* 9*/ "\005\000\002\006\004"
  3465. "GDT HA %u, Host Drive %lu is offline",
  3466. /*10*/ "\005\000\002\006\004"
  3467. "GDT HA %u, media change of Mirror Drive %lu",
  3468. /*11*/ "\005\000\002\006\004"
  3469. "GDT HA %u, Mirror Drive %lu is write protected",
  3470. /*12*/ "\005\000\002\006\004"
  3471. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3472. /*13*/ "\007\000\002\006\002\010\002"
  3473. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3474. /*14*/ "\005\000\002\006\002"
  3475. "GDT HA %u, Array Drive %u: FAIL state entered",
  3476. /*15*/ "\005\000\002\006\002"
  3477. "GDT HA %u, Array Drive %u: error",
  3478. /*16*/ "\007\000\002\006\002\010\002"
  3479. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3480. /*17*/ "\005\000\002\006\002"
  3481. "GDT HA %u, Array Drive %u: parity build failed",
  3482. /*18*/ "\005\000\002\006\002"
  3483. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3484. /*19*/ "\005\000\002\010\002"
  3485. "GDT HA %u, Test of Hot Fix %u failed",
  3486. /*20*/ "\005\000\002\006\002"
  3487. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3488. /*21*/ "\005\000\002\006\002"
  3489. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3490. /*22*/ "\007\000\002\006\002\010\002"
  3491. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3492. /*23*/ "\005\000\002\006\002"
  3493. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3494. /*24*/ "\005\000\002\010\002"
  3495. "GDT HA %u, mirror update on Cache Drive %u completed",
  3496. /*25*/ "\005\000\002\010\002"
  3497. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3498. /*26*/ "\005\000\002\006\002"
  3499. "GDT HA %u, Array Drive %u: drive rebuild started",
  3500. /*27*/ "\005\000\002\012\001"
  3501. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3502. /*28*/ "\005\000\002\012\001"
  3503. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3504. /*29*/ "\007\000\002\012\001\013\001"
  3505. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3506. /*30*/ "\007\000\002\012\001\013\001"
  3507. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3508. /*31*/ "\007\000\002\012\001\013\001"
  3509. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3510. /*32*/ "\007\000\002\012\001\013\001"
  3511. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3512. /*33*/ "\007\000\002\012\001\013\001"
  3513. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3514. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3515. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3516. /*35*/ "\007\000\002\012\001\013\001"
  3517. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3518. /*36*/ "\007\000\002\012\001\013\001"
  3519. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3520. /*37*/ "\007\000\002\012\001\006\004"
  3521. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3522. /*38*/ "\007\000\002\012\001\013\001"
  3523. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3524. /*39*/ "\007\000\002\012\001\013\001"
  3525. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3526. /*40*/ "\007\000\002\012\001\013\001"
  3527. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3528. /*41*/ "\007\000\002\012\001\013\001"
  3529. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3530. /*42*/ "\005\000\002\006\002"
  3531. "GDT HA %u, Array Drive %u: drive build started",
  3532. /*43*/ "\003\000\002"
  3533. "GDT HA %u, DRAM parity error detected",
  3534. /*44*/ "\005\000\002\006\002"
  3535. "GDT HA %u, Mirror Drive %u: update started",
  3536. /*45*/ "\007\000\002\006\002\010\002"
  3537. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3538. /*46*/ "\005\000\002\006\002"
  3539. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3540. /*47*/ "\005\000\002\006\002"
  3541. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3542. /*48*/ "\005\000\002\006\002"
  3543. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3544. /*49*/ "\005\000\002\006\002"
  3545. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3546. /*50*/ "\007\000\002\012\001\013\001"
  3547. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3548. /*51*/ "\005\000\002\006\002"
  3549. "GDT HA %u, Array Drive %u: expand started",
  3550. /*52*/ "\005\000\002\006\002"
  3551. "GDT HA %u, Array Drive %u: expand finished successfully",
  3552. /*53*/ "\005\000\002\006\002"
  3553. "GDT HA %u, Array Drive %u: expand failed",
  3554. /*54*/ "\003\000\002"
  3555. "GDT HA %u, CPU temperature critical",
  3556. /*55*/ "\003\000\002"
  3557. "GDT HA %u, CPU temperature OK",
  3558. /*56*/ "\005\000\002\006\004"
  3559. "GDT HA %u, Host drive %lu created",
  3560. /*57*/ "\005\000\002\006\002"
  3561. "GDT HA %u, Array Drive %u: expand restarted",
  3562. /*58*/ "\005\000\002\006\002"
  3563. "GDT HA %u, Array Drive %u: expand stopped",
  3564. /*59*/ "\005\000\002\010\002"
  3565. "GDT HA %u, Mirror Drive %u: drive build quited",
  3566. /*60*/ "\005\000\002\006\002"
  3567. "GDT HA %u, Array Drive %u: parity build quited",
  3568. /*61*/ "\005\000\002\006\002"
  3569. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3570. /*62*/ "\005\000\002\006\002"
  3571. "GDT HA %u, Array Drive %u: parity verify started",
  3572. /*63*/ "\005\000\002\006\002"
  3573. "GDT HA %u, Array Drive %u: parity verify done",
  3574. /*64*/ "\005\000\002\006\002"
  3575. "GDT HA %u, Array Drive %u: parity verify failed",
  3576. /*65*/ "\005\000\002\006\002"
  3577. "GDT HA %u, Array Drive %u: parity error detected",
  3578. /*66*/ "\005\000\002\006\002"
  3579. "GDT HA %u, Array Drive %u: parity verify quited",
  3580. /*67*/ "\005\000\002\006\002"
  3581. "GDT HA %u, Host Drive %u reserved",
  3582. /*68*/ "\005\000\002\006\002"
  3583. "GDT HA %u, Host Drive %u mounted and released",
  3584. /*69*/ "\005\000\002\006\002"
  3585. "GDT HA %u, Host Drive %u released",
  3586. /*70*/ "\003\000\002"
  3587. "GDT HA %u, DRAM error detected and corrected with ECC",
  3588. /*71*/ "\003\000\002"
  3589. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3590. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3591. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3592. /*73*/ "\005\000\002\006\002"
  3593. "GDT HA %u, Host drive %u resetted locally",
  3594. /*74*/ "\005\000\002\006\002"
  3595. "GDT HA %u, Host drive %u resetted remotely",
  3596. /*75*/ "\003\000\002"
  3597. "GDT HA %u, async. status 75 unknown",
  3598. };
  3599. static int gdth_async_event(int hanum)
  3600. {
  3601. gdth_ha_str *ha;
  3602. gdth_cmd_str *cmdp;
  3603. int cmd_index;
  3604. ha = HADATA(gdth_ctr_tab[hanum]);
  3605. cmdp= ha->pccb;
  3606. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3607. hanum,ha->service));
  3608. if (ha->service == SCREENSERVICE) {
  3609. if (ha->status == MSG_REQUEST) {
  3610. while (gdth_test_busy(hanum))
  3611. gdth_delay(0);
  3612. cmdp->Service = SCREENSERVICE;
  3613. cmdp->RequestBuffer = SCREEN_CMND;
  3614. cmd_index = gdth_get_cmd_index(hanum);
  3615. gdth_set_sema0(hanum);
  3616. cmdp->OpCode = GDT_READ;
  3617. cmdp->BoardNode = LOCALBOARD;
  3618. cmdp->u.screen.reserved = 0;
  3619. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3620. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3621. ha->cmd_offs_dpmem = 0;
  3622. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3623. + sizeof(ulong64);
  3624. ha->cmd_cnt = 0;
  3625. gdth_copy_command(hanum);
  3626. if (ha->type == GDT_EISA)
  3627. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3628. else if (ha->type == GDT_ISA)
  3629. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3630. else
  3631. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3632. (ushort)((ha->brd_phys>>3)&0x1f));
  3633. gdth_release_event(hanum);
  3634. }
  3635. } else {
  3636. if (ha->type == GDT_PCIMPR &&
  3637. (ha->fw_vers & 0xff) >= 0x1a) {
  3638. ha->dvr.size = 0;
  3639. ha->dvr.eu.async.ionode = hanum;
  3640. ha->dvr.eu.async.status = ha->status;
  3641. /* severity and event_string already set! */
  3642. } else {
  3643. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3644. ha->dvr.eu.async.ionode = hanum;
  3645. ha->dvr.eu.async.service = ha->service;
  3646. ha->dvr.eu.async.status = ha->status;
  3647. ha->dvr.eu.async.info = ha->info;
  3648. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3649. }
  3650. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3651. gdth_log_event( &ha->dvr, NULL );
  3652. /* new host drive from expand? */
  3653. if (ha->service == CACHESERVICE && ha->status == 56) {
  3654. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3655. (ushort)ha->info));
  3656. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3657. }
  3658. }
  3659. return 1;
  3660. }
  3661. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3662. {
  3663. gdth_stackframe stack;
  3664. char *f = NULL;
  3665. int i,j;
  3666. TRACE2(("gdth_log_event()\n"));
  3667. if (dvr->size == 0) {
  3668. if (buffer == NULL) {
  3669. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3670. } else {
  3671. sprintf(buffer,"Adapter %d: %s\n",
  3672. dvr->eu.async.ionode,dvr->event_string);
  3673. }
  3674. } else if (dvr->eu.async.service == CACHESERVICE &&
  3675. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3676. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3677. dvr->eu.async.status));
  3678. f = async_cache_tab[dvr->eu.async.status];
  3679. /* i: parameter to push, j: stack element to fill */
  3680. for (j=0,i=1; i < f[0]; i+=2) {
  3681. switch (f[i+1]) {
  3682. case 4:
  3683. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3684. break;
  3685. case 2:
  3686. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3687. break;
  3688. case 1:
  3689. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3690. break;
  3691. default:
  3692. break;
  3693. }
  3694. }
  3695. if (buffer == NULL) {
  3696. printk(&f[(int)f[0]],stack);
  3697. printk("\n");
  3698. } else {
  3699. sprintf(buffer,&f[(int)f[0]],stack);
  3700. }
  3701. } else {
  3702. if (buffer == NULL) {
  3703. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3704. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3705. } else {
  3706. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3707. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3708. }
  3709. }
  3710. }
  3711. #ifdef GDTH_STATISTICS
  3712. static void gdth_timeout(ulong data)
  3713. {
  3714. ulong32 i;
  3715. Scsi_Cmnd *nscp;
  3716. gdth_ha_str *ha;
  3717. ulong flags;
  3718. int hanum = 0;
  3719. ha = HADATA(gdth_ctr_tab[hanum]);
  3720. spin_lock_irqsave(&ha->smp_lock, flags);
  3721. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3722. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3723. ++act_stats;
  3724. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3725. ++act_rq;
  3726. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3727. act_ints, act_ios, act_stats, act_rq));
  3728. act_ints = act_ios = 0;
  3729. gdth_timer.expires = jiffies + 30 * HZ;
  3730. add_timer(&gdth_timer);
  3731. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3732. }
  3733. #endif
  3734. static void __init internal_setup(char *str,int *ints)
  3735. {
  3736. int i, argc;
  3737. char *cur_str, *argv;
  3738. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3739. str ? str:"NULL", ints ? ints[0]:0));
  3740. /* read irq[] from ints[] */
  3741. if (ints) {
  3742. argc = ints[0];
  3743. if (argc > 0) {
  3744. if (argc > MAXHA)
  3745. argc = MAXHA;
  3746. for (i = 0; i < argc; ++i)
  3747. irq[i] = ints[i+1];
  3748. }
  3749. }
  3750. /* analyse string */
  3751. argv = str;
  3752. while (argv && (cur_str = strchr(argv, ':'))) {
  3753. int val = 0, c = *++cur_str;
  3754. if (c == 'n' || c == 'N')
  3755. val = 0;
  3756. else if (c == 'y' || c == 'Y')
  3757. val = 1;
  3758. else
  3759. val = (int)simple_strtoul(cur_str, NULL, 0);
  3760. if (!strncmp(argv, "disable:", 8))
  3761. disable = val;
  3762. else if (!strncmp(argv, "reserve_mode:", 13))
  3763. reserve_mode = val;
  3764. else if (!strncmp(argv, "reverse_scan:", 13))
  3765. reverse_scan = val;
  3766. else if (!strncmp(argv, "hdr_channel:", 12))
  3767. hdr_channel = val;
  3768. else if (!strncmp(argv, "max_ids:", 8))
  3769. max_ids = val;
  3770. else if (!strncmp(argv, "rescan:", 7))
  3771. rescan = val;
  3772. else if (!strncmp(argv, "virt_ctr:", 9))
  3773. virt_ctr = val;
  3774. else if (!strncmp(argv, "shared_access:", 14))
  3775. shared_access = val;
  3776. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3777. probe_eisa_isa = val;
  3778. else if (!strncmp(argv, "reserve_list:", 13)) {
  3779. reserve_list[0] = val;
  3780. for (i = 1; i < MAX_RES_ARGS; i++) {
  3781. cur_str = strchr(cur_str, ',');
  3782. if (!cur_str)
  3783. break;
  3784. if (!isdigit((int)*++cur_str)) {
  3785. --cur_str;
  3786. break;
  3787. }
  3788. reserve_list[i] =
  3789. (int)simple_strtoul(cur_str, NULL, 0);
  3790. }
  3791. if (!cur_str)
  3792. break;
  3793. argv = ++cur_str;
  3794. continue;
  3795. }
  3796. if ((argv = strchr(argv, ',')))
  3797. ++argv;
  3798. }
  3799. }
  3800. int __init option_setup(char *str)
  3801. {
  3802. int ints[MAXHA];
  3803. char *cur = str;
  3804. int i = 1;
  3805. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3806. while (cur && isdigit(*cur) && i <= MAXHA) {
  3807. ints[i++] = simple_strtoul(cur, NULL, 0);
  3808. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3809. }
  3810. ints[0] = i - 1;
  3811. internal_setup(cur, ints);
  3812. return 1;
  3813. }
  3814. static int __init gdth_detect(struct scsi_host_template *shtp)
  3815. {
  3816. struct Scsi_Host *shp;
  3817. gdth_pci_str pcistr[MAXHA];
  3818. gdth_ha_str *ha;
  3819. ulong32 isa_bios;
  3820. ushort eisa_slot;
  3821. int i,hanum,cnt,ctr,err;
  3822. unchar b;
  3823. #ifdef DEBUG_GDTH
  3824. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3825. DebugState);
  3826. printk(" Destination of debugging information: ");
  3827. #ifdef __SERIAL__
  3828. #ifdef __COM2__
  3829. printk("Serial port COM2\n");
  3830. #else
  3831. printk("Serial port COM1\n");
  3832. #endif
  3833. #else
  3834. printk("Console\n");
  3835. #endif
  3836. gdth_delay(3000);
  3837. #endif
  3838. TRACE(("gdth_detect()\n"));
  3839. if (disable) {
  3840. printk("GDT-HA: Controller driver disabled from command line !\n");
  3841. return 0;
  3842. }
  3843. printk("GDT-HA: Storage RAID Controller Driver. Version: %s \n",GDTH_VERSION_STR);
  3844. /* initializations */
  3845. gdth_polling = TRUE; b = 0;
  3846. gdth_clear_events();
  3847. /* As default we do not probe for EISA or ISA controllers */
  3848. if (probe_eisa_isa) {
  3849. /* scanning for controllers, at first: ISA controller */
  3850. for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
  3851. dma_addr_t scratch_dma_handle;
  3852. scratch_dma_handle = 0;
  3853. if (gdth_ctr_count >= MAXHA)
  3854. break;
  3855. if (gdth_search_isa(isa_bios)) { /* controller found */
  3856. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3857. if (shp == NULL)
  3858. continue;
  3859. ha = HADATA(shp);
  3860. if (!gdth_init_isa(isa_bios,ha)) {
  3861. scsi_unregister(shp);
  3862. continue;
  3863. }
  3864. #ifdef __ia64__
  3865. break;
  3866. #else
  3867. /* controller found and initialized */
  3868. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  3869. isa_bios,ha->irq,ha->drq);
  3870. if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
  3871. printk("GDT-ISA: Unable to allocate IRQ\n");
  3872. scsi_unregister(shp);
  3873. continue;
  3874. }
  3875. if (request_dma(ha->drq,"gdth")) {
  3876. printk("GDT-ISA: Unable to allocate DMA channel\n");
  3877. free_irq(ha->irq,ha);
  3878. scsi_unregister(shp);
  3879. continue;
  3880. }
  3881. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  3882. enable_dma(ha->drq);
  3883. shp->unchecked_isa_dma = 1;
  3884. shp->irq = ha->irq;
  3885. shp->dma_channel = ha->drq;
  3886. hanum = gdth_ctr_count;
  3887. gdth_ctr_tab[gdth_ctr_count++] = shp;
  3888. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3889. NUMDATA(shp)->hanum = (ushort)hanum;
  3890. NUMDATA(shp)->busnum= 0;
  3891. ha->pccb = CMDDATA(shp);
  3892. ha->ccb_phys = 0L;
  3893. ha->pdev = NULL;
  3894. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  3895. &scratch_dma_handle);
  3896. ha->scratch_phys = scratch_dma_handle;
  3897. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  3898. &scratch_dma_handle);
  3899. ha->msg_phys = scratch_dma_handle;
  3900. #ifdef INT_COAL
  3901. ha->coal_stat = (gdth_coal_status *)
  3902. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3903. MAXOFFSETS, &scratch_dma_handle);
  3904. ha->coal_stat_phys = scratch_dma_handle;
  3905. #endif
  3906. ha->scratch_busy = FALSE;
  3907. ha->req_first = NULL;
  3908. ha->tid_cnt = MAX_HDRIVES;
  3909. if (max_ids > 0 && max_ids < ha->tid_cnt)
  3910. ha->tid_cnt = max_ids;
  3911. for (i=0; i<GDTH_MAXCMDS; ++i)
  3912. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3913. ha->scan_mode = rescan ? 0x10 : 0;
  3914. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  3915. !gdth_search_drives(hanum)) {
  3916. printk("GDT-ISA: Error during device scan\n");
  3917. --gdth_ctr_count;
  3918. --gdth_ctr_vcount;
  3919. #ifdef INT_COAL
  3920. if (ha->coal_stat)
  3921. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3922. MAXOFFSETS, ha->coal_stat,
  3923. ha->coal_stat_phys);
  3924. #endif
  3925. if (ha->pscratch)
  3926. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  3927. ha->pscratch, ha->scratch_phys);
  3928. if (ha->pmsg)
  3929. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  3930. ha->pmsg, ha->msg_phys);
  3931. free_irq(ha->irq,ha);
  3932. scsi_unregister(shp);
  3933. continue;
  3934. }
  3935. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  3936. hdr_channel = ha->bus_cnt;
  3937. ha->virt_bus = hdr_channel;
  3938. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  3939. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  3940. shp->highmem_io = 0;
  3941. #endif
  3942. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  3943. shp->max_cmd_len = 16;
  3944. shp->max_id = ha->tid_cnt;
  3945. shp->max_lun = MAXLUN;
  3946. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  3947. if (virt_ctr) {
  3948. virt_ctr = 1;
  3949. /* register addit. SCSI channels as virtual controllers */
  3950. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  3951. shp = scsi_register(shtp,sizeof(gdth_num_str));
  3952. shp->unchecked_isa_dma = 1;
  3953. shp->irq = ha->irq;
  3954. shp->dma_channel = ha->drq;
  3955. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3956. NUMDATA(shp)->hanum = (ushort)hanum;
  3957. NUMDATA(shp)->busnum = b;
  3958. }
  3959. }
  3960. spin_lock_init(&ha->smp_lock);
  3961. gdth_enable_int(hanum);
  3962. #endif /* !__ia64__ */
  3963. }
  3964. }
  3965. /* scanning for EISA controllers */
  3966. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  3967. dma_addr_t scratch_dma_handle;
  3968. scratch_dma_handle = 0;
  3969. if (gdth_ctr_count >= MAXHA)
  3970. break;
  3971. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  3972. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3973. if (shp == NULL)
  3974. continue;
  3975. ha = HADATA(shp);
  3976. if (!gdth_init_eisa(eisa_slot,ha)) {
  3977. scsi_unregister(shp);
  3978. continue;
  3979. }
  3980. /* controller found and initialized */
  3981. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  3982. eisa_slot>>12,ha->irq);
  3983. if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
  3984. printk("GDT-EISA: Unable to allocate IRQ\n");
  3985. scsi_unregister(shp);
  3986. continue;
  3987. }
  3988. shp->unchecked_isa_dma = 0;
  3989. shp->irq = ha->irq;
  3990. shp->dma_channel = 0xff;
  3991. hanum = gdth_ctr_count;
  3992. gdth_ctr_tab[gdth_ctr_count++] = shp;
  3993. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3994. NUMDATA(shp)->hanum = (ushort)hanum;
  3995. NUMDATA(shp)->busnum= 0;
  3996. TRACE2(("EISA detect Bus 0: hanum %d\n",
  3997. NUMDATA(shp)->hanum));
  3998. ha->pccb = CMDDATA(shp);
  3999. ha->ccb_phys = 0L;
  4000. ha->pdev = NULL;
  4001. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4002. &scratch_dma_handle);
  4003. ha->scratch_phys = scratch_dma_handle;
  4004. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4005. &scratch_dma_handle);
  4006. ha->msg_phys = scratch_dma_handle;
  4007. #ifdef INT_COAL
  4008. ha->coal_stat = (gdth_coal_status *)
  4009. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4010. MAXOFFSETS, &scratch_dma_handle);
  4011. ha->coal_stat_phys = scratch_dma_handle;
  4012. #endif
  4013. ha->ccb_phys =
  4014. pci_map_single(ha->pdev,ha->pccb,
  4015. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4016. ha->scratch_busy = FALSE;
  4017. ha->req_first = NULL;
  4018. ha->tid_cnt = MAX_HDRIVES;
  4019. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4020. ha->tid_cnt = max_ids;
  4021. for (i=0; i<GDTH_MAXCMDS; ++i)
  4022. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4023. ha->scan_mode = rescan ? 0x10 : 0;
  4024. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4025. !gdth_search_drives(hanum)) {
  4026. printk("GDT-EISA: Error during device scan\n");
  4027. --gdth_ctr_count;
  4028. --gdth_ctr_vcount;
  4029. #ifdef INT_COAL
  4030. if (ha->coal_stat)
  4031. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4032. MAXOFFSETS, ha->coal_stat,
  4033. ha->coal_stat_phys);
  4034. #endif
  4035. if (ha->pscratch)
  4036. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4037. ha->pscratch, ha->scratch_phys);
  4038. if (ha->pmsg)
  4039. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4040. ha->pmsg, ha->msg_phys);
  4041. if (ha->ccb_phys)
  4042. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4043. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4044. free_irq(ha->irq,ha);
  4045. scsi_unregister(shp);
  4046. continue;
  4047. }
  4048. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4049. hdr_channel = ha->bus_cnt;
  4050. ha->virt_bus = hdr_channel;
  4051. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4052. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4053. shp->highmem_io = 0;
  4054. #endif
  4055. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4056. shp->max_cmd_len = 16;
  4057. shp->max_id = ha->tid_cnt;
  4058. shp->max_lun = MAXLUN;
  4059. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4060. if (virt_ctr) {
  4061. virt_ctr = 1;
  4062. /* register addit. SCSI channels as virtual controllers */
  4063. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4064. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4065. shp->unchecked_isa_dma = 0;
  4066. shp->irq = ha->irq;
  4067. shp->dma_channel = 0xff;
  4068. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4069. NUMDATA(shp)->hanum = (ushort)hanum;
  4070. NUMDATA(shp)->busnum = b;
  4071. }
  4072. }
  4073. spin_lock_init(&ha->smp_lock);
  4074. gdth_enable_int(hanum);
  4075. }
  4076. }
  4077. }
  4078. /* scanning for PCI controllers */
  4079. cnt = gdth_search_pci(pcistr);
  4080. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4081. gdth_sort_pci(pcistr,cnt);
  4082. for (ctr = 0; ctr < cnt; ++ctr) {
  4083. dma_addr_t scratch_dma_handle;
  4084. scratch_dma_handle = 0;
  4085. if (gdth_ctr_count >= MAXHA)
  4086. break;
  4087. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4088. if (shp == NULL)
  4089. continue;
  4090. ha = HADATA(shp);
  4091. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4092. scsi_unregister(shp);
  4093. continue;
  4094. }
  4095. /* controller found and initialized */
  4096. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4097. pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
  4098. if (request_irq(ha->irq, gdth_interrupt,
  4099. SA_INTERRUPT|SA_SHIRQ, "gdth", ha))
  4100. {
  4101. printk("GDT-PCI: Unable to allocate IRQ\n");
  4102. scsi_unregister(shp);
  4103. continue;
  4104. }
  4105. shp->unchecked_isa_dma = 0;
  4106. shp->irq = ha->irq;
  4107. shp->dma_channel = 0xff;
  4108. hanum = gdth_ctr_count;
  4109. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4110. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4111. NUMDATA(shp)->hanum = (ushort)hanum;
  4112. NUMDATA(shp)->busnum= 0;
  4113. ha->pccb = CMDDATA(shp);
  4114. ha->ccb_phys = 0L;
  4115. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4116. &scratch_dma_handle);
  4117. ha->scratch_phys = scratch_dma_handle;
  4118. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4119. &scratch_dma_handle);
  4120. ha->msg_phys = scratch_dma_handle;
  4121. #ifdef INT_COAL
  4122. ha->coal_stat = (gdth_coal_status *)
  4123. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4124. MAXOFFSETS, &scratch_dma_handle);
  4125. ha->coal_stat_phys = scratch_dma_handle;
  4126. #endif
  4127. ha->scratch_busy = FALSE;
  4128. ha->req_first = NULL;
  4129. ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
  4130. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4131. ha->tid_cnt = max_ids;
  4132. for (i=0; i<GDTH_MAXCMDS; ++i)
  4133. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4134. ha->scan_mode = rescan ? 0x10 : 0;
  4135. err = FALSE;
  4136. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4137. !gdth_search_drives(hanum)) {
  4138. err = TRUE;
  4139. } else {
  4140. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4141. hdr_channel = ha->bus_cnt;
  4142. ha->virt_bus = hdr_channel;
  4143. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4144. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4145. #endif
  4146. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4147. /* 64-bit DMA only supported from FW >= x.43 */
  4148. (!ha->dma64_support)) {
  4149. if (pci_set_dma_mask(pcistr[ctr].pdev, 0xffffffff)) {
  4150. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4151. err = TRUE;
  4152. }
  4153. } else {
  4154. shp->max_cmd_len = 16;
  4155. if (!pci_set_dma_mask(pcistr[ctr].pdev, 0xffffffffffffffffULL)) {
  4156. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4157. } else if (pci_set_dma_mask(pcistr[ctr].pdev, 0xffffffff)) {
  4158. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4159. err = TRUE;
  4160. }
  4161. }
  4162. }
  4163. if (err) {
  4164. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4165. --gdth_ctr_count;
  4166. --gdth_ctr_vcount;
  4167. #ifdef INT_COAL
  4168. if (ha->coal_stat)
  4169. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4170. MAXOFFSETS, ha->coal_stat,
  4171. ha->coal_stat_phys);
  4172. #endif
  4173. if (ha->pscratch)
  4174. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4175. ha->pscratch, ha->scratch_phys);
  4176. if (ha->pmsg)
  4177. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4178. ha->pmsg, ha->msg_phys);
  4179. free_irq(ha->irq,ha);
  4180. scsi_unregister(shp);
  4181. continue;
  4182. }
  4183. shp->max_id = ha->tid_cnt;
  4184. shp->max_lun = MAXLUN;
  4185. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4186. if (virt_ctr) {
  4187. virt_ctr = 1;
  4188. /* register addit. SCSI channels as virtual controllers */
  4189. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4190. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4191. shp->unchecked_isa_dma = 0;
  4192. shp->irq = ha->irq;
  4193. shp->dma_channel = 0xff;
  4194. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4195. NUMDATA(shp)->hanum = (ushort)hanum;
  4196. NUMDATA(shp)->busnum = b;
  4197. }
  4198. }
  4199. spin_lock_init(&ha->smp_lock);
  4200. gdth_enable_int(hanum);
  4201. }
  4202. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4203. if (gdth_ctr_count > 0) {
  4204. #ifdef GDTH_STATISTICS
  4205. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4206. init_timer(&gdth_timer);
  4207. gdth_timer.expires = jiffies + HZ;
  4208. gdth_timer.data = 0L;
  4209. gdth_timer.function = gdth_timeout;
  4210. add_timer(&gdth_timer);
  4211. #endif
  4212. major = register_chrdev(0,"gdth",&gdth_fops);
  4213. notifier_disabled = 0;
  4214. register_reboot_notifier(&gdth_notifier);
  4215. }
  4216. gdth_polling = FALSE;
  4217. return gdth_ctr_vcount;
  4218. }
  4219. static int gdth_release(struct Scsi_Host *shp)
  4220. {
  4221. int hanum;
  4222. gdth_ha_str *ha;
  4223. TRACE2(("gdth_release()\n"));
  4224. if (NUMDATA(shp)->busnum == 0) {
  4225. hanum = NUMDATA(shp)->hanum;
  4226. ha = HADATA(gdth_ctr_tab[hanum]);
  4227. if (ha->sdev) {
  4228. scsi_free_host_dev(ha->sdev);
  4229. ha->sdev = NULL;
  4230. }
  4231. gdth_flush(hanum);
  4232. if (shp->irq) {
  4233. free_irq(shp->irq,ha);
  4234. }
  4235. #ifndef __ia64__
  4236. if (shp->dma_channel != 0xff) {
  4237. free_dma(shp->dma_channel);
  4238. }
  4239. #endif
  4240. #ifdef INT_COAL
  4241. if (ha->coal_stat)
  4242. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4243. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4244. #endif
  4245. if (ha->pscratch)
  4246. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4247. ha->pscratch, ha->scratch_phys);
  4248. if (ha->pmsg)
  4249. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4250. ha->pmsg, ha->msg_phys);
  4251. if (ha->ccb_phys)
  4252. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4253. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4254. gdth_ctr_released++;
  4255. TRACE2(("gdth_release(): HA %d of %d\n",
  4256. gdth_ctr_released, gdth_ctr_count));
  4257. if (gdth_ctr_released == gdth_ctr_count) {
  4258. #ifdef GDTH_STATISTICS
  4259. del_timer(&gdth_timer);
  4260. #endif
  4261. unregister_chrdev(major,"gdth");
  4262. unregister_reboot_notifier(&gdth_notifier);
  4263. }
  4264. }
  4265. scsi_unregister(shp);
  4266. return 0;
  4267. }
  4268. static const char *gdth_ctr_name(int hanum)
  4269. {
  4270. gdth_ha_str *ha;
  4271. TRACE2(("gdth_ctr_name()\n"));
  4272. ha = HADATA(gdth_ctr_tab[hanum]);
  4273. if (ha->type == GDT_EISA) {
  4274. switch (ha->stype) {
  4275. case GDT3_ID:
  4276. return("GDT3000/3020");
  4277. case GDT3A_ID:
  4278. return("GDT3000A/3020A/3050A");
  4279. case GDT3B_ID:
  4280. return("GDT3000B/3010A");
  4281. }
  4282. } else if (ha->type == GDT_ISA) {
  4283. return("GDT2000/2020");
  4284. } else if (ha->type == GDT_PCI) {
  4285. switch (ha->stype) {
  4286. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4287. return("GDT6000/6020/6050");
  4288. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4289. return("GDT6000B/6010");
  4290. }
  4291. }
  4292. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4293. return("");
  4294. }
  4295. static const char *gdth_info(struct Scsi_Host *shp)
  4296. {
  4297. int hanum;
  4298. gdth_ha_str *ha;
  4299. TRACE2(("gdth_info()\n"));
  4300. hanum = NUMDATA(shp)->hanum;
  4301. ha = HADATA(gdth_ctr_tab[hanum]);
  4302. return ((const char *)ha->binfo.type_string);
  4303. }
  4304. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4305. {
  4306. int i, hanum;
  4307. gdth_ha_str *ha;
  4308. ulong flags;
  4309. Scsi_Cmnd *cmnd;
  4310. unchar b;
  4311. TRACE2(("gdth_eh_bus_reset()\n"));
  4312. hanum = NUMDATA(scp->device->host)->hanum;
  4313. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4314. ha = HADATA(gdth_ctr_tab[hanum]);
  4315. /* clear command tab */
  4316. spin_lock_irqsave(&ha->smp_lock, flags);
  4317. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4318. cmnd = ha->cmd_tab[i].cmnd;
  4319. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4320. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4321. }
  4322. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4323. if (b == ha->virt_bus) {
  4324. /* host drives */
  4325. for (i = 0; i < MAX_HDRIVES; ++i) {
  4326. if (ha->hdr[i].present) {
  4327. spin_lock_irqsave(&ha->smp_lock, flags);
  4328. gdth_polling = TRUE;
  4329. while (gdth_test_busy(hanum))
  4330. gdth_delay(0);
  4331. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4332. GDT_CLUST_RESET, i, 0, 0))
  4333. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4334. gdth_polling = FALSE;
  4335. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4336. }
  4337. }
  4338. } else {
  4339. /* raw devices */
  4340. spin_lock_irqsave(&ha->smp_lock, flags);
  4341. for (i = 0; i < MAXID; ++i)
  4342. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4343. gdth_polling = TRUE;
  4344. while (gdth_test_busy(hanum))
  4345. gdth_delay(0);
  4346. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4347. BUS_L2P(ha,b), 0, 0);
  4348. gdth_polling = FALSE;
  4349. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4350. }
  4351. return SUCCESS;
  4352. }
  4353. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4354. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4355. #else
  4356. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4357. #endif
  4358. {
  4359. unchar b, t;
  4360. int hanum;
  4361. gdth_ha_str *ha;
  4362. struct scsi_device *sd;
  4363. unsigned capacity;
  4364. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4365. sd = sdev;
  4366. capacity = cap;
  4367. #else
  4368. sd = disk->device;
  4369. capacity = disk->capacity;
  4370. #endif
  4371. hanum = NUMDATA(sd->host)->hanum;
  4372. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4373. t = sd->id;
  4374. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4375. ha = HADATA(gdth_ctr_tab[hanum]);
  4376. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4377. /* raw device or host drive without mapping information */
  4378. TRACE2(("Evaluate mapping\n"));
  4379. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4380. } else {
  4381. ip[0] = ha->hdr[t].heads;
  4382. ip[1] = ha->hdr[t].secs;
  4383. ip[2] = capacity / ip[0] / ip[1];
  4384. }
  4385. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4386. ip[0],ip[1],ip[2]));
  4387. return 0;
  4388. }
  4389. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
  4390. {
  4391. int hanum;
  4392. int priority;
  4393. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4394. scp->scsi_done = (void *)done;
  4395. scp->SCp.have_data_in = 1;
  4396. scp->SCp.phase = -1;
  4397. scp->SCp.sent_command = -1;
  4398. scp->SCp.Status = GDTH_MAP_NONE;
  4399. scp->SCp.buffer = (struct scatterlist *)NULL;
  4400. hanum = NUMDATA(scp->device->host)->hanum;
  4401. #ifdef GDTH_STATISTICS
  4402. ++act_ios;
  4403. #endif
  4404. priority = DEFAULT_PRI;
  4405. if (scp->done == gdth_scsi_done)
  4406. priority = scp->SCp.this_residual;
  4407. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4408. gdth_putq( hanum, scp, priority );
  4409. gdth_next( hanum );
  4410. return 0;
  4411. }
  4412. static int gdth_open(struct inode *inode, struct file *filep)
  4413. {
  4414. gdth_ha_str *ha;
  4415. int i;
  4416. for (i = 0; i < gdth_ctr_count; i++) {
  4417. ha = HADATA(gdth_ctr_tab[i]);
  4418. if (!ha->sdev)
  4419. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4420. }
  4421. TRACE(("gdth_open()\n"));
  4422. return 0;
  4423. }
  4424. static int gdth_close(struct inode *inode, struct file *filep)
  4425. {
  4426. TRACE(("gdth_close()\n"));
  4427. return 0;
  4428. }
  4429. static int ioc_event(void __user *arg)
  4430. {
  4431. gdth_ioctl_event evt;
  4432. gdth_ha_str *ha;
  4433. ulong flags;
  4434. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4435. evt.ionode >= gdth_ctr_count)
  4436. return -EFAULT;
  4437. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4438. if (evt.erase == 0xff) {
  4439. if (evt.event.event_source == ES_TEST)
  4440. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4441. else if (evt.event.event_source == ES_DRIVER)
  4442. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4443. else if (evt.event.event_source == ES_SYNC)
  4444. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4445. else
  4446. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4447. spin_lock_irqsave(&ha->smp_lock, flags);
  4448. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4449. &evt.event.event_data);
  4450. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4451. } else if (evt.erase == 0xfe) {
  4452. gdth_clear_events();
  4453. } else if (evt.erase == 0) {
  4454. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4455. } else {
  4456. gdth_readapp_event(ha, evt.erase, &evt.event);
  4457. }
  4458. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4459. return -EFAULT;
  4460. return 0;
  4461. }
  4462. static int ioc_lockdrv(void __user *arg)
  4463. {
  4464. gdth_ioctl_lockdrv ldrv;
  4465. unchar i, j;
  4466. ulong flags;
  4467. gdth_ha_str *ha;
  4468. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4469. ldrv.ionode >= gdth_ctr_count)
  4470. return -EFAULT;
  4471. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4472. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4473. j = ldrv.drives[i];
  4474. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4475. continue;
  4476. if (ldrv.lock) {
  4477. spin_lock_irqsave(&ha->smp_lock, flags);
  4478. ha->hdr[j].lock = 1;
  4479. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4480. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4481. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4482. } else {
  4483. spin_lock_irqsave(&ha->smp_lock, flags);
  4484. ha->hdr[j].lock = 0;
  4485. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4486. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4487. gdth_next(ldrv.ionode);
  4488. }
  4489. }
  4490. return 0;
  4491. }
  4492. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4493. {
  4494. gdth_ioctl_reset res;
  4495. gdth_cmd_str cmd;
  4496. int hanum;
  4497. gdth_ha_str *ha;
  4498. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4499. Scsi_Request *srp;
  4500. #else
  4501. Scsi_Cmnd *scp;
  4502. #endif
  4503. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4504. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4505. return -EFAULT;
  4506. hanum = res.ionode;
  4507. ha = HADATA(gdth_ctr_tab[hanum]);
  4508. if (!ha->hdr[res.number].present)
  4509. return 0;
  4510. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4511. cmd.Service = CACHESERVICE;
  4512. cmd.OpCode = GDT_CLUST_RESET;
  4513. if (ha->cache_feat & GDT_64BIT)
  4514. cmd.u.cache64.DeviceNo = res.number;
  4515. else
  4516. cmd.u.cache.DeviceNo = res.number;
  4517. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4518. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4519. if (!srp)
  4520. return -ENOMEM;
  4521. srp->sr_cmd_len = 12;
  4522. srp->sr_use_sg = 0;
  4523. gdth_do_req(srp, &cmd, cmnd, 30);
  4524. res.status = (ushort)srp->sr_command->SCp.Status;
  4525. scsi_release_request(srp);
  4526. #else
  4527. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4528. if (!scp)
  4529. return -ENOMEM;
  4530. scp->cmd_len = 12;
  4531. scp->use_sg = 0;
  4532. gdth_do_cmd(scp, &cmd, cmnd, 30);
  4533. res.status = (ushort)scp->SCp.Status;
  4534. scsi_release_command(scp);
  4535. #endif
  4536. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4537. return -EFAULT;
  4538. return 0;
  4539. }
  4540. static int ioc_general(void __user *arg, char *cmnd)
  4541. {
  4542. gdth_ioctl_general gen;
  4543. char *buf = NULL;
  4544. ulong64 paddr;
  4545. int hanum;
  4546. gdth_ha_str *ha;
  4547. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4548. Scsi_Request *srp;
  4549. #else
  4550. Scsi_Cmnd *scp;
  4551. #endif
  4552. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4553. gen.ionode >= gdth_ctr_count)
  4554. return -EFAULT;
  4555. hanum = gen.ionode;
  4556. ha = HADATA(gdth_ctr_tab[hanum]);
  4557. if (gen.data_len + gen.sense_len != 0) {
  4558. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4559. FALSE, &paddr)))
  4560. return -EFAULT;
  4561. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4562. gen.data_len + gen.sense_len)) {
  4563. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4564. return -EFAULT;
  4565. }
  4566. if (gen.command.OpCode == GDT_IOCTL) {
  4567. gen.command.u.ioctl.p_param = paddr;
  4568. } else if (gen.command.Service == CACHESERVICE) {
  4569. if (ha->cache_feat & GDT_64BIT) {
  4570. /* copy elements from 32-bit IOCTL structure */
  4571. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4572. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4573. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4574. /* addresses */
  4575. if (ha->cache_feat & SCATTER_GATHER) {
  4576. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4577. gen.command.u.cache64.sg_canz = 1;
  4578. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4579. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4580. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4581. } else {
  4582. gen.command.u.cache64.DestAddr = paddr;
  4583. gen.command.u.cache64.sg_canz = 0;
  4584. }
  4585. } else {
  4586. if (ha->cache_feat & SCATTER_GATHER) {
  4587. gen.command.u.cache.DestAddr = 0xffffffff;
  4588. gen.command.u.cache.sg_canz = 1;
  4589. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4590. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4591. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4592. } else {
  4593. gen.command.u.cache.DestAddr = paddr;
  4594. gen.command.u.cache.sg_canz = 0;
  4595. }
  4596. }
  4597. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4598. if (ha->raw_feat & GDT_64BIT) {
  4599. /* copy elements from 32-bit IOCTL structure */
  4600. char cmd[16];
  4601. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4602. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4603. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4604. gen.command.u.raw64.target = gen.command.u.raw.target;
  4605. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4606. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4607. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4608. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4609. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4610. /* addresses */
  4611. if (ha->raw_feat & SCATTER_GATHER) {
  4612. gen.command.u.raw64.sdata = (ulong64)-1;
  4613. gen.command.u.raw64.sg_ranz = 1;
  4614. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4615. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4616. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4617. } else {
  4618. gen.command.u.raw64.sdata = paddr;
  4619. gen.command.u.raw64.sg_ranz = 0;
  4620. }
  4621. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4622. } else {
  4623. if (ha->raw_feat & SCATTER_GATHER) {
  4624. gen.command.u.raw.sdata = 0xffffffff;
  4625. gen.command.u.raw.sg_ranz = 1;
  4626. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4627. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4628. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4629. } else {
  4630. gen.command.u.raw.sdata = paddr;
  4631. gen.command.u.raw.sg_ranz = 0;
  4632. }
  4633. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4634. }
  4635. } else {
  4636. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4637. return -EFAULT;
  4638. }
  4639. }
  4640. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4641. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4642. if (!srp)
  4643. return -ENOMEM;
  4644. srp->sr_cmd_len = 12;
  4645. srp->sr_use_sg = 0;
  4646. gdth_do_req(srp, &gen.command, cmnd, gen.timeout);
  4647. gen.status = srp->sr_command->SCp.Status;
  4648. gen.info = srp->sr_command->SCp.Message;
  4649. scsi_release_request(srp);
  4650. #else
  4651. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4652. if (!scp)
  4653. return -ENOMEM;
  4654. scp->cmd_len = 12;
  4655. scp->use_sg = 0;
  4656. gdth_do_cmd(scp, &gen.command, cmnd, gen.timeout);
  4657. gen.status = scp->SCp.Status;
  4658. gen.info = scp->SCp.Message;
  4659. scsi_release_command(scp);
  4660. #endif
  4661. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4662. gen.data_len + gen.sense_len)) {
  4663. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4664. return -EFAULT;
  4665. }
  4666. if (copy_to_user(arg, &gen,
  4667. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4668. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4669. return -EFAULT;
  4670. }
  4671. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4672. return 0;
  4673. }
  4674. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4675. {
  4676. gdth_ioctl_rescan *rsc;
  4677. gdth_cmd_str *cmd;
  4678. gdth_ha_str *ha;
  4679. unchar i;
  4680. int hanum, rc = -ENOMEM;
  4681. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4682. Scsi_Request *srp;
  4683. #else
  4684. Scsi_Cmnd *scp;
  4685. #endif
  4686. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4687. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4688. if (!rsc || !cmd)
  4689. goto free_fail;
  4690. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4691. rsc->ionode >= gdth_ctr_count) {
  4692. rc = -EFAULT;
  4693. goto free_fail;
  4694. }
  4695. hanum = rsc->ionode;
  4696. ha = HADATA(gdth_ctr_tab[hanum]);
  4697. memset(cmd, 0, sizeof(gdth_cmd_str));
  4698. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4699. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4700. if (!srp)
  4701. goto free_fail;
  4702. srp->sr_cmd_len = 12;
  4703. srp->sr_use_sg = 0;
  4704. #else
  4705. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4706. if (!scp)
  4707. goto free_fail;
  4708. scp->cmd_len = 12;
  4709. scp->use_sg = 0;
  4710. #endif
  4711. for (i = 0; i < MAX_HDRIVES; ++i) {
  4712. if (!ha->hdr[i].present) {
  4713. rsc->hdr_list[i].bus = 0xff;
  4714. continue;
  4715. }
  4716. rsc->hdr_list[i].bus = ha->virt_bus;
  4717. rsc->hdr_list[i].target = i;
  4718. rsc->hdr_list[i].lun = 0;
  4719. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4720. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4721. cmd->Service = CACHESERVICE;
  4722. cmd->OpCode = GDT_CLUST_INFO;
  4723. if (ha->cache_feat & GDT_64BIT)
  4724. cmd->u.cache64.DeviceNo = i;
  4725. else
  4726. cmd->u.cache.DeviceNo = i;
  4727. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4728. gdth_do_req(srp, cmd, cmnd, 30);
  4729. if (srp->sr_command->SCp.Status == S_OK)
  4730. rsc->hdr_list[i].cluster_type = srp->sr_command->SCp.Message;
  4731. #else
  4732. gdth_do_cmd(scp, cmd, cmnd, 30);
  4733. if (scp->SCp.Status == S_OK)
  4734. rsc->hdr_list[i].cluster_type = scp->SCp.Message;
  4735. #endif
  4736. }
  4737. }
  4738. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4739. scsi_release_request(srp);
  4740. #else
  4741. scsi_release_command(scp);
  4742. #endif
  4743. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4744. rc = -EFAULT;
  4745. else
  4746. rc = 0;
  4747. free_fail:
  4748. kfree(rsc);
  4749. kfree(cmd);
  4750. return rc;
  4751. }
  4752. static int ioc_rescan(void __user *arg, char *cmnd)
  4753. {
  4754. gdth_ioctl_rescan *rsc;
  4755. gdth_cmd_str *cmd;
  4756. ushort i, status, hdr_cnt;
  4757. ulong32 info;
  4758. int hanum, cyls, hds, secs;
  4759. int rc = -ENOMEM;
  4760. ulong flags;
  4761. gdth_ha_str *ha;
  4762. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4763. Scsi_Request *srp;
  4764. #else
  4765. Scsi_Cmnd *scp;
  4766. #endif
  4767. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4768. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4769. if (!cmd || !rsc)
  4770. goto free_fail;
  4771. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4772. rsc->ionode >= gdth_ctr_count) {
  4773. rc = -EFAULT;
  4774. goto free_fail;
  4775. }
  4776. hanum = rsc->ionode;
  4777. ha = HADATA(gdth_ctr_tab[hanum]);
  4778. memset(cmd, 0, sizeof(gdth_cmd_str));
  4779. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4780. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4781. if (!srp)
  4782. goto free_fail;
  4783. srp->sr_cmd_len = 12;
  4784. srp->sr_use_sg = 0;
  4785. #else
  4786. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4787. if (!scp)
  4788. goto free_fail;
  4789. scp->cmd_len = 12;
  4790. scp->use_sg = 0;
  4791. #endif
  4792. if (rsc->flag == 0) {
  4793. /* old method: re-init. cache service */
  4794. cmd->Service = CACHESERVICE;
  4795. if (ha->cache_feat & GDT_64BIT) {
  4796. cmd->OpCode = GDT_X_INIT_HOST;
  4797. cmd->u.cache64.DeviceNo = LINUX_OS;
  4798. } else {
  4799. cmd->OpCode = GDT_INIT;
  4800. cmd->u.cache.DeviceNo = LINUX_OS;
  4801. }
  4802. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4803. gdth_do_req(srp, cmd, cmnd, 30);
  4804. status = (ushort)srp->sr_command->SCp.Status;
  4805. info = (ulong32)srp->sr_command->SCp.Message;
  4806. #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
  4807. gdth_do_cmd(scp, cmd, cmnd, 30);
  4808. status = (ushort)scp->SCp.Status;
  4809. info = (ulong32)scp->SCp.Message;
  4810. #else
  4811. gdth_do_cmd(&scp, cmd, cmnd, 30);
  4812. status = (ushort)scp.SCp.Status;
  4813. info = (ulong32)scp.SCp.Message;
  4814. #endif
  4815. i = 0;
  4816. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4817. } else {
  4818. i = rsc->hdr_no;
  4819. hdr_cnt = i + 1;
  4820. }
  4821. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4822. cmd->Service = CACHESERVICE;
  4823. cmd->OpCode = GDT_INFO;
  4824. if (ha->cache_feat & GDT_64BIT)
  4825. cmd->u.cache64.DeviceNo = i;
  4826. else
  4827. cmd->u.cache.DeviceNo = i;
  4828. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4829. gdth_do_req(srp, cmd, cmnd, 30);
  4830. status = (ushort)srp->sr_command->SCp.Status;
  4831. info = (ulong32)srp->sr_command->SCp.Message;
  4832. #else
  4833. gdth_do_cmd(scp, cmd, cmnd, 30);
  4834. status = (ushort)scp->SCp.Status;
  4835. info = (ulong32)scp->SCp.Message;
  4836. #endif
  4837. spin_lock_irqsave(&ha->smp_lock, flags);
  4838. rsc->hdr_list[i].bus = ha->virt_bus;
  4839. rsc->hdr_list[i].target = i;
  4840. rsc->hdr_list[i].lun = 0;
  4841. if (status != S_OK) {
  4842. ha->hdr[i].present = FALSE;
  4843. } else {
  4844. ha->hdr[i].present = TRUE;
  4845. ha->hdr[i].size = info;
  4846. /* evaluate mapping */
  4847. ha->hdr[i].size &= ~SECS32;
  4848. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4849. ha->hdr[i].heads = hds;
  4850. ha->hdr[i].secs = secs;
  4851. /* round size */
  4852. ha->hdr[i].size = cyls * hds * secs;
  4853. }
  4854. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4855. if (status != S_OK)
  4856. continue;
  4857. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4858. /* but we need ha->info2, not yet stored in scp->SCp */
  4859. /* devtype, cluster info, R/W attribs */
  4860. cmd->Service = CACHESERVICE;
  4861. cmd->OpCode = GDT_DEVTYPE;
  4862. if (ha->cache_feat & GDT_64BIT)
  4863. cmd->u.cache64.DeviceNo = i;
  4864. else
  4865. cmd->u.cache.DeviceNo = i;
  4866. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4867. gdth_do_req(srp, cmd, cmnd, 30);
  4868. status = (ushort)srp->sr_command->SCp.Status;
  4869. info = (ulong32)srp->sr_command->SCp.Message;
  4870. #else
  4871. gdth_do_cmd(scp, cmd, cmnd, 30);
  4872. status = (ushort)scp->SCp.Status;
  4873. info = (ulong32)scp->SCp.Message;
  4874. #endif
  4875. spin_lock_irqsave(&ha->smp_lock, flags);
  4876. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4877. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4878. cmd->Service = CACHESERVICE;
  4879. cmd->OpCode = GDT_CLUST_INFO;
  4880. if (ha->cache_feat & GDT_64BIT)
  4881. cmd->u.cache64.DeviceNo = i;
  4882. else
  4883. cmd->u.cache.DeviceNo = i;
  4884. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4885. gdth_do_req(srp, cmd, cmnd, 30);
  4886. status = (ushort)srp->sr_command->SCp.Status;
  4887. info = (ulong32)srp->sr_command->SCp.Message;
  4888. #else
  4889. gdth_do_cmd(scp, cmd, cmnd, 30);
  4890. status = (ushort)scp->SCp.Status;
  4891. info = (ulong32)scp->SCp.Message;
  4892. #endif
  4893. spin_lock_irqsave(&ha->smp_lock, flags);
  4894. ha->hdr[i].cluster_type =
  4895. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4896. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4897. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4898. cmd->Service = CACHESERVICE;
  4899. cmd->OpCode = GDT_RW_ATTRIBS;
  4900. if (ha->cache_feat & GDT_64BIT)
  4901. cmd->u.cache64.DeviceNo = i;
  4902. else
  4903. cmd->u.cache.DeviceNo = i;
  4904. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4905. gdth_do_req(srp, cmd, cmnd, 30);
  4906. status = (ushort)srp->sr_command->SCp.Status;
  4907. info = (ulong32)srp->sr_command->SCp.Message;
  4908. #else
  4909. gdth_do_cmd(scp, cmd, cmnd, 30);
  4910. status = (ushort)scp->SCp.Status;
  4911. info = (ulong32)scp->SCp.Message;
  4912. #endif
  4913. spin_lock_irqsave(&ha->smp_lock, flags);
  4914. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4915. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4916. }
  4917. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4918. scsi_release_request(srp);
  4919. #else
  4920. scsi_release_command(scp);
  4921. #endif
  4922. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4923. rc = -EFAULT;
  4924. else
  4925. rc = 0;
  4926. free_fail:
  4927. kfree(rsc);
  4928. kfree(cmd);
  4929. return rc;
  4930. }
  4931. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4932. unsigned int cmd, unsigned long arg)
  4933. {
  4934. gdth_ha_str *ha;
  4935. Scsi_Cmnd *scp;
  4936. ulong flags;
  4937. char cmnd[MAX_COMMAND_SIZE];
  4938. void __user *argp = (void __user *)arg;
  4939. memset(cmnd, 0xff, 12);
  4940. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4941. switch (cmd) {
  4942. case GDTIOCTL_CTRCNT:
  4943. {
  4944. int cnt = gdth_ctr_count;
  4945. if (put_user(cnt, (int __user *)argp))
  4946. return -EFAULT;
  4947. break;
  4948. }
  4949. case GDTIOCTL_DRVERS:
  4950. {
  4951. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4952. if (put_user(ver, (int __user *)argp))
  4953. return -EFAULT;
  4954. break;
  4955. }
  4956. case GDTIOCTL_OSVERS:
  4957. {
  4958. gdth_ioctl_osvers osv;
  4959. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4960. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4961. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4962. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4963. return -EFAULT;
  4964. break;
  4965. }
  4966. case GDTIOCTL_CTRTYPE:
  4967. {
  4968. gdth_ioctl_ctrtype ctrt;
  4969. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4970. ctrt.ionode >= gdth_ctr_count)
  4971. return -EFAULT;
  4972. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4973. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4974. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4975. } else {
  4976. if (ha->type != GDT_PCIMPR) {
  4977. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4978. } else {
  4979. ctrt.type =
  4980. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4981. if (ha->stype >= 0x300)
  4982. ctrt.ext_type = 0x6000 | ha->subdevice_id;
  4983. else
  4984. ctrt.ext_type = 0x6000 | ha->stype;
  4985. }
  4986. ctrt.device_id = ha->stype;
  4987. ctrt.sub_device_id = ha->subdevice_id;
  4988. }
  4989. ctrt.info = ha->brd_phys;
  4990. ctrt.oem_id = ha->oem_id;
  4991. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4992. return -EFAULT;
  4993. break;
  4994. }
  4995. case GDTIOCTL_GENERAL:
  4996. return ioc_general(argp, cmnd);
  4997. case GDTIOCTL_EVENT:
  4998. return ioc_event(argp);
  4999. case GDTIOCTL_LOCKDRV:
  5000. return ioc_lockdrv(argp);
  5001. case GDTIOCTL_LOCKCHN:
  5002. {
  5003. gdth_ioctl_lockchn lchn;
  5004. unchar i, j;
  5005. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  5006. lchn.ionode >= gdth_ctr_count)
  5007. return -EFAULT;
  5008. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  5009. i = lchn.channel;
  5010. if (i < ha->bus_cnt) {
  5011. if (lchn.lock) {
  5012. spin_lock_irqsave(&ha->smp_lock, flags);
  5013. ha->raw[i].lock = 1;
  5014. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5015. for (j = 0; j < ha->tid_cnt; ++j) {
  5016. gdth_wait_completion(lchn.ionode, i, j);
  5017. gdth_stop_timeout(lchn.ionode, i, j);
  5018. }
  5019. } else {
  5020. spin_lock_irqsave(&ha->smp_lock, flags);
  5021. ha->raw[i].lock = 0;
  5022. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5023. for (j = 0; j < ha->tid_cnt; ++j) {
  5024. gdth_start_timeout(lchn.ionode, i, j);
  5025. gdth_next(lchn.ionode);
  5026. }
  5027. }
  5028. }
  5029. break;
  5030. }
  5031. case GDTIOCTL_RESCAN:
  5032. return ioc_rescan(argp, cmnd);
  5033. case GDTIOCTL_HDRLIST:
  5034. return ioc_hdrlist(argp, cmnd);
  5035. case GDTIOCTL_RESET_BUS:
  5036. {
  5037. gdth_ioctl_reset res;
  5038. int hanum, rval;
  5039. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  5040. res.ionode >= gdth_ctr_count)
  5041. return -EFAULT;
  5042. hanum = res.ionode;
  5043. ha = HADATA(gdth_ctr_tab[hanum]);
  5044. /* Because we need a Scsi_Cmnd struct., we make a scsi_allocate device also for kernels >=2.6.x */
  5045. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5046. scp = scsi_get_command(ha->sdev, GFP_KERNEL);
  5047. if (!scp)
  5048. return -ENOMEM;
  5049. scp->cmd_len = 12;
  5050. scp->use_sg = 0;
  5051. scp->device->channel = virt_ctr ? 0 : res.number;
  5052. rval = gdth_eh_bus_reset(scp);
  5053. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5054. scsi_put_command(scp);
  5055. #else
  5056. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  5057. if (!scp)
  5058. return -ENOMEM;
  5059. scp->cmd_len = 12;
  5060. scp->use_sg = 0;
  5061. scp->channel = virt_ctr ? 0 : res.number;
  5062. rval = gdth_eh_bus_reset(scp);
  5063. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5064. scsi_release_command(scp);
  5065. #endif
  5066. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  5067. return -EFAULT;
  5068. break;
  5069. }
  5070. case GDTIOCTL_RESET_DRV:
  5071. return ioc_resetdrv(argp, cmnd);
  5072. default:
  5073. break;
  5074. }
  5075. return 0;
  5076. }
  5077. /* flush routine */
  5078. static void gdth_flush(int hanum)
  5079. {
  5080. int i;
  5081. gdth_ha_str *ha;
  5082. gdth_cmd_str gdtcmd;
  5083. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5084. Scsi_Request *srp;
  5085. #else
  5086. Scsi_Cmnd *scp;
  5087. #endif
  5088. struct scsi_device *sdev;
  5089. char cmnd[MAX_COMMAND_SIZE];
  5090. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5091. TRACE2(("gdth_flush() hanum %d\n",hanum));
  5092. ha = HADATA(gdth_ctr_tab[hanum]);
  5093. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5094. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5095. srp = scsi_allocate_request(sdev, GFP_KERNEL);
  5096. if (!srp)
  5097. return;
  5098. srp->sr_cmd_len = 12;
  5099. srp->sr_use_sg = 0;
  5100. #else
  5101. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5102. scp = scsi_allocate_device(sdev, 1, FALSE);
  5103. if (!scp)
  5104. return;
  5105. scp->cmd_len = 12;
  5106. scp->use_sg = 0;
  5107. #endif
  5108. for (i = 0; i < MAX_HDRIVES; ++i) {
  5109. if (ha->hdr[i].present) {
  5110. gdtcmd.BoardNode = LOCALBOARD;
  5111. gdtcmd.Service = CACHESERVICE;
  5112. gdtcmd.OpCode = GDT_FLUSH;
  5113. if (ha->cache_feat & GDT_64BIT) {
  5114. gdtcmd.u.cache64.DeviceNo = i;
  5115. gdtcmd.u.cache64.BlockNo = 1;
  5116. gdtcmd.u.cache64.sg_canz = 0;
  5117. } else {
  5118. gdtcmd.u.cache.DeviceNo = i;
  5119. gdtcmd.u.cache.BlockNo = 1;
  5120. gdtcmd.u.cache.sg_canz = 0;
  5121. }
  5122. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  5123. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5124. gdth_do_req(srp, &gdtcmd, cmnd, 30);
  5125. #else
  5126. gdth_do_cmd(scp, &gdtcmd, cmnd, 30);
  5127. #endif
  5128. }
  5129. }
  5130. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5131. scsi_release_request(srp);
  5132. scsi_free_host_dev(sdev);
  5133. #else
  5134. scsi_release_command(scp);
  5135. scsi_free_host_dev(sdev);
  5136. #endif
  5137. }
  5138. /* shutdown routine */
  5139. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  5140. {
  5141. int hanum;
  5142. #ifndef __alpha__
  5143. gdth_cmd_str gdtcmd;
  5144. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5145. Scsi_Request *srp;
  5146. struct scsi_device *sdev;
  5147. #else
  5148. Scsi_Cmnd *scp;
  5149. struct scsi_device *sdev;
  5150. #endif
  5151. char cmnd[MAX_COMMAND_SIZE];
  5152. #endif
  5153. if (notifier_disabled)
  5154. return NOTIFY_OK;
  5155. TRACE2(("gdth_halt() event %d\n",(int)event));
  5156. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5157. return NOTIFY_DONE;
  5158. notifier_disabled = 1;
  5159. printk("GDT-HA: Flushing all host drives .. ");
  5160. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5161. gdth_flush(hanum);
  5162. #ifndef __alpha__
  5163. /* controller reset */
  5164. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5165. gdtcmd.BoardNode = LOCALBOARD;
  5166. gdtcmd.Service = CACHESERVICE;
  5167. gdtcmd.OpCode = GDT_RESET;
  5168. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5169. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5170. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5171. srp = scsi_allocate_request(sdev, GFP_KERNEL);
  5172. if (!srp) {
  5173. unregister_reboot_notifier(&gdth_notifier);
  5174. return NOTIFY_OK;
  5175. }
  5176. srp->sr_cmd_len = 12;
  5177. srp->sr_use_sg = 0;
  5178. gdth_do_req(srp, &gdtcmd, cmnd, 10);
  5179. scsi_release_request(srp);
  5180. scsi_free_host_dev(sdev);
  5181. #else
  5182. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5183. scp = scsi_allocate_device(sdev, 1, FALSE);
  5184. if (!scp) {
  5185. unregister_reboot_notifier(&gdth_notifier);
  5186. return NOTIFY_OK;
  5187. }
  5188. scp->cmd_len = 12;
  5189. scp->use_sg = 0;
  5190. gdth_do_cmd(scp, &gdtcmd, cmnd, 10);
  5191. scsi_release_command(scp);
  5192. scsi_free_host_dev(sdev);
  5193. #endif
  5194. #endif
  5195. }
  5196. printk("Done.\n");
  5197. #ifdef GDTH_STATISTICS
  5198. del_timer(&gdth_timer);
  5199. #endif
  5200. return NOTIFY_OK;
  5201. }
  5202. static struct scsi_host_template driver_template = {
  5203. .proc_name = "gdth",
  5204. .proc_info = gdth_proc_info,
  5205. .name = "GDT SCSI Disk Array Controller",
  5206. .detect = gdth_detect,
  5207. .release = gdth_release,
  5208. .info = gdth_info,
  5209. .queuecommand = gdth_queuecommand,
  5210. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5211. .bios_param = gdth_bios_param,
  5212. .can_queue = GDTH_MAXCMDS,
  5213. .this_id = -1,
  5214. .sg_tablesize = GDTH_MAXSG,
  5215. .cmd_per_lun = GDTH_MAXC_P_L,
  5216. .unchecked_isa_dma = 1,
  5217. .use_clustering = ENABLE_CLUSTERING,
  5218. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5219. .use_new_eh_code = 1,
  5220. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5221. .highmem_io = 1,
  5222. #endif
  5223. #endif
  5224. };
  5225. #include "scsi_module.c"
  5226. #ifndef MODULE
  5227. __setup("gdth=", option_setup);
  5228. #endif