dmatest.c 21 KB

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  1. /*
  2. * DMA Engine test module
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/freezer.h>
  14. #include <linux/init.h>
  15. #include <linux/kthread.h>
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/random.h>
  19. #include <linux/slab.h>
  20. #include <linux/wait.h>
  21. static unsigned int test_buf_size = 16384;
  22. module_param(test_buf_size, uint, S_IRUGO);
  23. MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  24. static char test_channel[20];
  25. module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
  26. MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
  27. static char test_device[20];
  28. module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
  29. MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  30. static unsigned int threads_per_chan = 1;
  31. module_param(threads_per_chan, uint, S_IRUGO);
  32. MODULE_PARM_DESC(threads_per_chan,
  33. "Number of threads to start per channel (default: 1)");
  34. static unsigned int max_channels;
  35. module_param(max_channels, uint, S_IRUGO);
  36. MODULE_PARM_DESC(max_channels,
  37. "Maximum number of channels to use (default: all)");
  38. static unsigned int iterations;
  39. module_param(iterations, uint, S_IRUGO);
  40. MODULE_PARM_DESC(iterations,
  41. "Iterations before stopping test (default: infinite)");
  42. static unsigned int xor_sources = 3;
  43. module_param(xor_sources, uint, S_IRUGO);
  44. MODULE_PARM_DESC(xor_sources,
  45. "Number of xor source buffers (default: 3)");
  46. static unsigned int pq_sources = 3;
  47. module_param(pq_sources, uint, S_IRUGO);
  48. MODULE_PARM_DESC(pq_sources,
  49. "Number of p+q source buffers (default: 3)");
  50. static int timeout = 3000;
  51. module_param(timeout, uint, S_IRUGO);
  52. MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  53. "Pass -1 for infinite timeout");
  54. /*
  55. * Initialization patterns. All bytes in the source buffer has bit 7
  56. * set, all bytes in the destination buffer has bit 7 cleared.
  57. *
  58. * Bit 6 is set for all bytes which are to be copied by the DMA
  59. * engine. Bit 5 is set for all bytes which are to be overwritten by
  60. * the DMA engine.
  61. *
  62. * The remaining bits are the inverse of a counter which increments by
  63. * one for each byte address.
  64. */
  65. #define PATTERN_SRC 0x80
  66. #define PATTERN_DST 0x00
  67. #define PATTERN_COPY 0x40
  68. #define PATTERN_OVERWRITE 0x20
  69. #define PATTERN_COUNT_MASK 0x1f
  70. struct dmatest_info;
  71. struct dmatest_thread {
  72. struct list_head node;
  73. struct dmatest_info *info;
  74. struct task_struct *task;
  75. struct dma_chan *chan;
  76. u8 **srcs;
  77. u8 **dsts;
  78. enum dma_transaction_type type;
  79. };
  80. struct dmatest_chan {
  81. struct list_head node;
  82. struct dma_chan *chan;
  83. struct list_head threads;
  84. };
  85. /**
  86. * struct dmatest_info - test information.
  87. * @buf_size: size of the memcpy test buffer
  88. * @channel: bus ID of the channel to test
  89. * @device: bus ID of the DMA Engine to test
  90. * @threads_per_chan: number of threads to start per channel
  91. * @max_channels: maximum number of channels to use
  92. * @iterations: iterations before stopping test
  93. * @xor_sources: number of xor source buffers
  94. * @pq_sources: number of p+q source buffers
  95. * @timeout: transfer timeout in msec, -1 for infinite timeout
  96. */
  97. struct dmatest_info {
  98. unsigned int buf_size;
  99. char channel[20];
  100. char device[20];
  101. unsigned int threads_per_chan;
  102. unsigned int max_channels;
  103. unsigned int iterations;
  104. unsigned int xor_sources;
  105. unsigned int pq_sources;
  106. int timeout;
  107. };
  108. static struct dmatest_info test_info;
  109. /*
  110. * These are protected by dma_list_mutex since they're only used by
  111. * the DMA filter function callback
  112. */
  113. static LIST_HEAD(dmatest_channels);
  114. static unsigned int nr_channels;
  115. static bool dmatest_match_channel(struct dmatest_info *info,
  116. struct dma_chan *chan)
  117. {
  118. if (info->channel[0] == '\0')
  119. return true;
  120. return strcmp(dma_chan_name(chan), info->channel) == 0;
  121. }
  122. static bool dmatest_match_device(struct dmatest_info *info,
  123. struct dma_device *device)
  124. {
  125. if (info->device[0] == '\0')
  126. return true;
  127. return strcmp(dev_name(device->dev), info->device) == 0;
  128. }
  129. static unsigned long dmatest_random(void)
  130. {
  131. unsigned long buf;
  132. get_random_bytes(&buf, sizeof(buf));
  133. return buf;
  134. }
  135. static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
  136. unsigned int buf_size)
  137. {
  138. unsigned int i;
  139. u8 *buf;
  140. for (; (buf = *bufs); bufs++) {
  141. for (i = 0; i < start; i++)
  142. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  143. for ( ; i < start + len; i++)
  144. buf[i] = PATTERN_SRC | PATTERN_COPY
  145. | (~i & PATTERN_COUNT_MASK);
  146. for ( ; i < buf_size; i++)
  147. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  148. buf++;
  149. }
  150. }
  151. static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
  152. unsigned int buf_size)
  153. {
  154. unsigned int i;
  155. u8 *buf;
  156. for (; (buf = *bufs); bufs++) {
  157. for (i = 0; i < start; i++)
  158. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  159. for ( ; i < start + len; i++)
  160. buf[i] = PATTERN_DST | PATTERN_OVERWRITE
  161. | (~i & PATTERN_COUNT_MASK);
  162. for ( ; i < buf_size; i++)
  163. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  164. }
  165. }
  166. static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
  167. unsigned int counter, bool is_srcbuf)
  168. {
  169. u8 diff = actual ^ pattern;
  170. u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
  171. const char *thread_name = current->comm;
  172. if (is_srcbuf)
  173. pr_warning("%s: srcbuf[0x%x] overwritten!"
  174. " Expected %02x, got %02x\n",
  175. thread_name, index, expected, actual);
  176. else if ((pattern & PATTERN_COPY)
  177. && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
  178. pr_warning("%s: dstbuf[0x%x] not copied!"
  179. " Expected %02x, got %02x\n",
  180. thread_name, index, expected, actual);
  181. else if (diff & PATTERN_SRC)
  182. pr_warning("%s: dstbuf[0x%x] was copied!"
  183. " Expected %02x, got %02x\n",
  184. thread_name, index, expected, actual);
  185. else
  186. pr_warning("%s: dstbuf[0x%x] mismatch!"
  187. " Expected %02x, got %02x\n",
  188. thread_name, index, expected, actual);
  189. }
  190. static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
  191. unsigned int end, unsigned int counter, u8 pattern,
  192. bool is_srcbuf)
  193. {
  194. unsigned int i;
  195. unsigned int error_count = 0;
  196. u8 actual;
  197. u8 expected;
  198. u8 *buf;
  199. unsigned int counter_orig = counter;
  200. for (; (buf = *bufs); bufs++) {
  201. counter = counter_orig;
  202. for (i = start; i < end; i++) {
  203. actual = buf[i];
  204. expected = pattern | (~counter & PATTERN_COUNT_MASK);
  205. if (actual != expected) {
  206. if (error_count < 32)
  207. dmatest_mismatch(actual, pattern, i,
  208. counter, is_srcbuf);
  209. error_count++;
  210. }
  211. counter++;
  212. }
  213. }
  214. if (error_count > 32)
  215. pr_warning("%s: %u errors suppressed\n",
  216. current->comm, error_count - 32);
  217. return error_count;
  218. }
  219. /* poor man's completion - we want to use wait_event_freezable() on it */
  220. struct dmatest_done {
  221. bool done;
  222. wait_queue_head_t *wait;
  223. };
  224. static void dmatest_callback(void *arg)
  225. {
  226. struct dmatest_done *done = arg;
  227. done->done = true;
  228. wake_up_all(done->wait);
  229. }
  230. static inline void unmap_src(struct device *dev, dma_addr_t *addr, size_t len,
  231. unsigned int count)
  232. {
  233. while (count--)
  234. dma_unmap_single(dev, addr[count], len, DMA_TO_DEVICE);
  235. }
  236. static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
  237. unsigned int count)
  238. {
  239. while (count--)
  240. dma_unmap_single(dev, addr[count], len, DMA_BIDIRECTIONAL);
  241. }
  242. static unsigned int min_odd(unsigned int x, unsigned int y)
  243. {
  244. unsigned int val = min(x, y);
  245. return val % 2 ? val : val - 1;
  246. }
  247. /*
  248. * This function repeatedly tests DMA transfers of various lengths and
  249. * offsets for a given operation type until it is told to exit by
  250. * kthread_stop(). There may be multiple threads running this function
  251. * in parallel for a single channel, and there may be multiple channels
  252. * being tested in parallel.
  253. *
  254. * Before each test, the source and destination buffer is initialized
  255. * with a known pattern. This pattern is different depending on
  256. * whether it's in an area which is supposed to be copied or
  257. * overwritten, and different in the source and destination buffers.
  258. * So if the DMA engine doesn't copy exactly what we tell it to copy,
  259. * we'll notice.
  260. */
  261. static int dmatest_func(void *data)
  262. {
  263. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
  264. struct dmatest_thread *thread = data;
  265. struct dmatest_done done = { .wait = &done_wait };
  266. struct dmatest_info *info;
  267. struct dma_chan *chan;
  268. struct dma_device *dev;
  269. const char *thread_name;
  270. unsigned int src_off, dst_off, len;
  271. unsigned int error_count;
  272. unsigned int failed_tests = 0;
  273. unsigned int total_tests = 0;
  274. dma_cookie_t cookie;
  275. enum dma_status status;
  276. enum dma_ctrl_flags flags;
  277. u8 *pq_coefs = NULL;
  278. int ret;
  279. int src_cnt;
  280. int dst_cnt;
  281. int i;
  282. thread_name = current->comm;
  283. set_freezable();
  284. ret = -ENOMEM;
  285. smp_rmb();
  286. info = thread->info;
  287. chan = thread->chan;
  288. dev = chan->device;
  289. if (thread->type == DMA_MEMCPY)
  290. src_cnt = dst_cnt = 1;
  291. else if (thread->type == DMA_XOR) {
  292. /* force odd to ensure dst = src */
  293. src_cnt = min_odd(info->xor_sources | 1, dev->max_xor);
  294. dst_cnt = 1;
  295. } else if (thread->type == DMA_PQ) {
  296. /* force odd to ensure dst = src */
  297. src_cnt = min_odd(info->pq_sources | 1, dma_maxpq(dev, 0));
  298. dst_cnt = 2;
  299. pq_coefs = kmalloc(info->pq_sources+1, GFP_KERNEL);
  300. if (!pq_coefs)
  301. goto err_thread_type;
  302. for (i = 0; i < src_cnt; i++)
  303. pq_coefs[i] = 1;
  304. } else
  305. goto err_thread_type;
  306. thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
  307. if (!thread->srcs)
  308. goto err_srcs;
  309. for (i = 0; i < src_cnt; i++) {
  310. thread->srcs[i] = kmalloc(info->buf_size, GFP_KERNEL);
  311. if (!thread->srcs[i])
  312. goto err_srcbuf;
  313. }
  314. thread->srcs[i] = NULL;
  315. thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
  316. if (!thread->dsts)
  317. goto err_dsts;
  318. for (i = 0; i < dst_cnt; i++) {
  319. thread->dsts[i] = kmalloc(info->buf_size, GFP_KERNEL);
  320. if (!thread->dsts[i])
  321. goto err_dstbuf;
  322. }
  323. thread->dsts[i] = NULL;
  324. set_user_nice(current, 10);
  325. /*
  326. * src buffers are freed by the DMAEngine code with dma_unmap_single()
  327. * dst buffers are freed by ourselves below
  328. */
  329. flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
  330. | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
  331. while (!kthread_should_stop()
  332. && !(info->iterations && total_tests >= info->iterations)) {
  333. struct dma_async_tx_descriptor *tx = NULL;
  334. dma_addr_t dma_srcs[src_cnt];
  335. dma_addr_t dma_dsts[dst_cnt];
  336. u8 align = 0;
  337. total_tests++;
  338. /* honor alignment restrictions */
  339. if (thread->type == DMA_MEMCPY)
  340. align = dev->copy_align;
  341. else if (thread->type == DMA_XOR)
  342. align = dev->xor_align;
  343. else if (thread->type == DMA_PQ)
  344. align = dev->pq_align;
  345. if (1 << align > info->buf_size) {
  346. pr_err("%u-byte buffer too small for %d-byte alignment\n",
  347. info->buf_size, 1 << align);
  348. break;
  349. }
  350. len = dmatest_random() % info->buf_size + 1;
  351. len = (len >> align) << align;
  352. if (!len)
  353. len = 1 << align;
  354. src_off = dmatest_random() % (info->buf_size - len + 1);
  355. dst_off = dmatest_random() % (info->buf_size - len + 1);
  356. src_off = (src_off >> align) << align;
  357. dst_off = (dst_off >> align) << align;
  358. dmatest_init_srcs(thread->srcs, src_off, len, info->buf_size);
  359. dmatest_init_dsts(thread->dsts, dst_off, len, info->buf_size);
  360. for (i = 0; i < src_cnt; i++) {
  361. u8 *buf = thread->srcs[i] + src_off;
  362. dma_srcs[i] = dma_map_single(dev->dev, buf, len,
  363. DMA_TO_DEVICE);
  364. ret = dma_mapping_error(dev->dev, dma_srcs[i]);
  365. if (ret) {
  366. unmap_src(dev->dev, dma_srcs, len, i);
  367. pr_warn("%s: #%u: mapping error %d with "
  368. "src_off=0x%x len=0x%x\n",
  369. thread_name, total_tests - 1, ret,
  370. src_off, len);
  371. failed_tests++;
  372. continue;
  373. }
  374. }
  375. /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
  376. for (i = 0; i < dst_cnt; i++) {
  377. dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
  378. info->buf_size,
  379. DMA_BIDIRECTIONAL);
  380. ret = dma_mapping_error(dev->dev, dma_dsts[i]);
  381. if (ret) {
  382. unmap_src(dev->dev, dma_srcs, len, src_cnt);
  383. unmap_dst(dev->dev, dma_dsts, info->buf_size, i);
  384. pr_warn("%s: #%u: mapping error %d with "
  385. "dst_off=0x%x len=0x%x\n",
  386. thread_name, total_tests - 1, ret,
  387. dst_off, info->buf_size);
  388. failed_tests++;
  389. continue;
  390. }
  391. }
  392. if (thread->type == DMA_MEMCPY)
  393. tx = dev->device_prep_dma_memcpy(chan,
  394. dma_dsts[0] + dst_off,
  395. dma_srcs[0], len,
  396. flags);
  397. else if (thread->type == DMA_XOR)
  398. tx = dev->device_prep_dma_xor(chan,
  399. dma_dsts[0] + dst_off,
  400. dma_srcs, src_cnt,
  401. len, flags);
  402. else if (thread->type == DMA_PQ) {
  403. dma_addr_t dma_pq[dst_cnt];
  404. for (i = 0; i < dst_cnt; i++)
  405. dma_pq[i] = dma_dsts[i] + dst_off;
  406. tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
  407. src_cnt, pq_coefs,
  408. len, flags);
  409. }
  410. if (!tx) {
  411. unmap_src(dev->dev, dma_srcs, len, src_cnt);
  412. unmap_dst(dev->dev, dma_dsts, info->buf_size, dst_cnt);
  413. pr_warning("%s: #%u: prep error with src_off=0x%x "
  414. "dst_off=0x%x len=0x%x\n",
  415. thread_name, total_tests - 1,
  416. src_off, dst_off, len);
  417. msleep(100);
  418. failed_tests++;
  419. continue;
  420. }
  421. done.done = false;
  422. tx->callback = dmatest_callback;
  423. tx->callback_param = &done;
  424. cookie = tx->tx_submit(tx);
  425. if (dma_submit_error(cookie)) {
  426. pr_warning("%s: #%u: submit error %d with src_off=0x%x "
  427. "dst_off=0x%x len=0x%x\n",
  428. thread_name, total_tests - 1, cookie,
  429. src_off, dst_off, len);
  430. msleep(100);
  431. failed_tests++;
  432. continue;
  433. }
  434. dma_async_issue_pending(chan);
  435. wait_event_freezable_timeout(done_wait,
  436. done.done || kthread_should_stop(),
  437. msecs_to_jiffies(info->timeout));
  438. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  439. if (!done.done) {
  440. /*
  441. * We're leaving the timed out dma operation with
  442. * dangling pointer to done_wait. To make this
  443. * correct, we'll need to allocate wait_done for
  444. * each test iteration and perform "who's gonna
  445. * free it this time?" dancing. For now, just
  446. * leave it dangling.
  447. */
  448. pr_warning("%s: #%u: test timed out\n",
  449. thread_name, total_tests - 1);
  450. failed_tests++;
  451. continue;
  452. } else if (status != DMA_SUCCESS) {
  453. pr_warning("%s: #%u: got completion callback,"
  454. " but status is \'%s\'\n",
  455. thread_name, total_tests - 1,
  456. status == DMA_ERROR ? "error" : "in progress");
  457. failed_tests++;
  458. continue;
  459. }
  460. /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
  461. unmap_dst(dev->dev, dma_dsts, info->buf_size, dst_cnt);
  462. error_count = 0;
  463. pr_debug("%s: verifying source buffer...\n", thread_name);
  464. error_count += dmatest_verify(thread->srcs, 0, src_off,
  465. 0, PATTERN_SRC, true);
  466. error_count += dmatest_verify(thread->srcs, src_off,
  467. src_off + len, src_off,
  468. PATTERN_SRC | PATTERN_COPY, true);
  469. error_count += dmatest_verify(thread->srcs, src_off + len,
  470. info->buf_size, src_off + len,
  471. PATTERN_SRC, true);
  472. pr_debug("%s: verifying dest buffer...\n",
  473. thread->task->comm);
  474. error_count += dmatest_verify(thread->dsts, 0, dst_off,
  475. 0, PATTERN_DST, false);
  476. error_count += dmatest_verify(thread->dsts, dst_off,
  477. dst_off + len, src_off,
  478. PATTERN_SRC | PATTERN_COPY, false);
  479. error_count += dmatest_verify(thread->dsts, dst_off + len,
  480. info->buf_size, dst_off + len,
  481. PATTERN_DST, false);
  482. if (error_count) {
  483. pr_warning("%s: #%u: %u errors with "
  484. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  485. thread_name, total_tests - 1, error_count,
  486. src_off, dst_off, len);
  487. failed_tests++;
  488. } else {
  489. pr_debug("%s: #%u: No errors with "
  490. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  491. thread_name, total_tests - 1,
  492. src_off, dst_off, len);
  493. }
  494. }
  495. ret = 0;
  496. for (i = 0; thread->dsts[i]; i++)
  497. kfree(thread->dsts[i]);
  498. err_dstbuf:
  499. kfree(thread->dsts);
  500. err_dsts:
  501. for (i = 0; thread->srcs[i]; i++)
  502. kfree(thread->srcs[i]);
  503. err_srcbuf:
  504. kfree(thread->srcs);
  505. err_srcs:
  506. kfree(pq_coefs);
  507. err_thread_type:
  508. pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
  509. thread_name, total_tests, failed_tests, ret);
  510. /* terminate all transfers on specified channels */
  511. if (ret)
  512. dmaengine_terminate_all(chan);
  513. if (info->iterations > 0)
  514. while (!kthread_should_stop()) {
  515. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
  516. interruptible_sleep_on(&wait_dmatest_exit);
  517. }
  518. return ret;
  519. }
  520. static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
  521. {
  522. struct dmatest_thread *thread;
  523. struct dmatest_thread *_thread;
  524. int ret;
  525. list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
  526. ret = kthread_stop(thread->task);
  527. pr_debug("dmatest: thread %s exited with status %d\n",
  528. thread->task->comm, ret);
  529. list_del(&thread->node);
  530. kfree(thread);
  531. }
  532. /* terminate all transfers on specified channels */
  533. dmaengine_terminate_all(dtc->chan);
  534. kfree(dtc);
  535. }
  536. static int dmatest_add_threads(struct dmatest_info *info,
  537. struct dmatest_chan *dtc, enum dma_transaction_type type)
  538. {
  539. struct dmatest_thread *thread;
  540. struct dma_chan *chan = dtc->chan;
  541. char *op;
  542. unsigned int i;
  543. if (type == DMA_MEMCPY)
  544. op = "copy";
  545. else if (type == DMA_XOR)
  546. op = "xor";
  547. else if (type == DMA_PQ)
  548. op = "pq";
  549. else
  550. return -EINVAL;
  551. for (i = 0; i < info->threads_per_chan; i++) {
  552. thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
  553. if (!thread) {
  554. pr_warning("dmatest: No memory for %s-%s%u\n",
  555. dma_chan_name(chan), op, i);
  556. break;
  557. }
  558. thread->info = info;
  559. thread->chan = dtc->chan;
  560. thread->type = type;
  561. smp_wmb();
  562. thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
  563. dma_chan_name(chan), op, i);
  564. if (IS_ERR(thread->task)) {
  565. pr_warning("dmatest: Failed to run thread %s-%s%u\n",
  566. dma_chan_name(chan), op, i);
  567. kfree(thread);
  568. break;
  569. }
  570. /* srcbuf and dstbuf are allocated by the thread itself */
  571. list_add_tail(&thread->node, &dtc->threads);
  572. }
  573. return i;
  574. }
  575. static int dmatest_add_channel(struct dmatest_info *info,
  576. struct dma_chan *chan)
  577. {
  578. struct dmatest_chan *dtc;
  579. struct dma_device *dma_dev = chan->device;
  580. unsigned int thread_count = 0;
  581. int cnt;
  582. dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
  583. if (!dtc) {
  584. pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
  585. return -ENOMEM;
  586. }
  587. dtc->chan = chan;
  588. INIT_LIST_HEAD(&dtc->threads);
  589. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  590. cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
  591. thread_count += cnt > 0 ? cnt : 0;
  592. }
  593. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  594. cnt = dmatest_add_threads(info, dtc, DMA_XOR);
  595. thread_count += cnt > 0 ? cnt : 0;
  596. }
  597. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  598. cnt = dmatest_add_threads(info, dtc, DMA_PQ);
  599. thread_count += cnt > 0 ? cnt : 0;
  600. }
  601. pr_info("dmatest: Started %u threads using %s\n",
  602. thread_count, dma_chan_name(chan));
  603. list_add_tail(&dtc->node, &dmatest_channels);
  604. nr_channels++;
  605. return 0;
  606. }
  607. static bool filter(struct dma_chan *chan, void *param)
  608. {
  609. struct dmatest_info *info = param;
  610. if (!dmatest_match_channel(info, chan) ||
  611. !dmatest_match_device(info, chan->device))
  612. return false;
  613. else
  614. return true;
  615. }
  616. static int run_threaded_test(struct dmatest_info *info)
  617. {
  618. dma_cap_mask_t mask;
  619. struct dma_chan *chan;
  620. int err = 0;
  621. dma_cap_zero(mask);
  622. dma_cap_set(DMA_MEMCPY, mask);
  623. for (;;) {
  624. chan = dma_request_channel(mask, filter, info);
  625. if (chan) {
  626. err = dmatest_add_channel(info, chan);
  627. if (err) {
  628. dma_release_channel(chan);
  629. break; /* add_channel failed, punt */
  630. }
  631. } else
  632. break; /* no more channels available */
  633. if (info->max_channels && nr_channels >= info->max_channels)
  634. break; /* we have all we need */
  635. }
  636. return err;
  637. }
  638. static void stop_threaded_test(struct dmatest_info *info)
  639. {
  640. struct dmatest_chan *dtc, *_dtc;
  641. struct dma_chan *chan;
  642. list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) {
  643. list_del(&dtc->node);
  644. chan = dtc->chan;
  645. dmatest_cleanup_channel(dtc);
  646. pr_debug("dmatest: dropped channel %s\n",
  647. dma_chan_name(chan));
  648. dma_release_channel(chan);
  649. }
  650. }
  651. static int __init dmatest_init(void)
  652. {
  653. struct dmatest_info *info = &test_info;
  654. memset(info, 0, sizeof(*info));
  655. info->buf_size = test_buf_size;
  656. strlcpy(info->channel, test_channel, sizeof(info->channel));
  657. strlcpy(info->device, test_device, sizeof(info->device));
  658. info->threads_per_chan = threads_per_chan;
  659. info->max_channels = max_channels;
  660. info->iterations = iterations;
  661. info->xor_sources = xor_sources;
  662. info->pq_sources = pq_sources;
  663. info->timeout = timeout;
  664. return run_threaded_test(info);
  665. }
  666. /* when compiled-in wait for drivers to load first */
  667. late_initcall(dmatest_init);
  668. static void __exit dmatest_exit(void)
  669. {
  670. struct dmatest_info *info = &test_info;
  671. stop_threaded_test(info);
  672. }
  673. module_exit(dmatest_exit);
  674. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  675. MODULE_LICENSE("GPL v2");