iwl-4965.c 104 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-dev.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. #include "iwl-calib.h"
  45. /* module parameters */
  46. static struct iwl_mod_params iwl4965_mod_params = {
  47. .num_of_queues = IWL49_NUM_QUEUES,
  48. .enable_qos = 1,
  49. .amsdu_size_8K = 1,
  50. .restart_fw = 1,
  51. /* the rest are 0 by default */
  52. };
  53. #ifdef CONFIG_IWL4965_HT
  54. static const u16 default_tid_to_tx_fifo[] = {
  55. IWL_TX_FIFO_AC1,
  56. IWL_TX_FIFO_AC0,
  57. IWL_TX_FIFO_AC0,
  58. IWL_TX_FIFO_AC1,
  59. IWL_TX_FIFO_AC2,
  60. IWL_TX_FIFO_AC2,
  61. IWL_TX_FIFO_AC3,
  62. IWL_TX_FIFO_AC3,
  63. IWL_TX_FIFO_NONE,
  64. IWL_TX_FIFO_NONE,
  65. IWL_TX_FIFO_NONE,
  66. IWL_TX_FIFO_NONE,
  67. IWL_TX_FIFO_NONE,
  68. IWL_TX_FIFO_NONE,
  69. IWL_TX_FIFO_NONE,
  70. IWL_TX_FIFO_NONE,
  71. IWL_TX_FIFO_AC3
  72. };
  73. #endif /*CONFIG_IWL4965_HT */
  74. /* check contents of special bootstrap uCode SRAM */
  75. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  76. {
  77. __le32 *image = priv->ucode_boot.v_addr;
  78. u32 len = priv->ucode_boot.len;
  79. u32 reg;
  80. u32 val;
  81. IWL_DEBUG_INFO("Begin verify bsm\n");
  82. /* verify BSM SRAM contents */
  83. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  84. for (reg = BSM_SRAM_LOWER_BOUND;
  85. reg < BSM_SRAM_LOWER_BOUND + len;
  86. reg += sizeof(u32), image++) {
  87. val = iwl_read_prph(priv, reg);
  88. if (val != le32_to_cpu(*image)) {
  89. IWL_ERROR("BSM uCode verification failed at "
  90. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  91. BSM_SRAM_LOWER_BOUND,
  92. reg - BSM_SRAM_LOWER_BOUND, len,
  93. val, le32_to_cpu(*image));
  94. return -EIO;
  95. }
  96. }
  97. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  98. return 0;
  99. }
  100. /**
  101. * iwl4965_load_bsm - Load bootstrap instructions
  102. *
  103. * BSM operation:
  104. *
  105. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  106. * in special SRAM that does not power down during RFKILL. When powering back
  107. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  108. * the bootstrap program into the on-board processor, and starts it.
  109. *
  110. * The bootstrap program loads (via DMA) instructions and data for a new
  111. * program from host DRAM locations indicated by the host driver in the
  112. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  113. * automatically.
  114. *
  115. * When initializing the NIC, the host driver points the BSM to the
  116. * "initialize" uCode image. This uCode sets up some internal data, then
  117. * notifies host via "initialize alive" that it is complete.
  118. *
  119. * The host then replaces the BSM_DRAM_* pointer values to point to the
  120. * normal runtime uCode instructions and a backup uCode data cache buffer
  121. * (filled initially with starting data values for the on-board processor),
  122. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  123. * which begins normal operation.
  124. *
  125. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  126. * the backup data cache in DRAM before SRAM is powered down.
  127. *
  128. * When powering back up, the BSM loads the bootstrap program. This reloads
  129. * the runtime uCode instructions and the backup data cache into SRAM,
  130. * and re-launches the runtime uCode from where it left off.
  131. */
  132. static int iwl4965_load_bsm(struct iwl_priv *priv)
  133. {
  134. __le32 *image = priv->ucode_boot.v_addr;
  135. u32 len = priv->ucode_boot.len;
  136. dma_addr_t pinst;
  137. dma_addr_t pdata;
  138. u32 inst_len;
  139. u32 data_len;
  140. int i;
  141. u32 done;
  142. u32 reg_offset;
  143. int ret;
  144. IWL_DEBUG_INFO("Begin load bsm\n");
  145. /* make sure bootstrap program is no larger than BSM's SRAM size */
  146. if (len > IWL_MAX_BSM_SIZE)
  147. return -EINVAL;
  148. /* Tell bootstrap uCode where to find the "Initialize" uCode
  149. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  150. * NOTE: iwl4965_initialize_alive_start() will replace these values,
  151. * after the "initialize" uCode has run, to point to
  152. * runtime/protocol instructions and backup data cache. */
  153. pinst = priv->ucode_init.p_addr >> 4;
  154. pdata = priv->ucode_init_data.p_addr >> 4;
  155. inst_len = priv->ucode_init.len;
  156. data_len = priv->ucode_init_data.len;
  157. ret = iwl_grab_nic_access(priv);
  158. if (ret)
  159. return ret;
  160. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  161. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  162. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  163. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  164. /* Fill BSM memory with bootstrap instructions */
  165. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  166. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  167. reg_offset += sizeof(u32), image++)
  168. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  169. ret = iwl4965_verify_bsm(priv);
  170. if (ret) {
  171. iwl_release_nic_access(priv);
  172. return ret;
  173. }
  174. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  175. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  176. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  177. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  178. /* Load bootstrap code into instruction SRAM now,
  179. * to prepare to load "initialize" uCode */
  180. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  181. /* Wait for load of bootstrap uCode to finish */
  182. for (i = 0; i < 100; i++) {
  183. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  184. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  185. break;
  186. udelay(10);
  187. }
  188. if (i < 100)
  189. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  190. else {
  191. IWL_ERROR("BSM write did not complete!\n");
  192. return -EIO;
  193. }
  194. /* Enable future boot loads whenever power management unit triggers it
  195. * (e.g. when powering back up after power-save shutdown) */
  196. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  197. iwl_release_nic_access(priv);
  198. return 0;
  199. }
  200. /**
  201. * iwl4965_set_ucode_ptrs - Set uCode address location
  202. *
  203. * Tell initialization uCode where to find runtime uCode.
  204. *
  205. * BSM registers initially contain pointers to initialization uCode.
  206. * We need to replace them to load runtime uCode inst and data,
  207. * and to save runtime data when powering down.
  208. */
  209. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  210. {
  211. dma_addr_t pinst;
  212. dma_addr_t pdata;
  213. unsigned long flags;
  214. int ret = 0;
  215. /* bits 35:4 for 4965 */
  216. pinst = priv->ucode_code.p_addr >> 4;
  217. pdata = priv->ucode_data_backup.p_addr >> 4;
  218. spin_lock_irqsave(&priv->lock, flags);
  219. ret = iwl_grab_nic_access(priv);
  220. if (ret) {
  221. spin_unlock_irqrestore(&priv->lock, flags);
  222. return ret;
  223. }
  224. /* Tell bootstrap uCode where to find image to load */
  225. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  226. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  227. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  228. priv->ucode_data.len);
  229. /* Inst bytecount must be last to set up, bit 31 signals uCode
  230. * that all new ptr/size info is in place */
  231. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  232. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  233. iwl_release_nic_access(priv);
  234. spin_unlock_irqrestore(&priv->lock, flags);
  235. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  236. return ret;
  237. }
  238. /**
  239. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  240. *
  241. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  242. *
  243. * The 4965 "initialize" ALIVE reply contains calibration data for:
  244. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  245. * (3945 does not contain this data).
  246. *
  247. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  248. */
  249. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  250. {
  251. /* Check alive response for "valid" sign from uCode */
  252. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  253. /* We had an error bringing up the hardware, so take it
  254. * all the way back down so we can try again */
  255. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  256. goto restart;
  257. }
  258. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  259. * This is a paranoid check, because we would not have gotten the
  260. * "initialize" alive if code weren't properly loaded. */
  261. if (iwl_verify_ucode(priv)) {
  262. /* Runtime instruction load was bad;
  263. * take it all the way back down so we can try again */
  264. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  265. goto restart;
  266. }
  267. /* Calculate temperature */
  268. priv->temperature = iwl4965_get_temperature(priv);
  269. /* Send pointers to protocol/runtime uCode image ... init code will
  270. * load and launch runtime uCode, which will send us another "Alive"
  271. * notification. */
  272. IWL_DEBUG_INFO("Initialization Alive received.\n");
  273. if (iwl4965_set_ucode_ptrs(priv)) {
  274. /* Runtime instruction load won't happen;
  275. * take it all the way back down so we can try again */
  276. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  277. goto restart;
  278. }
  279. return;
  280. restart:
  281. queue_work(priv->workqueue, &priv->restart);
  282. }
  283. static int is_fat_channel(__le32 rxon_flags)
  284. {
  285. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  286. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  287. }
  288. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  289. {
  290. int idx = 0;
  291. /* 4965 HT rate format */
  292. if (rate_n_flags & RATE_MCS_HT_MSK) {
  293. idx = (rate_n_flags & 0xff);
  294. if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  295. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  296. idx += IWL_FIRST_OFDM_RATE;
  297. /* skip 9M not supported in ht*/
  298. if (idx >= IWL_RATE_9M_INDEX)
  299. idx += 1;
  300. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  301. return idx;
  302. /* 4965 legacy rate format, search for match in table */
  303. } else {
  304. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  305. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  306. return idx;
  307. }
  308. return -1;
  309. }
  310. /**
  311. * translate ucode response to mac80211 tx status control values
  312. */
  313. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  314. struct ieee80211_tx_info *control)
  315. {
  316. int rate_index;
  317. control->antenna_sel_tx =
  318. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  319. if (rate_n_flags & RATE_MCS_HT_MSK)
  320. control->flags |= IEEE80211_TX_CTL_OFDM_HT;
  321. if (rate_n_flags & RATE_MCS_GF_MSK)
  322. control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
  323. if (rate_n_flags & RATE_MCS_FAT_MSK)
  324. control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
  325. if (rate_n_flags & RATE_MCS_DUP_MSK)
  326. control->flags |= IEEE80211_TX_CTL_DUP_DATA;
  327. if (rate_n_flags & RATE_MCS_SGI_MSK)
  328. control->flags |= IEEE80211_TX_CTL_SHORT_GI;
  329. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  330. if (control->band == IEEE80211_BAND_5GHZ)
  331. rate_index -= IWL_FIRST_OFDM_RATE;
  332. control->tx_rate_idx = rate_index;
  333. }
  334. int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
  335. {
  336. int rc;
  337. unsigned long flags;
  338. spin_lock_irqsave(&priv->lock, flags);
  339. rc = iwl_grab_nic_access(priv);
  340. if (rc) {
  341. spin_unlock_irqrestore(&priv->lock, flags);
  342. return rc;
  343. }
  344. /* stop Rx DMA */
  345. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  346. rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  347. (1 << 24), 1000);
  348. if (rc < 0)
  349. IWL_ERROR("Can't stop Rx DMA.\n");
  350. iwl_release_nic_access(priv);
  351. spin_unlock_irqrestore(&priv->lock, flags);
  352. return 0;
  353. }
  354. /*
  355. * EEPROM handlers
  356. */
  357. static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
  358. {
  359. u16 eeprom_ver;
  360. u16 calib_ver;
  361. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  362. calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  363. if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
  364. calib_ver < EEPROM_4965_TX_POWER_VERSION)
  365. goto err;
  366. return 0;
  367. err:
  368. IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
  369. eeprom_ver, EEPROM_4965_EEPROM_VERSION,
  370. calib_ver, EEPROM_4965_TX_POWER_VERSION);
  371. return -EINVAL;
  372. }
  373. int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  374. {
  375. int ret;
  376. unsigned long flags;
  377. spin_lock_irqsave(&priv->lock, flags);
  378. ret = iwl_grab_nic_access(priv);
  379. if (ret) {
  380. spin_unlock_irqrestore(&priv->lock, flags);
  381. return ret;
  382. }
  383. if (src == IWL_PWR_SRC_VAUX) {
  384. u32 val;
  385. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  386. &val);
  387. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  388. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  389. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  390. ~APMG_PS_CTRL_MSK_PWR_SRC);
  391. }
  392. } else {
  393. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  394. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  395. ~APMG_PS_CTRL_MSK_PWR_SRC);
  396. }
  397. iwl_release_nic_access(priv);
  398. spin_unlock_irqrestore(&priv->lock, flags);
  399. return ret;
  400. }
  401. static int iwl4965_disable_tx_fifo(struct iwl_priv *priv)
  402. {
  403. unsigned long flags;
  404. int ret;
  405. spin_lock_irqsave(&priv->lock, flags);
  406. ret = iwl_grab_nic_access(priv);
  407. if (unlikely(ret)) {
  408. IWL_ERROR("Tx fifo reset failed");
  409. spin_unlock_irqrestore(&priv->lock, flags);
  410. return ret;
  411. }
  412. iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
  413. iwl_release_nic_access(priv);
  414. spin_unlock_irqrestore(&priv->lock, flags);
  415. return 0;
  416. }
  417. static int iwl4965_apm_init(struct iwl_priv *priv)
  418. {
  419. int ret = 0;
  420. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  421. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  422. /* set "initialization complete" bit to move adapter
  423. * D0U* --> D0A* state */
  424. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  425. /* wait for clock stabilization */
  426. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  427. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  428. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  429. if (ret < 0) {
  430. IWL_DEBUG_INFO("Failed to init the card\n");
  431. goto out;
  432. }
  433. ret = iwl_grab_nic_access(priv);
  434. if (ret)
  435. goto out;
  436. /* enable DMA */
  437. iwl_write_prph(priv, APMG_CLK_CTRL_REG,
  438. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  439. udelay(20);
  440. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  441. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  442. iwl_release_nic_access(priv);
  443. out:
  444. return ret;
  445. }
  446. static void iwl4965_nic_config(struct iwl_priv *priv)
  447. {
  448. unsigned long flags;
  449. u32 val;
  450. u16 radio_cfg;
  451. u8 val_link;
  452. spin_lock_irqsave(&priv->lock, flags);
  453. if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
  454. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  455. /* Enable No Snoop field */
  456. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  457. val & ~(1 << 11));
  458. }
  459. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  460. /* disable L1 entry -- workaround for pre-B1 */
  461. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  462. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  463. /* write radio config values to register */
  464. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  465. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  466. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  467. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  468. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  469. /* set CSR_HW_CONFIG_REG for uCode use */
  470. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  471. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  472. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  473. priv->calib_info = (struct iwl_eeprom_calib_info *)
  474. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  475. spin_unlock_irqrestore(&priv->lock, flags);
  476. }
  477. int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
  478. {
  479. int rc = 0;
  480. u32 reg_val;
  481. unsigned long flags;
  482. spin_lock_irqsave(&priv->lock, flags);
  483. /* set stop master bit */
  484. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  485. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  486. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  487. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  488. IWL_DEBUG_INFO("Card in power save, master is already "
  489. "stopped\n");
  490. else {
  491. rc = iwl_poll_bit(priv, CSR_RESET,
  492. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  493. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  494. if (rc < 0) {
  495. spin_unlock_irqrestore(&priv->lock, flags);
  496. return rc;
  497. }
  498. }
  499. spin_unlock_irqrestore(&priv->lock, flags);
  500. IWL_DEBUG_INFO("stop master\n");
  501. return rc;
  502. }
  503. /**
  504. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  505. */
  506. void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
  507. {
  508. int txq_id;
  509. unsigned long flags;
  510. /* Stop each Tx DMA channel, and wait for it to be idle */
  511. for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
  512. spin_lock_irqsave(&priv->lock, flags);
  513. if (iwl_grab_nic_access(priv)) {
  514. spin_unlock_irqrestore(&priv->lock, flags);
  515. continue;
  516. }
  517. iwl_write_direct32(priv,
  518. FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
  519. iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
  520. FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  521. (txq_id), 200);
  522. iwl_release_nic_access(priv);
  523. spin_unlock_irqrestore(&priv->lock, flags);
  524. }
  525. /* Deallocate memory for all Tx queues */
  526. iwl_hw_txq_ctx_free(priv);
  527. }
  528. int iwl4965_hw_nic_reset(struct iwl_priv *priv)
  529. {
  530. int rc = 0;
  531. unsigned long flags;
  532. iwl4965_hw_nic_stop_master(priv);
  533. spin_lock_irqsave(&priv->lock, flags);
  534. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  535. udelay(10);
  536. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  537. rc = iwl_poll_bit(priv, CSR_RESET,
  538. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  539. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  540. udelay(10);
  541. rc = iwl_grab_nic_access(priv);
  542. if (!rc) {
  543. iwl_write_prph(priv, APMG_CLK_EN_REG,
  544. APMG_CLK_VAL_DMA_CLK_RQT |
  545. APMG_CLK_VAL_BSM_CLK_RQT);
  546. udelay(10);
  547. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  548. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  549. iwl_release_nic_access(priv);
  550. }
  551. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  552. wake_up_interruptible(&priv->wait_command_queue);
  553. spin_unlock_irqrestore(&priv->lock, flags);
  554. return rc;
  555. }
  556. #define REG_RECALIB_PERIOD (60)
  557. /**
  558. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  559. *
  560. * This callback is provided in order to send a statistics request.
  561. *
  562. * This timer function is continually reset to execute within
  563. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  564. * was received. We need to ensure we receive the statistics in order
  565. * to update the temperature used for calibrating the TXPOWER.
  566. */
  567. static void iwl4965_bg_statistics_periodic(unsigned long data)
  568. {
  569. struct iwl_priv *priv = (struct iwl_priv *)data;
  570. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  571. return;
  572. iwl_send_statistics_request(priv, CMD_ASYNC);
  573. }
  574. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  575. {
  576. struct iwl4965_ct_kill_config cmd;
  577. unsigned long flags;
  578. int ret = 0;
  579. spin_lock_irqsave(&priv->lock, flags);
  580. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  581. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  582. spin_unlock_irqrestore(&priv->lock, flags);
  583. cmd.critical_temperature_R =
  584. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  585. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  586. sizeof(cmd), &cmd);
  587. if (ret)
  588. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  589. else
  590. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
  591. "critical temperature is %d\n",
  592. cmd.critical_temperature_R);
  593. }
  594. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  595. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  596. * Called after every association, but this runs only once!
  597. * ... once chain noise is calibrated the first time, it's good forever. */
  598. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  599. {
  600. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  601. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  602. struct iwl4965_calibration_cmd cmd;
  603. memset(&cmd, 0, sizeof(cmd));
  604. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  605. cmd.diff_gain_a = 0;
  606. cmd.diff_gain_b = 0;
  607. cmd.diff_gain_c = 0;
  608. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  609. sizeof(cmd), &cmd))
  610. IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
  611. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  612. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  613. }
  614. }
  615. static void iwl4965_gain_computation(struct iwl_priv *priv,
  616. u32 *average_noise,
  617. u16 min_average_noise_antenna_i,
  618. u32 min_average_noise)
  619. {
  620. int i, ret;
  621. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  622. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  623. for (i = 0; i < NUM_RX_CHAINS; i++) {
  624. s32 delta_g = 0;
  625. if (!(data->disconn_array[i]) &&
  626. (data->delta_gain_code[i] ==
  627. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  628. delta_g = average_noise[i] - min_average_noise;
  629. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  630. data->delta_gain_code[i] =
  631. min(data->delta_gain_code[i],
  632. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  633. data->delta_gain_code[i] =
  634. (data->delta_gain_code[i] | (1 << 2));
  635. } else {
  636. data->delta_gain_code[i] = 0;
  637. }
  638. }
  639. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  640. data->delta_gain_code[0],
  641. data->delta_gain_code[1],
  642. data->delta_gain_code[2]);
  643. /* Differential gain gets sent to uCode only once */
  644. if (!data->radio_write) {
  645. struct iwl4965_calibration_cmd cmd;
  646. data->radio_write = 1;
  647. memset(&cmd, 0, sizeof(cmd));
  648. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  649. cmd.diff_gain_a = data->delta_gain_code[0];
  650. cmd.diff_gain_b = data->delta_gain_code[1];
  651. cmd.diff_gain_c = data->delta_gain_code[2];
  652. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  653. sizeof(cmd), &cmd);
  654. if (ret)
  655. IWL_DEBUG_CALIB("fail sending cmd "
  656. "REPLY_PHY_CALIBRATION_CMD \n");
  657. /* TODO we might want recalculate
  658. * rx_chain in rxon cmd */
  659. /* Mark so we run this algo only once! */
  660. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  661. }
  662. data->chain_noise_a = 0;
  663. data->chain_noise_b = 0;
  664. data->chain_noise_c = 0;
  665. data->chain_signal_a = 0;
  666. data->chain_signal_b = 0;
  667. data->chain_signal_c = 0;
  668. data->beacon_count = 0;
  669. }
  670. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  671. {
  672. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  673. sensitivity_work);
  674. mutex_lock(&priv->mutex);
  675. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  676. test_bit(STATUS_SCANNING, &priv->status)) {
  677. mutex_unlock(&priv->mutex);
  678. return;
  679. }
  680. if (priv->start_calib) {
  681. iwl_chain_noise_calibration(priv, &priv->statistics);
  682. iwl_sensitivity_calibration(priv, &priv->statistics);
  683. }
  684. mutex_unlock(&priv->mutex);
  685. return;
  686. }
  687. #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
  688. static void iwl4965_bg_txpower_work(struct work_struct *work)
  689. {
  690. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  691. txpower_work);
  692. /* If a scan happened to start before we got here
  693. * then just return; the statistics notification will
  694. * kick off another scheduled work to compensate for
  695. * any temperature delta we missed here. */
  696. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  697. test_bit(STATUS_SCANNING, &priv->status))
  698. return;
  699. mutex_lock(&priv->mutex);
  700. /* Regardless of if we are assocaited, we must reconfigure the
  701. * TX power since frames can be sent on non-radar channels while
  702. * not associated */
  703. iwl4965_hw_reg_send_txpower(priv);
  704. /* Update last_temperature to keep is_calib_needed from running
  705. * when it isn't needed... */
  706. priv->last_temperature = priv->temperature;
  707. mutex_unlock(&priv->mutex);
  708. }
  709. /*
  710. * Acquire priv->lock before calling this function !
  711. */
  712. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  713. {
  714. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  715. (index & 0xff) | (txq_id << 8));
  716. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  717. }
  718. /**
  719. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  720. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  721. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  722. *
  723. * NOTE: Acquire priv->lock before calling this function !
  724. */
  725. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  726. struct iwl_tx_queue *txq,
  727. int tx_fifo_id, int scd_retry)
  728. {
  729. int txq_id = txq->q.id;
  730. /* Find out whether to activate Tx queue */
  731. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  732. /* Set up and activate */
  733. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  734. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  735. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  736. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  737. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  738. IWL49_SCD_QUEUE_STTS_REG_MSK);
  739. txq->sched_retry = scd_retry;
  740. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  741. active ? "Activate" : "Deactivate",
  742. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  743. }
  744. static const u16 default_queue_to_tx_fifo[] = {
  745. IWL_TX_FIFO_AC3,
  746. IWL_TX_FIFO_AC2,
  747. IWL_TX_FIFO_AC1,
  748. IWL_TX_FIFO_AC0,
  749. IWL49_CMD_FIFO_NUM,
  750. IWL_TX_FIFO_HCCA_1,
  751. IWL_TX_FIFO_HCCA_2
  752. };
  753. int iwl4965_alive_notify(struct iwl_priv *priv)
  754. {
  755. u32 a;
  756. int i = 0;
  757. unsigned long flags;
  758. int ret;
  759. spin_lock_irqsave(&priv->lock, flags);
  760. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  761. memset(&(priv->sensitivity_data), 0,
  762. sizeof(struct iwl_sensitivity_data));
  763. memset(&(priv->chain_noise_data), 0,
  764. sizeof(struct iwl_chain_noise_data));
  765. for (i = 0; i < NUM_RX_CHAINS; i++)
  766. priv->chain_noise_data.delta_gain_code[i] =
  767. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  768. #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
  769. ret = iwl_grab_nic_access(priv);
  770. if (ret) {
  771. spin_unlock_irqrestore(&priv->lock, flags);
  772. return ret;
  773. }
  774. /* Clear 4965's internal Tx Scheduler data base */
  775. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  776. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  777. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  778. iwl_write_targ_mem(priv, a, 0);
  779. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  780. iwl_write_targ_mem(priv, a, 0);
  781. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  782. iwl_write_targ_mem(priv, a, 0);
  783. /* Tel 4965 where to find Tx byte count tables */
  784. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  785. (priv->shared_phys +
  786. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  787. /* Disable chain mode for all queues */
  788. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  789. /* Initialize each Tx queue (including the command queue) */
  790. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  791. /* TFD circular buffer read/write indexes */
  792. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  793. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  794. /* Max Tx Window size for Scheduler-ACK mode */
  795. iwl_write_targ_mem(priv, priv->scd_base_addr +
  796. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  797. (SCD_WIN_SIZE <<
  798. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  799. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  800. /* Frame limit */
  801. iwl_write_targ_mem(priv, priv->scd_base_addr +
  802. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  803. sizeof(u32),
  804. (SCD_FRAME_LIMIT <<
  805. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  806. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  807. }
  808. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  809. (1 << priv->hw_params.max_txq_num) - 1);
  810. /* Activate all Tx DMA/FIFO channels */
  811. iwl_write_prph(priv, IWL49_SCD_TXFACT,
  812. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  813. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  814. /* Map each Tx/cmd queue to its corresponding fifo */
  815. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  816. int ac = default_queue_to_tx_fifo[i];
  817. iwl_txq_ctx_activate(priv, i);
  818. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  819. }
  820. iwl_release_nic_access(priv);
  821. spin_unlock_irqrestore(&priv->lock, flags);
  822. /* Ask for statistics now, the uCode will send statistics notification
  823. * periodically after association */
  824. iwl_send_statistics_request(priv, CMD_ASYNC);
  825. return ret;
  826. }
  827. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  828. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  829. .min_nrg_cck = 97,
  830. .max_nrg_cck = 0,
  831. .auto_corr_min_ofdm = 85,
  832. .auto_corr_min_ofdm_mrc = 170,
  833. .auto_corr_min_ofdm_x1 = 105,
  834. .auto_corr_min_ofdm_mrc_x1 = 220,
  835. .auto_corr_max_ofdm = 120,
  836. .auto_corr_max_ofdm_mrc = 210,
  837. .auto_corr_max_ofdm_x1 = 140,
  838. .auto_corr_max_ofdm_mrc_x1 = 270,
  839. .auto_corr_min_cck = 125,
  840. .auto_corr_max_cck = 200,
  841. .auto_corr_min_cck_mrc = 200,
  842. .auto_corr_max_cck_mrc = 400,
  843. .nrg_th_cck = 100,
  844. .nrg_th_ofdm = 100,
  845. };
  846. #endif
  847. /**
  848. * iwl4965_hw_set_hw_params
  849. *
  850. * Called when initializing driver
  851. */
  852. int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  853. {
  854. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  855. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  856. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  857. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  858. return -EINVAL;
  859. }
  860. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  861. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  862. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  863. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  864. if (priv->cfg->mod_params->amsdu_size_8K)
  865. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  866. else
  867. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  868. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  869. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  870. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  871. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  872. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  873. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  874. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  875. priv->hw_params.tx_chains_num = 2;
  876. priv->hw_params.rx_chains_num = 2;
  877. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  878. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  879. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  880. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  881. priv->hw_params.sens = &iwl4965_sensitivity;
  882. #endif
  883. return 0;
  884. }
  885. /* set card power command */
  886. static int iwl4965_set_power(struct iwl_priv *priv,
  887. void *cmd)
  888. {
  889. int ret = 0;
  890. ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
  891. sizeof(struct iwl4965_powertable_cmd),
  892. cmd, NULL);
  893. return ret;
  894. }
  895. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  896. {
  897. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  898. return -EINVAL;
  899. }
  900. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  901. {
  902. s32 sign = 1;
  903. if (num < 0) {
  904. sign = -sign;
  905. num = -num;
  906. }
  907. if (denom < 0) {
  908. sign = -sign;
  909. denom = -denom;
  910. }
  911. *res = 1;
  912. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  913. return 1;
  914. }
  915. /**
  916. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  917. *
  918. * Determines power supply voltage compensation for txpower calculations.
  919. * Returns number of 1/2-dB steps to subtract from gain table index,
  920. * to compensate for difference between power supply voltage during
  921. * factory measurements, vs. current power supply voltage.
  922. *
  923. * Voltage indication is higher for lower voltage.
  924. * Lower voltage requires more gain (lower gain table index).
  925. */
  926. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  927. s32 current_voltage)
  928. {
  929. s32 comp = 0;
  930. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  931. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  932. return 0;
  933. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  934. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  935. if (current_voltage > eeprom_voltage)
  936. comp *= 2;
  937. if ((comp < -2) || (comp > 2))
  938. comp = 0;
  939. return comp;
  940. }
  941. static const struct iwl_channel_info *
  942. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  943. enum ieee80211_band band, u16 channel)
  944. {
  945. const struct iwl_channel_info *ch_info;
  946. ch_info = iwl_get_channel_info(priv, band, channel);
  947. if (!is_channel_valid(ch_info))
  948. return NULL;
  949. return ch_info;
  950. }
  951. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  952. {
  953. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  954. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  955. return CALIB_CH_GROUP_5;
  956. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  957. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  958. return CALIB_CH_GROUP_1;
  959. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  960. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  961. return CALIB_CH_GROUP_2;
  962. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  963. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  964. return CALIB_CH_GROUP_3;
  965. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  966. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  967. return CALIB_CH_GROUP_4;
  968. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  969. return -1;
  970. }
  971. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  972. {
  973. s32 b = -1;
  974. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  975. if (priv->calib_info->band_info[b].ch_from == 0)
  976. continue;
  977. if ((channel >= priv->calib_info->band_info[b].ch_from)
  978. && (channel <= priv->calib_info->band_info[b].ch_to))
  979. break;
  980. }
  981. return b;
  982. }
  983. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  984. {
  985. s32 val;
  986. if (x2 == x1)
  987. return y1;
  988. else {
  989. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  990. return val + y2;
  991. }
  992. }
  993. /**
  994. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  995. *
  996. * Interpolates factory measurements from the two sample channels within a
  997. * sub-band, to apply to channel of interest. Interpolation is proportional to
  998. * differences in channel frequencies, which is proportional to differences
  999. * in channel number.
  1000. */
  1001. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1002. struct iwl_eeprom_calib_ch_info *chan_info)
  1003. {
  1004. s32 s = -1;
  1005. u32 c;
  1006. u32 m;
  1007. const struct iwl_eeprom_calib_measure *m1;
  1008. const struct iwl_eeprom_calib_measure *m2;
  1009. struct iwl_eeprom_calib_measure *omeas;
  1010. u32 ch_i1;
  1011. u32 ch_i2;
  1012. s = iwl4965_get_sub_band(priv, channel);
  1013. if (s >= EEPROM_TX_POWER_BANDS) {
  1014. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1015. return -1;
  1016. }
  1017. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  1018. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  1019. chan_info->ch_num = (u8) channel;
  1020. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1021. channel, s, ch_i1, ch_i2);
  1022. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1023. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1024. m1 = &(priv->calib_info->band_info[s].ch1.
  1025. measurements[c][m]);
  1026. m2 = &(priv->calib_info->band_info[s].ch2.
  1027. measurements[c][m]);
  1028. omeas = &(chan_info->measurements[c][m]);
  1029. omeas->actual_pow =
  1030. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1031. m1->actual_pow,
  1032. ch_i2,
  1033. m2->actual_pow);
  1034. omeas->gain_idx =
  1035. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1036. m1->gain_idx, ch_i2,
  1037. m2->gain_idx);
  1038. omeas->temperature =
  1039. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1040. m1->temperature,
  1041. ch_i2,
  1042. m2->temperature);
  1043. omeas->pa_det =
  1044. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1045. m1->pa_det, ch_i2,
  1046. m2->pa_det);
  1047. IWL_DEBUG_TXPOWER
  1048. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1049. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1050. IWL_DEBUG_TXPOWER
  1051. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1052. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1053. IWL_DEBUG_TXPOWER
  1054. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1055. m1->pa_det, m2->pa_det, omeas->pa_det);
  1056. IWL_DEBUG_TXPOWER
  1057. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1058. m1->temperature, m2->temperature,
  1059. omeas->temperature);
  1060. }
  1061. }
  1062. return 0;
  1063. }
  1064. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1065. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1066. static s32 back_off_table[] = {
  1067. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1068. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1069. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1070. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1071. 10 /* CCK */
  1072. };
  1073. /* Thermal compensation values for txpower for various frequency ranges ...
  1074. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1075. static struct iwl4965_txpower_comp_entry {
  1076. s32 degrees_per_05db_a;
  1077. s32 degrees_per_05db_a_denom;
  1078. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1079. {9, 2}, /* group 0 5.2, ch 34-43 */
  1080. {4, 1}, /* group 1 5.2, ch 44-70 */
  1081. {4, 1}, /* group 2 5.2, ch 71-124 */
  1082. {4, 1}, /* group 3 5.2, ch 125-200 */
  1083. {3, 1} /* group 4 2.4, ch all */
  1084. };
  1085. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1086. {
  1087. if (!band) {
  1088. if ((rate_power_index & 7) <= 4)
  1089. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1090. }
  1091. return MIN_TX_GAIN_INDEX;
  1092. }
  1093. struct gain_entry {
  1094. u8 dsp;
  1095. u8 radio;
  1096. };
  1097. static const struct gain_entry gain_table[2][108] = {
  1098. /* 5.2GHz power gain index table */
  1099. {
  1100. {123, 0x3F}, /* highest txpower */
  1101. {117, 0x3F},
  1102. {110, 0x3F},
  1103. {104, 0x3F},
  1104. {98, 0x3F},
  1105. {110, 0x3E},
  1106. {104, 0x3E},
  1107. {98, 0x3E},
  1108. {110, 0x3D},
  1109. {104, 0x3D},
  1110. {98, 0x3D},
  1111. {110, 0x3C},
  1112. {104, 0x3C},
  1113. {98, 0x3C},
  1114. {110, 0x3B},
  1115. {104, 0x3B},
  1116. {98, 0x3B},
  1117. {110, 0x3A},
  1118. {104, 0x3A},
  1119. {98, 0x3A},
  1120. {110, 0x39},
  1121. {104, 0x39},
  1122. {98, 0x39},
  1123. {110, 0x38},
  1124. {104, 0x38},
  1125. {98, 0x38},
  1126. {110, 0x37},
  1127. {104, 0x37},
  1128. {98, 0x37},
  1129. {110, 0x36},
  1130. {104, 0x36},
  1131. {98, 0x36},
  1132. {110, 0x35},
  1133. {104, 0x35},
  1134. {98, 0x35},
  1135. {110, 0x34},
  1136. {104, 0x34},
  1137. {98, 0x34},
  1138. {110, 0x33},
  1139. {104, 0x33},
  1140. {98, 0x33},
  1141. {110, 0x32},
  1142. {104, 0x32},
  1143. {98, 0x32},
  1144. {110, 0x31},
  1145. {104, 0x31},
  1146. {98, 0x31},
  1147. {110, 0x30},
  1148. {104, 0x30},
  1149. {98, 0x30},
  1150. {110, 0x25},
  1151. {104, 0x25},
  1152. {98, 0x25},
  1153. {110, 0x24},
  1154. {104, 0x24},
  1155. {98, 0x24},
  1156. {110, 0x23},
  1157. {104, 0x23},
  1158. {98, 0x23},
  1159. {110, 0x22},
  1160. {104, 0x18},
  1161. {98, 0x18},
  1162. {110, 0x17},
  1163. {104, 0x17},
  1164. {98, 0x17},
  1165. {110, 0x16},
  1166. {104, 0x16},
  1167. {98, 0x16},
  1168. {110, 0x15},
  1169. {104, 0x15},
  1170. {98, 0x15},
  1171. {110, 0x14},
  1172. {104, 0x14},
  1173. {98, 0x14},
  1174. {110, 0x13},
  1175. {104, 0x13},
  1176. {98, 0x13},
  1177. {110, 0x12},
  1178. {104, 0x08},
  1179. {98, 0x08},
  1180. {110, 0x07},
  1181. {104, 0x07},
  1182. {98, 0x07},
  1183. {110, 0x06},
  1184. {104, 0x06},
  1185. {98, 0x06},
  1186. {110, 0x05},
  1187. {104, 0x05},
  1188. {98, 0x05},
  1189. {110, 0x04},
  1190. {104, 0x04},
  1191. {98, 0x04},
  1192. {110, 0x03},
  1193. {104, 0x03},
  1194. {98, 0x03},
  1195. {110, 0x02},
  1196. {104, 0x02},
  1197. {98, 0x02},
  1198. {110, 0x01},
  1199. {104, 0x01},
  1200. {98, 0x01},
  1201. {110, 0x00},
  1202. {104, 0x00},
  1203. {98, 0x00},
  1204. {93, 0x00},
  1205. {88, 0x00},
  1206. {83, 0x00},
  1207. {78, 0x00},
  1208. },
  1209. /* 2.4GHz power gain index table */
  1210. {
  1211. {110, 0x3f}, /* highest txpower */
  1212. {104, 0x3f},
  1213. {98, 0x3f},
  1214. {110, 0x3e},
  1215. {104, 0x3e},
  1216. {98, 0x3e},
  1217. {110, 0x3d},
  1218. {104, 0x3d},
  1219. {98, 0x3d},
  1220. {110, 0x3c},
  1221. {104, 0x3c},
  1222. {98, 0x3c},
  1223. {110, 0x3b},
  1224. {104, 0x3b},
  1225. {98, 0x3b},
  1226. {110, 0x3a},
  1227. {104, 0x3a},
  1228. {98, 0x3a},
  1229. {110, 0x39},
  1230. {104, 0x39},
  1231. {98, 0x39},
  1232. {110, 0x38},
  1233. {104, 0x38},
  1234. {98, 0x38},
  1235. {110, 0x37},
  1236. {104, 0x37},
  1237. {98, 0x37},
  1238. {110, 0x36},
  1239. {104, 0x36},
  1240. {98, 0x36},
  1241. {110, 0x35},
  1242. {104, 0x35},
  1243. {98, 0x35},
  1244. {110, 0x34},
  1245. {104, 0x34},
  1246. {98, 0x34},
  1247. {110, 0x33},
  1248. {104, 0x33},
  1249. {98, 0x33},
  1250. {110, 0x32},
  1251. {104, 0x32},
  1252. {98, 0x32},
  1253. {110, 0x31},
  1254. {104, 0x31},
  1255. {98, 0x31},
  1256. {110, 0x30},
  1257. {104, 0x30},
  1258. {98, 0x30},
  1259. {110, 0x6},
  1260. {104, 0x6},
  1261. {98, 0x6},
  1262. {110, 0x5},
  1263. {104, 0x5},
  1264. {98, 0x5},
  1265. {110, 0x4},
  1266. {104, 0x4},
  1267. {98, 0x4},
  1268. {110, 0x3},
  1269. {104, 0x3},
  1270. {98, 0x3},
  1271. {110, 0x2},
  1272. {104, 0x2},
  1273. {98, 0x2},
  1274. {110, 0x1},
  1275. {104, 0x1},
  1276. {98, 0x1},
  1277. {110, 0x0},
  1278. {104, 0x0},
  1279. {98, 0x0},
  1280. {97, 0},
  1281. {96, 0},
  1282. {95, 0},
  1283. {94, 0},
  1284. {93, 0},
  1285. {92, 0},
  1286. {91, 0},
  1287. {90, 0},
  1288. {89, 0},
  1289. {88, 0},
  1290. {87, 0},
  1291. {86, 0},
  1292. {85, 0},
  1293. {84, 0},
  1294. {83, 0},
  1295. {82, 0},
  1296. {81, 0},
  1297. {80, 0},
  1298. {79, 0},
  1299. {78, 0},
  1300. {77, 0},
  1301. {76, 0},
  1302. {75, 0},
  1303. {74, 0},
  1304. {73, 0},
  1305. {72, 0},
  1306. {71, 0},
  1307. {70, 0},
  1308. {69, 0},
  1309. {68, 0},
  1310. {67, 0},
  1311. {66, 0},
  1312. {65, 0},
  1313. {64, 0},
  1314. {63, 0},
  1315. {62, 0},
  1316. {61, 0},
  1317. {60, 0},
  1318. {59, 0},
  1319. }
  1320. };
  1321. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1322. u8 is_fat, u8 ctrl_chan_high,
  1323. struct iwl4965_tx_power_db *tx_power_tbl)
  1324. {
  1325. u8 saturation_power;
  1326. s32 target_power;
  1327. s32 user_target_power;
  1328. s32 power_limit;
  1329. s32 current_temp;
  1330. s32 reg_limit;
  1331. s32 current_regulatory;
  1332. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1333. int i;
  1334. int c;
  1335. const struct iwl_channel_info *ch_info = NULL;
  1336. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1337. const struct iwl_eeprom_calib_measure *measurement;
  1338. s16 voltage;
  1339. s32 init_voltage;
  1340. s32 voltage_compensation;
  1341. s32 degrees_per_05db_num;
  1342. s32 degrees_per_05db_denom;
  1343. s32 factory_temp;
  1344. s32 temperature_comp[2];
  1345. s32 factory_gain_index[2];
  1346. s32 factory_actual_pwr[2];
  1347. s32 power_index;
  1348. /* Sanity check requested level (dBm) */
  1349. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1350. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1351. priv->user_txpower_limit);
  1352. return -EINVAL;
  1353. }
  1354. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1355. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1356. priv->user_txpower_limit);
  1357. return -EINVAL;
  1358. }
  1359. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1360. * are used for indexing into txpower table) */
  1361. user_target_power = 2 * priv->user_txpower_limit;
  1362. /* Get current (RXON) channel, band, width */
  1363. ch_info =
  1364. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  1365. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1366. is_fat);
  1367. if (!ch_info)
  1368. return -EINVAL;
  1369. /* get txatten group, used to select 1) thermal txpower adjustment
  1370. * and 2) mimo txpower balance between Tx chains. */
  1371. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1372. if (txatten_grp < 0)
  1373. return -EINVAL;
  1374. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1375. channel, txatten_grp);
  1376. if (is_fat) {
  1377. if (ctrl_chan_high)
  1378. channel -= 2;
  1379. else
  1380. channel += 2;
  1381. }
  1382. /* hardware txpower limits ...
  1383. * saturation (clipping distortion) txpowers are in half-dBm */
  1384. if (band)
  1385. saturation_power = priv->calib_info->saturation_power24;
  1386. else
  1387. saturation_power = priv->calib_info->saturation_power52;
  1388. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1389. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1390. if (band)
  1391. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1392. else
  1393. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1394. }
  1395. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1396. * max_power_avg values are in dBm, convert * 2 */
  1397. if (is_fat)
  1398. reg_limit = ch_info->fat_max_power_avg * 2;
  1399. else
  1400. reg_limit = ch_info->max_power_avg * 2;
  1401. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1402. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1403. if (band)
  1404. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1405. else
  1406. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1407. }
  1408. /* Interpolate txpower calibration values for this channel,
  1409. * based on factory calibration tests on spaced channels. */
  1410. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1411. /* calculate tx gain adjustment based on power supply voltage */
  1412. voltage = priv->calib_info->voltage;
  1413. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1414. voltage_compensation =
  1415. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1416. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1417. init_voltage,
  1418. voltage, voltage_compensation);
  1419. /* get current temperature (Celsius) */
  1420. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1421. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1422. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1423. /* select thermal txpower adjustment params, based on channel group
  1424. * (same frequency group used for mimo txatten adjustment) */
  1425. degrees_per_05db_num =
  1426. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1427. degrees_per_05db_denom =
  1428. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1429. /* get per-chain txpower values from factory measurements */
  1430. for (c = 0; c < 2; c++) {
  1431. measurement = &ch_eeprom_info.measurements[c][1];
  1432. /* txgain adjustment (in half-dB steps) based on difference
  1433. * between factory and current temperature */
  1434. factory_temp = measurement->temperature;
  1435. iwl4965_math_div_round((current_temp - factory_temp) *
  1436. degrees_per_05db_denom,
  1437. degrees_per_05db_num,
  1438. &temperature_comp[c]);
  1439. factory_gain_index[c] = measurement->gain_idx;
  1440. factory_actual_pwr[c] = measurement->actual_pow;
  1441. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  1442. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  1443. "curr tmp %d, comp %d steps\n",
  1444. factory_temp, current_temp,
  1445. temperature_comp[c]);
  1446. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  1447. factory_gain_index[c],
  1448. factory_actual_pwr[c]);
  1449. }
  1450. /* for each of 33 bit-rates (including 1 for CCK) */
  1451. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1452. u8 is_mimo_rate;
  1453. union iwl4965_tx_power_dual_stream tx_power;
  1454. /* for mimo, reduce each chain's txpower by half
  1455. * (3dB, 6 steps), so total output power is regulatory
  1456. * compliant. */
  1457. if (i & 0x8) {
  1458. current_regulatory = reg_limit -
  1459. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1460. is_mimo_rate = 1;
  1461. } else {
  1462. current_regulatory = reg_limit;
  1463. is_mimo_rate = 0;
  1464. }
  1465. /* find txpower limit, either hardware or regulatory */
  1466. power_limit = saturation_power - back_off_table[i];
  1467. if (power_limit > current_regulatory)
  1468. power_limit = current_regulatory;
  1469. /* reduce user's txpower request if necessary
  1470. * for this rate on this channel */
  1471. target_power = user_target_power;
  1472. if (target_power > power_limit)
  1473. target_power = power_limit;
  1474. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  1475. i, saturation_power - back_off_table[i],
  1476. current_regulatory, user_target_power,
  1477. target_power);
  1478. /* for each of 2 Tx chains (radio transmitters) */
  1479. for (c = 0; c < 2; c++) {
  1480. s32 atten_value;
  1481. if (is_mimo_rate)
  1482. atten_value =
  1483. (s32)le32_to_cpu(priv->card_alive_init.
  1484. tx_atten[txatten_grp][c]);
  1485. else
  1486. atten_value = 0;
  1487. /* calculate index; higher index means lower txpower */
  1488. power_index = (u8) (factory_gain_index[c] -
  1489. (target_power -
  1490. factory_actual_pwr[c]) -
  1491. temperature_comp[c] -
  1492. voltage_compensation +
  1493. atten_value);
  1494. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  1495. power_index); */
  1496. if (power_index < get_min_power_index(i, band))
  1497. power_index = get_min_power_index(i, band);
  1498. /* adjust 5 GHz index to support negative indexes */
  1499. if (!band)
  1500. power_index += 9;
  1501. /* CCK, rate 32, reduce txpower for CCK */
  1502. if (i == POWER_TABLE_CCK_ENTRY)
  1503. power_index +=
  1504. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1505. /* stay within the table! */
  1506. if (power_index > 107) {
  1507. IWL_WARNING("txpower index %d > 107\n",
  1508. power_index);
  1509. power_index = 107;
  1510. }
  1511. if (power_index < 0) {
  1512. IWL_WARNING("txpower index %d < 0\n",
  1513. power_index);
  1514. power_index = 0;
  1515. }
  1516. /* fill txpower command for this rate/chain */
  1517. tx_power.s.radio_tx_gain[c] =
  1518. gain_table[band][power_index].radio;
  1519. tx_power.s.dsp_predis_atten[c] =
  1520. gain_table[band][power_index].dsp;
  1521. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  1522. "gain 0x%02x dsp %d\n",
  1523. c, atten_value, power_index,
  1524. tx_power.s.radio_tx_gain[c],
  1525. tx_power.s.dsp_predis_atten[c]);
  1526. }/* for each chain */
  1527. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1528. }/* for each rate */
  1529. return 0;
  1530. }
  1531. /**
  1532. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  1533. *
  1534. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1535. * The power limit is taken from priv->user_txpower_limit.
  1536. */
  1537. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  1538. {
  1539. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1540. int ret;
  1541. u8 band = 0;
  1542. u8 is_fat = 0;
  1543. u8 ctrl_chan_high = 0;
  1544. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1545. /* If this gets hit a lot, switch it to a BUG() and catch
  1546. * the stack trace to find out who is calling this during
  1547. * a scan. */
  1548. IWL_WARNING("TX Power requested while scanning!\n");
  1549. return -EAGAIN;
  1550. }
  1551. band = priv->band == IEEE80211_BAND_2GHZ;
  1552. is_fat = is_fat_channel(priv->active_rxon.flags);
  1553. if (is_fat &&
  1554. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1555. ctrl_chan_high = 1;
  1556. cmd.band = band;
  1557. cmd.channel = priv->active_rxon.channel;
  1558. ret = iwl4965_fill_txpower_tbl(priv, band,
  1559. le16_to_cpu(priv->active_rxon.channel),
  1560. is_fat, ctrl_chan_high, &cmd.tx_power);
  1561. if (ret)
  1562. goto out;
  1563. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1564. out:
  1565. return ret;
  1566. }
  1567. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1568. {
  1569. int ret = 0;
  1570. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1571. const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
  1572. const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
  1573. if ((rxon1->flags == rxon2->flags) &&
  1574. (rxon1->filter_flags == rxon2->filter_flags) &&
  1575. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1576. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1577. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1578. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1579. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1580. (rxon1->rx_chain == rxon2->rx_chain) &&
  1581. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1582. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  1583. return 0;
  1584. }
  1585. rxon_assoc.flags = priv->staging_rxon.flags;
  1586. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1587. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1588. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1589. rxon_assoc.reserved = 0;
  1590. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1591. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1592. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1593. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1594. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1595. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1596. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1597. if (ret)
  1598. return ret;
  1599. return ret;
  1600. }
  1601. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1602. {
  1603. int rc;
  1604. u8 band = 0;
  1605. u8 is_fat = 0;
  1606. u8 ctrl_chan_high = 0;
  1607. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1608. const struct iwl_channel_info *ch_info;
  1609. band = priv->band == IEEE80211_BAND_2GHZ;
  1610. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1611. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1612. if (is_fat &&
  1613. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1614. ctrl_chan_high = 1;
  1615. cmd.band = band;
  1616. cmd.expect_beacon = 0;
  1617. cmd.channel = cpu_to_le16(channel);
  1618. cmd.rxon_flags = priv->active_rxon.flags;
  1619. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1620. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1621. if (ch_info)
  1622. cmd.expect_beacon = is_channel_radar(ch_info);
  1623. else
  1624. cmd.expect_beacon = 1;
  1625. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1626. ctrl_chan_high, &cmd.tx_power);
  1627. if (rc) {
  1628. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  1629. return rc;
  1630. }
  1631. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1632. return rc;
  1633. }
  1634. static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
  1635. {
  1636. struct iwl4965_shared *s = priv->shared_virt;
  1637. return le32_to_cpu(s->rb_closed) & 0xFFF;
  1638. }
  1639. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  1640. {
  1641. return priv->temperature;
  1642. }
  1643. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  1644. struct iwl_frame *frame, u8 rate)
  1645. {
  1646. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  1647. unsigned int frame_size;
  1648. tx_beacon_cmd = &frame->u.beacon;
  1649. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  1650. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  1651. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1652. frame_size = iwl4965_fill_beacon_frame(priv,
  1653. tx_beacon_cmd->frame,
  1654. iwl_bcast_addr,
  1655. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  1656. BUG_ON(frame_size > MAX_MPDU_SIZE);
  1657. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  1658. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  1659. tx_beacon_cmd->tx.rate_n_flags =
  1660. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  1661. else
  1662. tx_beacon_cmd->tx.rate_n_flags =
  1663. iwl4965_hw_set_rate_n_flags(rate, 0);
  1664. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  1665. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  1666. return (sizeof(*tx_beacon_cmd) + frame_size);
  1667. }
  1668. static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
  1669. {
  1670. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  1671. sizeof(struct iwl4965_shared),
  1672. &priv->shared_phys);
  1673. if (!priv->shared_virt)
  1674. return -ENOMEM;
  1675. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  1676. priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
  1677. return 0;
  1678. }
  1679. static void iwl4965_free_shared_mem(struct iwl_priv *priv)
  1680. {
  1681. if (priv->shared_virt)
  1682. pci_free_consistent(priv->pci_dev,
  1683. sizeof(struct iwl4965_shared),
  1684. priv->shared_virt,
  1685. priv->shared_phys);
  1686. }
  1687. /**
  1688. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1689. */
  1690. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1691. struct iwl_tx_queue *txq,
  1692. u16 byte_cnt)
  1693. {
  1694. int len;
  1695. int txq_id = txq->q.id;
  1696. struct iwl4965_shared *shared_data = priv->shared_virt;
  1697. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1698. /* Set up byte count within first 256 entries */
  1699. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1700. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  1701. /* If within first 64 entries, duplicate at end */
  1702. if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
  1703. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1704. tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
  1705. byte_cnt, len);
  1706. }
  1707. /**
  1708. * sign_extend - Sign extend a value using specified bit as sign-bit
  1709. *
  1710. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1711. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1712. *
  1713. * @param oper value to sign extend
  1714. * @param index 0 based bit index (0<=index<32) to sign bit
  1715. */
  1716. static s32 sign_extend(u32 oper, int index)
  1717. {
  1718. u8 shift = 31 - index;
  1719. return (s32)(oper << shift) >> shift;
  1720. }
  1721. /**
  1722. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  1723. * @statistics: Provides the temperature reading from the uCode
  1724. *
  1725. * A return of <0 indicates bogus data in the statistics
  1726. */
  1727. int iwl4965_get_temperature(const struct iwl_priv *priv)
  1728. {
  1729. s32 temperature;
  1730. s32 vt;
  1731. s32 R1, R2, R3;
  1732. u32 R4;
  1733. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1734. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1735. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  1736. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1737. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1738. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1739. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1740. } else {
  1741. IWL_DEBUG_TEMP("Running temperature calibration\n");
  1742. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1743. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1744. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1745. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1746. }
  1747. /*
  1748. * Temperature is only 23 bits, so sign extend out to 32.
  1749. *
  1750. * NOTE If we haven't received a statistics notification yet
  1751. * with an updated temperature, use R4 provided to us in the
  1752. * "initialize" ALIVE response.
  1753. */
  1754. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1755. vt = sign_extend(R4, 23);
  1756. else
  1757. vt = sign_extend(
  1758. le32_to_cpu(priv->statistics.general.temperature), 23);
  1759. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  1760. R1, R2, R3, vt);
  1761. if (R3 == R1) {
  1762. IWL_ERROR("Calibration conflict R1 == R3\n");
  1763. return -1;
  1764. }
  1765. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1766. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1767. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1768. temperature /= (R3 - R1);
  1769. temperature = (temperature * 97) / 100 +
  1770. TEMPERATURE_CALIB_KELVIN_OFFSET;
  1771. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  1772. KELVIN_TO_CELSIUS(temperature));
  1773. return temperature;
  1774. }
  1775. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1776. #define IWL_TEMPERATURE_THRESHOLD 3
  1777. /**
  1778. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1779. *
  1780. * If the temperature changed has changed sufficiently, then a recalibration
  1781. * is needed.
  1782. *
  1783. * Assumes caller will replace priv->last_temperature once calibration
  1784. * executed.
  1785. */
  1786. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1787. {
  1788. int temp_diff;
  1789. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1790. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  1791. return 0;
  1792. }
  1793. temp_diff = priv->temperature - priv->last_temperature;
  1794. /* get absolute value */
  1795. if (temp_diff < 0) {
  1796. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  1797. temp_diff = -temp_diff;
  1798. } else if (temp_diff == 0)
  1799. IWL_DEBUG_POWER("Same temp, \n");
  1800. else
  1801. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  1802. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1803. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  1804. return 0;
  1805. }
  1806. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  1807. return 1;
  1808. }
  1809. /* Calculate noise level, based on measurements during network silence just
  1810. * before arriving beacon. This measurement can be done only if we know
  1811. * exactly when to expect beacons, therefore only when we're associated. */
  1812. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  1813. {
  1814. struct statistics_rx_non_phy *rx_info
  1815. = &(priv->statistics.rx.general);
  1816. int num_active_rx = 0;
  1817. int total_silence = 0;
  1818. int bcn_silence_a =
  1819. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  1820. int bcn_silence_b =
  1821. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  1822. int bcn_silence_c =
  1823. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  1824. if (bcn_silence_a) {
  1825. total_silence += bcn_silence_a;
  1826. num_active_rx++;
  1827. }
  1828. if (bcn_silence_b) {
  1829. total_silence += bcn_silence_b;
  1830. num_active_rx++;
  1831. }
  1832. if (bcn_silence_c) {
  1833. total_silence += bcn_silence_c;
  1834. num_active_rx++;
  1835. }
  1836. /* Average among active antennas */
  1837. if (num_active_rx)
  1838. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  1839. else
  1840. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1841. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  1842. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  1843. priv->last_rx_noise);
  1844. }
  1845. void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
  1846. struct iwl_rx_mem_buffer *rxb)
  1847. {
  1848. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1849. int change;
  1850. s32 temp;
  1851. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  1852. (int)sizeof(priv->statistics), pkt->len);
  1853. change = ((priv->statistics.general.temperature !=
  1854. pkt->u.stats.general.temperature) ||
  1855. ((priv->statistics.flag &
  1856. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  1857. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  1858. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  1859. set_bit(STATUS_STATISTICS, &priv->status);
  1860. /* Reschedule the statistics timer to occur in
  1861. * REG_RECALIB_PERIOD seconds to ensure we get a
  1862. * thermal update even if the uCode doesn't give
  1863. * us one */
  1864. mod_timer(&priv->statistics_periodic, jiffies +
  1865. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  1866. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1867. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  1868. iwl4965_rx_calc_noise(priv);
  1869. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  1870. queue_work(priv->workqueue, &priv->sensitivity_work);
  1871. #endif
  1872. }
  1873. iwl_leds_background(priv);
  1874. /* If the hardware hasn't reported a change in
  1875. * temperature then don't bother computing a
  1876. * calibrated temperature value */
  1877. if (!change)
  1878. return;
  1879. temp = iwl4965_get_temperature(priv);
  1880. if (temp < 0)
  1881. return;
  1882. if (priv->temperature != temp) {
  1883. if (priv->temperature)
  1884. IWL_DEBUG_TEMP("Temperature changed "
  1885. "from %dC to %dC\n",
  1886. KELVIN_TO_CELSIUS(priv->temperature),
  1887. KELVIN_TO_CELSIUS(temp));
  1888. else
  1889. IWL_DEBUG_TEMP("Temperature "
  1890. "initialized to %dC\n",
  1891. KELVIN_TO_CELSIUS(temp));
  1892. }
  1893. priv->temperature = temp;
  1894. set_bit(STATUS_TEMPERATURE, &priv->status);
  1895. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1896. iwl4965_is_temp_calib_needed(priv))
  1897. queue_work(priv->workqueue, &priv->txpower_work);
  1898. }
  1899. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  1900. struct sk_buff *skb,
  1901. struct iwl4965_rx_phy_res *rx_start,
  1902. struct ieee80211_rx_status *stats,
  1903. u32 ampdu_status)
  1904. {
  1905. s8 signal = stats->signal;
  1906. s8 noise = 0;
  1907. int rate = stats->rate_idx;
  1908. u64 tsf = stats->mactime;
  1909. __le16 antenna;
  1910. __le16 phy_flags_hw = rx_start->phy_flags;
  1911. struct iwl4965_rt_rx_hdr {
  1912. struct ieee80211_radiotap_header rt_hdr;
  1913. __le64 rt_tsf; /* TSF */
  1914. u8 rt_flags; /* radiotap packet flags */
  1915. u8 rt_rate; /* rate in 500kb/s */
  1916. __le16 rt_channelMHz; /* channel in MHz */
  1917. __le16 rt_chbitmask; /* channel bitfield */
  1918. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  1919. s8 rt_dbmnoise;
  1920. u8 rt_antenna; /* antenna number */
  1921. } __attribute__ ((packed)) *iwl4965_rt;
  1922. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  1923. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  1924. if (net_ratelimit())
  1925. printk(KERN_ERR "not enough headroom [%d] for "
  1926. "radiotap head [%zd]\n",
  1927. skb_headroom(skb), sizeof(*iwl4965_rt));
  1928. return;
  1929. }
  1930. /* put radiotap header in front of 802.11 header and data */
  1931. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  1932. /* initialise radiotap header */
  1933. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  1934. iwl4965_rt->rt_hdr.it_pad = 0;
  1935. /* total header + data */
  1936. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  1937. &iwl4965_rt->rt_hdr.it_len);
  1938. /* Indicate all the fields we add to the radiotap header */
  1939. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  1940. (1 << IEEE80211_RADIOTAP_FLAGS) |
  1941. (1 << IEEE80211_RADIOTAP_RATE) |
  1942. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  1943. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  1944. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  1945. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  1946. &iwl4965_rt->rt_hdr.it_present);
  1947. /* Zero the flags, we'll add to them as we go */
  1948. iwl4965_rt->rt_flags = 0;
  1949. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  1950. iwl4965_rt->rt_dbmsignal = signal;
  1951. iwl4965_rt->rt_dbmnoise = noise;
  1952. /* Convert the channel frequency and set the flags */
  1953. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  1954. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  1955. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1956. IEEE80211_CHAN_5GHZ),
  1957. &iwl4965_rt->rt_chbitmask);
  1958. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  1959. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  1960. IEEE80211_CHAN_2GHZ),
  1961. &iwl4965_rt->rt_chbitmask);
  1962. else /* 802.11g */
  1963. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1964. IEEE80211_CHAN_2GHZ),
  1965. &iwl4965_rt->rt_chbitmask);
  1966. if (rate == -1)
  1967. iwl4965_rt->rt_rate = 0;
  1968. else
  1969. iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
  1970. /*
  1971. * "antenna number"
  1972. *
  1973. * It seems that the antenna field in the phy flags value
  1974. * is actually a bitfield. This is undefined by radiotap,
  1975. * it wants an actual antenna number but I always get "7"
  1976. * for most legacy frames I receive indicating that the
  1977. * same frame was received on all three RX chains.
  1978. *
  1979. * I think this field should be removed in favour of a
  1980. * new 802.11n radiotap field "RX chains" that is defined
  1981. * as a bitmask.
  1982. */
  1983. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  1984. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  1985. /* set the preamble flag if appropriate */
  1986. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1987. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  1988. stats->flag |= RX_FLAG_RADIOTAP;
  1989. }
  1990. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  1991. {
  1992. /* 0 - mgmt, 1 - cnt, 2 - data */
  1993. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  1994. priv->rx_stats[idx].cnt++;
  1995. priv->rx_stats[idx].bytes += len;
  1996. }
  1997. /*
  1998. * returns non-zero if packet should be dropped
  1999. */
  2000. static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
  2001. struct ieee80211_hdr *hdr,
  2002. u32 decrypt_res,
  2003. struct ieee80211_rx_status *stats)
  2004. {
  2005. u16 fc = le16_to_cpu(hdr->frame_control);
  2006. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2007. return 0;
  2008. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2009. return 0;
  2010. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2011. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2012. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2013. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2014. * Decryption will be done in SW. */
  2015. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2016. RX_RES_STATUS_BAD_KEY_TTAK)
  2017. break;
  2018. case RX_RES_STATUS_SEC_TYPE_WEP:
  2019. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2020. RX_RES_STATUS_BAD_ICV_MIC) {
  2021. /* bad ICV, the packet is destroyed since the
  2022. * decryption is inplace, drop it */
  2023. IWL_DEBUG_RX("Packet destroyed\n");
  2024. return -1;
  2025. }
  2026. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2027. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2028. RX_RES_STATUS_DECRYPT_OK) {
  2029. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2030. stats->flag |= RX_FLAG_DECRYPTED;
  2031. }
  2032. break;
  2033. default:
  2034. break;
  2035. }
  2036. return 0;
  2037. }
  2038. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  2039. {
  2040. u32 decrypt_out = 0;
  2041. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  2042. RX_RES_STATUS_STATION_FOUND)
  2043. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  2044. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  2045. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  2046. /* packet was not encrypted */
  2047. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2048. RX_RES_STATUS_SEC_TYPE_NONE)
  2049. return decrypt_out;
  2050. /* packet was encrypted with unknown alg */
  2051. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2052. RX_RES_STATUS_SEC_TYPE_ERR)
  2053. return decrypt_out;
  2054. /* decryption was not done in HW */
  2055. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  2056. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  2057. return decrypt_out;
  2058. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  2059. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2060. /* alg is CCM: check MIC only */
  2061. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  2062. /* Bad MIC */
  2063. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2064. else
  2065. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2066. break;
  2067. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2068. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  2069. /* Bad TTAK */
  2070. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  2071. break;
  2072. }
  2073. /* fall through if TTAK OK */
  2074. default:
  2075. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  2076. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2077. else
  2078. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2079. break;
  2080. };
  2081. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  2082. decrypt_in, decrypt_out);
  2083. return decrypt_out;
  2084. }
  2085. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  2086. int include_phy,
  2087. struct iwl_rx_mem_buffer *rxb,
  2088. struct ieee80211_rx_status *stats)
  2089. {
  2090. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2091. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2092. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  2093. struct ieee80211_hdr *hdr;
  2094. u16 len;
  2095. __le32 *rx_end;
  2096. unsigned int skblen;
  2097. u32 ampdu_status;
  2098. u32 ampdu_status_legacy;
  2099. if (!include_phy && priv->last_phy_res[0])
  2100. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2101. if (!rx_start) {
  2102. IWL_ERROR("MPDU frame without a PHY data\n");
  2103. return;
  2104. }
  2105. if (include_phy) {
  2106. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  2107. rx_start->cfg_phy_cnt);
  2108. len = le16_to_cpu(rx_start->byte_count);
  2109. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2110. sizeof(struct iwl4965_rx_phy_res) +
  2111. rx_start->cfg_phy_cnt + len);
  2112. } else {
  2113. struct iwl4965_rx_mpdu_res_start *amsdu =
  2114. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2115. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2116. sizeof(struct iwl4965_rx_mpdu_res_start));
  2117. len = le16_to_cpu(amsdu->byte_count);
  2118. rx_start->byte_count = amsdu->byte_count;
  2119. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2120. }
  2121. /* In monitor mode allow 802.11 ACk frames (10 bytes) */
  2122. if (len > priv->hw_params.max_pkt_size ||
  2123. len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
  2124. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  2125. return;
  2126. }
  2127. ampdu_status = le32_to_cpu(*rx_end);
  2128. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2129. if (!include_phy) {
  2130. /* New status scheme, need to translate */
  2131. ampdu_status_legacy = ampdu_status;
  2132. ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
  2133. }
  2134. /* start from MAC */
  2135. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2136. skb_put(rxb->skb, len); /* end where data ends */
  2137. /* We only process data packets if the interface is open */
  2138. if (unlikely(!priv->is_open)) {
  2139. IWL_DEBUG_DROP_LIMIT
  2140. ("Dropping packet while interface is not open.\n");
  2141. return;
  2142. }
  2143. stats->flag = 0;
  2144. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2145. /* in case of HW accelerated crypto and bad decryption, drop */
  2146. if (!priv->hw_params.sw_crypto &&
  2147. iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  2148. return;
  2149. if (priv->add_radiotap)
  2150. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2151. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  2152. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2153. priv->alloc_rxb_skb--;
  2154. rxb->skb = NULL;
  2155. }
  2156. /* Calc max signal level (dBm) among 3 possible receivers */
  2157. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  2158. struct iwl4965_rx_phy_res *rx_resp)
  2159. {
  2160. /* data from PHY/DSP regarding signal strength, etc.,
  2161. * contents are always there, not configurable by host. */
  2162. struct iwl4965_rx_non_cfg_phy *ncphy =
  2163. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2164. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2165. >> IWL_AGC_DB_POS;
  2166. u32 valid_antennae =
  2167. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2168. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2169. u8 max_rssi = 0;
  2170. u32 i;
  2171. /* Find max rssi among 3 possible receivers.
  2172. * These values are measured by the digital signal processor (DSP).
  2173. * They should stay fairly constant even as the signal strength varies,
  2174. * if the radio's automatic gain control (AGC) is working right.
  2175. * AGC value (see below) will provide the "interesting" info. */
  2176. for (i = 0; i < 3; i++)
  2177. if (valid_antennae & (1 << i))
  2178. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2179. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2180. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2181. max_rssi, agc);
  2182. /* dBm = max_rssi dB - agc dB - constant.
  2183. * Higher AGC (higher radio gain) means lower signal. */
  2184. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2185. }
  2186. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  2187. {
  2188. unsigned long flags;
  2189. spin_lock_irqsave(&priv->sta_lock, flags);
  2190. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2191. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2192. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2193. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2194. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2195. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2196. }
  2197. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  2198. {
  2199. /* FIXME: need locking over ps_status ??? */
  2200. u8 sta_id = iwl_find_station(priv, addr);
  2201. if (sta_id != IWL_INVALID_STATION) {
  2202. u8 sta_awake = priv->stations[sta_id].
  2203. ps_status == STA_PS_STATUS_WAKE;
  2204. if (sta_awake && ps_bit)
  2205. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  2206. else if (!sta_awake && !ps_bit) {
  2207. iwl4965_sta_modify_ps_wake(priv, sta_id);
  2208. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  2209. }
  2210. }
  2211. }
  2212. #ifdef CONFIG_IWLWIFI_DEBUG
  2213. /**
  2214. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  2215. *
  2216. * You may hack this function to show different aspects of received frames,
  2217. * including selective frame dumps.
  2218. * group100 parameter selects whether to show 1 out of 100 good frames.
  2219. *
  2220. * TODO: This was originally written for 3945, need to audit for
  2221. * proper operation with 4965.
  2222. */
  2223. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2224. struct iwl_rx_packet *pkt,
  2225. struct ieee80211_hdr *header, int group100)
  2226. {
  2227. u32 to_us;
  2228. u32 print_summary = 0;
  2229. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  2230. u32 hundred = 0;
  2231. u32 dataframe = 0;
  2232. u16 fc;
  2233. u16 seq_ctl;
  2234. u16 channel;
  2235. u16 phy_flags;
  2236. int rate_sym;
  2237. u16 length;
  2238. u16 status;
  2239. u16 bcn_tmr;
  2240. u32 tsf_low;
  2241. u64 tsf;
  2242. u8 rssi;
  2243. u8 agc;
  2244. u16 sig_avg;
  2245. u16 noise_diff;
  2246. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  2247. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  2248. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  2249. u8 *data = IWL_RX_DATA(pkt);
  2250. if (likely(!(priv->debug_level & IWL_DL_RX)))
  2251. return;
  2252. /* MAC header */
  2253. fc = le16_to_cpu(header->frame_control);
  2254. seq_ctl = le16_to_cpu(header->seq_ctrl);
  2255. /* metadata */
  2256. channel = le16_to_cpu(rx_hdr->channel);
  2257. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  2258. rate_sym = rx_hdr->rate;
  2259. length = le16_to_cpu(rx_hdr->len);
  2260. /* end-of-frame status and timestamp */
  2261. status = le32_to_cpu(rx_end->status);
  2262. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  2263. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  2264. tsf = le64_to_cpu(rx_end->timestamp);
  2265. /* signal statistics */
  2266. rssi = rx_stats->rssi;
  2267. agc = rx_stats->agc;
  2268. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  2269. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  2270. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  2271. /* if data frame is to us and all is good,
  2272. * (optionally) print summary for only 1 out of every 100 */
  2273. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  2274. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  2275. dataframe = 1;
  2276. if (!group100)
  2277. print_summary = 1; /* print each frame */
  2278. else if (priv->framecnt_to_us < 100) {
  2279. priv->framecnt_to_us++;
  2280. print_summary = 0;
  2281. } else {
  2282. priv->framecnt_to_us = 0;
  2283. print_summary = 1;
  2284. hundred = 1;
  2285. }
  2286. } else {
  2287. /* print summary for all other frames */
  2288. print_summary = 1;
  2289. }
  2290. if (print_summary) {
  2291. char *title;
  2292. int rate_idx;
  2293. u32 bitrate;
  2294. if (hundred)
  2295. title = "100Frames";
  2296. else if (fc & IEEE80211_FCTL_RETRY)
  2297. title = "Retry";
  2298. else if (ieee80211_is_assoc_response(fc))
  2299. title = "AscRsp";
  2300. else if (ieee80211_is_reassoc_response(fc))
  2301. title = "RasRsp";
  2302. else if (ieee80211_is_probe_response(fc)) {
  2303. title = "PrbRsp";
  2304. print_dump = 1; /* dump frame contents */
  2305. } else if (ieee80211_is_beacon(fc)) {
  2306. title = "Beacon";
  2307. print_dump = 1; /* dump frame contents */
  2308. } else if (ieee80211_is_atim(fc))
  2309. title = "ATIM";
  2310. else if (ieee80211_is_auth(fc))
  2311. title = "Auth";
  2312. else if (ieee80211_is_deauth(fc))
  2313. title = "DeAuth";
  2314. else if (ieee80211_is_disassoc(fc))
  2315. title = "DisAssoc";
  2316. else
  2317. title = "Frame";
  2318. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  2319. if (unlikely(rate_idx == -1))
  2320. bitrate = 0;
  2321. else
  2322. bitrate = iwl_rates[rate_idx].ieee / 2;
  2323. /* print frame summary.
  2324. * MAC addresses show just the last byte (for brevity),
  2325. * but you can hack it to show more, if you'd like to. */
  2326. if (dataframe)
  2327. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  2328. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  2329. title, fc, header->addr1[5],
  2330. length, rssi, channel, bitrate);
  2331. else {
  2332. /* src/dst addresses assume managed mode */
  2333. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  2334. "src=0x%02x, rssi=%u, tim=%lu usec, "
  2335. "phy=0x%02x, chnl=%d\n",
  2336. title, fc, header->addr1[5],
  2337. header->addr3[5], rssi,
  2338. tsf_low - priv->scan_start_tsf,
  2339. phy_flags, channel);
  2340. }
  2341. }
  2342. if (print_dump)
  2343. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  2344. }
  2345. #else
  2346. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2347. struct iwl_rx_packet *pkt,
  2348. struct ieee80211_hdr *header,
  2349. int group100)
  2350. {
  2351. }
  2352. #endif
  2353. /* Called for REPLY_RX (legacy ABG frames), or
  2354. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  2355. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  2356. struct iwl_rx_mem_buffer *rxb)
  2357. {
  2358. struct ieee80211_hdr *header;
  2359. struct ieee80211_rx_status rx_status;
  2360. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2361. /* Use phy data (Rx signal strength, etc.) contained within
  2362. * this rx packet for legacy frames,
  2363. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  2364. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  2365. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2366. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  2367. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2368. __le32 *rx_end;
  2369. unsigned int len = 0;
  2370. u16 fc;
  2371. u8 network_packet;
  2372. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  2373. rx_status.freq =
  2374. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  2375. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  2376. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  2377. rx_status.rate_idx =
  2378. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  2379. if (rx_status.band == IEEE80211_BAND_5GHZ)
  2380. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  2381. rx_status.antenna = 0;
  2382. rx_status.flag = 0;
  2383. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  2384. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  2385. rx_start->cfg_phy_cnt);
  2386. return;
  2387. }
  2388. if (!include_phy) {
  2389. if (priv->last_phy_res[0])
  2390. rx_start = (struct iwl4965_rx_phy_res *)
  2391. &priv->last_phy_res[1];
  2392. else
  2393. rx_start = NULL;
  2394. }
  2395. if (!rx_start) {
  2396. IWL_ERROR("MPDU frame without a PHY data\n");
  2397. return;
  2398. }
  2399. if (include_phy) {
  2400. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  2401. + rx_start->cfg_phy_cnt);
  2402. len = le16_to_cpu(rx_start->byte_count);
  2403. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  2404. sizeof(struct iwl4965_rx_phy_res) + len);
  2405. } else {
  2406. struct iwl4965_rx_mpdu_res_start *amsdu =
  2407. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2408. header = (void *)(pkt->u.raw +
  2409. sizeof(struct iwl4965_rx_mpdu_res_start));
  2410. len = le16_to_cpu(amsdu->byte_count);
  2411. rx_end = (__le32 *) (pkt->u.raw +
  2412. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  2413. }
  2414. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  2415. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  2416. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  2417. le32_to_cpu(*rx_end));
  2418. return;
  2419. }
  2420. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  2421. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  2422. rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
  2423. /* Meaningful noise values are available only from beacon statistics,
  2424. * which are gathered only when associated, and indicate noise
  2425. * only for the associated network channel ...
  2426. * Ignore these noise values while scanning (other channels) */
  2427. if (iwl_is_associated(priv) &&
  2428. !test_bit(STATUS_SCANNING, &priv->status)) {
  2429. rx_status.noise = priv->last_rx_noise;
  2430. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
  2431. rx_status.noise);
  2432. } else {
  2433. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2434. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
  2435. }
  2436. /* Reset beacon noise level if not associated. */
  2437. if (!iwl_is_associated(priv))
  2438. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2439. /* Set "1" to report good data frames in groups of 100 */
  2440. /* FIXME: need to optimze the call: */
  2441. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  2442. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  2443. rx_status.signal, rx_status.noise, rx_status.signal,
  2444. (unsigned long long)rx_status.mactime);
  2445. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2446. iwl4965_handle_data_packet(priv, 1, include_phy,
  2447. rxb, &rx_status);
  2448. return;
  2449. }
  2450. network_packet = iwl4965_is_network_packet(priv, header);
  2451. if (network_packet) {
  2452. priv->last_rx_rssi = rx_status.signal;
  2453. priv->last_beacon_time = priv->ucode_beacon_time;
  2454. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  2455. }
  2456. fc = le16_to_cpu(header->frame_control);
  2457. switch (fc & IEEE80211_FCTL_FTYPE) {
  2458. case IEEE80211_FTYPE_MGMT:
  2459. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2460. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2461. header->addr2);
  2462. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  2463. break;
  2464. case IEEE80211_FTYPE_CTL:
  2465. #ifdef CONFIG_IWL4965_HT
  2466. switch (fc & IEEE80211_FCTL_STYPE) {
  2467. case IEEE80211_STYPE_BACK_REQ:
  2468. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  2469. iwl4965_handle_data_packet(priv, 0, include_phy,
  2470. rxb, &rx_status);
  2471. break;
  2472. default:
  2473. break;
  2474. }
  2475. #endif
  2476. break;
  2477. case IEEE80211_FTYPE_DATA: {
  2478. DECLARE_MAC_BUF(mac1);
  2479. DECLARE_MAC_BUF(mac2);
  2480. DECLARE_MAC_BUF(mac3);
  2481. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2482. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2483. header->addr2);
  2484. if (unlikely(!network_packet))
  2485. IWL_DEBUG_DROP("Dropping (non network): "
  2486. "%s, %s, %s\n",
  2487. print_mac(mac1, header->addr1),
  2488. print_mac(mac2, header->addr2),
  2489. print_mac(mac3, header->addr3));
  2490. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  2491. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  2492. print_mac(mac1, header->addr1),
  2493. print_mac(mac2, header->addr2),
  2494. print_mac(mac3, header->addr3));
  2495. else
  2496. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  2497. &rx_status);
  2498. break;
  2499. }
  2500. default:
  2501. break;
  2502. }
  2503. }
  2504. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  2505. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  2506. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  2507. struct iwl_rx_mem_buffer *rxb)
  2508. {
  2509. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2510. priv->last_phy_res[0] = 1;
  2511. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  2512. sizeof(struct iwl4965_rx_phy_res));
  2513. }
  2514. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  2515. struct iwl_rx_mem_buffer *rxb)
  2516. {
  2517. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  2518. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2519. struct iwl4965_missed_beacon_notif *missed_beacon;
  2520. missed_beacon = &pkt->u.missed_beacon;
  2521. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  2522. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  2523. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  2524. le32_to_cpu(missed_beacon->total_missed_becons),
  2525. le32_to_cpu(missed_beacon->num_recvd_beacons),
  2526. le32_to_cpu(missed_beacon->num_expected_beacons));
  2527. if (!test_bit(STATUS_SCANNING, &priv->status))
  2528. iwl_init_sensitivity(priv);
  2529. }
  2530. #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
  2531. }
  2532. #ifdef CONFIG_IWL4965_HT
  2533. /**
  2534. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  2535. */
  2536. static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  2537. int sta_id, int tid)
  2538. {
  2539. unsigned long flags;
  2540. /* Remove "disable" flag, to enable Tx for this TID */
  2541. spin_lock_irqsave(&priv->sta_lock, flags);
  2542. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  2543. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  2544. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2545. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2546. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2547. }
  2548. /**
  2549. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  2550. *
  2551. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  2552. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  2553. */
  2554. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  2555. struct iwl_ht_agg *agg,
  2556. struct iwl4965_compressed_ba_resp*
  2557. ba_resp)
  2558. {
  2559. int i, sh, ack;
  2560. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  2561. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2562. u64 bitmap;
  2563. int successes = 0;
  2564. struct ieee80211_tx_info *info;
  2565. if (unlikely(!agg->wait_for_ba)) {
  2566. IWL_ERROR("Received BA when not expected\n");
  2567. return -EINVAL;
  2568. }
  2569. /* Mark that the expected block-ack response arrived */
  2570. agg->wait_for_ba = 0;
  2571. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  2572. /* Calculate shift to align block-ack bits with our Tx window bits */
  2573. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  2574. if (sh < 0) /* tbw something is wrong with indices */
  2575. sh += 0x100;
  2576. /* don't use 64-bit values for now */
  2577. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  2578. if (agg->frame_count > (64 - sh)) {
  2579. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  2580. return -1;
  2581. }
  2582. /* check for success or failure according to the
  2583. * transmitted bitmap and block-ack bitmap */
  2584. bitmap &= agg->bitmap;
  2585. /* For each frame attempted in aggregation,
  2586. * update driver's record of tx frame's status. */
  2587. for (i = 0; i < agg->frame_count ; i++) {
  2588. ack = bitmap & (1 << i);
  2589. successes += !!ack;
  2590. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  2591. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  2592. agg->start_idx + i);
  2593. }
  2594. info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
  2595. memset(&info->status, 0, sizeof(info->status));
  2596. info->flags = IEEE80211_TX_STAT_ACK;
  2597. info->flags |= IEEE80211_TX_STAT_AMPDU;
  2598. info->status.ampdu_ack_map = successes;
  2599. info->status.ampdu_ack_len = agg->frame_count;
  2600. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
  2601. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  2602. return 0;
  2603. }
  2604. /**
  2605. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  2606. */
  2607. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  2608. u16 txq_id)
  2609. {
  2610. /* Simply stop the queue, but don't change any configuration;
  2611. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  2612. iwl_write_prph(priv,
  2613. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2614. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  2615. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  2616. }
  2617. /**
  2618. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  2619. * priv->lock must be held by the caller
  2620. */
  2621. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  2622. u16 ssn_idx, u8 tx_fifo)
  2623. {
  2624. int ret = 0;
  2625. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  2626. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2627. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2628. return -EINVAL;
  2629. }
  2630. ret = iwl_grab_nic_access(priv);
  2631. if (ret)
  2632. return ret;
  2633. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2634. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2635. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2636. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2637. /* supposes that ssn_idx is valid (!= 0xFFF) */
  2638. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2639. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2640. iwl_txq_ctx_deactivate(priv, txq_id);
  2641. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  2642. iwl_release_nic_access(priv);
  2643. return 0;
  2644. }
  2645. int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
  2646. u8 tid, int txq_id)
  2647. {
  2648. struct iwl_queue *q = &priv->txq[txq_id].q;
  2649. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  2650. struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  2651. switch (priv->stations[sta_id].tid[tid].agg.state) {
  2652. case IWL_EMPTYING_HW_QUEUE_DELBA:
  2653. /* We are reclaiming the last packet of the */
  2654. /* aggregated HW queue */
  2655. if (txq_id == tid_data->agg.txq_id &&
  2656. q->read_ptr == q->write_ptr) {
  2657. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  2658. int tx_fifo = default_tid_to_tx_fifo[tid];
  2659. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  2660. iwl4965_tx_queue_agg_disable(priv, txq_id,
  2661. ssn, tx_fifo);
  2662. tid_data->agg.state = IWL_AGG_OFF;
  2663. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  2664. }
  2665. break;
  2666. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  2667. /* We are reclaiming the last packet of the queue */
  2668. if (tid_data->tfds_in_queue == 0) {
  2669. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  2670. tid_data->agg.state = IWL_AGG_ON;
  2671. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  2672. }
  2673. break;
  2674. }
  2675. return 0;
  2676. }
  2677. /**
  2678. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  2679. *
  2680. * Handles block-acknowledge notification from device, which reports success
  2681. * of frames sent via aggregation.
  2682. */
  2683. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  2684. struct iwl_rx_mem_buffer *rxb)
  2685. {
  2686. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2687. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  2688. int index;
  2689. struct iwl_tx_queue *txq = NULL;
  2690. struct iwl_ht_agg *agg;
  2691. DECLARE_MAC_BUF(mac);
  2692. /* "flow" corresponds to Tx queue */
  2693. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2694. /* "ssn" is start of block-ack Tx window, corresponds to index
  2695. * (in Tx queue's circular buffer) of first TFD/frame in window */
  2696. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  2697. if (scd_flow >= priv->hw_params.max_txq_num) {
  2698. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  2699. return;
  2700. }
  2701. txq = &priv->txq[scd_flow];
  2702. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  2703. /* Find index just before block-ack window */
  2704. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  2705. /* TODO: Need to get this copy more safely - now good for debug */
  2706. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  2707. "sta_id = %d\n",
  2708. agg->wait_for_ba,
  2709. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  2710. ba_resp->sta_id);
  2711. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  2712. "%d, scd_ssn = %d\n",
  2713. ba_resp->tid,
  2714. ba_resp->seq_ctl,
  2715. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  2716. ba_resp->scd_flow,
  2717. ba_resp->scd_ssn);
  2718. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  2719. agg->start_idx,
  2720. (unsigned long long)agg->bitmap);
  2721. /* Update driver's record of ACK vs. not for each frame in window */
  2722. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  2723. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  2724. * block-ack window (we assume that they've been successfully
  2725. * transmitted ... if not, it's too late anyway). */
  2726. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  2727. /* calculate mac80211 ampdu sw queue to wake */
  2728. int ampdu_q =
  2729. scd_flow - IWL_BACK_QUEUE_FIRST_ID + priv->hw->queues;
  2730. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  2731. priv->stations[ba_resp->sta_id].
  2732. tid[ba_resp->tid].tfds_in_queue -= freed;
  2733. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2734. priv->mac80211_registered &&
  2735. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  2736. ieee80211_wake_queue(priv->hw, ampdu_q);
  2737. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  2738. ba_resp->tid, scd_flow);
  2739. }
  2740. }
  2741. /**
  2742. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  2743. */
  2744. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  2745. u16 txq_id)
  2746. {
  2747. u32 tbl_dw_addr;
  2748. u32 tbl_dw;
  2749. u16 scd_q2ratid;
  2750. scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  2751. tbl_dw_addr = priv->scd_base_addr +
  2752. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  2753. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  2754. if (txq_id & 0x1)
  2755. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  2756. else
  2757. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  2758. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  2759. return 0;
  2760. }
  2761. /**
  2762. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  2763. *
  2764. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  2765. * i.e. it must be one of the higher queues used for aggregation
  2766. */
  2767. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  2768. int tx_fifo, int sta_id, int tid,
  2769. u16 ssn_idx)
  2770. {
  2771. unsigned long flags;
  2772. int rc;
  2773. u16 ra_tid;
  2774. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  2775. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2776. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2777. ra_tid = BUILD_RAxTID(sta_id, tid);
  2778. /* Modify device's station table to Tx this TID */
  2779. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  2780. spin_lock_irqsave(&priv->lock, flags);
  2781. rc = iwl_grab_nic_access(priv);
  2782. if (rc) {
  2783. spin_unlock_irqrestore(&priv->lock, flags);
  2784. return rc;
  2785. }
  2786. /* Stop this Tx queue before configuring it */
  2787. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2788. /* Map receiver-address / traffic-ID to this queue */
  2789. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  2790. /* Set this queue as a chain-building queue */
  2791. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2792. /* Place first TFD at index corresponding to start sequence number.
  2793. * Assumes that ssn_idx is valid (!= 0xFFF) */
  2794. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2795. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2796. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2797. /* Set up Tx window size and frame limit for this queue */
  2798. iwl_write_targ_mem(priv,
  2799. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  2800. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  2801. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  2802. iwl_write_targ_mem(priv, priv->scd_base_addr +
  2803. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  2804. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  2805. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  2806. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2807. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  2808. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  2809. iwl_release_nic_access(priv);
  2810. spin_unlock_irqrestore(&priv->lock, flags);
  2811. return 0;
  2812. }
  2813. #endif /* CONFIG_IWL4965_HT */
  2814. #ifdef CONFIG_IWL4965_HT
  2815. static int iwl4965_rx_agg_start(struct iwl_priv *priv,
  2816. const u8 *addr, int tid, u16 ssn)
  2817. {
  2818. unsigned long flags;
  2819. int sta_id;
  2820. sta_id = iwl_find_station(priv, addr);
  2821. if (sta_id == IWL_INVALID_STATION)
  2822. return -ENXIO;
  2823. spin_lock_irqsave(&priv->sta_lock, flags);
  2824. priv->stations[sta_id].sta.station_flags_msk = 0;
  2825. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  2826. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  2827. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  2828. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2829. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2830. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2831. CMD_ASYNC);
  2832. }
  2833. static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
  2834. const u8 *addr, int tid)
  2835. {
  2836. unsigned long flags;
  2837. int sta_id;
  2838. sta_id = iwl_find_station(priv, addr);
  2839. if (sta_id == IWL_INVALID_STATION)
  2840. return -ENXIO;
  2841. spin_lock_irqsave(&priv->sta_lock, flags);
  2842. priv->stations[sta_id].sta.station_flags_msk = 0;
  2843. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  2844. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  2845. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2846. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2847. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2848. CMD_ASYNC);
  2849. }
  2850. /*
  2851. * Find first available (lowest unused) Tx Queue, mark it "active".
  2852. * Called only when finding queue for aggregation.
  2853. * Should never return anything < 7, because they should already
  2854. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  2855. */
  2856. static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
  2857. {
  2858. int txq_id;
  2859. for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
  2860. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  2861. return txq_id;
  2862. return -1;
  2863. }
  2864. static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
  2865. u16 tid, u16 *start_seq_num)
  2866. {
  2867. struct iwl_priv *priv = hw->priv;
  2868. int sta_id;
  2869. int tx_fifo;
  2870. int txq_id;
  2871. int ssn = -1;
  2872. int ret = 0;
  2873. unsigned long flags;
  2874. struct iwl_tid_data *tid_data;
  2875. DECLARE_MAC_BUF(mac);
  2876. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  2877. tx_fifo = default_tid_to_tx_fifo[tid];
  2878. else
  2879. return -EINVAL;
  2880. IWL_WARNING("%s on ra = %s tid = %d\n",
  2881. __func__, print_mac(mac, ra), tid);
  2882. sta_id = iwl_find_station(priv, ra);
  2883. if (sta_id == IWL_INVALID_STATION)
  2884. return -ENXIO;
  2885. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  2886. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  2887. return -ENXIO;
  2888. }
  2889. txq_id = iwl4965_txq_ctx_activate_free(priv);
  2890. if (txq_id == -1)
  2891. return -ENXIO;
  2892. spin_lock_irqsave(&priv->sta_lock, flags);
  2893. tid_data = &priv->stations[sta_id].tid[tid];
  2894. ssn = SEQ_TO_SN(tid_data->seq_number);
  2895. tid_data->agg.txq_id = txq_id;
  2896. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2897. *start_seq_num = ssn;
  2898. ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  2899. sta_id, tid, ssn);
  2900. if (ret)
  2901. return ret;
  2902. ret = 0;
  2903. if (tid_data->tfds_in_queue == 0) {
  2904. printk(KERN_ERR "HW queue is empty\n");
  2905. tid_data->agg.state = IWL_AGG_ON;
  2906. ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
  2907. } else {
  2908. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  2909. tid_data->tfds_in_queue);
  2910. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  2911. }
  2912. return ret;
  2913. }
  2914. static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
  2915. {
  2916. struct iwl_priv *priv = hw->priv;
  2917. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  2918. struct iwl_tid_data *tid_data;
  2919. int ret, write_ptr, read_ptr;
  2920. unsigned long flags;
  2921. DECLARE_MAC_BUF(mac);
  2922. if (!ra) {
  2923. IWL_ERROR("ra = NULL\n");
  2924. return -EINVAL;
  2925. }
  2926. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  2927. tx_fifo_id = default_tid_to_tx_fifo[tid];
  2928. else
  2929. return -EINVAL;
  2930. sta_id = iwl_find_station(priv, ra);
  2931. if (sta_id == IWL_INVALID_STATION)
  2932. return -ENXIO;
  2933. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  2934. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  2935. tid_data = &priv->stations[sta_id].tid[tid];
  2936. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  2937. txq_id = tid_data->agg.txq_id;
  2938. write_ptr = priv->txq[txq_id].q.write_ptr;
  2939. read_ptr = priv->txq[txq_id].q.read_ptr;
  2940. /* The queue is not empty */
  2941. if (write_ptr != read_ptr) {
  2942. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  2943. priv->stations[sta_id].tid[tid].agg.state =
  2944. IWL_EMPTYING_HW_QUEUE_DELBA;
  2945. return 0;
  2946. }
  2947. IWL_DEBUG_HT("HW queue is empty\n");
  2948. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  2949. spin_lock_irqsave(&priv->lock, flags);
  2950. ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  2951. spin_unlock_irqrestore(&priv->lock, flags);
  2952. if (ret)
  2953. return ret;
  2954. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
  2955. return 0;
  2956. }
  2957. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  2958. enum ieee80211_ampdu_mlme_action action,
  2959. const u8 *addr, u16 tid, u16 *ssn)
  2960. {
  2961. struct iwl_priv *priv = hw->priv;
  2962. DECLARE_MAC_BUF(mac);
  2963. IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
  2964. print_mac(mac, addr), tid);
  2965. switch (action) {
  2966. case IEEE80211_AMPDU_RX_START:
  2967. IWL_DEBUG_HT("start Rx\n");
  2968. return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
  2969. case IEEE80211_AMPDU_RX_STOP:
  2970. IWL_DEBUG_HT("stop Rx\n");
  2971. return iwl4965_rx_agg_stop(priv, addr, tid);
  2972. case IEEE80211_AMPDU_TX_START:
  2973. IWL_DEBUG_HT("start Tx\n");
  2974. return iwl4965_tx_agg_start(hw, addr, tid, ssn);
  2975. case IEEE80211_AMPDU_TX_STOP:
  2976. IWL_DEBUG_HT("stop Tx\n");
  2977. return iwl4965_tx_agg_stop(hw, addr, tid);
  2978. default:
  2979. IWL_DEBUG_HT("unknown\n");
  2980. return -EINVAL;
  2981. break;
  2982. }
  2983. return 0;
  2984. }
  2985. #endif /* CONFIG_IWL4965_HT */
  2986. static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
  2987. {
  2988. switch (cmd_id) {
  2989. case REPLY_RXON:
  2990. return (u16) sizeof(struct iwl4965_rxon_cmd);
  2991. default:
  2992. return len;
  2993. }
  2994. }
  2995. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  2996. {
  2997. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  2998. addsta->mode = cmd->mode;
  2999. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  3000. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  3001. addsta->station_flags = cmd->station_flags;
  3002. addsta->station_flags_msk = cmd->station_flags_msk;
  3003. addsta->tid_disable_tx = cmd->tid_disable_tx;
  3004. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  3005. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  3006. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  3007. addsta->reserved1 = __constant_cpu_to_le16(0);
  3008. addsta->reserved2 = __constant_cpu_to_le32(0);
  3009. return (u16)sizeof(struct iwl4965_addsta_cmd);
  3010. }
  3011. /* Set up 4965-specific Rx frame reply handlers */
  3012. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  3013. {
  3014. /* Legacy Rx frames */
  3015. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  3016. /* High-throughput (HT) Rx frames */
  3017. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  3018. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  3019. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  3020. iwl4965_rx_missed_beacon_notif;
  3021. #ifdef CONFIG_IWL4965_HT
  3022. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  3023. #endif /* CONFIG_IWL4965_HT */
  3024. }
  3025. void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
  3026. {
  3027. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  3028. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  3029. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  3030. #endif
  3031. init_timer(&priv->statistics_periodic);
  3032. priv->statistics_periodic.data = (unsigned long)priv;
  3033. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  3034. }
  3035. void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
  3036. {
  3037. del_timer_sync(&priv->statistics_periodic);
  3038. cancel_delayed_work(&priv->init_alive_start);
  3039. }
  3040. static struct iwl_hcmd_ops iwl4965_hcmd = {
  3041. .rxon_assoc = iwl4965_send_rxon_assoc,
  3042. };
  3043. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  3044. .get_hcmd_size = iwl4965_get_hcmd_size,
  3045. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  3046. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  3047. .chain_noise_reset = iwl4965_chain_noise_reset,
  3048. .gain_computation = iwl4965_gain_computation,
  3049. #endif
  3050. };
  3051. static struct iwl_lib_ops iwl4965_lib = {
  3052. .set_hw_params = iwl4965_hw_set_hw_params,
  3053. .alloc_shared_mem = iwl4965_alloc_shared_mem,
  3054. .free_shared_mem = iwl4965_free_shared_mem,
  3055. .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
  3056. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  3057. .disable_tx_fifo = iwl4965_disable_tx_fifo,
  3058. .rx_handler_setup = iwl4965_rx_handler_setup,
  3059. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  3060. .alive_notify = iwl4965_alive_notify,
  3061. .init_alive_start = iwl4965_init_alive_start,
  3062. .load_ucode = iwl4965_load_bsm,
  3063. .apm_ops = {
  3064. .init = iwl4965_apm_init,
  3065. .config = iwl4965_nic_config,
  3066. .set_pwr_src = iwl4965_set_pwr_src,
  3067. },
  3068. .eeprom_ops = {
  3069. .regulatory_bands = {
  3070. EEPROM_REGULATORY_BAND_1_CHANNELS,
  3071. EEPROM_REGULATORY_BAND_2_CHANNELS,
  3072. EEPROM_REGULATORY_BAND_3_CHANNELS,
  3073. EEPROM_REGULATORY_BAND_4_CHANNELS,
  3074. EEPROM_REGULATORY_BAND_5_CHANNELS,
  3075. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  3076. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  3077. },
  3078. .verify_signature = iwlcore_eeprom_verify_signature,
  3079. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  3080. .release_semaphore = iwlcore_eeprom_release_semaphore,
  3081. .check_version = iwl4965_eeprom_check_version,
  3082. .query_addr = iwlcore_eeprom_query_addr,
  3083. },
  3084. .radio_kill_sw = iwl4965_radio_kill_sw,
  3085. .set_power = iwl4965_set_power,
  3086. .update_chain_flags = iwl4965_update_chain_flags,
  3087. };
  3088. static struct iwl_ops iwl4965_ops = {
  3089. .lib = &iwl4965_lib,
  3090. .hcmd = &iwl4965_hcmd,
  3091. .utils = &iwl4965_hcmd_utils,
  3092. };
  3093. struct iwl_cfg iwl4965_agn_cfg = {
  3094. .name = "4965AGN",
  3095. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  3096. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  3097. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  3098. .ops = &iwl4965_ops,
  3099. .mod_params = &iwl4965_mod_params,
  3100. };
  3101. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  3102. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3103. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  3104. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  3105. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  3106. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
  3107. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  3108. MODULE_PARM_DESC(debug, "debug output mask");
  3109. module_param_named(
  3110. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  3111. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3112. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  3113. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3114. /* QoS */
  3115. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  3116. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  3117. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  3118. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3119. module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
  3120. MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");