qeth_core_main.c 131 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. struct kmem_cache *qeth_core_header_cache;
  47. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  48. static struct device *qeth_core_root_dev;
  49. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  50. static struct lock_class_key qdio_out_skb_queue_key;
  51. static void qeth_send_control_data_cb(struct qeth_channel *,
  52. struct qeth_cmd_buffer *);
  53. static int qeth_issue_next_read(struct qeth_card *);
  54. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  55. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  56. static void qeth_free_buffer_pool(struct qeth_card *);
  57. static int qeth_qdio_establish(struct qeth_card *);
  58. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  59. struct qdio_buffer *buffer, int is_tso,
  60. int *next_element_to_fill)
  61. {
  62. struct skb_frag_struct *frag;
  63. int fragno;
  64. unsigned long addr;
  65. int element, cnt, dlen;
  66. fragno = skb_shinfo(skb)->nr_frags;
  67. element = *next_element_to_fill;
  68. dlen = 0;
  69. if (is_tso)
  70. buffer->element[element].flags =
  71. SBAL_FLAGS_MIDDLE_FRAG;
  72. else
  73. buffer->element[element].flags =
  74. SBAL_FLAGS_FIRST_FRAG;
  75. dlen = skb->len - skb->data_len;
  76. if (dlen) {
  77. buffer->element[element].addr = skb->data;
  78. buffer->element[element].length = dlen;
  79. element++;
  80. }
  81. for (cnt = 0; cnt < fragno; cnt++) {
  82. frag = &skb_shinfo(skb)->frags[cnt];
  83. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  84. frag->page_offset;
  85. buffer->element[element].addr = (char *)addr;
  86. buffer->element[element].length = frag->size;
  87. if (cnt < (fragno - 1))
  88. buffer->element[element].flags =
  89. SBAL_FLAGS_MIDDLE_FRAG;
  90. else
  91. buffer->element[element].flags =
  92. SBAL_FLAGS_LAST_FRAG;
  93. element++;
  94. }
  95. *next_element_to_fill = element;
  96. }
  97. static inline const char *qeth_get_cardname(struct qeth_card *card)
  98. {
  99. if (card->info.guestlan) {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. return " Guest LAN QDIO";
  103. case QETH_CARD_TYPE_IQD:
  104. return " Guest LAN Hiper";
  105. case QETH_CARD_TYPE_OSM:
  106. return " Guest LAN QDIO - OSM";
  107. case QETH_CARD_TYPE_OSX:
  108. return " Guest LAN QDIO - OSX";
  109. default:
  110. return " unknown";
  111. }
  112. } else {
  113. switch (card->info.type) {
  114. case QETH_CARD_TYPE_OSD:
  115. return " OSD Express";
  116. case QETH_CARD_TYPE_IQD:
  117. return " HiperSockets";
  118. case QETH_CARD_TYPE_OSN:
  119. return " OSN QDIO";
  120. case QETH_CARD_TYPE_OSM:
  121. return " OSM QDIO";
  122. case QETH_CARD_TYPE_OSX:
  123. return " OSX QDIO";
  124. default:
  125. return " unknown";
  126. }
  127. }
  128. return " n/a";
  129. }
  130. /* max length to be returned: 14 */
  131. const char *qeth_get_cardname_short(struct qeth_card *card)
  132. {
  133. if (card->info.guestlan) {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSD:
  136. return "GuestLAN QDIO";
  137. case QETH_CARD_TYPE_IQD:
  138. return "GuestLAN Hiper";
  139. case QETH_CARD_TYPE_OSM:
  140. return "GuestLAN OSM";
  141. case QETH_CARD_TYPE_OSX:
  142. return "GuestLAN OSX";
  143. default:
  144. return "unknown";
  145. }
  146. } else {
  147. switch (card->info.type) {
  148. case QETH_CARD_TYPE_OSD:
  149. switch (card->info.link_type) {
  150. case QETH_LINK_TYPE_FAST_ETH:
  151. return "OSD_100";
  152. case QETH_LINK_TYPE_HSTR:
  153. return "HSTR";
  154. case QETH_LINK_TYPE_GBIT_ETH:
  155. return "OSD_1000";
  156. case QETH_LINK_TYPE_10GBIT_ETH:
  157. return "OSD_10GIG";
  158. case QETH_LINK_TYPE_LANE_ETH100:
  159. return "OSD_FE_LANE";
  160. case QETH_LINK_TYPE_LANE_TR:
  161. return "OSD_TR_LANE";
  162. case QETH_LINK_TYPE_LANE_ETH1000:
  163. return "OSD_GbE_LANE";
  164. case QETH_LINK_TYPE_LANE:
  165. return "OSD_ATM_LANE";
  166. default:
  167. return "OSD_Express";
  168. }
  169. case QETH_CARD_TYPE_IQD:
  170. return "HiperSockets";
  171. case QETH_CARD_TYPE_OSN:
  172. return "OSN";
  173. case QETH_CARD_TYPE_OSM:
  174. return "OSM_1000";
  175. case QETH_CARD_TYPE_OSX:
  176. return "OSX_10GIG";
  177. default:
  178. return "unknown";
  179. }
  180. }
  181. return "n/a";
  182. }
  183. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  184. int clear_start_mask)
  185. {
  186. unsigned long flags;
  187. spin_lock_irqsave(&card->thread_mask_lock, flags);
  188. card->thread_allowed_mask = threads;
  189. if (clear_start_mask)
  190. card->thread_start_mask &= threads;
  191. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  192. wake_up(&card->wait_q);
  193. }
  194. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  195. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  196. {
  197. unsigned long flags;
  198. int rc = 0;
  199. spin_lock_irqsave(&card->thread_mask_lock, flags);
  200. rc = (card->thread_running_mask & threads);
  201. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  202. return rc;
  203. }
  204. EXPORT_SYMBOL_GPL(qeth_threads_running);
  205. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  206. {
  207. return wait_event_interruptible(card->wait_q,
  208. qeth_threads_running(card, threads) == 0);
  209. }
  210. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  211. void qeth_clear_working_pool_list(struct qeth_card *card)
  212. {
  213. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  214. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  215. list_for_each_entry_safe(pool_entry, tmp,
  216. &card->qdio.in_buf_pool.entry_list, list){
  217. list_del(&pool_entry->list);
  218. }
  219. }
  220. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  221. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  222. {
  223. struct qeth_buffer_pool_entry *pool_entry;
  224. void *ptr;
  225. int i, j;
  226. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  227. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  228. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  229. if (!pool_entry) {
  230. qeth_free_buffer_pool(card);
  231. return -ENOMEM;
  232. }
  233. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  234. ptr = (void *) __get_free_page(GFP_KERNEL);
  235. if (!ptr) {
  236. while (j > 0)
  237. free_page((unsigned long)
  238. pool_entry->elements[--j]);
  239. kfree(pool_entry);
  240. qeth_free_buffer_pool(card);
  241. return -ENOMEM;
  242. }
  243. pool_entry->elements[j] = ptr;
  244. }
  245. list_add(&pool_entry->init_list,
  246. &card->qdio.init_pool.entry_list);
  247. }
  248. return 0;
  249. }
  250. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  251. {
  252. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  253. if ((card->state != CARD_STATE_DOWN) &&
  254. (card->state != CARD_STATE_RECOVER))
  255. return -EPERM;
  256. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  257. qeth_clear_working_pool_list(card);
  258. qeth_free_buffer_pool(card);
  259. card->qdio.in_buf_pool.buf_count = bufcnt;
  260. card->qdio.init_pool.buf_count = bufcnt;
  261. return qeth_alloc_buffer_pool(card);
  262. }
  263. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  264. static int qeth_issue_next_read(struct qeth_card *card)
  265. {
  266. int rc;
  267. struct qeth_cmd_buffer *iob;
  268. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  269. if (card->read.state != CH_STATE_UP)
  270. return -EIO;
  271. iob = qeth_get_buffer(&card->read);
  272. if (!iob) {
  273. dev_warn(&card->gdev->dev, "The qeth device driver "
  274. "failed to recover an error on the device\n");
  275. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  276. "available\n", dev_name(&card->gdev->dev));
  277. return -ENOMEM;
  278. }
  279. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  280. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  281. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  282. (addr_t) iob, 0, 0);
  283. if (rc) {
  284. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  285. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  286. atomic_set(&card->read.irq_pending, 0);
  287. qeth_schedule_recovery(card);
  288. wake_up(&card->wait_q);
  289. }
  290. return rc;
  291. }
  292. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  293. {
  294. struct qeth_reply *reply;
  295. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  296. if (reply) {
  297. atomic_set(&reply->refcnt, 1);
  298. atomic_set(&reply->received, 0);
  299. reply->card = card;
  300. };
  301. return reply;
  302. }
  303. static void qeth_get_reply(struct qeth_reply *reply)
  304. {
  305. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  306. atomic_inc(&reply->refcnt);
  307. }
  308. static void qeth_put_reply(struct qeth_reply *reply)
  309. {
  310. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  311. if (atomic_dec_and_test(&reply->refcnt))
  312. kfree(reply);
  313. }
  314. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  315. struct qeth_card *card)
  316. {
  317. char *ipa_name;
  318. int com = cmd->hdr.command;
  319. ipa_name = qeth_get_ipa_cmd_name(com);
  320. if (rc)
  321. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  322. ipa_name, com, QETH_CARD_IFNAME(card),
  323. rc, qeth_get_ipa_msg(rc));
  324. else
  325. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  326. ipa_name, com, QETH_CARD_IFNAME(card));
  327. }
  328. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  329. struct qeth_cmd_buffer *iob)
  330. {
  331. struct qeth_ipa_cmd *cmd = NULL;
  332. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  333. if (IS_IPA(iob->data)) {
  334. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  335. if (IS_IPA_REPLY(cmd)) {
  336. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  337. cmd->hdr.command != IPA_CMD_DELCCID &&
  338. cmd->hdr.command != IPA_CMD_MODCCID &&
  339. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  340. qeth_issue_ipa_msg(cmd,
  341. cmd->hdr.return_code, card);
  342. return cmd;
  343. } else {
  344. switch (cmd->hdr.command) {
  345. case IPA_CMD_STOPLAN:
  346. dev_warn(&card->gdev->dev,
  347. "The link for interface %s on CHPID"
  348. " 0x%X failed\n",
  349. QETH_CARD_IFNAME(card),
  350. card->info.chpid);
  351. card->lan_online = 0;
  352. if (card->dev && netif_carrier_ok(card->dev))
  353. netif_carrier_off(card->dev);
  354. return NULL;
  355. case IPA_CMD_STARTLAN:
  356. dev_info(&card->gdev->dev,
  357. "The link for %s on CHPID 0x%X has"
  358. " been restored\n",
  359. QETH_CARD_IFNAME(card),
  360. card->info.chpid);
  361. netif_carrier_on(card->dev);
  362. card->lan_online = 1;
  363. qeth_schedule_recovery(card);
  364. return NULL;
  365. case IPA_CMD_MODCCID:
  366. return cmd;
  367. case IPA_CMD_REGISTER_LOCAL_ADDR:
  368. QETH_DBF_TEXT(TRACE, 3, "irla");
  369. break;
  370. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  371. QETH_DBF_TEXT(TRACE, 3, "urla");
  372. break;
  373. default:
  374. QETH_DBF_MESSAGE(2, "Received data is IPA "
  375. "but not a reply!\n");
  376. break;
  377. }
  378. }
  379. }
  380. return cmd;
  381. }
  382. void qeth_clear_ipacmd_list(struct qeth_card *card)
  383. {
  384. struct qeth_reply *reply, *r;
  385. unsigned long flags;
  386. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  387. spin_lock_irqsave(&card->lock, flags);
  388. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  389. qeth_get_reply(reply);
  390. reply->rc = -EIO;
  391. atomic_inc(&reply->received);
  392. list_del_init(&reply->list);
  393. wake_up(&reply->wait_q);
  394. qeth_put_reply(reply);
  395. }
  396. spin_unlock_irqrestore(&card->lock, flags);
  397. }
  398. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  399. static int qeth_check_idx_response(struct qeth_card *card,
  400. unsigned char *buffer)
  401. {
  402. if (!buffer)
  403. return 0;
  404. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  405. if ((buffer[2] & 0xc0) == 0xc0) {
  406. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  407. "with cause code 0x%02x%s\n",
  408. buffer[4],
  409. ((buffer[4] == 0x22) ?
  410. " -- try another portname" : ""));
  411. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  412. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  413. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  414. if (buffer[4] == 0xf6) {
  415. dev_err(&card->gdev->dev,
  416. "The qeth device is not configured "
  417. "for the OSI layer required by z/VM\n");
  418. return -EPERM;
  419. }
  420. return -EIO;
  421. }
  422. return 0;
  423. }
  424. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  425. __u32 len)
  426. {
  427. struct qeth_card *card;
  428. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  429. card = CARD_FROM_CDEV(channel->ccwdev);
  430. if (channel == &card->read)
  431. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  432. else
  433. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  434. channel->ccw.count = len;
  435. channel->ccw.cda = (__u32) __pa(iob);
  436. }
  437. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  438. {
  439. __u8 index;
  440. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  441. index = channel->io_buf_no;
  442. do {
  443. if (channel->iob[index].state == BUF_STATE_FREE) {
  444. channel->iob[index].state = BUF_STATE_LOCKED;
  445. channel->io_buf_no = (channel->io_buf_no + 1) %
  446. QETH_CMD_BUFFER_NO;
  447. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  448. return channel->iob + index;
  449. }
  450. index = (index + 1) % QETH_CMD_BUFFER_NO;
  451. } while (index != channel->io_buf_no);
  452. return NULL;
  453. }
  454. void qeth_release_buffer(struct qeth_channel *channel,
  455. struct qeth_cmd_buffer *iob)
  456. {
  457. unsigned long flags;
  458. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  459. spin_lock_irqsave(&channel->iob_lock, flags);
  460. memset(iob->data, 0, QETH_BUFSIZE);
  461. iob->state = BUF_STATE_FREE;
  462. iob->callback = qeth_send_control_data_cb;
  463. iob->rc = 0;
  464. spin_unlock_irqrestore(&channel->iob_lock, flags);
  465. }
  466. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  467. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  468. {
  469. struct qeth_cmd_buffer *buffer = NULL;
  470. unsigned long flags;
  471. spin_lock_irqsave(&channel->iob_lock, flags);
  472. buffer = __qeth_get_buffer(channel);
  473. spin_unlock_irqrestore(&channel->iob_lock, flags);
  474. return buffer;
  475. }
  476. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  477. {
  478. struct qeth_cmd_buffer *buffer;
  479. wait_event(channel->wait_q,
  480. ((buffer = qeth_get_buffer(channel)) != NULL));
  481. return buffer;
  482. }
  483. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  484. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  485. {
  486. int cnt;
  487. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  488. qeth_release_buffer(channel, &channel->iob[cnt]);
  489. channel->buf_no = 0;
  490. channel->io_buf_no = 0;
  491. }
  492. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  493. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  494. struct qeth_cmd_buffer *iob)
  495. {
  496. struct qeth_card *card;
  497. struct qeth_reply *reply, *r;
  498. struct qeth_ipa_cmd *cmd;
  499. unsigned long flags;
  500. int keep_reply;
  501. int rc = 0;
  502. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  503. card = CARD_FROM_CDEV(channel->ccwdev);
  504. rc = qeth_check_idx_response(card, iob->data);
  505. switch (rc) {
  506. case 0:
  507. break;
  508. case -EIO:
  509. qeth_clear_ipacmd_list(card);
  510. qeth_schedule_recovery(card);
  511. default:
  512. goto out;
  513. }
  514. cmd = qeth_check_ipa_data(card, iob);
  515. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  516. goto out;
  517. /*in case of OSN : check if cmd is set */
  518. if (card->info.type == QETH_CARD_TYPE_OSN &&
  519. cmd &&
  520. cmd->hdr.command != IPA_CMD_STARTLAN &&
  521. card->osn_info.assist_cb != NULL) {
  522. card->osn_info.assist_cb(card->dev, cmd);
  523. goto out;
  524. }
  525. spin_lock_irqsave(&card->lock, flags);
  526. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  527. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  528. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  529. qeth_get_reply(reply);
  530. list_del_init(&reply->list);
  531. spin_unlock_irqrestore(&card->lock, flags);
  532. keep_reply = 0;
  533. if (reply->callback != NULL) {
  534. if (cmd) {
  535. reply->offset = (__u16)((char *)cmd -
  536. (char *)iob->data);
  537. keep_reply = reply->callback(card,
  538. reply,
  539. (unsigned long)cmd);
  540. } else
  541. keep_reply = reply->callback(card,
  542. reply,
  543. (unsigned long)iob);
  544. }
  545. if (cmd)
  546. reply->rc = (u16) cmd->hdr.return_code;
  547. else if (iob->rc)
  548. reply->rc = iob->rc;
  549. if (keep_reply) {
  550. spin_lock_irqsave(&card->lock, flags);
  551. list_add_tail(&reply->list,
  552. &card->cmd_waiter_list);
  553. spin_unlock_irqrestore(&card->lock, flags);
  554. } else {
  555. atomic_inc(&reply->received);
  556. wake_up(&reply->wait_q);
  557. }
  558. qeth_put_reply(reply);
  559. goto out;
  560. }
  561. }
  562. spin_unlock_irqrestore(&card->lock, flags);
  563. out:
  564. memcpy(&card->seqno.pdu_hdr_ack,
  565. QETH_PDU_HEADER_SEQ_NO(iob->data),
  566. QETH_SEQ_NO_LENGTH);
  567. qeth_release_buffer(channel, iob);
  568. }
  569. static int qeth_setup_channel(struct qeth_channel *channel)
  570. {
  571. int cnt;
  572. QETH_DBF_TEXT(SETUP, 2, "setupch");
  573. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  574. channel->iob[cnt].data =
  575. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  576. if (channel->iob[cnt].data == NULL)
  577. break;
  578. channel->iob[cnt].state = BUF_STATE_FREE;
  579. channel->iob[cnt].channel = channel;
  580. channel->iob[cnt].callback = qeth_send_control_data_cb;
  581. channel->iob[cnt].rc = 0;
  582. }
  583. if (cnt < QETH_CMD_BUFFER_NO) {
  584. while (cnt-- > 0)
  585. kfree(channel->iob[cnt].data);
  586. return -ENOMEM;
  587. }
  588. channel->buf_no = 0;
  589. channel->io_buf_no = 0;
  590. atomic_set(&channel->irq_pending, 0);
  591. spin_lock_init(&channel->iob_lock);
  592. init_waitqueue_head(&channel->wait_q);
  593. return 0;
  594. }
  595. static int qeth_set_thread_start_bit(struct qeth_card *card,
  596. unsigned long thread)
  597. {
  598. unsigned long flags;
  599. spin_lock_irqsave(&card->thread_mask_lock, flags);
  600. if (!(card->thread_allowed_mask & thread) ||
  601. (card->thread_start_mask & thread)) {
  602. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  603. return -EPERM;
  604. }
  605. card->thread_start_mask |= thread;
  606. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  607. return 0;
  608. }
  609. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  610. {
  611. unsigned long flags;
  612. spin_lock_irqsave(&card->thread_mask_lock, flags);
  613. card->thread_start_mask &= ~thread;
  614. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  615. wake_up(&card->wait_q);
  616. }
  617. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  618. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  619. {
  620. unsigned long flags;
  621. spin_lock_irqsave(&card->thread_mask_lock, flags);
  622. card->thread_running_mask &= ~thread;
  623. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  624. wake_up(&card->wait_q);
  625. }
  626. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  627. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  628. {
  629. unsigned long flags;
  630. int rc = 0;
  631. spin_lock_irqsave(&card->thread_mask_lock, flags);
  632. if (card->thread_start_mask & thread) {
  633. if ((card->thread_allowed_mask & thread) &&
  634. !(card->thread_running_mask & thread)) {
  635. rc = 1;
  636. card->thread_start_mask &= ~thread;
  637. card->thread_running_mask |= thread;
  638. } else
  639. rc = -EPERM;
  640. }
  641. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  642. return rc;
  643. }
  644. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  645. {
  646. int rc = 0;
  647. wait_event(card->wait_q,
  648. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  649. return rc;
  650. }
  651. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  652. void qeth_schedule_recovery(struct qeth_card *card)
  653. {
  654. QETH_DBF_TEXT(TRACE, 2, "startrec");
  655. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  656. schedule_work(&card->kernel_thread_starter);
  657. }
  658. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  659. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  660. {
  661. int dstat, cstat;
  662. char *sense;
  663. sense = (char *) irb->ecw;
  664. cstat = irb->scsw.cmd.cstat;
  665. dstat = irb->scsw.cmd.dstat;
  666. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  667. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  668. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  669. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  670. dev_warn(&cdev->dev, "The qeth device driver "
  671. "failed to recover an error on the device\n");
  672. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  673. dev_name(&cdev->dev), dstat, cstat);
  674. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  675. 16, 1, irb, 64, 1);
  676. return 1;
  677. }
  678. if (dstat & DEV_STAT_UNIT_CHECK) {
  679. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  680. SENSE_RESETTING_EVENT_FLAG) {
  681. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  682. return 1;
  683. }
  684. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  685. SENSE_COMMAND_REJECT_FLAG) {
  686. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  687. return 1;
  688. }
  689. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  690. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  691. return 1;
  692. }
  693. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  694. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  695. return 0;
  696. }
  697. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  698. return 1;
  699. }
  700. return 0;
  701. }
  702. static long __qeth_check_irb_error(struct ccw_device *cdev,
  703. unsigned long intparm, struct irb *irb)
  704. {
  705. if (!IS_ERR(irb))
  706. return 0;
  707. switch (PTR_ERR(irb)) {
  708. case -EIO:
  709. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  710. dev_name(&cdev->dev));
  711. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  712. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  713. break;
  714. case -ETIMEDOUT:
  715. dev_warn(&cdev->dev, "A hardware operation timed out"
  716. " on the device\n");
  717. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  718. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  719. if (intparm == QETH_RCD_PARM) {
  720. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  721. if (card && (card->data.ccwdev == cdev)) {
  722. card->data.state = CH_STATE_DOWN;
  723. wake_up(&card->wait_q);
  724. }
  725. }
  726. break;
  727. default:
  728. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  729. dev_name(&cdev->dev), PTR_ERR(irb));
  730. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  731. QETH_DBF_TEXT(TRACE, 2, " rc???");
  732. }
  733. return PTR_ERR(irb);
  734. }
  735. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  736. struct irb *irb)
  737. {
  738. int rc;
  739. int cstat, dstat;
  740. struct qeth_cmd_buffer *buffer;
  741. struct qeth_channel *channel;
  742. struct qeth_card *card;
  743. struct qeth_cmd_buffer *iob;
  744. __u8 index;
  745. QETH_DBF_TEXT(TRACE, 5, "irq");
  746. if (__qeth_check_irb_error(cdev, intparm, irb))
  747. return;
  748. cstat = irb->scsw.cmd.cstat;
  749. dstat = irb->scsw.cmd.dstat;
  750. card = CARD_FROM_CDEV(cdev);
  751. if (!card)
  752. return;
  753. if (card->read.ccwdev == cdev) {
  754. channel = &card->read;
  755. QETH_DBF_TEXT(TRACE, 5, "read");
  756. } else if (card->write.ccwdev == cdev) {
  757. channel = &card->write;
  758. QETH_DBF_TEXT(TRACE, 5, "write");
  759. } else {
  760. channel = &card->data;
  761. QETH_DBF_TEXT(TRACE, 5, "data");
  762. }
  763. atomic_set(&channel->irq_pending, 0);
  764. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  765. channel->state = CH_STATE_STOPPED;
  766. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  767. channel->state = CH_STATE_HALTED;
  768. /*let's wake up immediately on data channel*/
  769. if ((channel == &card->data) && (intparm != 0) &&
  770. (intparm != QETH_RCD_PARM))
  771. goto out;
  772. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  773. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  774. /* we don't have to handle this further */
  775. intparm = 0;
  776. }
  777. if (intparm == QETH_HALT_CHANNEL_PARM) {
  778. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  779. /* we don't have to handle this further */
  780. intparm = 0;
  781. }
  782. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  783. (dstat & DEV_STAT_UNIT_CHECK) ||
  784. (cstat)) {
  785. if (irb->esw.esw0.erw.cons) {
  786. dev_warn(&channel->ccwdev->dev,
  787. "The qeth device driver failed to recover "
  788. "an error on the device\n");
  789. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  790. "0x%X dstat 0x%X\n",
  791. dev_name(&channel->ccwdev->dev), cstat, dstat);
  792. print_hex_dump(KERN_WARNING, "qeth: irb ",
  793. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  794. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  795. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  796. }
  797. if (intparm == QETH_RCD_PARM) {
  798. channel->state = CH_STATE_DOWN;
  799. goto out;
  800. }
  801. rc = qeth_get_problem(cdev, irb);
  802. if (rc) {
  803. qeth_clear_ipacmd_list(card);
  804. qeth_schedule_recovery(card);
  805. goto out;
  806. }
  807. }
  808. if (intparm == QETH_RCD_PARM) {
  809. channel->state = CH_STATE_RCD_DONE;
  810. goto out;
  811. }
  812. if (intparm) {
  813. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  814. buffer->state = BUF_STATE_PROCESSED;
  815. }
  816. if (channel == &card->data)
  817. return;
  818. if (channel == &card->read &&
  819. channel->state == CH_STATE_UP)
  820. qeth_issue_next_read(card);
  821. iob = channel->iob;
  822. index = channel->buf_no;
  823. while (iob[index].state == BUF_STATE_PROCESSED) {
  824. if (iob[index].callback != NULL)
  825. iob[index].callback(channel, iob + index);
  826. index = (index + 1) % QETH_CMD_BUFFER_NO;
  827. }
  828. channel->buf_no = index;
  829. out:
  830. wake_up(&card->wait_q);
  831. return;
  832. }
  833. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  834. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  835. {
  836. int i;
  837. struct sk_buff *skb;
  838. /* is PCI flag set on buffer? */
  839. if (buf->buffer->element[0].flags & 0x40)
  840. atomic_dec(&queue->set_pci_flags_count);
  841. if (!qeth_skip_skb) {
  842. skb = skb_dequeue(&buf->skb_list);
  843. while (skb) {
  844. atomic_dec(&skb->users);
  845. dev_kfree_skb_any(skb);
  846. skb = skb_dequeue(&buf->skb_list);
  847. }
  848. }
  849. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  850. if (buf->buffer->element[i].addr && buf->is_header[i])
  851. kmem_cache_free(qeth_core_header_cache,
  852. buf->buffer->element[i].addr);
  853. buf->is_header[i] = 0;
  854. buf->buffer->element[i].length = 0;
  855. buf->buffer->element[i].addr = NULL;
  856. buf->buffer->element[i].flags = 0;
  857. }
  858. buf->buffer->element[15].flags = 0;
  859. buf->next_element_to_fill = 0;
  860. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  861. }
  862. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  863. struct qeth_qdio_out_buffer *buf)
  864. {
  865. __qeth_clear_output_buffer(queue, buf, 0);
  866. }
  867. void qeth_clear_qdio_buffers(struct qeth_card *card)
  868. {
  869. int i, j;
  870. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  871. /* clear outbound buffers to free skbs */
  872. for (i = 0; i < card->qdio.no_out_queues; ++i)
  873. if (card->qdio.out_qs[i]) {
  874. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  875. qeth_clear_output_buffer(card->qdio.out_qs[i],
  876. &card->qdio.out_qs[i]->bufs[j]);
  877. }
  878. }
  879. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  880. static void qeth_free_buffer_pool(struct qeth_card *card)
  881. {
  882. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  883. int i = 0;
  884. QETH_DBF_TEXT(TRACE, 5, "freepool");
  885. list_for_each_entry_safe(pool_entry, tmp,
  886. &card->qdio.init_pool.entry_list, init_list){
  887. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  888. free_page((unsigned long)pool_entry->elements[i]);
  889. list_del(&pool_entry->init_list);
  890. kfree(pool_entry);
  891. }
  892. }
  893. static void qeth_free_qdio_buffers(struct qeth_card *card)
  894. {
  895. int i, j;
  896. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  897. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  898. QETH_QDIO_UNINITIALIZED)
  899. return;
  900. kfree(card->qdio.in_q);
  901. card->qdio.in_q = NULL;
  902. /* inbound buffer pool */
  903. qeth_free_buffer_pool(card);
  904. /* free outbound qdio_qs */
  905. if (card->qdio.out_qs) {
  906. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  907. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  908. qeth_clear_output_buffer(card->qdio.out_qs[i],
  909. &card->qdio.out_qs[i]->bufs[j]);
  910. kfree(card->qdio.out_qs[i]);
  911. }
  912. kfree(card->qdio.out_qs);
  913. card->qdio.out_qs = NULL;
  914. }
  915. }
  916. static void qeth_clean_channel(struct qeth_channel *channel)
  917. {
  918. int cnt;
  919. QETH_DBF_TEXT(SETUP, 2, "freech");
  920. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  921. kfree(channel->iob[cnt].data);
  922. }
  923. static void qeth_get_channel_path_desc(struct qeth_card *card)
  924. {
  925. struct ccw_device *ccwdev;
  926. struct channelPath_dsc {
  927. u8 flags;
  928. u8 lsn;
  929. u8 desc;
  930. u8 chpid;
  931. u8 swla;
  932. u8 zeroes;
  933. u8 chla;
  934. u8 chpp;
  935. } *chp_dsc;
  936. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  937. ccwdev = card->data.ccwdev;
  938. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  939. if (chp_dsc != NULL) {
  940. /* CHPP field bit 6 == 1 -> single queue */
  941. if ((chp_dsc->chpp & 0x02) == 0x02)
  942. card->qdio.no_out_queues = 1;
  943. card->info.func_level = 0x4100 + chp_dsc->desc;
  944. kfree(chp_dsc);
  945. }
  946. if (card->qdio.no_out_queues == 1) {
  947. card->qdio.default_out_queue = 0;
  948. dev_info(&card->gdev->dev,
  949. "Priority Queueing not supported\n");
  950. }
  951. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  952. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  953. return;
  954. }
  955. static void qeth_init_qdio_info(struct qeth_card *card)
  956. {
  957. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  958. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  959. /* inbound */
  960. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  961. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  962. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  963. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  964. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  965. }
  966. static void qeth_set_intial_options(struct qeth_card *card)
  967. {
  968. card->options.route4.type = NO_ROUTER;
  969. card->options.route6.type = NO_ROUTER;
  970. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  971. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  972. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  973. card->options.fake_broadcast = 0;
  974. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  975. card->options.performance_stats = 0;
  976. card->options.rx_sg_cb = QETH_RX_SG_CB;
  977. card->options.isolation = ISOLATION_MODE_NONE;
  978. }
  979. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  980. {
  981. unsigned long flags;
  982. int rc = 0;
  983. spin_lock_irqsave(&card->thread_mask_lock, flags);
  984. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  985. (u8) card->thread_start_mask,
  986. (u8) card->thread_allowed_mask,
  987. (u8) card->thread_running_mask);
  988. rc = (card->thread_start_mask & thread);
  989. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  990. return rc;
  991. }
  992. static void qeth_start_kernel_thread(struct work_struct *work)
  993. {
  994. struct qeth_card *card = container_of(work, struct qeth_card,
  995. kernel_thread_starter);
  996. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  997. if (card->read.state != CH_STATE_UP &&
  998. card->write.state != CH_STATE_UP)
  999. return;
  1000. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  1001. kthread_run(card->discipline.recover, (void *) card,
  1002. "qeth_recover");
  1003. }
  1004. static int qeth_setup_card(struct qeth_card *card)
  1005. {
  1006. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1007. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1008. card->read.state = CH_STATE_DOWN;
  1009. card->write.state = CH_STATE_DOWN;
  1010. card->data.state = CH_STATE_DOWN;
  1011. card->state = CARD_STATE_DOWN;
  1012. card->lan_online = 0;
  1013. card->use_hard_stop = 0;
  1014. card->dev = NULL;
  1015. spin_lock_init(&card->vlanlock);
  1016. spin_lock_init(&card->mclock);
  1017. card->vlangrp = NULL;
  1018. spin_lock_init(&card->lock);
  1019. spin_lock_init(&card->ip_lock);
  1020. spin_lock_init(&card->thread_mask_lock);
  1021. mutex_init(&card->conf_mutex);
  1022. card->thread_start_mask = 0;
  1023. card->thread_allowed_mask = 0;
  1024. card->thread_running_mask = 0;
  1025. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1026. INIT_LIST_HEAD(&card->ip_list);
  1027. INIT_LIST_HEAD(card->ip_tbd_list);
  1028. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1029. init_waitqueue_head(&card->wait_q);
  1030. /* intial options */
  1031. qeth_set_intial_options(card);
  1032. /* IP address takeover */
  1033. INIT_LIST_HEAD(&card->ipato.entries);
  1034. card->ipato.enabled = 0;
  1035. card->ipato.invert4 = 0;
  1036. card->ipato.invert6 = 0;
  1037. /* init QDIO stuff */
  1038. qeth_init_qdio_info(card);
  1039. return 0;
  1040. }
  1041. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1042. {
  1043. struct qeth_card *card = container_of(slr, struct qeth_card,
  1044. qeth_service_level);
  1045. if (card->info.mcl_level[0])
  1046. seq_printf(m, "qeth: %s firmware level %s\n",
  1047. CARD_BUS_ID(card), card->info.mcl_level);
  1048. }
  1049. static struct qeth_card *qeth_alloc_card(void)
  1050. {
  1051. struct qeth_card *card;
  1052. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1053. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1054. if (!card)
  1055. goto out;
  1056. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1057. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1058. if (!card->ip_tbd_list) {
  1059. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1060. goto out_card;
  1061. }
  1062. if (qeth_setup_channel(&card->read))
  1063. goto out_ip;
  1064. if (qeth_setup_channel(&card->write))
  1065. goto out_channel;
  1066. card->options.layer2 = -1;
  1067. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1068. register_service_level(&card->qeth_service_level);
  1069. return card;
  1070. out_channel:
  1071. qeth_clean_channel(&card->read);
  1072. out_ip:
  1073. kfree(card->ip_tbd_list);
  1074. out_card:
  1075. kfree(card);
  1076. out:
  1077. return NULL;
  1078. }
  1079. static int qeth_determine_card_type(struct qeth_card *card)
  1080. {
  1081. int i = 0;
  1082. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1083. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1084. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1085. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1086. if ((CARD_RDEV(card)->id.dev_type ==
  1087. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1088. (CARD_RDEV(card)->id.dev_model ==
  1089. known_devices[i][QETH_DEV_MODEL_IND])) {
  1090. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1091. card->qdio.no_out_queues =
  1092. known_devices[i][QETH_QUEUE_NO_IND];
  1093. card->info.is_multicast_different =
  1094. known_devices[i][QETH_MULTICAST_IND];
  1095. qeth_get_channel_path_desc(card);
  1096. return 0;
  1097. }
  1098. i++;
  1099. }
  1100. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1101. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1102. "unknown type\n");
  1103. return -ENOENT;
  1104. }
  1105. static int qeth_clear_channel(struct qeth_channel *channel)
  1106. {
  1107. unsigned long flags;
  1108. struct qeth_card *card;
  1109. int rc;
  1110. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1111. card = CARD_FROM_CDEV(channel->ccwdev);
  1112. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1113. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1114. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1115. if (rc)
  1116. return rc;
  1117. rc = wait_event_interruptible_timeout(card->wait_q,
  1118. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1119. if (rc == -ERESTARTSYS)
  1120. return rc;
  1121. if (channel->state != CH_STATE_STOPPED)
  1122. return -ETIME;
  1123. channel->state = CH_STATE_DOWN;
  1124. return 0;
  1125. }
  1126. static int qeth_halt_channel(struct qeth_channel *channel)
  1127. {
  1128. unsigned long flags;
  1129. struct qeth_card *card;
  1130. int rc;
  1131. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1132. card = CARD_FROM_CDEV(channel->ccwdev);
  1133. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1134. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1135. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1136. if (rc)
  1137. return rc;
  1138. rc = wait_event_interruptible_timeout(card->wait_q,
  1139. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1140. if (rc == -ERESTARTSYS)
  1141. return rc;
  1142. if (channel->state != CH_STATE_HALTED)
  1143. return -ETIME;
  1144. return 0;
  1145. }
  1146. static int qeth_halt_channels(struct qeth_card *card)
  1147. {
  1148. int rc1 = 0, rc2 = 0, rc3 = 0;
  1149. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1150. rc1 = qeth_halt_channel(&card->read);
  1151. rc2 = qeth_halt_channel(&card->write);
  1152. rc3 = qeth_halt_channel(&card->data);
  1153. if (rc1)
  1154. return rc1;
  1155. if (rc2)
  1156. return rc2;
  1157. return rc3;
  1158. }
  1159. static int qeth_clear_channels(struct qeth_card *card)
  1160. {
  1161. int rc1 = 0, rc2 = 0, rc3 = 0;
  1162. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1163. rc1 = qeth_clear_channel(&card->read);
  1164. rc2 = qeth_clear_channel(&card->write);
  1165. rc3 = qeth_clear_channel(&card->data);
  1166. if (rc1)
  1167. return rc1;
  1168. if (rc2)
  1169. return rc2;
  1170. return rc3;
  1171. }
  1172. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1173. {
  1174. int rc = 0;
  1175. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1176. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1177. if (halt)
  1178. rc = qeth_halt_channels(card);
  1179. if (rc)
  1180. return rc;
  1181. return qeth_clear_channels(card);
  1182. }
  1183. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1184. {
  1185. int rc = 0;
  1186. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1187. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1188. QETH_QDIO_CLEANING)) {
  1189. case QETH_QDIO_ESTABLISHED:
  1190. if (card->info.type == QETH_CARD_TYPE_IQD)
  1191. rc = qdio_shutdown(CARD_DDEV(card),
  1192. QDIO_FLAG_CLEANUP_USING_HALT);
  1193. else
  1194. rc = qdio_shutdown(CARD_DDEV(card),
  1195. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1196. if (rc)
  1197. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1198. qdio_free(CARD_DDEV(card));
  1199. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1200. break;
  1201. case QETH_QDIO_CLEANING:
  1202. return rc;
  1203. default:
  1204. break;
  1205. }
  1206. rc = qeth_clear_halt_card(card, use_halt);
  1207. if (rc)
  1208. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1209. card->state = CARD_STATE_DOWN;
  1210. return rc;
  1211. }
  1212. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1213. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1214. int *length)
  1215. {
  1216. struct ciw *ciw;
  1217. char *rcd_buf;
  1218. int ret;
  1219. struct qeth_channel *channel = &card->data;
  1220. unsigned long flags;
  1221. /*
  1222. * scan for RCD command in extended SenseID data
  1223. */
  1224. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1225. if (!ciw || ciw->cmd == 0)
  1226. return -EOPNOTSUPP;
  1227. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1228. if (!rcd_buf)
  1229. return -ENOMEM;
  1230. channel->ccw.cmd_code = ciw->cmd;
  1231. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1232. channel->ccw.count = ciw->count;
  1233. channel->ccw.flags = CCW_FLAG_SLI;
  1234. channel->state = CH_STATE_RCD;
  1235. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1236. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1237. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1238. QETH_RCD_TIMEOUT);
  1239. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1240. if (!ret)
  1241. wait_event(card->wait_q,
  1242. (channel->state == CH_STATE_RCD_DONE ||
  1243. channel->state == CH_STATE_DOWN));
  1244. if (channel->state == CH_STATE_DOWN)
  1245. ret = -EIO;
  1246. else
  1247. channel->state = CH_STATE_DOWN;
  1248. if (ret) {
  1249. kfree(rcd_buf);
  1250. *buffer = NULL;
  1251. *length = 0;
  1252. } else {
  1253. *length = ciw->count;
  1254. *buffer = rcd_buf;
  1255. }
  1256. return ret;
  1257. }
  1258. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1259. {
  1260. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1261. card->info.chpid = prcd[30];
  1262. card->info.unit_addr2 = prcd[31];
  1263. card->info.cula = prcd[63];
  1264. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1265. (prcd[0x11] == _ascebc['M']));
  1266. }
  1267. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1268. {
  1269. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1270. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1271. card->info.blkt.time_total = 250;
  1272. card->info.blkt.inter_packet = 5;
  1273. card->info.blkt.inter_packet_jumbo = 15;
  1274. } else {
  1275. card->info.blkt.time_total = 0;
  1276. card->info.blkt.inter_packet = 0;
  1277. card->info.blkt.inter_packet_jumbo = 0;
  1278. }
  1279. }
  1280. static void qeth_init_tokens(struct qeth_card *card)
  1281. {
  1282. card->token.issuer_rm_w = 0x00010103UL;
  1283. card->token.cm_filter_w = 0x00010108UL;
  1284. card->token.cm_connection_w = 0x0001010aUL;
  1285. card->token.ulp_filter_w = 0x0001010bUL;
  1286. card->token.ulp_connection_w = 0x0001010dUL;
  1287. }
  1288. static void qeth_init_func_level(struct qeth_card *card)
  1289. {
  1290. switch (card->info.type) {
  1291. case QETH_CARD_TYPE_IQD:
  1292. if (card->ipato.enabled)
  1293. card->info.func_level =
  1294. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1295. else
  1296. card->info.func_level =
  1297. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1298. break;
  1299. case QETH_CARD_TYPE_OSD:
  1300. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1301. break;
  1302. default:
  1303. break;
  1304. }
  1305. }
  1306. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1307. void (*idx_reply_cb)(struct qeth_channel *,
  1308. struct qeth_cmd_buffer *))
  1309. {
  1310. struct qeth_cmd_buffer *iob;
  1311. unsigned long flags;
  1312. int rc;
  1313. struct qeth_card *card;
  1314. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1315. card = CARD_FROM_CDEV(channel->ccwdev);
  1316. iob = qeth_get_buffer(channel);
  1317. iob->callback = idx_reply_cb;
  1318. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1319. channel->ccw.count = QETH_BUFSIZE;
  1320. channel->ccw.cda = (__u32) __pa(iob->data);
  1321. wait_event(card->wait_q,
  1322. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1323. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1324. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1325. rc = ccw_device_start(channel->ccwdev,
  1326. &channel->ccw, (addr_t) iob, 0, 0);
  1327. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1328. if (rc) {
  1329. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1330. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1331. atomic_set(&channel->irq_pending, 0);
  1332. wake_up(&card->wait_q);
  1333. return rc;
  1334. }
  1335. rc = wait_event_interruptible_timeout(card->wait_q,
  1336. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1337. if (rc == -ERESTARTSYS)
  1338. return rc;
  1339. if (channel->state != CH_STATE_UP) {
  1340. rc = -ETIME;
  1341. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1342. qeth_clear_cmd_buffers(channel);
  1343. } else
  1344. rc = 0;
  1345. return rc;
  1346. }
  1347. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1348. void (*idx_reply_cb)(struct qeth_channel *,
  1349. struct qeth_cmd_buffer *))
  1350. {
  1351. struct qeth_card *card;
  1352. struct qeth_cmd_buffer *iob;
  1353. unsigned long flags;
  1354. __u16 temp;
  1355. __u8 tmp;
  1356. int rc;
  1357. struct ccw_dev_id temp_devid;
  1358. card = CARD_FROM_CDEV(channel->ccwdev);
  1359. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1360. iob = qeth_get_buffer(channel);
  1361. iob->callback = idx_reply_cb;
  1362. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1363. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1364. channel->ccw.cda = (__u32) __pa(iob->data);
  1365. if (channel == &card->write) {
  1366. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1367. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1368. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1369. card->seqno.trans_hdr++;
  1370. } else {
  1371. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1372. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1373. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1374. }
  1375. tmp = ((__u8)card->info.portno) | 0x80;
  1376. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1377. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1378. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1379. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1380. &card->info.func_level, sizeof(__u16));
  1381. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1382. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1383. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1384. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1385. wait_event(card->wait_q,
  1386. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1387. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1388. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1389. rc = ccw_device_start(channel->ccwdev,
  1390. &channel->ccw, (addr_t) iob, 0, 0);
  1391. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1392. if (rc) {
  1393. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1394. rc);
  1395. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1396. atomic_set(&channel->irq_pending, 0);
  1397. wake_up(&card->wait_q);
  1398. return rc;
  1399. }
  1400. rc = wait_event_interruptible_timeout(card->wait_q,
  1401. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1402. if (rc == -ERESTARTSYS)
  1403. return rc;
  1404. if (channel->state != CH_STATE_ACTIVATING) {
  1405. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1406. " failed to recover an error on the device\n");
  1407. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1408. dev_name(&channel->ccwdev->dev));
  1409. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1410. qeth_clear_cmd_buffers(channel);
  1411. return -ETIME;
  1412. }
  1413. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1414. }
  1415. static int qeth_peer_func_level(int level)
  1416. {
  1417. if ((level & 0xff) == 8)
  1418. return (level & 0xff) + 0x400;
  1419. if (((level >> 8) & 3) == 1)
  1420. return (level & 0xff) + 0x200;
  1421. return level;
  1422. }
  1423. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1424. struct qeth_cmd_buffer *iob)
  1425. {
  1426. struct qeth_card *card;
  1427. __u16 temp;
  1428. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1429. if (channel->state == CH_STATE_DOWN) {
  1430. channel->state = CH_STATE_ACTIVATING;
  1431. goto out;
  1432. }
  1433. card = CARD_FROM_CDEV(channel->ccwdev);
  1434. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1435. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1436. dev_err(&card->write.ccwdev->dev,
  1437. "The adapter is used exclusively by another "
  1438. "host\n");
  1439. else
  1440. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1441. " negative reply\n",
  1442. dev_name(&card->write.ccwdev->dev));
  1443. goto out;
  1444. }
  1445. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1446. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1447. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1448. "function level mismatch (sent: 0x%x, received: "
  1449. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1450. card->info.func_level, temp);
  1451. goto out;
  1452. }
  1453. channel->state = CH_STATE_UP;
  1454. out:
  1455. qeth_release_buffer(channel, iob);
  1456. }
  1457. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1458. struct qeth_cmd_buffer *iob)
  1459. {
  1460. struct qeth_card *card;
  1461. __u16 temp;
  1462. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1463. if (channel->state == CH_STATE_DOWN) {
  1464. channel->state = CH_STATE_ACTIVATING;
  1465. goto out;
  1466. }
  1467. card = CARD_FROM_CDEV(channel->ccwdev);
  1468. if (qeth_check_idx_response(card, iob->data))
  1469. goto out;
  1470. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1471. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1472. case QETH_IDX_ACT_ERR_EXCL:
  1473. dev_err(&card->write.ccwdev->dev,
  1474. "The adapter is used exclusively by another "
  1475. "host\n");
  1476. break;
  1477. case QETH_IDX_ACT_ERR_AUTH:
  1478. dev_err(&card->read.ccwdev->dev,
  1479. "Setting the device online failed because of "
  1480. "insufficient LPAR authorization\n");
  1481. break;
  1482. default:
  1483. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1484. " negative reply\n",
  1485. dev_name(&card->read.ccwdev->dev));
  1486. }
  1487. goto out;
  1488. }
  1489. /**
  1490. * * temporary fix for microcode bug
  1491. * * to revert it,replace OR by AND
  1492. * */
  1493. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1494. (card->info.type == QETH_CARD_TYPE_OSD))
  1495. card->info.portname_required = 1;
  1496. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1497. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1498. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1499. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1500. dev_name(&card->read.ccwdev->dev),
  1501. card->info.func_level, temp);
  1502. goto out;
  1503. }
  1504. memcpy(&card->token.issuer_rm_r,
  1505. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1506. QETH_MPC_TOKEN_LENGTH);
  1507. memcpy(&card->info.mcl_level[0],
  1508. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1509. channel->state = CH_STATE_UP;
  1510. out:
  1511. qeth_release_buffer(channel, iob);
  1512. }
  1513. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1514. struct qeth_cmd_buffer *iob)
  1515. {
  1516. qeth_setup_ccw(&card->write, iob->data, len);
  1517. iob->callback = qeth_release_buffer;
  1518. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1519. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1520. card->seqno.trans_hdr++;
  1521. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1522. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1523. card->seqno.pdu_hdr++;
  1524. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1525. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1526. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1527. }
  1528. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1529. int qeth_send_control_data(struct qeth_card *card, int len,
  1530. struct qeth_cmd_buffer *iob,
  1531. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1532. unsigned long),
  1533. void *reply_param)
  1534. {
  1535. int rc;
  1536. unsigned long flags;
  1537. struct qeth_reply *reply = NULL;
  1538. unsigned long timeout, event_timeout;
  1539. struct qeth_ipa_cmd *cmd;
  1540. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1541. reply = qeth_alloc_reply(card);
  1542. if (!reply) {
  1543. return -ENOMEM;
  1544. }
  1545. reply->callback = reply_cb;
  1546. reply->param = reply_param;
  1547. if (card->state == CARD_STATE_DOWN)
  1548. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1549. else
  1550. reply->seqno = card->seqno.ipa++;
  1551. init_waitqueue_head(&reply->wait_q);
  1552. spin_lock_irqsave(&card->lock, flags);
  1553. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1554. spin_unlock_irqrestore(&card->lock, flags);
  1555. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1556. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1557. qeth_prepare_control_data(card, len, iob);
  1558. if (IS_IPA(iob->data))
  1559. event_timeout = QETH_IPA_TIMEOUT;
  1560. else
  1561. event_timeout = QETH_TIMEOUT;
  1562. timeout = jiffies + event_timeout;
  1563. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1564. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1565. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1566. (addr_t) iob, 0, 0);
  1567. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1568. if (rc) {
  1569. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1570. "ccw_device_start rc = %i\n",
  1571. dev_name(&card->write.ccwdev->dev), rc);
  1572. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1573. spin_lock_irqsave(&card->lock, flags);
  1574. list_del_init(&reply->list);
  1575. qeth_put_reply(reply);
  1576. spin_unlock_irqrestore(&card->lock, flags);
  1577. qeth_release_buffer(iob->channel, iob);
  1578. atomic_set(&card->write.irq_pending, 0);
  1579. wake_up(&card->wait_q);
  1580. return rc;
  1581. }
  1582. /* we have only one long running ipassist, since we can ensure
  1583. process context of this command we can sleep */
  1584. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1585. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1586. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1587. if (!wait_event_timeout(reply->wait_q,
  1588. atomic_read(&reply->received), event_timeout))
  1589. goto time_err;
  1590. } else {
  1591. while (!atomic_read(&reply->received)) {
  1592. if (time_after(jiffies, timeout))
  1593. goto time_err;
  1594. cpu_relax();
  1595. };
  1596. }
  1597. rc = reply->rc;
  1598. qeth_put_reply(reply);
  1599. return rc;
  1600. time_err:
  1601. spin_lock_irqsave(&reply->card->lock, flags);
  1602. list_del_init(&reply->list);
  1603. spin_unlock_irqrestore(&reply->card->lock, flags);
  1604. reply->rc = -ETIME;
  1605. atomic_inc(&reply->received);
  1606. wake_up(&reply->wait_q);
  1607. rc = reply->rc;
  1608. qeth_put_reply(reply);
  1609. return rc;
  1610. }
  1611. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1612. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1613. unsigned long data)
  1614. {
  1615. struct qeth_cmd_buffer *iob;
  1616. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1617. iob = (struct qeth_cmd_buffer *) data;
  1618. memcpy(&card->token.cm_filter_r,
  1619. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1620. QETH_MPC_TOKEN_LENGTH);
  1621. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1622. return 0;
  1623. }
  1624. static int qeth_cm_enable(struct qeth_card *card)
  1625. {
  1626. int rc;
  1627. struct qeth_cmd_buffer *iob;
  1628. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1629. iob = qeth_wait_for_buffer(&card->write);
  1630. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1631. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1632. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1633. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1634. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1635. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1636. qeth_cm_enable_cb, NULL);
  1637. return rc;
  1638. }
  1639. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1640. unsigned long data)
  1641. {
  1642. struct qeth_cmd_buffer *iob;
  1643. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1644. iob = (struct qeth_cmd_buffer *) data;
  1645. memcpy(&card->token.cm_connection_r,
  1646. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1647. QETH_MPC_TOKEN_LENGTH);
  1648. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1649. return 0;
  1650. }
  1651. static int qeth_cm_setup(struct qeth_card *card)
  1652. {
  1653. int rc;
  1654. struct qeth_cmd_buffer *iob;
  1655. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1656. iob = qeth_wait_for_buffer(&card->write);
  1657. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1658. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1659. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1660. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1661. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1662. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1663. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1664. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1665. qeth_cm_setup_cb, NULL);
  1666. return rc;
  1667. }
  1668. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1669. {
  1670. switch (card->info.type) {
  1671. case QETH_CARD_TYPE_UNKNOWN:
  1672. return 1500;
  1673. case QETH_CARD_TYPE_IQD:
  1674. return card->info.max_mtu;
  1675. case QETH_CARD_TYPE_OSD:
  1676. switch (card->info.link_type) {
  1677. case QETH_LINK_TYPE_HSTR:
  1678. case QETH_LINK_TYPE_LANE_TR:
  1679. return 2000;
  1680. default:
  1681. return 1492;
  1682. }
  1683. case QETH_CARD_TYPE_OSM:
  1684. case QETH_CARD_TYPE_OSX:
  1685. return 1492;
  1686. default:
  1687. return 1500;
  1688. }
  1689. }
  1690. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1691. {
  1692. switch (cardtype) {
  1693. case QETH_CARD_TYPE_UNKNOWN:
  1694. case QETH_CARD_TYPE_OSD:
  1695. case QETH_CARD_TYPE_OSN:
  1696. case QETH_CARD_TYPE_OSM:
  1697. case QETH_CARD_TYPE_OSX:
  1698. return 61440;
  1699. case QETH_CARD_TYPE_IQD:
  1700. return 57344;
  1701. default:
  1702. return 1500;
  1703. }
  1704. }
  1705. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1706. {
  1707. switch (cardtype) {
  1708. case QETH_CARD_TYPE_IQD:
  1709. return 1;
  1710. default:
  1711. return 0;
  1712. }
  1713. }
  1714. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1715. {
  1716. switch (framesize) {
  1717. case 0x4000:
  1718. return 8192;
  1719. case 0x6000:
  1720. return 16384;
  1721. case 0xa000:
  1722. return 32768;
  1723. case 0xffff:
  1724. return 57344;
  1725. default:
  1726. return 0;
  1727. }
  1728. }
  1729. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1730. {
  1731. switch (card->info.type) {
  1732. case QETH_CARD_TYPE_OSD:
  1733. case QETH_CARD_TYPE_OSM:
  1734. case QETH_CARD_TYPE_OSX:
  1735. return ((mtu >= 576) && (mtu <= 61440));
  1736. case QETH_CARD_TYPE_IQD:
  1737. return ((mtu >= 576) &&
  1738. (mtu <= card->info.max_mtu + 4096 - 32));
  1739. case QETH_CARD_TYPE_OSN:
  1740. case QETH_CARD_TYPE_UNKNOWN:
  1741. default:
  1742. return 1;
  1743. }
  1744. }
  1745. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1746. unsigned long data)
  1747. {
  1748. __u16 mtu, framesize;
  1749. __u16 len;
  1750. __u8 link_type;
  1751. struct qeth_cmd_buffer *iob;
  1752. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1753. iob = (struct qeth_cmd_buffer *) data;
  1754. memcpy(&card->token.ulp_filter_r,
  1755. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1756. QETH_MPC_TOKEN_LENGTH);
  1757. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1758. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1759. mtu = qeth_get_mtu_outof_framesize(framesize);
  1760. if (!mtu) {
  1761. iob->rc = -EINVAL;
  1762. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1763. return 0;
  1764. }
  1765. card->info.max_mtu = mtu;
  1766. card->info.initial_mtu = mtu;
  1767. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1768. } else {
  1769. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1770. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1771. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1772. }
  1773. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1774. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1775. memcpy(&link_type,
  1776. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1777. card->info.link_type = link_type;
  1778. } else
  1779. card->info.link_type = 0;
  1780. QETH_DBF_TEXT_(SETUP, 2, "link%d", link_type);
  1781. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1782. return 0;
  1783. }
  1784. static int qeth_ulp_enable(struct qeth_card *card)
  1785. {
  1786. int rc;
  1787. char prot_type;
  1788. struct qeth_cmd_buffer *iob;
  1789. /*FIXME: trace view callbacks*/
  1790. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1791. iob = qeth_wait_for_buffer(&card->write);
  1792. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1793. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1794. (__u8) card->info.portno;
  1795. if (card->options.layer2)
  1796. if (card->info.type == QETH_CARD_TYPE_OSN)
  1797. prot_type = QETH_PROT_OSN2;
  1798. else
  1799. prot_type = QETH_PROT_LAYER2;
  1800. else
  1801. prot_type = QETH_PROT_TCPIP;
  1802. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1803. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1804. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1805. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1806. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1807. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1808. card->info.portname, 9);
  1809. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1810. qeth_ulp_enable_cb, NULL);
  1811. return rc;
  1812. }
  1813. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1814. unsigned long data)
  1815. {
  1816. struct qeth_cmd_buffer *iob;
  1817. int rc = 0;
  1818. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1819. iob = (struct qeth_cmd_buffer *) data;
  1820. memcpy(&card->token.ulp_connection_r,
  1821. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1822. QETH_MPC_TOKEN_LENGTH);
  1823. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1824. 3)) {
  1825. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1826. dev_err(&card->gdev->dev, "A connection could not be "
  1827. "established because of an OLM limit\n");
  1828. rc = -EMLINK;
  1829. }
  1830. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1831. return rc;
  1832. }
  1833. static int qeth_ulp_setup(struct qeth_card *card)
  1834. {
  1835. int rc;
  1836. __u16 temp;
  1837. struct qeth_cmd_buffer *iob;
  1838. struct ccw_dev_id dev_id;
  1839. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1840. iob = qeth_wait_for_buffer(&card->write);
  1841. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1842. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1843. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1844. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1845. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1846. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1847. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1848. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1849. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1850. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1851. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1852. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1853. qeth_ulp_setup_cb, NULL);
  1854. return rc;
  1855. }
  1856. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1857. {
  1858. int i, j;
  1859. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1860. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1861. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1862. return 0;
  1863. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1864. GFP_KERNEL);
  1865. if (!card->qdio.in_q)
  1866. goto out_nomem;
  1867. QETH_DBF_TEXT(SETUP, 2, "inq");
  1868. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1869. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1870. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1871. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1872. card->qdio.in_q->bufs[i].buffer =
  1873. &card->qdio.in_q->qdio_bufs[i];
  1874. /* inbound buffer pool */
  1875. if (qeth_alloc_buffer_pool(card))
  1876. goto out_freeinq;
  1877. /* outbound */
  1878. card->qdio.out_qs =
  1879. kmalloc(card->qdio.no_out_queues *
  1880. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1881. if (!card->qdio.out_qs)
  1882. goto out_freepool;
  1883. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1884. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1885. GFP_KERNEL);
  1886. if (!card->qdio.out_qs[i])
  1887. goto out_freeoutq;
  1888. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1889. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1890. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1891. card->qdio.out_qs[i]->queue_no = i;
  1892. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1893. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1894. card->qdio.out_qs[i]->bufs[j].buffer =
  1895. &card->qdio.out_qs[i]->qdio_bufs[j];
  1896. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1897. skb_list);
  1898. lockdep_set_class(
  1899. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1900. &qdio_out_skb_queue_key);
  1901. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1902. }
  1903. }
  1904. return 0;
  1905. out_freeoutq:
  1906. while (i > 0)
  1907. kfree(card->qdio.out_qs[--i]);
  1908. kfree(card->qdio.out_qs);
  1909. card->qdio.out_qs = NULL;
  1910. out_freepool:
  1911. qeth_free_buffer_pool(card);
  1912. out_freeinq:
  1913. kfree(card->qdio.in_q);
  1914. card->qdio.in_q = NULL;
  1915. out_nomem:
  1916. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1917. return -ENOMEM;
  1918. }
  1919. static void qeth_create_qib_param_field(struct qeth_card *card,
  1920. char *param_field)
  1921. {
  1922. param_field[0] = _ascebc['P'];
  1923. param_field[1] = _ascebc['C'];
  1924. param_field[2] = _ascebc['I'];
  1925. param_field[3] = _ascebc['T'];
  1926. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1927. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1928. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1929. }
  1930. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1931. char *param_field)
  1932. {
  1933. param_field[16] = _ascebc['B'];
  1934. param_field[17] = _ascebc['L'];
  1935. param_field[18] = _ascebc['K'];
  1936. param_field[19] = _ascebc['T'];
  1937. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1938. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1939. *((unsigned int *) (&param_field[28])) =
  1940. card->info.blkt.inter_packet_jumbo;
  1941. }
  1942. static int qeth_qdio_activate(struct qeth_card *card)
  1943. {
  1944. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1945. return qdio_activate(CARD_DDEV(card));
  1946. }
  1947. static int qeth_dm_act(struct qeth_card *card)
  1948. {
  1949. int rc;
  1950. struct qeth_cmd_buffer *iob;
  1951. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1952. iob = qeth_wait_for_buffer(&card->write);
  1953. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1954. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1955. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1956. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1957. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1958. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1959. return rc;
  1960. }
  1961. static int qeth_mpc_initialize(struct qeth_card *card)
  1962. {
  1963. int rc;
  1964. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1965. rc = qeth_issue_next_read(card);
  1966. if (rc) {
  1967. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1968. return rc;
  1969. }
  1970. rc = qeth_cm_enable(card);
  1971. if (rc) {
  1972. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1973. goto out_qdio;
  1974. }
  1975. rc = qeth_cm_setup(card);
  1976. if (rc) {
  1977. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1978. goto out_qdio;
  1979. }
  1980. rc = qeth_ulp_enable(card);
  1981. if (rc) {
  1982. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1983. goto out_qdio;
  1984. }
  1985. rc = qeth_ulp_setup(card);
  1986. if (rc) {
  1987. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1988. goto out_qdio;
  1989. }
  1990. rc = qeth_alloc_qdio_buffers(card);
  1991. if (rc) {
  1992. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1993. goto out_qdio;
  1994. }
  1995. rc = qeth_qdio_establish(card);
  1996. if (rc) {
  1997. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1998. qeth_free_qdio_buffers(card);
  1999. goto out_qdio;
  2000. }
  2001. rc = qeth_qdio_activate(card);
  2002. if (rc) {
  2003. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2004. goto out_qdio;
  2005. }
  2006. rc = qeth_dm_act(card);
  2007. if (rc) {
  2008. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2009. goto out_qdio;
  2010. }
  2011. return 0;
  2012. out_qdio:
  2013. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2014. return rc;
  2015. }
  2016. static void qeth_print_status_with_portname(struct qeth_card *card)
  2017. {
  2018. char dbf_text[15];
  2019. int i;
  2020. sprintf(dbf_text, "%s", card->info.portname + 1);
  2021. for (i = 0; i < 8; i++)
  2022. dbf_text[i] =
  2023. (char) _ebcasc[(__u8) dbf_text[i]];
  2024. dbf_text[8] = 0;
  2025. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2026. "with link type %s (portname: %s)\n",
  2027. qeth_get_cardname(card),
  2028. (card->info.mcl_level[0]) ? " (level: " : "",
  2029. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2030. (card->info.mcl_level[0]) ? ")" : "",
  2031. qeth_get_cardname_short(card),
  2032. dbf_text);
  2033. }
  2034. static void qeth_print_status_no_portname(struct qeth_card *card)
  2035. {
  2036. if (card->info.portname[0])
  2037. dev_info(&card->gdev->dev, "Device is a%s "
  2038. "card%s%s%s\nwith link type %s "
  2039. "(no portname needed by interface).\n",
  2040. qeth_get_cardname(card),
  2041. (card->info.mcl_level[0]) ? " (level: " : "",
  2042. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2043. (card->info.mcl_level[0]) ? ")" : "",
  2044. qeth_get_cardname_short(card));
  2045. else
  2046. dev_info(&card->gdev->dev, "Device is a%s "
  2047. "card%s%s%s\nwith link type %s.\n",
  2048. qeth_get_cardname(card),
  2049. (card->info.mcl_level[0]) ? " (level: " : "",
  2050. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2051. (card->info.mcl_level[0]) ? ")" : "",
  2052. qeth_get_cardname_short(card));
  2053. }
  2054. void qeth_print_status_message(struct qeth_card *card)
  2055. {
  2056. switch (card->info.type) {
  2057. case QETH_CARD_TYPE_OSD:
  2058. case QETH_CARD_TYPE_OSM:
  2059. case QETH_CARD_TYPE_OSX:
  2060. /* VM will use a non-zero first character
  2061. * to indicate a HiperSockets like reporting
  2062. * of the level OSA sets the first character to zero
  2063. * */
  2064. if (!card->info.mcl_level[0]) {
  2065. sprintf(card->info.mcl_level, "%02x%02x",
  2066. card->info.mcl_level[2],
  2067. card->info.mcl_level[3]);
  2068. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2069. break;
  2070. }
  2071. /* fallthrough */
  2072. case QETH_CARD_TYPE_IQD:
  2073. if ((card->info.guestlan) ||
  2074. (card->info.mcl_level[0] & 0x80)) {
  2075. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2076. card->info.mcl_level[0]];
  2077. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2078. card->info.mcl_level[1]];
  2079. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2080. card->info.mcl_level[2]];
  2081. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2082. card->info.mcl_level[3]];
  2083. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2084. }
  2085. break;
  2086. default:
  2087. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2088. }
  2089. if (card->info.portname_required)
  2090. qeth_print_status_with_portname(card);
  2091. else
  2092. qeth_print_status_no_portname(card);
  2093. }
  2094. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2095. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2096. {
  2097. struct qeth_buffer_pool_entry *entry;
  2098. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2099. list_for_each_entry(entry,
  2100. &card->qdio.init_pool.entry_list, init_list) {
  2101. qeth_put_buffer_pool_entry(card, entry);
  2102. }
  2103. }
  2104. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2105. struct qeth_card *card)
  2106. {
  2107. struct list_head *plh;
  2108. struct qeth_buffer_pool_entry *entry;
  2109. int i, free;
  2110. struct page *page;
  2111. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2112. return NULL;
  2113. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2114. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2115. free = 1;
  2116. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2117. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2118. free = 0;
  2119. break;
  2120. }
  2121. }
  2122. if (free) {
  2123. list_del_init(&entry->list);
  2124. return entry;
  2125. }
  2126. }
  2127. /* no free buffer in pool so take first one and swap pages */
  2128. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2129. struct qeth_buffer_pool_entry, list);
  2130. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2131. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2132. page = alloc_page(GFP_ATOMIC);
  2133. if (!page) {
  2134. return NULL;
  2135. } else {
  2136. free_page((unsigned long)entry->elements[i]);
  2137. entry->elements[i] = page_address(page);
  2138. if (card->options.performance_stats)
  2139. card->perf_stats.sg_alloc_page_rx++;
  2140. }
  2141. }
  2142. }
  2143. list_del_init(&entry->list);
  2144. return entry;
  2145. }
  2146. static int qeth_init_input_buffer(struct qeth_card *card,
  2147. struct qeth_qdio_buffer *buf)
  2148. {
  2149. struct qeth_buffer_pool_entry *pool_entry;
  2150. int i;
  2151. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2152. if (!pool_entry)
  2153. return 1;
  2154. /*
  2155. * since the buffer is accessed only from the input_tasklet
  2156. * there shouldn't be a need to synchronize; also, since we use
  2157. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2158. * buffers
  2159. */
  2160. buf->pool_entry = pool_entry;
  2161. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2162. buf->buffer->element[i].length = PAGE_SIZE;
  2163. buf->buffer->element[i].addr = pool_entry->elements[i];
  2164. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2165. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2166. else
  2167. buf->buffer->element[i].flags = 0;
  2168. }
  2169. return 0;
  2170. }
  2171. int qeth_init_qdio_queues(struct qeth_card *card)
  2172. {
  2173. int i, j;
  2174. int rc;
  2175. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2176. /* inbound queue */
  2177. memset(card->qdio.in_q->qdio_bufs, 0,
  2178. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2179. qeth_initialize_working_pool_list(card);
  2180. /*give only as many buffers to hardware as we have buffer pool entries*/
  2181. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2182. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2183. card->qdio.in_q->next_buf_to_init =
  2184. card->qdio.in_buf_pool.buf_count - 1;
  2185. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2186. card->qdio.in_buf_pool.buf_count - 1);
  2187. if (rc) {
  2188. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2189. return rc;
  2190. }
  2191. /* outbound queue */
  2192. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2193. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2194. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2195. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2196. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2197. &card->qdio.out_qs[i]->bufs[j]);
  2198. }
  2199. card->qdio.out_qs[i]->card = card;
  2200. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2201. card->qdio.out_qs[i]->do_pack = 0;
  2202. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2203. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2204. atomic_set(&card->qdio.out_qs[i]->state,
  2205. QETH_OUT_Q_UNLOCKED);
  2206. }
  2207. return 0;
  2208. }
  2209. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2210. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2211. {
  2212. switch (link_type) {
  2213. case QETH_LINK_TYPE_HSTR:
  2214. return 2;
  2215. default:
  2216. return 1;
  2217. }
  2218. }
  2219. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2220. struct qeth_ipa_cmd *cmd, __u8 command,
  2221. enum qeth_prot_versions prot)
  2222. {
  2223. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2224. cmd->hdr.command = command;
  2225. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2226. cmd->hdr.seqno = card->seqno.ipa;
  2227. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2228. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2229. if (card->options.layer2)
  2230. cmd->hdr.prim_version_no = 2;
  2231. else
  2232. cmd->hdr.prim_version_no = 1;
  2233. cmd->hdr.param_count = 1;
  2234. cmd->hdr.prot_version = prot;
  2235. cmd->hdr.ipa_supported = 0;
  2236. cmd->hdr.ipa_enabled = 0;
  2237. }
  2238. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2239. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2240. {
  2241. struct qeth_cmd_buffer *iob;
  2242. struct qeth_ipa_cmd *cmd;
  2243. iob = qeth_wait_for_buffer(&card->write);
  2244. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2245. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2246. return iob;
  2247. }
  2248. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2249. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2250. char prot_type)
  2251. {
  2252. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2253. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2254. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2255. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2256. }
  2257. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2258. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2259. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2260. unsigned long),
  2261. void *reply_param)
  2262. {
  2263. int rc;
  2264. char prot_type;
  2265. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2266. if (card->options.layer2)
  2267. if (card->info.type == QETH_CARD_TYPE_OSN)
  2268. prot_type = QETH_PROT_OSN2;
  2269. else
  2270. prot_type = QETH_PROT_LAYER2;
  2271. else
  2272. prot_type = QETH_PROT_TCPIP;
  2273. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2274. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2275. iob, reply_cb, reply_param);
  2276. return rc;
  2277. }
  2278. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2279. static int qeth_send_startstoplan(struct qeth_card *card,
  2280. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2281. {
  2282. int rc;
  2283. struct qeth_cmd_buffer *iob;
  2284. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2285. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2286. return rc;
  2287. }
  2288. int qeth_send_startlan(struct qeth_card *card)
  2289. {
  2290. int rc;
  2291. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2292. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2293. return rc;
  2294. }
  2295. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2296. int qeth_send_stoplan(struct qeth_card *card)
  2297. {
  2298. int rc = 0;
  2299. /*
  2300. * TODO: according to the IPA format document page 14,
  2301. * TCP/IP (we!) never issue a STOPLAN
  2302. * is this right ?!?
  2303. */
  2304. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2305. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2306. return rc;
  2307. }
  2308. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2309. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2310. struct qeth_reply *reply, unsigned long data)
  2311. {
  2312. struct qeth_ipa_cmd *cmd;
  2313. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2314. cmd = (struct qeth_ipa_cmd *) data;
  2315. if (cmd->hdr.return_code == 0)
  2316. cmd->hdr.return_code =
  2317. cmd->data.setadapterparms.hdr.return_code;
  2318. return 0;
  2319. }
  2320. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2321. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2322. struct qeth_reply *reply, unsigned long data)
  2323. {
  2324. struct qeth_ipa_cmd *cmd;
  2325. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2326. cmd = (struct qeth_ipa_cmd *) data;
  2327. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2328. card->info.link_type =
  2329. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2330. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2331. }
  2332. card->options.adp.supported_funcs =
  2333. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2334. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2335. }
  2336. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2337. __u32 command, __u32 cmdlen)
  2338. {
  2339. struct qeth_cmd_buffer *iob;
  2340. struct qeth_ipa_cmd *cmd;
  2341. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2342. QETH_PROT_IPV4);
  2343. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2344. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2345. cmd->data.setadapterparms.hdr.command_code = command;
  2346. cmd->data.setadapterparms.hdr.used_total = 1;
  2347. cmd->data.setadapterparms.hdr.seq_no = 1;
  2348. return iob;
  2349. }
  2350. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2351. int qeth_query_setadapterparms(struct qeth_card *card)
  2352. {
  2353. int rc;
  2354. struct qeth_cmd_buffer *iob;
  2355. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2356. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2357. sizeof(struct qeth_ipacmd_setadpparms));
  2358. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2359. return rc;
  2360. }
  2361. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2362. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2363. unsigned int qdio_error, const char *dbftext)
  2364. {
  2365. if (qdio_error) {
  2366. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2367. QETH_DBF_TEXT(QERR, 2, dbftext);
  2368. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2369. buf->element[15].flags & 0xff);
  2370. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2371. buf->element[14].flags & 0xff);
  2372. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2373. if ((buf->element[15].flags & 0xff) == 0x12) {
  2374. card->stats.rx_dropped++;
  2375. return 0;
  2376. } else
  2377. return 1;
  2378. }
  2379. return 0;
  2380. }
  2381. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2382. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2383. {
  2384. struct qeth_qdio_q *queue = card->qdio.in_q;
  2385. int count;
  2386. int i;
  2387. int rc;
  2388. int newcount = 0;
  2389. count = (index < queue->next_buf_to_init)?
  2390. card->qdio.in_buf_pool.buf_count -
  2391. (queue->next_buf_to_init - index) :
  2392. card->qdio.in_buf_pool.buf_count -
  2393. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2394. /* only requeue at a certain threshold to avoid SIGAs */
  2395. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2396. for (i = queue->next_buf_to_init;
  2397. i < queue->next_buf_to_init + count; ++i) {
  2398. if (qeth_init_input_buffer(card,
  2399. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2400. break;
  2401. } else {
  2402. newcount++;
  2403. }
  2404. }
  2405. if (newcount < count) {
  2406. /* we are in memory shortage so we switch back to
  2407. traditional skb allocation and drop packages */
  2408. atomic_set(&card->force_alloc_skb, 3);
  2409. count = newcount;
  2410. } else {
  2411. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2412. }
  2413. /*
  2414. * according to old code it should be avoided to requeue all
  2415. * 128 buffers in order to benefit from PCI avoidance.
  2416. * this function keeps at least one buffer (the buffer at
  2417. * 'index') un-requeued -> this buffer is the first buffer that
  2418. * will be requeued the next time
  2419. */
  2420. if (card->options.performance_stats) {
  2421. card->perf_stats.inbound_do_qdio_cnt++;
  2422. card->perf_stats.inbound_do_qdio_start_time =
  2423. qeth_get_micros();
  2424. }
  2425. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2426. queue->next_buf_to_init, count);
  2427. if (card->options.performance_stats)
  2428. card->perf_stats.inbound_do_qdio_time +=
  2429. qeth_get_micros() -
  2430. card->perf_stats.inbound_do_qdio_start_time;
  2431. if (rc) {
  2432. dev_warn(&card->gdev->dev,
  2433. "QDIO reported an error, rc=%i\n", rc);
  2434. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2435. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2436. }
  2437. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2438. QDIO_MAX_BUFFERS_PER_Q;
  2439. }
  2440. }
  2441. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2442. static int qeth_handle_send_error(struct qeth_card *card,
  2443. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2444. {
  2445. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2446. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2447. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2448. if (sbalf15 == 0) {
  2449. qdio_err = 0;
  2450. } else {
  2451. qdio_err = 1;
  2452. }
  2453. }
  2454. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2455. if (!qdio_err)
  2456. return QETH_SEND_ERROR_NONE;
  2457. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2458. return QETH_SEND_ERROR_RETRY;
  2459. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2460. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2461. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2462. (u16)qdio_err, (u8)sbalf15);
  2463. return QETH_SEND_ERROR_LINK_FAILURE;
  2464. }
  2465. /*
  2466. * Switched to packing state if the number of used buffers on a queue
  2467. * reaches a certain limit.
  2468. */
  2469. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2470. {
  2471. if (!queue->do_pack) {
  2472. if (atomic_read(&queue->used_buffers)
  2473. >= QETH_HIGH_WATERMARK_PACK){
  2474. /* switch non-PACKING -> PACKING */
  2475. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2476. if (queue->card->options.performance_stats)
  2477. queue->card->perf_stats.sc_dp_p++;
  2478. queue->do_pack = 1;
  2479. }
  2480. }
  2481. }
  2482. /*
  2483. * Switches from packing to non-packing mode. If there is a packing
  2484. * buffer on the queue this buffer will be prepared to be flushed.
  2485. * In that case 1 is returned to inform the caller. If no buffer
  2486. * has to be flushed, zero is returned.
  2487. */
  2488. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2489. {
  2490. struct qeth_qdio_out_buffer *buffer;
  2491. int flush_count = 0;
  2492. if (queue->do_pack) {
  2493. if (atomic_read(&queue->used_buffers)
  2494. <= QETH_LOW_WATERMARK_PACK) {
  2495. /* switch PACKING -> non-PACKING */
  2496. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2497. if (queue->card->options.performance_stats)
  2498. queue->card->perf_stats.sc_p_dp++;
  2499. queue->do_pack = 0;
  2500. /* flush packing buffers */
  2501. buffer = &queue->bufs[queue->next_buf_to_fill];
  2502. if ((atomic_read(&buffer->state) ==
  2503. QETH_QDIO_BUF_EMPTY) &&
  2504. (buffer->next_element_to_fill > 0)) {
  2505. atomic_set(&buffer->state,
  2506. QETH_QDIO_BUF_PRIMED);
  2507. flush_count++;
  2508. queue->next_buf_to_fill =
  2509. (queue->next_buf_to_fill + 1) %
  2510. QDIO_MAX_BUFFERS_PER_Q;
  2511. }
  2512. }
  2513. }
  2514. return flush_count;
  2515. }
  2516. /*
  2517. * Called to flush a packing buffer if no more pci flags are on the queue.
  2518. * Checks if there is a packing buffer and prepares it to be flushed.
  2519. * In that case returns 1, otherwise zero.
  2520. */
  2521. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2522. {
  2523. struct qeth_qdio_out_buffer *buffer;
  2524. buffer = &queue->bufs[queue->next_buf_to_fill];
  2525. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2526. (buffer->next_element_to_fill > 0)) {
  2527. /* it's a packing buffer */
  2528. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2529. queue->next_buf_to_fill =
  2530. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2531. return 1;
  2532. }
  2533. return 0;
  2534. }
  2535. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2536. int count)
  2537. {
  2538. struct qeth_qdio_out_buffer *buf;
  2539. int rc;
  2540. int i;
  2541. unsigned int qdio_flags;
  2542. for (i = index; i < index + count; ++i) {
  2543. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2544. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2545. SBAL_FLAGS_LAST_ENTRY;
  2546. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2547. continue;
  2548. if (!queue->do_pack) {
  2549. if ((atomic_read(&queue->used_buffers) >=
  2550. (QETH_HIGH_WATERMARK_PACK -
  2551. QETH_WATERMARK_PACK_FUZZ)) &&
  2552. !atomic_read(&queue->set_pci_flags_count)) {
  2553. /* it's likely that we'll go to packing
  2554. * mode soon */
  2555. atomic_inc(&queue->set_pci_flags_count);
  2556. buf->buffer->element[0].flags |= 0x40;
  2557. }
  2558. } else {
  2559. if (!atomic_read(&queue->set_pci_flags_count)) {
  2560. /*
  2561. * there's no outstanding PCI any more, so we
  2562. * have to request a PCI to be sure the the PCI
  2563. * will wake at some time in the future then we
  2564. * can flush packed buffers that might still be
  2565. * hanging around, which can happen if no
  2566. * further send was requested by the stack
  2567. */
  2568. atomic_inc(&queue->set_pci_flags_count);
  2569. buf->buffer->element[0].flags |= 0x40;
  2570. }
  2571. }
  2572. }
  2573. queue->sync_iqdio_error = 0;
  2574. queue->card->dev->trans_start = jiffies;
  2575. if (queue->card->options.performance_stats) {
  2576. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2577. queue->card->perf_stats.outbound_do_qdio_start_time =
  2578. qeth_get_micros();
  2579. }
  2580. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2581. if (atomic_read(&queue->set_pci_flags_count))
  2582. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2583. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2584. queue->queue_no, index, count);
  2585. if (queue->card->options.performance_stats)
  2586. queue->card->perf_stats.outbound_do_qdio_time +=
  2587. qeth_get_micros() -
  2588. queue->card->perf_stats.outbound_do_qdio_start_time;
  2589. if (rc > 0) {
  2590. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2591. queue->sync_iqdio_error = rc & 3;
  2592. }
  2593. if (rc) {
  2594. queue->card->stats.tx_errors += count;
  2595. /* ignore temporary SIGA errors without busy condition */
  2596. if (rc == QDIO_ERROR_SIGA_TARGET)
  2597. return;
  2598. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2599. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2600. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2601. /* this must not happen under normal circumstances. if it
  2602. * happens something is really wrong -> recover */
  2603. qeth_schedule_recovery(queue->card);
  2604. return;
  2605. }
  2606. atomic_add(count, &queue->used_buffers);
  2607. if (queue->card->options.performance_stats)
  2608. queue->card->perf_stats.bufs_sent += count;
  2609. }
  2610. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2611. {
  2612. int index;
  2613. int flush_cnt = 0;
  2614. int q_was_packing = 0;
  2615. /*
  2616. * check if weed have to switch to non-packing mode or if
  2617. * we have to get a pci flag out on the queue
  2618. */
  2619. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2620. !atomic_read(&queue->set_pci_flags_count)) {
  2621. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2622. QETH_OUT_Q_UNLOCKED) {
  2623. /*
  2624. * If we get in here, there was no action in
  2625. * do_send_packet. So, we check if there is a
  2626. * packing buffer to be flushed here.
  2627. */
  2628. netif_stop_queue(queue->card->dev);
  2629. index = queue->next_buf_to_fill;
  2630. q_was_packing = queue->do_pack;
  2631. /* queue->do_pack may change */
  2632. barrier();
  2633. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2634. if (!flush_cnt &&
  2635. !atomic_read(&queue->set_pci_flags_count))
  2636. flush_cnt +=
  2637. qeth_flush_buffers_on_no_pci(queue);
  2638. if (queue->card->options.performance_stats &&
  2639. q_was_packing)
  2640. queue->card->perf_stats.bufs_sent_pack +=
  2641. flush_cnt;
  2642. if (flush_cnt)
  2643. qeth_flush_buffers(queue, index, flush_cnt);
  2644. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2645. }
  2646. }
  2647. }
  2648. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2649. unsigned int qdio_error, int __queue, int first_element,
  2650. int count, unsigned long card_ptr)
  2651. {
  2652. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2653. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2654. struct qeth_qdio_out_buffer *buffer;
  2655. int i;
  2656. unsigned qeth_send_err;
  2657. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2658. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2659. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2660. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2661. netif_stop_queue(card->dev);
  2662. qeth_schedule_recovery(card);
  2663. return;
  2664. }
  2665. if (card->options.performance_stats) {
  2666. card->perf_stats.outbound_handler_cnt++;
  2667. card->perf_stats.outbound_handler_start_time =
  2668. qeth_get_micros();
  2669. }
  2670. for (i = first_element; i < (first_element + count); ++i) {
  2671. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2672. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2673. __qeth_clear_output_buffer(queue, buffer,
  2674. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2675. }
  2676. atomic_sub(count, &queue->used_buffers);
  2677. /* check if we need to do something on this outbound queue */
  2678. if (card->info.type != QETH_CARD_TYPE_IQD)
  2679. qeth_check_outbound_queue(queue);
  2680. netif_wake_queue(queue->card->dev);
  2681. if (card->options.performance_stats)
  2682. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2683. card->perf_stats.outbound_handler_start_time;
  2684. }
  2685. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2686. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2687. int ipv, int cast_type)
  2688. {
  2689. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2690. card->info.type == QETH_CARD_TYPE_OSX))
  2691. return card->qdio.default_out_queue;
  2692. switch (card->qdio.no_out_queues) {
  2693. case 4:
  2694. if (cast_type && card->info.is_multicast_different)
  2695. return card->info.is_multicast_different &
  2696. (card->qdio.no_out_queues - 1);
  2697. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2698. const u8 tos = ip_hdr(skb)->tos;
  2699. if (card->qdio.do_prio_queueing ==
  2700. QETH_PRIO_Q_ING_TOS) {
  2701. if (tos & IP_TOS_NOTIMPORTANT)
  2702. return 3;
  2703. if (tos & IP_TOS_HIGHRELIABILITY)
  2704. return 2;
  2705. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2706. return 1;
  2707. if (tos & IP_TOS_LOWDELAY)
  2708. return 0;
  2709. }
  2710. if (card->qdio.do_prio_queueing ==
  2711. QETH_PRIO_Q_ING_PREC)
  2712. return 3 - (tos >> 6);
  2713. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2714. /* TODO: IPv6!!! */
  2715. }
  2716. return card->qdio.default_out_queue;
  2717. case 1: /* fallthrough for single-out-queue 1920-device */
  2718. default:
  2719. return card->qdio.default_out_queue;
  2720. }
  2721. }
  2722. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2723. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2724. struct sk_buff *skb, int elems)
  2725. {
  2726. int elements_needed = 0;
  2727. if (skb_shinfo(skb)->nr_frags > 0)
  2728. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2729. if (elements_needed == 0)
  2730. elements_needed = 1 + (((((unsigned long) skb->data) %
  2731. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2732. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2733. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2734. "(Number=%d / Length=%d). Discarded.\n",
  2735. (elements_needed+elems), skb->len);
  2736. return 0;
  2737. }
  2738. return elements_needed;
  2739. }
  2740. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2741. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2742. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2743. int offset)
  2744. {
  2745. int length = skb->len;
  2746. int length_here;
  2747. int element;
  2748. char *data;
  2749. int first_lap ;
  2750. element = *next_element_to_fill;
  2751. data = skb->data;
  2752. first_lap = (is_tso == 0 ? 1 : 0);
  2753. if (offset >= 0) {
  2754. data = skb->data + offset;
  2755. length -= offset;
  2756. first_lap = 0;
  2757. }
  2758. while (length > 0) {
  2759. /* length_here is the remaining amount of data in this page */
  2760. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2761. if (length < length_here)
  2762. length_here = length;
  2763. buffer->element[element].addr = data;
  2764. buffer->element[element].length = length_here;
  2765. length -= length_here;
  2766. if (!length) {
  2767. if (first_lap)
  2768. buffer->element[element].flags = 0;
  2769. else
  2770. buffer->element[element].flags =
  2771. SBAL_FLAGS_LAST_FRAG;
  2772. } else {
  2773. if (first_lap)
  2774. buffer->element[element].flags =
  2775. SBAL_FLAGS_FIRST_FRAG;
  2776. else
  2777. buffer->element[element].flags =
  2778. SBAL_FLAGS_MIDDLE_FRAG;
  2779. }
  2780. data += length_here;
  2781. element++;
  2782. first_lap = 0;
  2783. }
  2784. *next_element_to_fill = element;
  2785. }
  2786. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2787. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2788. struct qeth_hdr *hdr, int offset, int hd_len)
  2789. {
  2790. struct qdio_buffer *buffer;
  2791. int flush_cnt = 0, hdr_len, large_send = 0;
  2792. buffer = buf->buffer;
  2793. atomic_inc(&skb->users);
  2794. skb_queue_tail(&buf->skb_list, skb);
  2795. /*check first on TSO ....*/
  2796. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2797. int element = buf->next_element_to_fill;
  2798. hdr_len = sizeof(struct qeth_hdr_tso) +
  2799. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2800. /*fill first buffer entry only with header information */
  2801. buffer->element[element].addr = skb->data;
  2802. buffer->element[element].length = hdr_len;
  2803. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2804. buf->next_element_to_fill++;
  2805. skb->data += hdr_len;
  2806. skb->len -= hdr_len;
  2807. large_send = 1;
  2808. }
  2809. if (offset >= 0) {
  2810. int element = buf->next_element_to_fill;
  2811. buffer->element[element].addr = hdr;
  2812. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2813. hd_len;
  2814. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2815. buf->is_header[element] = 1;
  2816. buf->next_element_to_fill++;
  2817. }
  2818. if (skb_shinfo(skb)->nr_frags == 0)
  2819. __qeth_fill_buffer(skb, buffer, large_send,
  2820. (int *)&buf->next_element_to_fill, offset);
  2821. else
  2822. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2823. (int *)&buf->next_element_to_fill);
  2824. if (!queue->do_pack) {
  2825. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2826. /* set state to PRIMED -> will be flushed */
  2827. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2828. flush_cnt = 1;
  2829. } else {
  2830. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2831. if (queue->card->options.performance_stats)
  2832. queue->card->perf_stats.skbs_sent_pack++;
  2833. if (buf->next_element_to_fill >=
  2834. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2835. /*
  2836. * packed buffer if full -> set state PRIMED
  2837. * -> will be flushed
  2838. */
  2839. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2840. flush_cnt = 1;
  2841. }
  2842. }
  2843. return flush_cnt;
  2844. }
  2845. int qeth_do_send_packet_fast(struct qeth_card *card,
  2846. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2847. struct qeth_hdr *hdr, int elements_needed,
  2848. int offset, int hd_len)
  2849. {
  2850. struct qeth_qdio_out_buffer *buffer;
  2851. struct sk_buff *skb1;
  2852. struct qeth_skb_data *retry_ctrl;
  2853. int index;
  2854. int rc;
  2855. /* spin until we get the queue ... */
  2856. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2857. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2858. /* ... now we've got the queue */
  2859. index = queue->next_buf_to_fill;
  2860. buffer = &queue->bufs[queue->next_buf_to_fill];
  2861. /*
  2862. * check if buffer is empty to make sure that we do not 'overtake'
  2863. * ourselves and try to fill a buffer that is already primed
  2864. */
  2865. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2866. goto out;
  2867. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2868. QDIO_MAX_BUFFERS_PER_Q;
  2869. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2870. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2871. qeth_flush_buffers(queue, index, 1);
  2872. if (queue->sync_iqdio_error == 2) {
  2873. skb1 = skb_dequeue(&buffer->skb_list);
  2874. while (skb1) {
  2875. atomic_dec(&skb1->users);
  2876. skb1 = skb_dequeue(&buffer->skb_list);
  2877. }
  2878. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2879. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2880. retry_ctrl->magic = QETH_SKB_MAGIC;
  2881. retry_ctrl->count = 0;
  2882. }
  2883. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2884. retry_ctrl->count++;
  2885. rc = dev_queue_xmit(skb);
  2886. } else {
  2887. dev_kfree_skb_any(skb);
  2888. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2889. }
  2890. }
  2891. return 0;
  2892. out:
  2893. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2894. return -EBUSY;
  2895. }
  2896. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2897. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2898. struct sk_buff *skb, struct qeth_hdr *hdr,
  2899. int elements_needed)
  2900. {
  2901. struct qeth_qdio_out_buffer *buffer;
  2902. int start_index;
  2903. int flush_count = 0;
  2904. int do_pack = 0;
  2905. int tmp;
  2906. int rc = 0;
  2907. /* spin until we get the queue ... */
  2908. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2909. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2910. start_index = queue->next_buf_to_fill;
  2911. buffer = &queue->bufs[queue->next_buf_to_fill];
  2912. /*
  2913. * check if buffer is empty to make sure that we do not 'overtake'
  2914. * ourselves and try to fill a buffer that is already primed
  2915. */
  2916. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2917. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2918. return -EBUSY;
  2919. }
  2920. /* check if we need to switch packing state of this queue */
  2921. qeth_switch_to_packing_if_needed(queue);
  2922. if (queue->do_pack) {
  2923. do_pack = 1;
  2924. /* does packet fit in current buffer? */
  2925. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2926. buffer->next_element_to_fill) < elements_needed) {
  2927. /* ... no -> set state PRIMED */
  2928. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2929. flush_count++;
  2930. queue->next_buf_to_fill =
  2931. (queue->next_buf_to_fill + 1) %
  2932. QDIO_MAX_BUFFERS_PER_Q;
  2933. buffer = &queue->bufs[queue->next_buf_to_fill];
  2934. /* we did a step forward, so check buffer state
  2935. * again */
  2936. if (atomic_read(&buffer->state) !=
  2937. QETH_QDIO_BUF_EMPTY) {
  2938. qeth_flush_buffers(queue, start_index,
  2939. flush_count);
  2940. atomic_set(&queue->state,
  2941. QETH_OUT_Q_UNLOCKED);
  2942. return -EBUSY;
  2943. }
  2944. }
  2945. }
  2946. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2947. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2948. QDIO_MAX_BUFFERS_PER_Q;
  2949. flush_count += tmp;
  2950. if (flush_count)
  2951. qeth_flush_buffers(queue, start_index, flush_count);
  2952. else if (!atomic_read(&queue->set_pci_flags_count))
  2953. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2954. /*
  2955. * queue->state will go from LOCKED -> UNLOCKED or from
  2956. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2957. * (switch packing state or flush buffer to get another pci flag out).
  2958. * In that case we will enter this loop
  2959. */
  2960. while (atomic_dec_return(&queue->state)) {
  2961. flush_count = 0;
  2962. start_index = queue->next_buf_to_fill;
  2963. /* check if we can go back to non-packing state */
  2964. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2965. /*
  2966. * check if we need to flush a packing buffer to get a pci
  2967. * flag out on the queue
  2968. */
  2969. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2970. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2971. if (flush_count)
  2972. qeth_flush_buffers(queue, start_index, flush_count);
  2973. }
  2974. /* at this point the queue is UNLOCKED again */
  2975. if (queue->card->options.performance_stats && do_pack)
  2976. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2977. return rc;
  2978. }
  2979. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2980. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2981. struct qeth_reply *reply, unsigned long data)
  2982. {
  2983. struct qeth_ipa_cmd *cmd;
  2984. struct qeth_ipacmd_setadpparms *setparms;
  2985. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2986. cmd = (struct qeth_ipa_cmd *) data;
  2987. setparms = &(cmd->data.setadapterparms);
  2988. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2989. if (cmd->hdr.return_code) {
  2990. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2991. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2992. }
  2993. card->info.promisc_mode = setparms->data.mode;
  2994. return 0;
  2995. }
  2996. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2997. {
  2998. enum qeth_ipa_promisc_modes mode;
  2999. struct net_device *dev = card->dev;
  3000. struct qeth_cmd_buffer *iob;
  3001. struct qeth_ipa_cmd *cmd;
  3002. QETH_DBF_TEXT(TRACE, 4, "setprom");
  3003. if (((dev->flags & IFF_PROMISC) &&
  3004. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3005. (!(dev->flags & IFF_PROMISC) &&
  3006. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3007. return;
  3008. mode = SET_PROMISC_MODE_OFF;
  3009. if (dev->flags & IFF_PROMISC)
  3010. mode = SET_PROMISC_MODE_ON;
  3011. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3012. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3013. sizeof(struct qeth_ipacmd_setadpparms));
  3014. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3015. cmd->data.setadapterparms.data.mode = mode;
  3016. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3017. }
  3018. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3019. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3020. {
  3021. struct qeth_card *card;
  3022. char dbf_text[15];
  3023. card = dev->ml_priv;
  3024. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3025. sprintf(dbf_text, "%8x", new_mtu);
  3026. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3027. if (new_mtu < 64)
  3028. return -EINVAL;
  3029. if (new_mtu > 65535)
  3030. return -EINVAL;
  3031. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3032. (!qeth_mtu_is_valid(card, new_mtu)))
  3033. return -EINVAL;
  3034. dev->mtu = new_mtu;
  3035. return 0;
  3036. }
  3037. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3038. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3039. {
  3040. struct qeth_card *card;
  3041. card = dev->ml_priv;
  3042. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3043. return &card->stats;
  3044. }
  3045. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3046. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3047. struct qeth_reply *reply, unsigned long data)
  3048. {
  3049. struct qeth_ipa_cmd *cmd;
  3050. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3051. cmd = (struct qeth_ipa_cmd *) data;
  3052. if (!card->options.layer2 ||
  3053. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3054. memcpy(card->dev->dev_addr,
  3055. &cmd->data.setadapterparms.data.change_addr.addr,
  3056. OSA_ADDR_LEN);
  3057. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3058. }
  3059. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3060. return 0;
  3061. }
  3062. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3063. {
  3064. int rc;
  3065. struct qeth_cmd_buffer *iob;
  3066. struct qeth_ipa_cmd *cmd;
  3067. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3068. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3069. sizeof(struct qeth_ipacmd_setadpparms));
  3070. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3071. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3072. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3073. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3074. card->dev->dev_addr, OSA_ADDR_LEN);
  3075. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3076. NULL);
  3077. return rc;
  3078. }
  3079. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3080. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3081. struct qeth_reply *reply, unsigned long data)
  3082. {
  3083. struct qeth_ipa_cmd *cmd;
  3084. struct qeth_set_access_ctrl *access_ctrl_req;
  3085. int rc;
  3086. QETH_DBF_TEXT(TRACE, 4, "setaccb");
  3087. cmd = (struct qeth_ipa_cmd *) data;
  3088. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3089. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3090. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3091. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3092. cmd->data.setadapterparms.hdr.return_code);
  3093. switch (cmd->data.setadapterparms.hdr.return_code) {
  3094. case SET_ACCESS_CTRL_RC_SUCCESS:
  3095. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3096. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3097. {
  3098. card->options.isolation = access_ctrl_req->subcmd_code;
  3099. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3100. dev_info(&card->gdev->dev,
  3101. "QDIO data connection isolation is deactivated\n");
  3102. } else {
  3103. dev_info(&card->gdev->dev,
  3104. "QDIO data connection isolation is activated\n");
  3105. }
  3106. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3107. card->gdev->dev.kobj.name,
  3108. access_ctrl_req->subcmd_code,
  3109. cmd->data.setadapterparms.hdr.return_code);
  3110. rc = 0;
  3111. break;
  3112. }
  3113. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3114. {
  3115. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3116. card->gdev->dev.kobj.name,
  3117. access_ctrl_req->subcmd_code,
  3118. cmd->data.setadapterparms.hdr.return_code);
  3119. dev_err(&card->gdev->dev, "Adapter does not "
  3120. "support QDIO data connection isolation\n");
  3121. /* ensure isolation mode is "none" */
  3122. card->options.isolation = ISOLATION_MODE_NONE;
  3123. rc = -EOPNOTSUPP;
  3124. break;
  3125. }
  3126. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3127. {
  3128. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3129. card->gdev->dev.kobj.name,
  3130. access_ctrl_req->subcmd_code,
  3131. cmd->data.setadapterparms.hdr.return_code);
  3132. dev_err(&card->gdev->dev,
  3133. "Adapter is dedicated. "
  3134. "QDIO data connection isolation not supported\n");
  3135. /* ensure isolation mode is "none" */
  3136. card->options.isolation = ISOLATION_MODE_NONE;
  3137. rc = -EOPNOTSUPP;
  3138. break;
  3139. }
  3140. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3141. {
  3142. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3143. card->gdev->dev.kobj.name,
  3144. access_ctrl_req->subcmd_code,
  3145. cmd->data.setadapterparms.hdr.return_code);
  3146. dev_err(&card->gdev->dev,
  3147. "TSO does not permit QDIO data connection isolation\n");
  3148. /* ensure isolation mode is "none" */
  3149. card->options.isolation = ISOLATION_MODE_NONE;
  3150. rc = -EPERM;
  3151. break;
  3152. }
  3153. default:
  3154. {
  3155. /* this should never happen */
  3156. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3157. "==UNKNOWN\n",
  3158. card->gdev->dev.kobj.name,
  3159. access_ctrl_req->subcmd_code,
  3160. cmd->data.setadapterparms.hdr.return_code);
  3161. /* ensure isolation mode is "none" */
  3162. card->options.isolation = ISOLATION_MODE_NONE;
  3163. rc = 0;
  3164. break;
  3165. }
  3166. }
  3167. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3168. return rc;
  3169. }
  3170. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3171. enum qeth_ipa_isolation_modes isolation)
  3172. {
  3173. int rc;
  3174. struct qeth_cmd_buffer *iob;
  3175. struct qeth_ipa_cmd *cmd;
  3176. struct qeth_set_access_ctrl *access_ctrl_req;
  3177. QETH_DBF_TEXT(TRACE, 4, "setacctl");
  3178. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3179. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3180. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3181. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3182. sizeof(struct qeth_set_access_ctrl));
  3183. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3184. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3185. access_ctrl_req->subcmd_code = isolation;
  3186. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3187. NULL);
  3188. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3189. return rc;
  3190. }
  3191. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3192. {
  3193. int rc = 0;
  3194. QETH_DBF_TEXT(TRACE, 4, "setactlo");
  3195. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3196. card->info.type == QETH_CARD_TYPE_OSX) &&
  3197. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3198. rc = qeth_setadpparms_set_access_ctrl(card,
  3199. card->options.isolation);
  3200. if (rc) {
  3201. QETH_DBF_MESSAGE(3,
  3202. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3203. card->gdev->dev.kobj.name,
  3204. rc);
  3205. }
  3206. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3207. card->options.isolation = ISOLATION_MODE_NONE;
  3208. dev_err(&card->gdev->dev, "Adapter does not "
  3209. "support QDIO data connection isolation\n");
  3210. rc = -EOPNOTSUPP;
  3211. }
  3212. return rc;
  3213. }
  3214. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3215. void qeth_tx_timeout(struct net_device *dev)
  3216. {
  3217. struct qeth_card *card;
  3218. QETH_DBF_TEXT(TRACE, 4, "txtimeo");
  3219. card = dev->ml_priv;
  3220. card->stats.tx_errors++;
  3221. qeth_schedule_recovery(card);
  3222. }
  3223. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3224. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3225. {
  3226. struct qeth_card *card = dev->ml_priv;
  3227. int rc = 0;
  3228. switch (regnum) {
  3229. case MII_BMCR: /* Basic mode control register */
  3230. rc = BMCR_FULLDPLX;
  3231. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3232. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3233. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3234. rc |= BMCR_SPEED100;
  3235. break;
  3236. case MII_BMSR: /* Basic mode status register */
  3237. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3238. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3239. BMSR_100BASE4;
  3240. break;
  3241. case MII_PHYSID1: /* PHYS ID 1 */
  3242. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3243. dev->dev_addr[2];
  3244. rc = (rc >> 5) & 0xFFFF;
  3245. break;
  3246. case MII_PHYSID2: /* PHYS ID 2 */
  3247. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3248. break;
  3249. case MII_ADVERTISE: /* Advertisement control reg */
  3250. rc = ADVERTISE_ALL;
  3251. break;
  3252. case MII_LPA: /* Link partner ability reg */
  3253. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3254. LPA_100BASE4 | LPA_LPACK;
  3255. break;
  3256. case MII_EXPANSION: /* Expansion register */
  3257. break;
  3258. case MII_DCOUNTER: /* disconnect counter */
  3259. break;
  3260. case MII_FCSCOUNTER: /* false carrier counter */
  3261. break;
  3262. case MII_NWAYTEST: /* N-way auto-neg test register */
  3263. break;
  3264. case MII_RERRCOUNTER: /* rx error counter */
  3265. rc = card->stats.rx_errors;
  3266. break;
  3267. case MII_SREVISION: /* silicon revision */
  3268. break;
  3269. case MII_RESV1: /* reserved 1 */
  3270. break;
  3271. case MII_LBRERROR: /* loopback, rx, bypass error */
  3272. break;
  3273. case MII_PHYADDR: /* physical address */
  3274. break;
  3275. case MII_RESV2: /* reserved 2 */
  3276. break;
  3277. case MII_TPISTATUS: /* TPI status for 10mbps */
  3278. break;
  3279. case MII_NCONFIG: /* network interface config */
  3280. break;
  3281. default:
  3282. break;
  3283. }
  3284. return rc;
  3285. }
  3286. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3287. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3288. struct qeth_cmd_buffer *iob, int len,
  3289. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3290. unsigned long),
  3291. void *reply_param)
  3292. {
  3293. u16 s1, s2;
  3294. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3295. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3296. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3297. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3298. /* adjust PDU length fields in IPA_PDU_HEADER */
  3299. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3300. s2 = (u32) len;
  3301. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3302. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3303. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3304. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3305. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3306. reply_cb, reply_param);
  3307. }
  3308. static int qeth_snmp_command_cb(struct qeth_card *card,
  3309. struct qeth_reply *reply, unsigned long sdata)
  3310. {
  3311. struct qeth_ipa_cmd *cmd;
  3312. struct qeth_arp_query_info *qinfo;
  3313. struct qeth_snmp_cmd *snmp;
  3314. unsigned char *data;
  3315. __u16 data_len;
  3316. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3317. cmd = (struct qeth_ipa_cmd *) sdata;
  3318. data = (unsigned char *)((char *)cmd - reply->offset);
  3319. qinfo = (struct qeth_arp_query_info *) reply->param;
  3320. snmp = &cmd->data.setadapterparms.data.snmp;
  3321. if (cmd->hdr.return_code) {
  3322. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3323. return 0;
  3324. }
  3325. if (cmd->data.setadapterparms.hdr.return_code) {
  3326. cmd->hdr.return_code =
  3327. cmd->data.setadapterparms.hdr.return_code;
  3328. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3329. return 0;
  3330. }
  3331. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3332. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3333. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3334. else
  3335. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3336. /* check if there is enough room in userspace */
  3337. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3338. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3339. cmd->hdr.return_code = -ENOMEM;
  3340. return 0;
  3341. }
  3342. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3343. cmd->data.setadapterparms.hdr.used_total);
  3344. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3345. cmd->data.setadapterparms.hdr.seq_no);
  3346. /*copy entries to user buffer*/
  3347. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3348. memcpy(qinfo->udata + qinfo->udata_offset,
  3349. (char *)snmp,
  3350. data_len + offsetof(struct qeth_snmp_cmd, data));
  3351. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3352. } else {
  3353. memcpy(qinfo->udata + qinfo->udata_offset,
  3354. (char *)&snmp->request, data_len);
  3355. }
  3356. qinfo->udata_offset += data_len;
  3357. /* check if all replies received ... */
  3358. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3359. cmd->data.setadapterparms.hdr.used_total);
  3360. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3361. cmd->data.setadapterparms.hdr.seq_no);
  3362. if (cmd->data.setadapterparms.hdr.seq_no <
  3363. cmd->data.setadapterparms.hdr.used_total)
  3364. return 1;
  3365. return 0;
  3366. }
  3367. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3368. {
  3369. struct qeth_cmd_buffer *iob;
  3370. struct qeth_ipa_cmd *cmd;
  3371. struct qeth_snmp_ureq *ureq;
  3372. int req_len;
  3373. struct qeth_arp_query_info qinfo = {0, };
  3374. int rc = 0;
  3375. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3376. if (card->info.guestlan)
  3377. return -EOPNOTSUPP;
  3378. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3379. (!card->options.layer2)) {
  3380. return -EOPNOTSUPP;
  3381. }
  3382. /* skip 4 bytes (data_len struct member) to get req_len */
  3383. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3384. return -EFAULT;
  3385. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3386. if (!ureq) {
  3387. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3388. return -ENOMEM;
  3389. }
  3390. if (copy_from_user(ureq, udata,
  3391. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3392. kfree(ureq);
  3393. return -EFAULT;
  3394. }
  3395. qinfo.udata_len = ureq->hdr.data_len;
  3396. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3397. if (!qinfo.udata) {
  3398. kfree(ureq);
  3399. return -ENOMEM;
  3400. }
  3401. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3402. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3403. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3404. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3405. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3406. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3407. qeth_snmp_command_cb, (void *)&qinfo);
  3408. if (rc)
  3409. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3410. QETH_CARD_IFNAME(card), rc);
  3411. else {
  3412. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3413. rc = -EFAULT;
  3414. }
  3415. kfree(ureq);
  3416. kfree(qinfo.udata);
  3417. return rc;
  3418. }
  3419. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3420. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3421. {
  3422. switch (card->info.type) {
  3423. case QETH_CARD_TYPE_IQD:
  3424. return 2;
  3425. default:
  3426. return 0;
  3427. }
  3428. }
  3429. static int qeth_qdio_establish(struct qeth_card *card)
  3430. {
  3431. struct qdio_initialize init_data;
  3432. char *qib_param_field;
  3433. struct qdio_buffer **in_sbal_ptrs;
  3434. struct qdio_buffer **out_sbal_ptrs;
  3435. int i, j, k;
  3436. int rc = 0;
  3437. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3438. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3439. GFP_KERNEL);
  3440. if (!qib_param_field)
  3441. return -ENOMEM;
  3442. qeth_create_qib_param_field(card, qib_param_field);
  3443. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3444. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3445. GFP_KERNEL);
  3446. if (!in_sbal_ptrs) {
  3447. kfree(qib_param_field);
  3448. return -ENOMEM;
  3449. }
  3450. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3451. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3452. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3453. out_sbal_ptrs =
  3454. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3455. sizeof(void *), GFP_KERNEL);
  3456. if (!out_sbal_ptrs) {
  3457. kfree(in_sbal_ptrs);
  3458. kfree(qib_param_field);
  3459. return -ENOMEM;
  3460. }
  3461. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3462. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3463. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3464. card->qdio.out_qs[i]->bufs[j].buffer);
  3465. }
  3466. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3467. init_data.cdev = CARD_DDEV(card);
  3468. init_data.q_format = qeth_get_qdio_q_format(card);
  3469. init_data.qib_param_field_format = 0;
  3470. init_data.qib_param_field = qib_param_field;
  3471. init_data.no_input_qs = 1;
  3472. init_data.no_output_qs = card->qdio.no_out_queues;
  3473. init_data.input_handler = card->discipline.input_handler;
  3474. init_data.output_handler = card->discipline.output_handler;
  3475. init_data.int_parm = (unsigned long) card;
  3476. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3477. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3478. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3479. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3480. rc = qdio_allocate(&init_data);
  3481. if (rc) {
  3482. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3483. goto out;
  3484. }
  3485. rc = qdio_establish(&init_data);
  3486. if (rc) {
  3487. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3488. qdio_free(CARD_DDEV(card));
  3489. }
  3490. }
  3491. out:
  3492. kfree(out_sbal_ptrs);
  3493. kfree(in_sbal_ptrs);
  3494. kfree(qib_param_field);
  3495. return rc;
  3496. }
  3497. static void qeth_core_free_card(struct qeth_card *card)
  3498. {
  3499. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3500. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3501. qeth_clean_channel(&card->read);
  3502. qeth_clean_channel(&card->write);
  3503. if (card->dev)
  3504. free_netdev(card->dev);
  3505. kfree(card->ip_tbd_list);
  3506. qeth_free_qdio_buffers(card);
  3507. unregister_service_level(&card->qeth_service_level);
  3508. kfree(card);
  3509. }
  3510. static struct ccw_device_id qeth_ids[] = {
  3511. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3512. .driver_info = QETH_CARD_TYPE_OSD},
  3513. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3514. .driver_info = QETH_CARD_TYPE_IQD},
  3515. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3516. .driver_info = QETH_CARD_TYPE_OSN},
  3517. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3518. .driver_info = QETH_CARD_TYPE_OSM},
  3519. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3520. .driver_info = QETH_CARD_TYPE_OSX},
  3521. {},
  3522. };
  3523. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3524. static struct ccw_driver qeth_ccw_driver = {
  3525. .name = "qeth",
  3526. .ids = qeth_ids,
  3527. .probe = ccwgroup_probe_ccwdev,
  3528. .remove = ccwgroup_remove_ccwdev,
  3529. };
  3530. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3531. unsigned long driver_id)
  3532. {
  3533. return ccwgroup_create_from_string(root_dev, driver_id,
  3534. &qeth_ccw_driver, 3, buf);
  3535. }
  3536. int qeth_core_hardsetup_card(struct qeth_card *card)
  3537. {
  3538. int retries = 0;
  3539. int rc;
  3540. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3541. atomic_set(&card->force_alloc_skb, 0);
  3542. retry:
  3543. if (retries)
  3544. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3545. dev_name(&card->gdev->dev));
  3546. ccw_device_set_offline(CARD_DDEV(card));
  3547. ccw_device_set_offline(CARD_WDEV(card));
  3548. ccw_device_set_offline(CARD_RDEV(card));
  3549. rc = ccw_device_set_online(CARD_RDEV(card));
  3550. if (rc)
  3551. goto retriable;
  3552. rc = ccw_device_set_online(CARD_WDEV(card));
  3553. if (rc)
  3554. goto retriable;
  3555. rc = ccw_device_set_online(CARD_DDEV(card));
  3556. if (rc)
  3557. goto retriable;
  3558. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3559. retriable:
  3560. if (rc == -ERESTARTSYS) {
  3561. QETH_DBF_TEXT(SETUP, 2, "break1");
  3562. return rc;
  3563. } else if (rc) {
  3564. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3565. if (++retries > 3)
  3566. goto out;
  3567. else
  3568. goto retry;
  3569. }
  3570. qeth_init_tokens(card);
  3571. qeth_init_func_level(card);
  3572. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3573. if (rc == -ERESTARTSYS) {
  3574. QETH_DBF_TEXT(SETUP, 2, "break2");
  3575. return rc;
  3576. } else if (rc) {
  3577. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3578. if (--retries < 0)
  3579. goto out;
  3580. else
  3581. goto retry;
  3582. }
  3583. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3584. if (rc == -ERESTARTSYS) {
  3585. QETH_DBF_TEXT(SETUP, 2, "break3");
  3586. return rc;
  3587. } else if (rc) {
  3588. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3589. if (--retries < 0)
  3590. goto out;
  3591. else
  3592. goto retry;
  3593. }
  3594. rc = qeth_mpc_initialize(card);
  3595. if (rc) {
  3596. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3597. goto out;
  3598. }
  3599. return 0;
  3600. out:
  3601. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3602. "an error on the device\n");
  3603. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3604. dev_name(&card->gdev->dev), rc);
  3605. return rc;
  3606. }
  3607. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3608. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3609. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3610. {
  3611. struct page *page = virt_to_page(element->addr);
  3612. if (*pskb == NULL) {
  3613. /* the upper protocol layers assume that there is data in the
  3614. * skb itself. Copy a small amount (64 bytes) to make them
  3615. * happy. */
  3616. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3617. if (!(*pskb))
  3618. return -ENOMEM;
  3619. skb_reserve(*pskb, ETH_HLEN);
  3620. if (data_len <= 64) {
  3621. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3622. data_len);
  3623. } else {
  3624. get_page(page);
  3625. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3626. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3627. data_len - 64);
  3628. (*pskb)->data_len += data_len - 64;
  3629. (*pskb)->len += data_len - 64;
  3630. (*pskb)->truesize += data_len - 64;
  3631. (*pfrag)++;
  3632. }
  3633. } else {
  3634. get_page(page);
  3635. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3636. (*pskb)->data_len += data_len;
  3637. (*pskb)->len += data_len;
  3638. (*pskb)->truesize += data_len;
  3639. (*pfrag)++;
  3640. }
  3641. return 0;
  3642. }
  3643. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3644. struct qdio_buffer *buffer,
  3645. struct qdio_buffer_element **__element, int *__offset,
  3646. struct qeth_hdr **hdr)
  3647. {
  3648. struct qdio_buffer_element *element = *__element;
  3649. int offset = *__offset;
  3650. struct sk_buff *skb = NULL;
  3651. int skb_len = 0;
  3652. void *data_ptr;
  3653. int data_len;
  3654. int headroom = 0;
  3655. int use_rx_sg = 0;
  3656. int frag = 0;
  3657. /* qeth_hdr must not cross element boundaries */
  3658. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3659. if (qeth_is_last_sbale(element))
  3660. return NULL;
  3661. element++;
  3662. offset = 0;
  3663. if (element->length < sizeof(struct qeth_hdr))
  3664. return NULL;
  3665. }
  3666. *hdr = element->addr + offset;
  3667. offset += sizeof(struct qeth_hdr);
  3668. switch ((*hdr)->hdr.l2.id) {
  3669. case QETH_HEADER_TYPE_LAYER2:
  3670. skb_len = (*hdr)->hdr.l2.pkt_length;
  3671. break;
  3672. case QETH_HEADER_TYPE_LAYER3:
  3673. skb_len = (*hdr)->hdr.l3.length;
  3674. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3675. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3676. headroom = TR_HLEN;
  3677. else
  3678. headroom = ETH_HLEN;
  3679. break;
  3680. case QETH_HEADER_TYPE_OSN:
  3681. skb_len = (*hdr)->hdr.osn.pdu_length;
  3682. headroom = sizeof(struct qeth_hdr);
  3683. break;
  3684. default:
  3685. break;
  3686. }
  3687. if (!skb_len)
  3688. return NULL;
  3689. if ((skb_len >= card->options.rx_sg_cb) &&
  3690. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3691. (!atomic_read(&card->force_alloc_skb))) {
  3692. use_rx_sg = 1;
  3693. } else {
  3694. skb = dev_alloc_skb(skb_len + headroom);
  3695. if (!skb)
  3696. goto no_mem;
  3697. if (headroom)
  3698. skb_reserve(skb, headroom);
  3699. }
  3700. data_ptr = element->addr + offset;
  3701. while (skb_len) {
  3702. data_len = min(skb_len, (int)(element->length - offset));
  3703. if (data_len) {
  3704. if (use_rx_sg) {
  3705. if (qeth_create_skb_frag(element, &skb, offset,
  3706. &frag, data_len))
  3707. goto no_mem;
  3708. } else {
  3709. memcpy(skb_put(skb, data_len), data_ptr,
  3710. data_len);
  3711. }
  3712. }
  3713. skb_len -= data_len;
  3714. if (skb_len) {
  3715. if (qeth_is_last_sbale(element)) {
  3716. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3717. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3718. CARD_BUS_ID(card));
  3719. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3720. QETH_DBF_TEXT_(QERR, 2, "%s",
  3721. CARD_BUS_ID(card));
  3722. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3723. dev_kfree_skb_any(skb);
  3724. card->stats.rx_errors++;
  3725. return NULL;
  3726. }
  3727. element++;
  3728. offset = 0;
  3729. data_ptr = element->addr;
  3730. } else {
  3731. offset += data_len;
  3732. }
  3733. }
  3734. *__element = element;
  3735. *__offset = offset;
  3736. if (use_rx_sg && card->options.performance_stats) {
  3737. card->perf_stats.sg_skbs_rx++;
  3738. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3739. }
  3740. return skb;
  3741. no_mem:
  3742. if (net_ratelimit()) {
  3743. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3744. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3745. }
  3746. card->stats.rx_dropped++;
  3747. return NULL;
  3748. }
  3749. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3750. static void qeth_unregister_dbf_views(void)
  3751. {
  3752. int x;
  3753. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3754. debug_unregister(qeth_dbf[x].id);
  3755. qeth_dbf[x].id = NULL;
  3756. }
  3757. }
  3758. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3759. {
  3760. char dbf_txt_buf[32];
  3761. va_list args;
  3762. if (level > (qeth_dbf[dbf_nix].id)->level)
  3763. return;
  3764. va_start(args, fmt);
  3765. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3766. va_end(args);
  3767. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3768. }
  3769. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3770. static int qeth_register_dbf_views(void)
  3771. {
  3772. int ret;
  3773. int x;
  3774. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3775. /* register the areas */
  3776. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3777. qeth_dbf[x].pages,
  3778. qeth_dbf[x].areas,
  3779. qeth_dbf[x].len);
  3780. if (qeth_dbf[x].id == NULL) {
  3781. qeth_unregister_dbf_views();
  3782. return -ENOMEM;
  3783. }
  3784. /* register a view */
  3785. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3786. if (ret) {
  3787. qeth_unregister_dbf_views();
  3788. return ret;
  3789. }
  3790. /* set a passing level */
  3791. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3792. }
  3793. return 0;
  3794. }
  3795. int qeth_core_load_discipline(struct qeth_card *card,
  3796. enum qeth_discipline_id discipline)
  3797. {
  3798. int rc = 0;
  3799. switch (discipline) {
  3800. case QETH_DISCIPLINE_LAYER3:
  3801. card->discipline.ccwgdriver = try_then_request_module(
  3802. symbol_get(qeth_l3_ccwgroup_driver),
  3803. "qeth_l3");
  3804. break;
  3805. case QETH_DISCIPLINE_LAYER2:
  3806. card->discipline.ccwgdriver = try_then_request_module(
  3807. symbol_get(qeth_l2_ccwgroup_driver),
  3808. "qeth_l2");
  3809. break;
  3810. }
  3811. if (!card->discipline.ccwgdriver) {
  3812. dev_err(&card->gdev->dev, "There is no kernel module to "
  3813. "support discipline %d\n", discipline);
  3814. rc = -EINVAL;
  3815. }
  3816. return rc;
  3817. }
  3818. void qeth_core_free_discipline(struct qeth_card *card)
  3819. {
  3820. if (card->options.layer2)
  3821. symbol_put(qeth_l2_ccwgroup_driver);
  3822. else
  3823. symbol_put(qeth_l3_ccwgroup_driver);
  3824. card->discipline.ccwgdriver = NULL;
  3825. }
  3826. static void qeth_determine_capabilities(struct qeth_card *card)
  3827. {
  3828. int rc;
  3829. int length;
  3830. char *prcd;
  3831. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3832. rc = ccw_device_set_online(CARD_DDEV(card));
  3833. if (rc) {
  3834. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3835. goto out;
  3836. }
  3837. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3838. if (rc) {
  3839. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3840. dev_name(&card->gdev->dev), rc);
  3841. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3842. goto out_offline;
  3843. }
  3844. qeth_configure_unitaddr(card, prcd);
  3845. qeth_configure_blkt_default(card, prcd);
  3846. kfree(prcd);
  3847. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3848. if (rc)
  3849. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3850. out_offline:
  3851. ccw_device_set_offline(CARD_DDEV(card));
  3852. out:
  3853. return;
  3854. }
  3855. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3856. {
  3857. struct qeth_card *card;
  3858. struct device *dev;
  3859. int rc;
  3860. unsigned long flags;
  3861. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3862. dev = &gdev->dev;
  3863. if (!get_device(dev))
  3864. return -ENODEV;
  3865. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3866. card = qeth_alloc_card();
  3867. if (!card) {
  3868. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3869. rc = -ENOMEM;
  3870. goto err_dev;
  3871. }
  3872. card->read.ccwdev = gdev->cdev[0];
  3873. card->write.ccwdev = gdev->cdev[1];
  3874. card->data.ccwdev = gdev->cdev[2];
  3875. dev_set_drvdata(&gdev->dev, card);
  3876. card->gdev = gdev;
  3877. gdev->cdev[0]->handler = qeth_irq;
  3878. gdev->cdev[1]->handler = qeth_irq;
  3879. gdev->cdev[2]->handler = qeth_irq;
  3880. rc = qeth_determine_card_type(card);
  3881. if (rc) {
  3882. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3883. goto err_card;
  3884. }
  3885. rc = qeth_setup_card(card);
  3886. if (rc) {
  3887. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3888. goto err_card;
  3889. }
  3890. if (card->info.type == QETH_CARD_TYPE_OSN)
  3891. rc = qeth_core_create_osn_attributes(dev);
  3892. else
  3893. rc = qeth_core_create_device_attributes(dev);
  3894. if (rc)
  3895. goto err_card;
  3896. switch (card->info.type) {
  3897. case QETH_CARD_TYPE_OSN:
  3898. case QETH_CARD_TYPE_OSM:
  3899. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3900. if (rc)
  3901. goto err_attr;
  3902. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3903. if (rc)
  3904. goto err_disc;
  3905. case QETH_CARD_TYPE_OSD:
  3906. case QETH_CARD_TYPE_OSX:
  3907. default:
  3908. break;
  3909. }
  3910. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3911. list_add_tail(&card->list, &qeth_core_card_list.list);
  3912. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3913. qeth_determine_capabilities(card);
  3914. return 0;
  3915. err_disc:
  3916. qeth_core_free_discipline(card);
  3917. err_attr:
  3918. if (card->info.type == QETH_CARD_TYPE_OSN)
  3919. qeth_core_remove_osn_attributes(dev);
  3920. else
  3921. qeth_core_remove_device_attributes(dev);
  3922. err_card:
  3923. qeth_core_free_card(card);
  3924. err_dev:
  3925. put_device(dev);
  3926. return rc;
  3927. }
  3928. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3929. {
  3930. unsigned long flags;
  3931. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3932. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3933. if (card->discipline.ccwgdriver) {
  3934. card->discipline.ccwgdriver->remove(gdev);
  3935. qeth_core_free_discipline(card);
  3936. }
  3937. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3938. qeth_core_remove_osn_attributes(&gdev->dev);
  3939. } else {
  3940. qeth_core_remove_device_attributes(&gdev->dev);
  3941. }
  3942. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3943. list_del(&card->list);
  3944. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3945. qeth_core_free_card(card);
  3946. dev_set_drvdata(&gdev->dev, NULL);
  3947. put_device(&gdev->dev);
  3948. return;
  3949. }
  3950. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3951. {
  3952. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3953. int rc = 0;
  3954. int def_discipline;
  3955. if (!card->discipline.ccwgdriver) {
  3956. if (card->info.type == QETH_CARD_TYPE_IQD)
  3957. def_discipline = QETH_DISCIPLINE_LAYER3;
  3958. else
  3959. def_discipline = QETH_DISCIPLINE_LAYER2;
  3960. rc = qeth_core_load_discipline(card, def_discipline);
  3961. if (rc)
  3962. goto err;
  3963. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3964. if (rc)
  3965. goto err;
  3966. }
  3967. rc = card->discipline.ccwgdriver->set_online(gdev);
  3968. err:
  3969. return rc;
  3970. }
  3971. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3972. {
  3973. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3974. return card->discipline.ccwgdriver->set_offline(gdev);
  3975. }
  3976. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3977. {
  3978. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3979. if (card->discipline.ccwgdriver &&
  3980. card->discipline.ccwgdriver->shutdown)
  3981. card->discipline.ccwgdriver->shutdown(gdev);
  3982. }
  3983. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3984. {
  3985. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3986. if (card->discipline.ccwgdriver &&
  3987. card->discipline.ccwgdriver->prepare)
  3988. return card->discipline.ccwgdriver->prepare(gdev);
  3989. return 0;
  3990. }
  3991. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3992. {
  3993. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3994. if (card->discipline.ccwgdriver &&
  3995. card->discipline.ccwgdriver->complete)
  3996. card->discipline.ccwgdriver->complete(gdev);
  3997. }
  3998. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3999. {
  4000. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4001. if (card->discipline.ccwgdriver &&
  4002. card->discipline.ccwgdriver->freeze)
  4003. return card->discipline.ccwgdriver->freeze(gdev);
  4004. return 0;
  4005. }
  4006. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4007. {
  4008. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4009. if (card->discipline.ccwgdriver &&
  4010. card->discipline.ccwgdriver->thaw)
  4011. return card->discipline.ccwgdriver->thaw(gdev);
  4012. return 0;
  4013. }
  4014. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4015. {
  4016. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4017. if (card->discipline.ccwgdriver &&
  4018. card->discipline.ccwgdriver->restore)
  4019. return card->discipline.ccwgdriver->restore(gdev);
  4020. return 0;
  4021. }
  4022. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4023. .owner = THIS_MODULE,
  4024. .name = "qeth",
  4025. .driver_id = 0xD8C5E3C8,
  4026. .probe = qeth_core_probe_device,
  4027. .remove = qeth_core_remove_device,
  4028. .set_online = qeth_core_set_online,
  4029. .set_offline = qeth_core_set_offline,
  4030. .shutdown = qeth_core_shutdown,
  4031. .prepare = qeth_core_prepare,
  4032. .complete = qeth_core_complete,
  4033. .freeze = qeth_core_freeze,
  4034. .thaw = qeth_core_thaw,
  4035. .restore = qeth_core_restore,
  4036. };
  4037. static ssize_t
  4038. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4039. size_t count)
  4040. {
  4041. int err;
  4042. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4043. qeth_core_ccwgroup_driver.driver_id);
  4044. if (err)
  4045. return err;
  4046. else
  4047. return count;
  4048. }
  4049. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4050. static struct {
  4051. const char str[ETH_GSTRING_LEN];
  4052. } qeth_ethtool_stats_keys[] = {
  4053. /* 0 */{"rx skbs"},
  4054. {"rx buffers"},
  4055. {"tx skbs"},
  4056. {"tx buffers"},
  4057. {"tx skbs no packing"},
  4058. {"tx buffers no packing"},
  4059. {"tx skbs packing"},
  4060. {"tx buffers packing"},
  4061. {"tx sg skbs"},
  4062. {"tx sg frags"},
  4063. /* 10 */{"rx sg skbs"},
  4064. {"rx sg frags"},
  4065. {"rx sg page allocs"},
  4066. {"tx large kbytes"},
  4067. {"tx large count"},
  4068. {"tx pk state ch n->p"},
  4069. {"tx pk state ch p->n"},
  4070. {"tx pk watermark low"},
  4071. {"tx pk watermark high"},
  4072. {"queue 0 buffer usage"},
  4073. /* 20 */{"queue 1 buffer usage"},
  4074. {"queue 2 buffer usage"},
  4075. {"queue 3 buffer usage"},
  4076. {"rx handler time"},
  4077. {"rx handler count"},
  4078. {"rx do_QDIO time"},
  4079. {"rx do_QDIO count"},
  4080. {"tx handler time"},
  4081. {"tx handler count"},
  4082. {"tx time"},
  4083. /* 30 */{"tx count"},
  4084. {"tx do_QDIO time"},
  4085. {"tx do_QDIO count"},
  4086. {"tx csum"},
  4087. {"tx lin"},
  4088. };
  4089. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4090. {
  4091. switch (stringset) {
  4092. case ETH_SS_STATS:
  4093. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4094. default:
  4095. return -EINVAL;
  4096. }
  4097. }
  4098. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4099. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4100. struct ethtool_stats *stats, u64 *data)
  4101. {
  4102. struct qeth_card *card = dev->ml_priv;
  4103. data[0] = card->stats.rx_packets -
  4104. card->perf_stats.initial_rx_packets;
  4105. data[1] = card->perf_stats.bufs_rec;
  4106. data[2] = card->stats.tx_packets -
  4107. card->perf_stats.initial_tx_packets;
  4108. data[3] = card->perf_stats.bufs_sent;
  4109. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4110. - card->perf_stats.skbs_sent_pack;
  4111. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4112. data[6] = card->perf_stats.skbs_sent_pack;
  4113. data[7] = card->perf_stats.bufs_sent_pack;
  4114. data[8] = card->perf_stats.sg_skbs_sent;
  4115. data[9] = card->perf_stats.sg_frags_sent;
  4116. data[10] = card->perf_stats.sg_skbs_rx;
  4117. data[11] = card->perf_stats.sg_frags_rx;
  4118. data[12] = card->perf_stats.sg_alloc_page_rx;
  4119. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4120. data[14] = card->perf_stats.large_send_cnt;
  4121. data[15] = card->perf_stats.sc_dp_p;
  4122. data[16] = card->perf_stats.sc_p_dp;
  4123. data[17] = QETH_LOW_WATERMARK_PACK;
  4124. data[18] = QETH_HIGH_WATERMARK_PACK;
  4125. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4126. data[20] = (card->qdio.no_out_queues > 1) ?
  4127. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4128. data[21] = (card->qdio.no_out_queues > 2) ?
  4129. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4130. data[22] = (card->qdio.no_out_queues > 3) ?
  4131. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4132. data[23] = card->perf_stats.inbound_time;
  4133. data[24] = card->perf_stats.inbound_cnt;
  4134. data[25] = card->perf_stats.inbound_do_qdio_time;
  4135. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4136. data[27] = card->perf_stats.outbound_handler_time;
  4137. data[28] = card->perf_stats.outbound_handler_cnt;
  4138. data[29] = card->perf_stats.outbound_time;
  4139. data[30] = card->perf_stats.outbound_cnt;
  4140. data[31] = card->perf_stats.outbound_do_qdio_time;
  4141. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4142. data[33] = card->perf_stats.tx_csum;
  4143. data[34] = card->perf_stats.tx_lin;
  4144. }
  4145. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4146. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4147. {
  4148. switch (stringset) {
  4149. case ETH_SS_STATS:
  4150. memcpy(data, &qeth_ethtool_stats_keys,
  4151. sizeof(qeth_ethtool_stats_keys));
  4152. break;
  4153. default:
  4154. WARN_ON(1);
  4155. break;
  4156. }
  4157. }
  4158. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4159. void qeth_core_get_drvinfo(struct net_device *dev,
  4160. struct ethtool_drvinfo *info)
  4161. {
  4162. struct qeth_card *card = dev->ml_priv;
  4163. if (card->options.layer2)
  4164. strcpy(info->driver, "qeth_l2");
  4165. else
  4166. strcpy(info->driver, "qeth_l3");
  4167. strcpy(info->version, "1.0");
  4168. strcpy(info->fw_version, card->info.mcl_level);
  4169. sprintf(info->bus_info, "%s/%s/%s",
  4170. CARD_RDEV_ID(card),
  4171. CARD_WDEV_ID(card),
  4172. CARD_DDEV_ID(card));
  4173. }
  4174. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4175. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4176. struct ethtool_cmd *ecmd)
  4177. {
  4178. struct qeth_card *card = netdev->ml_priv;
  4179. enum qeth_link_types link_type;
  4180. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4181. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4182. else
  4183. link_type = card->info.link_type;
  4184. ecmd->transceiver = XCVR_INTERNAL;
  4185. ecmd->supported = SUPPORTED_Autoneg;
  4186. ecmd->advertising = ADVERTISED_Autoneg;
  4187. ecmd->duplex = DUPLEX_FULL;
  4188. ecmd->autoneg = AUTONEG_ENABLE;
  4189. switch (link_type) {
  4190. case QETH_LINK_TYPE_FAST_ETH:
  4191. case QETH_LINK_TYPE_LANE_ETH100:
  4192. ecmd->supported |= SUPPORTED_10baseT_Half |
  4193. SUPPORTED_10baseT_Full |
  4194. SUPPORTED_100baseT_Half |
  4195. SUPPORTED_100baseT_Full |
  4196. SUPPORTED_TP;
  4197. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4198. ADVERTISED_10baseT_Full |
  4199. ADVERTISED_100baseT_Half |
  4200. ADVERTISED_100baseT_Full |
  4201. ADVERTISED_TP;
  4202. ecmd->speed = SPEED_100;
  4203. ecmd->port = PORT_TP;
  4204. break;
  4205. case QETH_LINK_TYPE_GBIT_ETH:
  4206. case QETH_LINK_TYPE_LANE_ETH1000:
  4207. ecmd->supported |= SUPPORTED_10baseT_Half |
  4208. SUPPORTED_10baseT_Full |
  4209. SUPPORTED_100baseT_Half |
  4210. SUPPORTED_100baseT_Full |
  4211. SUPPORTED_1000baseT_Half |
  4212. SUPPORTED_1000baseT_Full |
  4213. SUPPORTED_FIBRE;
  4214. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4215. ADVERTISED_10baseT_Full |
  4216. ADVERTISED_100baseT_Half |
  4217. ADVERTISED_100baseT_Full |
  4218. ADVERTISED_1000baseT_Half |
  4219. ADVERTISED_1000baseT_Full |
  4220. ADVERTISED_FIBRE;
  4221. ecmd->speed = SPEED_1000;
  4222. ecmd->port = PORT_FIBRE;
  4223. break;
  4224. case QETH_LINK_TYPE_10GBIT_ETH:
  4225. ecmd->supported |= SUPPORTED_10baseT_Half |
  4226. SUPPORTED_10baseT_Full |
  4227. SUPPORTED_100baseT_Half |
  4228. SUPPORTED_100baseT_Full |
  4229. SUPPORTED_1000baseT_Half |
  4230. SUPPORTED_1000baseT_Full |
  4231. SUPPORTED_10000baseT_Full |
  4232. SUPPORTED_FIBRE;
  4233. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4234. ADVERTISED_10baseT_Full |
  4235. ADVERTISED_100baseT_Half |
  4236. ADVERTISED_100baseT_Full |
  4237. ADVERTISED_1000baseT_Half |
  4238. ADVERTISED_1000baseT_Full |
  4239. ADVERTISED_10000baseT_Full |
  4240. ADVERTISED_FIBRE;
  4241. ecmd->speed = SPEED_10000;
  4242. ecmd->port = PORT_FIBRE;
  4243. break;
  4244. default:
  4245. ecmd->supported |= SUPPORTED_10baseT_Half |
  4246. SUPPORTED_10baseT_Full |
  4247. SUPPORTED_TP;
  4248. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4249. ADVERTISED_10baseT_Full |
  4250. ADVERTISED_TP;
  4251. ecmd->speed = SPEED_10;
  4252. ecmd->port = PORT_TP;
  4253. }
  4254. return 0;
  4255. }
  4256. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4257. static int __init qeth_core_init(void)
  4258. {
  4259. int rc;
  4260. pr_info("loading core functions\n");
  4261. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4262. rwlock_init(&qeth_core_card_list.rwlock);
  4263. rc = qeth_register_dbf_views();
  4264. if (rc)
  4265. goto out_err;
  4266. rc = ccw_driver_register(&qeth_ccw_driver);
  4267. if (rc)
  4268. goto ccw_err;
  4269. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4270. if (rc)
  4271. goto ccwgroup_err;
  4272. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4273. &driver_attr_group);
  4274. if (rc)
  4275. goto driver_err;
  4276. qeth_core_root_dev = root_device_register("qeth");
  4277. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4278. if (rc)
  4279. goto register_err;
  4280. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4281. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4282. if (!qeth_core_header_cache) {
  4283. rc = -ENOMEM;
  4284. goto slab_err;
  4285. }
  4286. return 0;
  4287. slab_err:
  4288. root_device_unregister(qeth_core_root_dev);
  4289. register_err:
  4290. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4291. &driver_attr_group);
  4292. driver_err:
  4293. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4294. ccwgroup_err:
  4295. ccw_driver_unregister(&qeth_ccw_driver);
  4296. ccw_err:
  4297. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4298. qeth_unregister_dbf_views();
  4299. out_err:
  4300. pr_err("Initializing the qeth device driver failed\n");
  4301. return rc;
  4302. }
  4303. static void __exit qeth_core_exit(void)
  4304. {
  4305. root_device_unregister(qeth_core_root_dev);
  4306. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4307. &driver_attr_group);
  4308. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4309. ccw_driver_unregister(&qeth_ccw_driver);
  4310. kmem_cache_destroy(qeth_core_header_cache);
  4311. qeth_unregister_dbf_views();
  4312. pr_info("core functions removed\n");
  4313. }
  4314. module_init(qeth_core_init);
  4315. module_exit(qeth_core_exit);
  4316. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4317. MODULE_DESCRIPTION("qeth core functions");
  4318. MODULE_LICENSE("GPL");