pcie_pme.c 14 KB

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  1. /*
  2. * PCIe Native PME support
  3. *
  4. * Copyright (C) 2007 - 2009 Intel Corp
  5. * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
  6. * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License V2. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/slab.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/device.h>
  20. #include <linux/pcieport_if.h>
  21. #include <linux/acpi.h>
  22. #include <linux/pci-acpi.h>
  23. #include <linux/pm_runtime.h>
  24. #include "../../pci.h"
  25. #include "pcie_pme.h"
  26. #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
  27. #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
  28. /*
  29. * If set, this switch will prevent the PCIe root port PME service driver from
  30. * being registered. Consequently, the interrupt-based PCIe PME signaling will
  31. * not be used by any PCIe root ports in that case.
  32. */
  33. static bool pcie_pme_disabled = true;
  34. /*
  35. * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
  36. * "In order to maintain compatibility with non-PCI Express-aware system
  37. * software, system power management logic must be configured by firmware to use
  38. * the legacy mechanism of signaling PME by default. PCI Express-aware system
  39. * software must notify the firmware prior to enabling native, interrupt-based
  40. * PME signaling." However, if the platform doesn't provide us with a suitable
  41. * notification mechanism or the notification fails, it is not clear whether or
  42. * not we are supposed to use the interrupt-based PCIe PME signaling. The
  43. * switch below can be used to indicate the desired behaviour. When set, it
  44. * will make the kernel use the interrupt-based PCIe PME signaling regardless of
  45. * the platform notification status, although the kernel will attempt to notify
  46. * the platform anyway. When unset, it will prevent the kernel from using the
  47. * the interrupt-based PCIe PME signaling if the platform notification fails,
  48. * which is the default.
  49. */
  50. static bool pcie_pme_force_enable;
  51. /*
  52. * If this switch is set, MSI will not be used for PCIe PME signaling. This
  53. * causes the PCIe port driver to use INTx interrupts only, but it turns out
  54. * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based
  55. * wake-up from system sleep states.
  56. */
  57. bool pcie_pme_msi_disabled;
  58. static int __init pcie_pme_setup(char *str)
  59. {
  60. if (!strncmp(str, "auto", 4))
  61. pcie_pme_disabled = false;
  62. else if (!strncmp(str, "force", 5))
  63. pcie_pme_force_enable = true;
  64. str = strchr(str, ',');
  65. if (str) {
  66. str++;
  67. str += strspn(str, " \t");
  68. if (*str && !strcmp(str, "nomsi"))
  69. pcie_pme_msi_disabled = true;
  70. }
  71. return 1;
  72. }
  73. __setup("pcie_pme=", pcie_pme_setup);
  74. /**
  75. * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME.
  76. * @srv: PCIe PME root port service to use for carrying out the check.
  77. *
  78. * Notify the platform that the native PCIe PME is going to be used and return
  79. * 'true' if the control of the PCIe PME registers has been acquired from the
  80. * platform.
  81. */
  82. static bool pcie_pme_platform_setup(struct pcie_device *srv)
  83. {
  84. if (!pcie_pme_platform_notify(srv))
  85. return true;
  86. return pcie_pme_force_enable;
  87. }
  88. struct pcie_pme_service_data {
  89. spinlock_t lock;
  90. struct pcie_device *srv;
  91. struct work_struct work;
  92. bool noirq; /* Don't enable the PME interrupt used by this service. */
  93. };
  94. /**
  95. * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
  96. * @dev: PCIe root port or event collector.
  97. * @enable: Enable or disable the interrupt.
  98. */
  99. static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
  100. {
  101. int rtctl_pos;
  102. u16 rtctl;
  103. rtctl_pos = pci_pcie_cap(dev) + PCI_EXP_RTCTL;
  104. pci_read_config_word(dev, rtctl_pos, &rtctl);
  105. if (enable)
  106. rtctl |= PCI_EXP_RTCTL_PMEIE;
  107. else
  108. rtctl &= ~PCI_EXP_RTCTL_PMEIE;
  109. pci_write_config_word(dev, rtctl_pos, rtctl);
  110. }
  111. /**
  112. * pcie_pme_clear_status - Clear root port PME interrupt status.
  113. * @dev: PCIe root port or event collector.
  114. */
  115. static void pcie_pme_clear_status(struct pci_dev *dev)
  116. {
  117. int rtsta_pos;
  118. u32 rtsta;
  119. rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
  120. pci_read_config_dword(dev, rtsta_pos, &rtsta);
  121. rtsta |= PCI_EXP_RTSTA_PME;
  122. pci_write_config_dword(dev, rtsta_pos, rtsta);
  123. }
  124. /**
  125. * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#.
  126. * @bus: PCI bus to scan.
  127. *
  128. * Scan given PCI bus and all buses under it for devices asserting PME#.
  129. */
  130. static bool pcie_pme_walk_bus(struct pci_bus *bus)
  131. {
  132. struct pci_dev *dev;
  133. bool ret = false;
  134. list_for_each_entry(dev, &bus->devices, bus_list) {
  135. /* Skip PCIe devices in case we started from a root port. */
  136. if (!pci_is_pcie(dev) && pci_check_pme_status(dev)) {
  137. pm_request_resume(&dev->dev);
  138. ret = true;
  139. }
  140. if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate))
  141. ret = true;
  142. }
  143. return ret;
  144. }
  145. /**
  146. * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME.
  147. * @bus: Secondary bus of the bridge.
  148. * @devfn: Device/function number to check.
  149. *
  150. * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band
  151. * PCIe PME message. In such that case the bridge should use the Requester ID
  152. * of device/function number 0 on its secondary bus.
  153. */
  154. static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
  155. {
  156. struct pci_dev *dev;
  157. bool found = false;
  158. if (devfn)
  159. return false;
  160. dev = pci_dev_get(bus->self);
  161. if (!dev)
  162. return false;
  163. if (pci_is_pcie(dev) && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
  164. down_read(&pci_bus_sem);
  165. if (pcie_pme_walk_bus(bus))
  166. found = true;
  167. up_read(&pci_bus_sem);
  168. }
  169. pci_dev_put(dev);
  170. return found;
  171. }
  172. /**
  173. * pcie_pme_handle_request - Find device that generated PME and handle it.
  174. * @port: Root port or event collector that generated the PME interrupt.
  175. * @req_id: PCIe Requester ID of the device that generated the PME.
  176. */
  177. static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
  178. {
  179. u8 busnr = req_id >> 8, devfn = req_id & 0xff;
  180. struct pci_bus *bus;
  181. struct pci_dev *dev;
  182. bool found = false;
  183. /* First, check if the PME is from the root port itself. */
  184. if (port->devfn == devfn && port->bus->number == busnr) {
  185. if (pci_check_pme_status(port)) {
  186. pm_request_resume(&port->dev);
  187. found = true;
  188. } else {
  189. /*
  190. * Apparently, the root port generated the PME on behalf
  191. * of a non-PCIe device downstream. If this is done by
  192. * a root port, the Requester ID field in its status
  193. * register may contain either the root port's, or the
  194. * source device's information (PCI Express Base
  195. * Specification, Rev. 2.0, Section 6.1.9).
  196. */
  197. down_read(&pci_bus_sem);
  198. found = pcie_pme_walk_bus(port->subordinate);
  199. up_read(&pci_bus_sem);
  200. }
  201. goto out;
  202. }
  203. /* Second, find the bus the source device is on. */
  204. bus = pci_find_bus(pci_domain_nr(port->bus), busnr);
  205. if (!bus)
  206. goto out;
  207. /* Next, check if the PME is from a PCIe-PCI bridge. */
  208. found = pcie_pme_from_pci_bridge(bus, devfn);
  209. if (found)
  210. goto out;
  211. /* Finally, try to find the PME source on the bus. */
  212. down_read(&pci_bus_sem);
  213. list_for_each_entry(dev, &bus->devices, bus_list) {
  214. pci_dev_get(dev);
  215. if (dev->devfn == devfn) {
  216. found = true;
  217. break;
  218. }
  219. pci_dev_put(dev);
  220. }
  221. up_read(&pci_bus_sem);
  222. if (found) {
  223. /* The device is there, but we have to check its PME status. */
  224. found = pci_check_pme_status(dev);
  225. if (found)
  226. pm_request_resume(&dev->dev);
  227. pci_dev_put(dev);
  228. } else if (devfn) {
  229. /*
  230. * The device is not there, but we can still try to recover by
  231. * assuming that the PME was reported by a PCIe-PCI bridge that
  232. * used devfn different from zero.
  233. */
  234. dev_dbg(&port->dev, "PME interrupt generated for "
  235. "non-existent device %02x:%02x.%d\n",
  236. busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
  237. found = pcie_pme_from_pci_bridge(bus, 0);
  238. }
  239. out:
  240. if (!found)
  241. dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
  242. }
  243. /**
  244. * pcie_pme_work_fn - Work handler for PCIe PME interrupt.
  245. * @work: Work structure giving access to service data.
  246. */
  247. static void pcie_pme_work_fn(struct work_struct *work)
  248. {
  249. struct pcie_pme_service_data *data =
  250. container_of(work, struct pcie_pme_service_data, work);
  251. struct pci_dev *port = data->srv->port;
  252. int rtsta_pos;
  253. u32 rtsta;
  254. rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
  255. spin_lock_irq(&data->lock);
  256. for (;;) {
  257. if (data->noirq)
  258. break;
  259. pci_read_config_dword(port, rtsta_pos, &rtsta);
  260. if (rtsta & PCI_EXP_RTSTA_PME) {
  261. /*
  262. * Clear PME status of the port. If there are other
  263. * pending PMEs, the status will be set again.
  264. */
  265. pcie_pme_clear_status(port);
  266. spin_unlock_irq(&data->lock);
  267. pcie_pme_handle_request(port, rtsta & 0xffff);
  268. spin_lock_irq(&data->lock);
  269. continue;
  270. }
  271. /* No need to loop if there are no more PMEs pending. */
  272. if (!(rtsta & PCI_EXP_RTSTA_PENDING))
  273. break;
  274. spin_unlock_irq(&data->lock);
  275. cpu_relax();
  276. spin_lock_irq(&data->lock);
  277. }
  278. if (!data->noirq)
  279. pcie_pme_interrupt_enable(port, true);
  280. spin_unlock_irq(&data->lock);
  281. }
  282. /**
  283. * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt.
  284. * @irq: Interrupt vector.
  285. * @context: Interrupt context pointer.
  286. */
  287. static irqreturn_t pcie_pme_irq(int irq, void *context)
  288. {
  289. struct pci_dev *port;
  290. struct pcie_pme_service_data *data;
  291. int rtsta_pos;
  292. u32 rtsta;
  293. unsigned long flags;
  294. port = ((struct pcie_device *)context)->port;
  295. data = get_service_data((struct pcie_device *)context);
  296. rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
  297. spin_lock_irqsave(&data->lock, flags);
  298. pci_read_config_dword(port, rtsta_pos, &rtsta);
  299. if (!(rtsta & PCI_EXP_RTSTA_PME)) {
  300. spin_unlock_irqrestore(&data->lock, flags);
  301. return IRQ_NONE;
  302. }
  303. pcie_pme_interrupt_enable(port, false);
  304. spin_unlock_irqrestore(&data->lock, flags);
  305. /* We don't use pm_wq, because it's freezable. */
  306. schedule_work(&data->work);
  307. return IRQ_HANDLED;
  308. }
  309. /**
  310. * pcie_pme_set_native - Set the PME interrupt flag for given device.
  311. * @dev: PCI device to handle.
  312. * @ign: Ignored.
  313. */
  314. static int pcie_pme_set_native(struct pci_dev *dev, void *ign)
  315. {
  316. dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n");
  317. device_set_run_wake(&dev->dev, true);
  318. dev->pme_interrupt = true;
  319. return 0;
  320. }
  321. /**
  322. * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port.
  323. * @port: PCIe root port or event collector to handle.
  324. *
  325. * For each device below given root port, including the port itself (or for each
  326. * root complex integrated endpoint if @port is a root complex event collector)
  327. * set the flag indicating that it can signal run-time wake-up events via PCIe
  328. * PME interrupts.
  329. */
  330. static void pcie_pme_mark_devices(struct pci_dev *port)
  331. {
  332. pcie_pme_set_native(port, NULL);
  333. if (port->subordinate) {
  334. pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL);
  335. } else {
  336. struct pci_bus *bus = port->bus;
  337. struct pci_dev *dev;
  338. /* Check if this is a root port event collector. */
  339. if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
  340. return;
  341. down_read(&pci_bus_sem);
  342. list_for_each_entry(dev, &bus->devices, bus_list)
  343. if (pci_is_pcie(dev)
  344. && dev->pcie_type == PCI_EXP_TYPE_RC_END)
  345. pcie_pme_set_native(dev, NULL);
  346. up_read(&pci_bus_sem);
  347. }
  348. }
  349. /**
  350. * pcie_pme_probe - Initialize PCIe PME service for given root port.
  351. * @srv: PCIe service to initialize.
  352. */
  353. static int pcie_pme_probe(struct pcie_device *srv)
  354. {
  355. struct pci_dev *port;
  356. struct pcie_pme_service_data *data;
  357. int ret;
  358. if (!pcie_pme_platform_setup(srv))
  359. return -EACCES;
  360. data = kzalloc(sizeof(*data), GFP_KERNEL);
  361. if (!data)
  362. return -ENOMEM;
  363. spin_lock_init(&data->lock);
  364. INIT_WORK(&data->work, pcie_pme_work_fn);
  365. data->srv = srv;
  366. set_service_data(srv, data);
  367. port = srv->port;
  368. pcie_pme_interrupt_enable(port, false);
  369. pcie_pme_clear_status(port);
  370. ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv);
  371. if (ret) {
  372. kfree(data);
  373. } else {
  374. pcie_pme_mark_devices(port);
  375. pcie_pme_interrupt_enable(port, true);
  376. }
  377. return ret;
  378. }
  379. /**
  380. * pcie_pme_suspend - Suspend PCIe PME service device.
  381. * @srv: PCIe service device to suspend.
  382. */
  383. static int pcie_pme_suspend(struct pcie_device *srv)
  384. {
  385. struct pcie_pme_service_data *data = get_service_data(srv);
  386. struct pci_dev *port = srv->port;
  387. spin_lock_irq(&data->lock);
  388. pcie_pme_interrupt_enable(port, false);
  389. pcie_pme_clear_status(port);
  390. data->noirq = true;
  391. spin_unlock_irq(&data->lock);
  392. synchronize_irq(srv->irq);
  393. return 0;
  394. }
  395. /**
  396. * pcie_pme_resume - Resume PCIe PME service device.
  397. * @srv - PCIe service device to resume.
  398. */
  399. static int pcie_pme_resume(struct pcie_device *srv)
  400. {
  401. struct pcie_pme_service_data *data = get_service_data(srv);
  402. struct pci_dev *port = srv->port;
  403. spin_lock_irq(&data->lock);
  404. data->noirq = false;
  405. pcie_pme_clear_status(port);
  406. pcie_pme_interrupt_enable(port, true);
  407. spin_unlock_irq(&data->lock);
  408. return 0;
  409. }
  410. /**
  411. * pcie_pme_remove - Prepare PCIe PME service device for removal.
  412. * @srv - PCIe service device to resume.
  413. */
  414. static void pcie_pme_remove(struct pcie_device *srv)
  415. {
  416. pcie_pme_suspend(srv);
  417. free_irq(srv->irq, srv);
  418. kfree(get_service_data(srv));
  419. }
  420. static struct pcie_port_service_driver pcie_pme_driver = {
  421. .name = "pcie_pme",
  422. .port_type = PCI_EXP_TYPE_ROOT_PORT,
  423. .service = PCIE_PORT_SERVICE_PME,
  424. .probe = pcie_pme_probe,
  425. .suspend = pcie_pme_suspend,
  426. .resume = pcie_pme_resume,
  427. .remove = pcie_pme_remove,
  428. };
  429. /**
  430. * pcie_pme_service_init - Register the PCIe PME service driver.
  431. */
  432. static int __init pcie_pme_service_init(void)
  433. {
  434. return pcie_pme_disabled ?
  435. -ENODEV : pcie_port_service_register(&pcie_pme_driver);
  436. }
  437. module_init(pcie_pme_service_init);