rt2800lib.c 91 KB

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  1. /*
  2. Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
  3. Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
  4. Based on the original rt2800pci.c and rt2800usb.c.
  5. Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
  6. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  7. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  8. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  9. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  10. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  11. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  12. <http://rt2x00.serialmonkey.com>
  13. This program is free software; you can redistribute it and/or modify
  14. it under the terms of the GNU General Public License as published by
  15. the Free Software Foundation; either version 2 of the License, or
  16. (at your option) any later version.
  17. This program is distributed in the hope that it will be useful,
  18. but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. GNU General Public License for more details.
  21. You should have received a copy of the GNU General Public License
  22. along with this program; if not, write to the
  23. Free Software Foundation, Inc.,
  24. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  25. */
  26. /*
  27. Module: rt2800lib
  28. Abstract: rt2800 generic device routines.
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/slab.h>
  33. #include "rt2x00.h"
  34. #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  35. #include "rt2x00usb.h"
  36. #endif
  37. #include "rt2800lib.h"
  38. #include "rt2800.h"
  39. #include "rt2800usb.h"
  40. MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  41. MODULE_DESCRIPTION("rt2800 library");
  42. MODULE_LICENSE("GPL");
  43. /*
  44. * Register access.
  45. * All access to the CSR registers will go through the methods
  46. * rt2800_register_read and rt2800_register_write.
  47. * BBP and RF register require indirect register access,
  48. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  49. * These indirect registers work with busy bits,
  50. * and we will try maximal REGISTER_BUSY_COUNT times to access
  51. * the register while taking a REGISTER_BUSY_DELAY us delay
  52. * between each attampt. When the busy bit is still set at that time,
  53. * the access attempt is considered to have failed,
  54. * and we will print an error.
  55. * The _lock versions must be used if you already hold the csr_mutex
  56. */
  57. #define WAIT_FOR_BBP(__dev, __reg) \
  58. rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  59. #define WAIT_FOR_RFCSR(__dev, __reg) \
  60. rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  61. #define WAIT_FOR_RF(__dev, __reg) \
  62. rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  63. #define WAIT_FOR_MCU(__dev, __reg) \
  64. rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  65. H2M_MAILBOX_CSR_OWNER, (__reg))
  66. static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  67. {
  68. /* check for rt2872 on SoC */
  69. if (!rt2x00_is_soc(rt2x00dev) ||
  70. !rt2x00_rt(rt2x00dev, RT2872))
  71. return false;
  72. /* we know for sure that these rf chipsets are used on rt305x boards */
  73. if (rt2x00_rf(rt2x00dev, RF3020) ||
  74. rt2x00_rf(rt2x00dev, RF3021) ||
  75. rt2x00_rf(rt2x00dev, RF3022))
  76. return true;
  77. NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  78. return false;
  79. }
  80. static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  81. const unsigned int word, const u8 value)
  82. {
  83. u32 reg;
  84. mutex_lock(&rt2x00dev->csr_mutex);
  85. /*
  86. * Wait until the BBP becomes available, afterwards we
  87. * can safely write the new data into the register.
  88. */
  89. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  90. reg = 0;
  91. rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  92. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  93. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  94. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  95. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  96. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  97. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  98. }
  99. mutex_unlock(&rt2x00dev->csr_mutex);
  100. }
  101. static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
  102. const unsigned int word, u8 *value)
  103. {
  104. u32 reg;
  105. mutex_lock(&rt2x00dev->csr_mutex);
  106. /*
  107. * Wait until the BBP becomes available, afterwards we
  108. * can safely write the read request into the register.
  109. * After the data has been written, we wait until hardware
  110. * returns the correct value, if at any time the register
  111. * doesn't become available in time, reg will be 0xffffffff
  112. * which means we return 0xff to the caller.
  113. */
  114. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  115. reg = 0;
  116. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  117. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  118. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
  119. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  120. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  121. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  122. WAIT_FOR_BBP(rt2x00dev, &reg);
  123. }
  124. *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
  125. mutex_unlock(&rt2x00dev->csr_mutex);
  126. }
  127. static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  128. const unsigned int word, const u8 value)
  129. {
  130. u32 reg;
  131. mutex_lock(&rt2x00dev->csr_mutex);
  132. /*
  133. * Wait until the RFCSR becomes available, afterwards we
  134. * can safely write the new data into the register.
  135. */
  136. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  137. reg = 0;
  138. rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  139. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  140. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  141. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  142. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  143. }
  144. mutex_unlock(&rt2x00dev->csr_mutex);
  145. }
  146. static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  147. const unsigned int word, u8 *value)
  148. {
  149. u32 reg;
  150. mutex_lock(&rt2x00dev->csr_mutex);
  151. /*
  152. * Wait until the RFCSR becomes available, afterwards we
  153. * can safely write the read request into the register.
  154. * After the data has been written, we wait until hardware
  155. * returns the correct value, if at any time the register
  156. * doesn't become available in time, reg will be 0xffffffff
  157. * which means we return 0xff to the caller.
  158. */
  159. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  160. reg = 0;
  161. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  162. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  163. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  164. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  165. WAIT_FOR_RFCSR(rt2x00dev, &reg);
  166. }
  167. *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  168. mutex_unlock(&rt2x00dev->csr_mutex);
  169. }
  170. static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
  171. const unsigned int word, const u32 value)
  172. {
  173. u32 reg;
  174. mutex_lock(&rt2x00dev->csr_mutex);
  175. /*
  176. * Wait until the RF becomes available, afterwards we
  177. * can safely write the new data into the register.
  178. */
  179. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  180. reg = 0;
  181. rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
  182. rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
  183. rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
  184. rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
  185. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
  186. rt2x00_rf_write(rt2x00dev, word, value);
  187. }
  188. mutex_unlock(&rt2x00dev->csr_mutex);
  189. }
  190. void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
  191. const u8 command, const u8 token,
  192. const u8 arg0, const u8 arg1)
  193. {
  194. u32 reg;
  195. /*
  196. * SOC devices don't support MCU requests.
  197. */
  198. if (rt2x00_is_soc(rt2x00dev))
  199. return;
  200. mutex_lock(&rt2x00dev->csr_mutex);
  201. /*
  202. * Wait until the MCU becomes available, afterwards we
  203. * can safely write the new data into the register.
  204. */
  205. if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  206. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  207. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  208. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  209. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  210. rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
  211. reg = 0;
  212. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  213. rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
  214. }
  215. mutex_unlock(&rt2x00dev->csr_mutex);
  216. }
  217. EXPORT_SYMBOL_GPL(rt2800_mcu_request);
  218. int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
  219. {
  220. unsigned int i;
  221. u32 reg;
  222. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  223. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  224. if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
  225. !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
  226. return 0;
  227. msleep(1);
  228. }
  229. ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
  230. return -EACCES;
  231. }
  232. EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
  233. void rt2800_write_txwi(struct sk_buff *skb, struct txentry_desc *txdesc)
  234. {
  235. __le32 *txwi = (__le32 *)(skb->data - TXWI_DESC_SIZE);
  236. u32 word;
  237. /*
  238. * Initialize TX Info descriptor
  239. */
  240. rt2x00_desc_read(txwi, 0, &word);
  241. rt2x00_set_field32(&word, TXWI_W0_FRAG,
  242. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  243. rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
  244. rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
  245. rt2x00_set_field32(&word, TXWI_W0_TS,
  246. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  247. rt2x00_set_field32(&word, TXWI_W0_AMPDU,
  248. test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
  249. rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
  250. rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
  251. rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
  252. rt2x00_set_field32(&word, TXWI_W0_BW,
  253. test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
  254. rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
  255. test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
  256. rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
  257. rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
  258. rt2x00_desc_write(txwi, 0, word);
  259. rt2x00_desc_read(txwi, 1, &word);
  260. rt2x00_set_field32(&word, TXWI_W1_ACK,
  261. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  262. rt2x00_set_field32(&word, TXWI_W1_NSEQ,
  263. test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
  264. rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
  265. rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
  266. test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
  267. txdesc->key_idx : 0xff);
  268. rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
  269. txdesc->length);
  270. rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
  271. rt2x00_desc_write(txwi, 1, word);
  272. /*
  273. * Always write 0 to IV/EIV fields, hardware will insert the IV
  274. * from the IVEIV register when TXD_W3_WIV is set to 0.
  275. * When TXD_W3_WIV is set to 1 it will use the IV data
  276. * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
  277. * crypto entry in the registers should be used to encrypt the frame.
  278. */
  279. _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
  280. _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
  281. }
  282. EXPORT_SYMBOL_GPL(rt2800_write_txwi);
  283. void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
  284. {
  285. __le32 *rxwi = (__le32 *) skb->data;
  286. u32 word;
  287. rt2x00_desc_read(rxwi, 0, &word);
  288. rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
  289. rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
  290. rt2x00_desc_read(rxwi, 1, &word);
  291. if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
  292. rxdesc->flags |= RX_FLAG_SHORT_GI;
  293. if (rt2x00_get_field32(word, RXWI_W1_BW))
  294. rxdesc->flags |= RX_FLAG_40MHZ;
  295. /*
  296. * Detect RX rate, always use MCS as signal type.
  297. */
  298. rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
  299. rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
  300. rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
  301. /*
  302. * Mask of 0x8 bit to remove the short preamble flag.
  303. */
  304. if (rxdesc->rate_mode == RATE_MODE_CCK)
  305. rxdesc->signal &= ~0x8;
  306. rt2x00_desc_read(rxwi, 2, &word);
  307. rxdesc->rssi =
  308. (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
  309. rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
  310. /*
  311. * Remove RXWI descriptor from start of buffer.
  312. */
  313. skb_pull(skb, RXWI_DESC_SIZE);
  314. }
  315. EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
  316. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  317. const struct rt2x00debug rt2800_rt2x00debug = {
  318. .owner = THIS_MODULE,
  319. .csr = {
  320. .read = rt2800_register_read,
  321. .write = rt2800_register_write,
  322. .flags = RT2X00DEBUGFS_OFFSET,
  323. .word_base = CSR_REG_BASE,
  324. .word_size = sizeof(u32),
  325. .word_count = CSR_REG_SIZE / sizeof(u32),
  326. },
  327. .eeprom = {
  328. .read = rt2x00_eeprom_read,
  329. .write = rt2x00_eeprom_write,
  330. .word_base = EEPROM_BASE,
  331. .word_size = sizeof(u16),
  332. .word_count = EEPROM_SIZE / sizeof(u16),
  333. },
  334. .bbp = {
  335. .read = rt2800_bbp_read,
  336. .write = rt2800_bbp_write,
  337. .word_base = BBP_BASE,
  338. .word_size = sizeof(u8),
  339. .word_count = BBP_SIZE / sizeof(u8),
  340. },
  341. .rf = {
  342. .read = rt2x00_rf_read,
  343. .write = rt2800_rf_write,
  344. .word_base = RF_BASE,
  345. .word_size = sizeof(u32),
  346. .word_count = RF_SIZE / sizeof(u32),
  347. },
  348. };
  349. EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
  350. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  351. int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  352. {
  353. u32 reg;
  354. rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
  355. return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
  356. }
  357. EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
  358. #ifdef CONFIG_RT2X00_LIB_LEDS
  359. static void rt2800_brightness_set(struct led_classdev *led_cdev,
  360. enum led_brightness brightness)
  361. {
  362. struct rt2x00_led *led =
  363. container_of(led_cdev, struct rt2x00_led, led_dev);
  364. unsigned int enabled = brightness != LED_OFF;
  365. unsigned int bg_mode =
  366. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  367. unsigned int polarity =
  368. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  369. EEPROM_FREQ_LED_POLARITY);
  370. unsigned int ledmode =
  371. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  372. EEPROM_FREQ_LED_MODE);
  373. if (led->type == LED_TYPE_RADIO) {
  374. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  375. enabled ? 0x20 : 0);
  376. } else if (led->type == LED_TYPE_ASSOC) {
  377. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  378. enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
  379. } else if (led->type == LED_TYPE_QUALITY) {
  380. /*
  381. * The brightness is divided into 6 levels (0 - 5),
  382. * The specs tell us the following levels:
  383. * 0, 1 ,3, 7, 15, 31
  384. * to determine the level in a simple way we can simply
  385. * work with bitshifting:
  386. * (1 << level) - 1
  387. */
  388. rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
  389. (1 << brightness / (LED_FULL / 6)) - 1,
  390. polarity);
  391. }
  392. }
  393. static int rt2800_blink_set(struct led_classdev *led_cdev,
  394. unsigned long *delay_on, unsigned long *delay_off)
  395. {
  396. struct rt2x00_led *led =
  397. container_of(led_cdev, struct rt2x00_led, led_dev);
  398. u32 reg;
  399. rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
  400. rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
  401. rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
  402. rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
  403. return 0;
  404. }
  405. static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
  406. struct rt2x00_led *led, enum led_type type)
  407. {
  408. led->rt2x00dev = rt2x00dev;
  409. led->type = type;
  410. led->led_dev.brightness_set = rt2800_brightness_set;
  411. led->led_dev.blink_set = rt2800_blink_set;
  412. led->flags = LED_INITIALIZED;
  413. }
  414. #endif /* CONFIG_RT2X00_LIB_LEDS */
  415. /*
  416. * Configuration handlers.
  417. */
  418. static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
  419. struct rt2x00lib_crypto *crypto,
  420. struct ieee80211_key_conf *key)
  421. {
  422. struct mac_wcid_entry wcid_entry;
  423. struct mac_iveiv_entry iveiv_entry;
  424. u32 offset;
  425. u32 reg;
  426. offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
  427. rt2800_register_read(rt2x00dev, offset, &reg);
  428. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
  429. !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
  430. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
  431. (crypto->cmd == SET_KEY) * crypto->cipher);
  432. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
  433. (crypto->cmd == SET_KEY) * crypto->bssidx);
  434. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
  435. rt2800_register_write(rt2x00dev, offset, reg);
  436. offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
  437. memset(&iveiv_entry, 0, sizeof(iveiv_entry));
  438. if ((crypto->cipher == CIPHER_TKIP) ||
  439. (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
  440. (crypto->cipher == CIPHER_AES))
  441. iveiv_entry.iv[3] |= 0x20;
  442. iveiv_entry.iv[3] |= key->keyidx << 6;
  443. rt2800_register_multiwrite(rt2x00dev, offset,
  444. &iveiv_entry, sizeof(iveiv_entry));
  445. offset = MAC_WCID_ENTRY(key->hw_key_idx);
  446. memset(&wcid_entry, 0, sizeof(wcid_entry));
  447. if (crypto->cmd == SET_KEY)
  448. memcpy(&wcid_entry, crypto->address, ETH_ALEN);
  449. rt2800_register_multiwrite(rt2x00dev, offset,
  450. &wcid_entry, sizeof(wcid_entry));
  451. }
  452. int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
  453. struct rt2x00lib_crypto *crypto,
  454. struct ieee80211_key_conf *key)
  455. {
  456. struct hw_key_entry key_entry;
  457. struct rt2x00_field32 field;
  458. u32 offset;
  459. u32 reg;
  460. if (crypto->cmd == SET_KEY) {
  461. key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
  462. memcpy(key_entry.key, crypto->key,
  463. sizeof(key_entry.key));
  464. memcpy(key_entry.tx_mic, crypto->tx_mic,
  465. sizeof(key_entry.tx_mic));
  466. memcpy(key_entry.rx_mic, crypto->rx_mic,
  467. sizeof(key_entry.rx_mic));
  468. offset = SHARED_KEY_ENTRY(key->hw_key_idx);
  469. rt2800_register_multiwrite(rt2x00dev, offset,
  470. &key_entry, sizeof(key_entry));
  471. }
  472. /*
  473. * The cipher types are stored over multiple registers
  474. * starting with SHARED_KEY_MODE_BASE each word will have
  475. * 32 bits and contains the cipher types for 2 bssidx each.
  476. * Using the correct defines correctly will cause overhead,
  477. * so just calculate the correct offset.
  478. */
  479. field.bit_offset = 4 * (key->hw_key_idx % 8);
  480. field.bit_mask = 0x7 << field.bit_offset;
  481. offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
  482. rt2800_register_read(rt2x00dev, offset, &reg);
  483. rt2x00_set_field32(&reg, field,
  484. (crypto->cmd == SET_KEY) * crypto->cipher);
  485. rt2800_register_write(rt2x00dev, offset, reg);
  486. /*
  487. * Update WCID information
  488. */
  489. rt2800_config_wcid_attr(rt2x00dev, crypto, key);
  490. return 0;
  491. }
  492. EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
  493. int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
  494. struct rt2x00lib_crypto *crypto,
  495. struct ieee80211_key_conf *key)
  496. {
  497. struct hw_key_entry key_entry;
  498. u32 offset;
  499. if (crypto->cmd == SET_KEY) {
  500. /*
  501. * 1 pairwise key is possible per AID, this means that the AID
  502. * equals our hw_key_idx. Make sure the WCID starts _after_ the
  503. * last possible shared key entry.
  504. */
  505. if (crypto->aid > (256 - 32))
  506. return -ENOSPC;
  507. key->hw_key_idx = 32 + crypto->aid;
  508. memcpy(key_entry.key, crypto->key,
  509. sizeof(key_entry.key));
  510. memcpy(key_entry.tx_mic, crypto->tx_mic,
  511. sizeof(key_entry.tx_mic));
  512. memcpy(key_entry.rx_mic, crypto->rx_mic,
  513. sizeof(key_entry.rx_mic));
  514. offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
  515. rt2800_register_multiwrite(rt2x00dev, offset,
  516. &key_entry, sizeof(key_entry));
  517. }
  518. /*
  519. * Update WCID information
  520. */
  521. rt2800_config_wcid_attr(rt2x00dev, crypto, key);
  522. return 0;
  523. }
  524. EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
  525. void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
  526. const unsigned int filter_flags)
  527. {
  528. u32 reg;
  529. /*
  530. * Start configuration steps.
  531. * Note that the version error will always be dropped
  532. * and broadcast frames will always be accepted since
  533. * there is no filter for it at this time.
  534. */
  535. rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
  536. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
  537. !(filter_flags & FIF_FCSFAIL));
  538. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
  539. !(filter_flags & FIF_PLCPFAIL));
  540. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
  541. !(filter_flags & FIF_PROMISC_IN_BSS));
  542. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
  543. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
  544. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
  545. !(filter_flags & FIF_ALLMULTI));
  546. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
  547. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
  548. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
  549. !(filter_flags & FIF_CONTROL));
  550. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
  551. !(filter_flags & FIF_CONTROL));
  552. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
  553. !(filter_flags & FIF_CONTROL));
  554. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
  555. !(filter_flags & FIF_CONTROL));
  556. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
  557. !(filter_flags & FIF_CONTROL));
  558. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
  559. !(filter_flags & FIF_PSPOLL));
  560. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
  561. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
  562. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
  563. !(filter_flags & FIF_CONTROL));
  564. rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
  565. }
  566. EXPORT_SYMBOL_GPL(rt2800_config_filter);
  567. void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
  568. struct rt2x00intf_conf *conf, const unsigned int flags)
  569. {
  570. unsigned int beacon_base;
  571. u32 reg;
  572. if (flags & CONFIG_UPDATE_TYPE) {
  573. /*
  574. * Clear current synchronisation setup.
  575. * For the Beacon base registers we only need to clear
  576. * the first byte since that byte contains the VALID and OWNER
  577. * bits which (when set to 0) will invalidate the entire beacon.
  578. */
  579. beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
  580. rt2800_register_write(rt2x00dev, beacon_base, 0);
  581. /*
  582. * Enable synchronisation.
  583. */
  584. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  585. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
  586. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
  587. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
  588. (conf->sync == TSF_SYNC_BEACON));
  589. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  590. }
  591. if (flags & CONFIG_UPDATE_MAC) {
  592. reg = le32_to_cpu(conf->mac[1]);
  593. rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
  594. conf->mac[1] = cpu_to_le32(reg);
  595. rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
  596. conf->mac, sizeof(conf->mac));
  597. }
  598. if (flags & CONFIG_UPDATE_BSSID) {
  599. reg = le32_to_cpu(conf->bssid[1]);
  600. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
  601. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
  602. conf->bssid[1] = cpu_to_le32(reg);
  603. rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
  604. conf->bssid, sizeof(conf->bssid));
  605. }
  606. }
  607. EXPORT_SYMBOL_GPL(rt2800_config_intf);
  608. void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
  609. {
  610. u32 reg;
  611. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  612. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
  613. !!erp->short_preamble);
  614. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
  615. !!erp->short_preamble);
  616. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  617. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  618. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
  619. erp->cts_protection ? 2 : 0);
  620. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  621. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
  622. erp->basic_rates);
  623. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  624. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  625. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
  626. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  627. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  628. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
  629. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  630. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  631. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
  632. erp->beacon_int * 16);
  633. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  634. }
  635. EXPORT_SYMBOL_GPL(rt2800_config_erp);
  636. void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
  637. {
  638. u8 r1;
  639. u8 r3;
  640. rt2800_bbp_read(rt2x00dev, 1, &r1);
  641. rt2800_bbp_read(rt2x00dev, 3, &r3);
  642. /*
  643. * Configure the TX antenna.
  644. */
  645. switch ((int)ant->tx) {
  646. case 1:
  647. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
  648. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  649. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  650. break;
  651. case 2:
  652. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
  653. break;
  654. case 3:
  655. /* Do nothing */
  656. break;
  657. }
  658. /*
  659. * Configure the RX antenna.
  660. */
  661. switch ((int)ant->rx) {
  662. case 1:
  663. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  664. break;
  665. case 2:
  666. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
  667. break;
  668. case 3:
  669. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
  670. break;
  671. }
  672. rt2800_bbp_write(rt2x00dev, 3, r3);
  673. rt2800_bbp_write(rt2x00dev, 1, r1);
  674. }
  675. EXPORT_SYMBOL_GPL(rt2800_config_ant);
  676. static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
  677. struct rt2x00lib_conf *libconf)
  678. {
  679. u16 eeprom;
  680. short lna_gain;
  681. if (libconf->rf.channel <= 14) {
  682. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  683. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
  684. } else if (libconf->rf.channel <= 64) {
  685. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  686. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
  687. } else if (libconf->rf.channel <= 128) {
  688. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
  689. lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
  690. } else {
  691. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
  692. lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
  693. }
  694. rt2x00dev->lna_gain = lna_gain;
  695. }
  696. static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
  697. struct ieee80211_conf *conf,
  698. struct rf_channel *rf,
  699. struct channel_info *info)
  700. {
  701. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  702. if (rt2x00dev->default_ant.tx == 1)
  703. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
  704. if (rt2x00dev->default_ant.rx == 1) {
  705. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
  706. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  707. } else if (rt2x00dev->default_ant.rx == 2)
  708. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  709. if (rf->channel > 14) {
  710. /*
  711. * When TX power is below 0, we should increase it by 7 to
  712. * make it a positive value (Minumum value is -7).
  713. * However this means that values between 0 and 7 have
  714. * double meaning, and we should set a 7DBm boost flag.
  715. */
  716. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
  717. (info->tx_power1 >= 0));
  718. if (info->tx_power1 < 0)
  719. info->tx_power1 += 7;
  720. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
  721. TXPOWER_A_TO_DEV(info->tx_power1));
  722. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
  723. (info->tx_power2 >= 0));
  724. if (info->tx_power2 < 0)
  725. info->tx_power2 += 7;
  726. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
  727. TXPOWER_A_TO_DEV(info->tx_power2));
  728. } else {
  729. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
  730. TXPOWER_G_TO_DEV(info->tx_power1));
  731. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
  732. TXPOWER_G_TO_DEV(info->tx_power2));
  733. }
  734. rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
  735. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  736. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  737. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  738. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  739. udelay(200);
  740. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  741. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  742. rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  743. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  744. udelay(200);
  745. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  746. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  747. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  748. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  749. }
  750. static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
  751. struct ieee80211_conf *conf,
  752. struct rf_channel *rf,
  753. struct channel_info *info)
  754. {
  755. u8 rfcsr;
  756. rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
  757. rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
  758. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  759. rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
  760. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  761. rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
  762. rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
  763. TXPOWER_G_TO_DEV(info->tx_power1));
  764. rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
  765. rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
  766. rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
  767. TXPOWER_G_TO_DEV(info->tx_power2));
  768. rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
  769. rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
  770. rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
  771. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  772. rt2800_rfcsr_write(rt2x00dev, 24,
  773. rt2x00dev->calibration[conf_is_ht40(conf)]);
  774. rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
  775. rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
  776. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  777. }
  778. static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  779. struct ieee80211_conf *conf,
  780. struct rf_channel *rf,
  781. struct channel_info *info)
  782. {
  783. u32 reg;
  784. unsigned int tx_pin;
  785. u8 bbp;
  786. if (rt2x00_rf(rt2x00dev, RF2020) ||
  787. rt2x00_rf(rt2x00dev, RF3020) ||
  788. rt2x00_rf(rt2x00dev, RF3021) ||
  789. rt2x00_rf(rt2x00dev, RF3022))
  790. rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
  791. else
  792. rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
  793. /*
  794. * Change BBP settings
  795. */
  796. rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
  797. rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
  798. rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
  799. rt2800_bbp_write(rt2x00dev, 86, 0);
  800. if (rf->channel <= 14) {
  801. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  802. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  803. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  804. } else {
  805. rt2800_bbp_write(rt2x00dev, 82, 0x84);
  806. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  807. }
  808. } else {
  809. rt2800_bbp_write(rt2x00dev, 82, 0xf2);
  810. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  811. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  812. else
  813. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  814. }
  815. rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
  816. rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
  817. rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
  818. rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
  819. rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
  820. tx_pin = 0;
  821. /* Turn on unused PA or LNA when not using 1T or 1R */
  822. if (rt2x00dev->default_ant.tx != 1) {
  823. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
  824. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
  825. }
  826. /* Turn on unused PA or LNA when not using 1T or 1R */
  827. if (rt2x00dev->default_ant.rx != 1) {
  828. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
  829. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
  830. }
  831. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
  832. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
  833. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
  834. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
  835. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
  836. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
  837. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  838. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  839. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
  840. rt2800_bbp_write(rt2x00dev, 4, bbp);
  841. rt2800_bbp_read(rt2x00dev, 3, &bbp);
  842. rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
  843. rt2800_bbp_write(rt2x00dev, 3, bbp);
  844. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
  845. if (conf_is_ht40(conf)) {
  846. rt2800_bbp_write(rt2x00dev, 69, 0x1a);
  847. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  848. rt2800_bbp_write(rt2x00dev, 73, 0x16);
  849. } else {
  850. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  851. rt2800_bbp_write(rt2x00dev, 70, 0x08);
  852. rt2800_bbp_write(rt2x00dev, 73, 0x11);
  853. }
  854. }
  855. msleep(1);
  856. }
  857. static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
  858. const int txpower)
  859. {
  860. u32 reg;
  861. u32 value = TXPOWER_G_TO_DEV(txpower);
  862. u8 r1;
  863. rt2800_bbp_read(rt2x00dev, 1, &r1);
  864. rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
  865. rt2800_bbp_write(rt2x00dev, 1, r1);
  866. rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
  867. rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
  868. rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
  869. rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
  870. rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
  871. rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
  872. rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
  873. rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
  874. rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
  875. rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
  876. rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
  877. rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
  878. rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
  879. rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
  880. rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
  881. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
  882. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
  883. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
  884. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
  885. rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
  886. rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
  887. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
  888. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
  889. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
  890. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
  891. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
  892. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
  893. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
  894. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
  895. rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
  896. rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
  897. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
  898. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
  899. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
  900. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
  901. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
  902. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
  903. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
  904. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
  905. rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
  906. rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
  907. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
  908. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
  909. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
  910. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
  911. rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
  912. }
  913. static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  914. struct rt2x00lib_conf *libconf)
  915. {
  916. u32 reg;
  917. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  918. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
  919. libconf->conf->short_frame_max_tx_count);
  920. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
  921. libconf->conf->long_frame_max_tx_count);
  922. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  923. }
  924. static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
  925. struct rt2x00lib_conf *libconf)
  926. {
  927. enum dev_state state =
  928. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  929. STATE_SLEEP : STATE_AWAKE;
  930. u32 reg;
  931. if (state == STATE_SLEEP) {
  932. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
  933. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  934. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
  935. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
  936. libconf->conf->listen_interval - 1);
  937. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
  938. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  939. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  940. } else {
  941. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  942. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
  943. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
  944. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
  945. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  946. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  947. }
  948. }
  949. void rt2800_config(struct rt2x00_dev *rt2x00dev,
  950. struct rt2x00lib_conf *libconf,
  951. const unsigned int flags)
  952. {
  953. /* Always recalculate LNA gain before changing configuration */
  954. rt2800_config_lna_gain(rt2x00dev, libconf);
  955. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  956. rt2800_config_channel(rt2x00dev, libconf->conf,
  957. &libconf->rf, &libconf->channel);
  958. if (flags & IEEE80211_CONF_CHANGE_POWER)
  959. rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
  960. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  961. rt2800_config_retry_limit(rt2x00dev, libconf);
  962. if (flags & IEEE80211_CONF_CHANGE_PS)
  963. rt2800_config_ps(rt2x00dev, libconf);
  964. }
  965. EXPORT_SYMBOL_GPL(rt2800_config);
  966. /*
  967. * Link tuning
  968. */
  969. void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  970. {
  971. u32 reg;
  972. /*
  973. * Update FCS error count from register.
  974. */
  975. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  976. qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
  977. }
  978. EXPORT_SYMBOL_GPL(rt2800_link_stats);
  979. static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
  980. {
  981. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
  982. if (rt2x00_rt(rt2x00dev, RT3070) ||
  983. rt2x00_rt(rt2x00dev, RT3071) ||
  984. rt2x00_rt(rt2x00dev, RT3090) ||
  985. rt2x00_rt(rt2x00dev, RT3390))
  986. return 0x1c + (2 * rt2x00dev->lna_gain);
  987. else
  988. return 0x2e + rt2x00dev->lna_gain;
  989. }
  990. if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
  991. return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
  992. else
  993. return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
  994. }
  995. static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
  996. struct link_qual *qual, u8 vgc_level)
  997. {
  998. if (qual->vgc_level != vgc_level) {
  999. rt2800_bbp_write(rt2x00dev, 66, vgc_level);
  1000. qual->vgc_level = vgc_level;
  1001. qual->vgc_level_reg = vgc_level;
  1002. }
  1003. }
  1004. void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  1005. {
  1006. rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
  1007. }
  1008. EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
  1009. void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
  1010. const u32 count)
  1011. {
  1012. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
  1013. return;
  1014. /*
  1015. * When RSSI is better then -80 increase VGC level with 0x10
  1016. */
  1017. rt2800_set_vgc(rt2x00dev, qual,
  1018. rt2800_get_default_vgc(rt2x00dev) +
  1019. ((qual->rssi > -80) * 0x10));
  1020. }
  1021. EXPORT_SYMBOL_GPL(rt2800_link_tuner);
  1022. /*
  1023. * Initialization functions.
  1024. */
  1025. int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
  1026. {
  1027. u32 reg;
  1028. u16 eeprom;
  1029. unsigned int i;
  1030. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  1031. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  1032. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  1033. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  1034. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  1035. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
  1036. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  1037. if (rt2x00_is_usb(rt2x00dev)) {
  1038. /*
  1039. * Wait until BBP and RF are ready.
  1040. */
  1041. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1042. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  1043. if (reg && reg != ~0)
  1044. break;
  1045. msleep(1);
  1046. }
  1047. if (i == REGISTER_BUSY_COUNT) {
  1048. ERROR(rt2x00dev, "Unstable hardware.\n");
  1049. return -EBUSY;
  1050. }
  1051. rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
  1052. rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
  1053. reg & ~0x00002000);
  1054. } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
  1055. /*
  1056. * Reset DMA indexes
  1057. */
  1058. rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
  1059. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
  1060. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
  1061. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
  1062. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
  1063. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
  1064. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
  1065. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
  1066. rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
  1067. rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
  1068. rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
  1069. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  1070. }
  1071. rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  1072. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
  1073. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
  1074. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  1075. if (rt2x00_is_usb(rt2x00dev)) {
  1076. rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
  1077. #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  1078. rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
  1079. USB_MODE_RESET, REGISTER_TIMEOUT);
  1080. #endif
  1081. }
  1082. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  1083. rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
  1084. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
  1085. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
  1086. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
  1087. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
  1088. rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
  1089. rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
  1090. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
  1091. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
  1092. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
  1093. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
  1094. rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
  1095. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
  1096. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  1097. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  1098. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  1099. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
  1100. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
  1101. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
  1102. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
  1103. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  1104. rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
  1105. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  1106. rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
  1107. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  1108. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
  1109. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
  1110. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  1111. if (rt2x00_rt(rt2x00dev, RT3071) ||
  1112. rt2x00_rt(rt2x00dev, RT3090) ||
  1113. rt2x00_rt(rt2x00dev, RT3390)) {
  1114. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  1115. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  1116. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1117. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  1118. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
  1119. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1120. if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
  1121. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  1122. 0x0000002c);
  1123. else
  1124. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  1125. 0x0000000f);
  1126. } else {
  1127. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1128. }
  1129. rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
  1130. } else if (rt2x00_rt(rt2x00dev, RT3070)) {
  1131. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  1132. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
  1133. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  1134. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
  1135. } else {
  1136. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1137. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1138. }
  1139. } else {
  1140. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
  1141. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1142. }
  1143. rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
  1144. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
  1145. rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
  1146. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
  1147. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
  1148. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
  1149. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
  1150. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
  1151. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
  1152. rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
  1153. rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
  1154. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
  1155. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
  1156. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
  1157. rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
  1158. rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
  1159. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
  1160. if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
  1161. rt2x00_rt(rt2x00dev, RT2883) ||
  1162. rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
  1163. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
  1164. else
  1165. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
  1166. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
  1167. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
  1168. rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
  1169. rt2800_register_read(rt2x00dev, LED_CFG, &reg);
  1170. rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
  1171. rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
  1172. rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
  1173. rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
  1174. rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
  1175. rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
  1176. rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
  1177. rt2800_register_write(rt2x00dev, LED_CFG, reg);
  1178. rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
  1179. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  1180. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
  1181. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
  1182. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
  1183. rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
  1184. rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
  1185. rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
  1186. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  1187. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  1188. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
  1189. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
  1190. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
  1191. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
  1192. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
  1193. rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
  1194. rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
  1195. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  1196. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  1197. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
  1198. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
  1199. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
  1200. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1201. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1202. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1203. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1204. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1205. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1206. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
  1207. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  1208. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  1209. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
  1210. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
  1211. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
  1212. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1213. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1214. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1215. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1216. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1217. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1218. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
  1219. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  1220. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  1221. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
  1222. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
  1223. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
  1224. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1225. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1226. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1227. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1228. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1229. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1230. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
  1231. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  1232. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  1233. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
  1234. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
  1235. !rt2x00_is_usb(rt2x00dev));
  1236. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
  1237. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1238. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1239. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1240. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1241. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1242. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1243. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
  1244. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  1245. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  1246. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
  1247. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
  1248. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
  1249. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1250. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1251. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1252. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1253. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1254. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1255. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
  1256. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  1257. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  1258. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
  1259. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
  1260. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
  1261. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1262. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1263. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1264. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1265. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1266. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1267. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
  1268. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  1269. if (rt2x00_is_usb(rt2x00dev)) {
  1270. rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
  1271. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  1272. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  1273. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  1274. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  1275. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  1276. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
  1277. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
  1278. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
  1279. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
  1280. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
  1281. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  1282. }
  1283. rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
  1284. rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
  1285. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  1286. rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
  1287. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
  1288. IEEE80211_MAX_RTS_THRESHOLD);
  1289. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
  1290. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  1291. rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
  1292. /*
  1293. * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
  1294. * time should be set to 16. However, the original Ralink driver uses
  1295. * 16 for both and indeed using a value of 10 for CCK SIFS results in
  1296. * connection problems with 11g + CTS protection. Hence, use the same
  1297. * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
  1298. */
  1299. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  1300. rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
  1301. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
  1302. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
  1303. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
  1304. rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
  1305. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  1306. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  1307. /*
  1308. * ASIC will keep garbage value after boot, clear encryption keys.
  1309. */
  1310. for (i = 0; i < 4; i++)
  1311. rt2800_register_write(rt2x00dev,
  1312. SHARED_KEY_MODE_ENTRY(i), 0);
  1313. for (i = 0; i < 256; i++) {
  1314. u32 wcid[2] = { 0xffffffff, 0x00ffffff };
  1315. rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
  1316. wcid, sizeof(wcid));
  1317. rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
  1318. rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
  1319. }
  1320. /*
  1321. * Clear all beacons
  1322. * For the Beacon base registers we only need to clear
  1323. * the first byte since that byte contains the VALID and OWNER
  1324. * bits which (when set to 0) will invalidate the entire beacon.
  1325. */
  1326. rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  1327. rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  1328. rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  1329. rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  1330. rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
  1331. rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
  1332. rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
  1333. rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
  1334. if (rt2x00_is_usb(rt2x00dev)) {
  1335. rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
  1336. rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
  1337. rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
  1338. }
  1339. rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
  1340. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
  1341. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
  1342. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
  1343. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
  1344. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
  1345. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
  1346. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
  1347. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
  1348. rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
  1349. rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
  1350. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
  1351. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
  1352. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
  1353. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
  1354. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
  1355. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
  1356. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
  1357. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
  1358. rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
  1359. rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
  1360. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
  1361. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
  1362. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
  1363. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
  1364. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
  1365. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
  1366. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
  1367. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
  1368. rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
  1369. rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
  1370. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
  1371. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
  1372. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
  1373. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
  1374. rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
  1375. /*
  1376. * We must clear the error counters.
  1377. * These registers are cleared on read,
  1378. * so we may pass a useless variable to store the value.
  1379. */
  1380. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  1381. rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
  1382. rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
  1383. rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
  1384. rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
  1385. rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
  1386. return 0;
  1387. }
  1388. EXPORT_SYMBOL_GPL(rt2800_init_registers);
  1389. static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
  1390. {
  1391. unsigned int i;
  1392. u32 reg;
  1393. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1394. rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
  1395. if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
  1396. return 0;
  1397. udelay(REGISTER_BUSY_DELAY);
  1398. }
  1399. ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
  1400. return -EACCES;
  1401. }
  1402. static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  1403. {
  1404. unsigned int i;
  1405. u8 value;
  1406. /*
  1407. * BBP was enabled after firmware was loaded,
  1408. * but we need to reactivate it now.
  1409. */
  1410. rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  1411. rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  1412. msleep(1);
  1413. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1414. rt2800_bbp_read(rt2x00dev, 0, &value);
  1415. if ((value != 0xff) && (value != 0x00))
  1416. return 0;
  1417. udelay(REGISTER_BUSY_DELAY);
  1418. }
  1419. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1420. return -EACCES;
  1421. }
  1422. int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
  1423. {
  1424. unsigned int i;
  1425. u16 eeprom;
  1426. u8 reg_id;
  1427. u8 value;
  1428. if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
  1429. rt2800_wait_bbp_ready(rt2x00dev)))
  1430. return -EACCES;
  1431. if (rt2800_is_305x_soc(rt2x00dev))
  1432. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  1433. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  1434. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  1435. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
  1436. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  1437. rt2800_bbp_write(rt2x00dev, 73, 0x12);
  1438. } else {
  1439. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  1440. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  1441. }
  1442. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  1443. if (rt2x00_rt(rt2x00dev, RT3070) ||
  1444. rt2x00_rt(rt2x00dev, RT3071) ||
  1445. rt2x00_rt(rt2x00dev, RT3090) ||
  1446. rt2x00_rt(rt2x00dev, RT3390)) {
  1447. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  1448. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  1449. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  1450. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  1451. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  1452. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  1453. } else {
  1454. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  1455. }
  1456. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  1457. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  1458. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
  1459. rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
  1460. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  1461. else
  1462. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  1463. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  1464. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  1465. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  1466. if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
  1467. rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
  1468. rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
  1469. rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
  1470. rt2800_is_305x_soc(rt2x00dev))
  1471. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  1472. else
  1473. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  1474. if (rt2800_is_305x_soc(rt2x00dev))
  1475. rt2800_bbp_write(rt2x00dev, 105, 0x01);
  1476. else
  1477. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  1478. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  1479. if (rt2x00_rt(rt2x00dev, RT3071) ||
  1480. rt2x00_rt(rt2x00dev, RT3090) ||
  1481. rt2x00_rt(rt2x00dev, RT3390)) {
  1482. rt2800_bbp_read(rt2x00dev, 138, &value);
  1483. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1484. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
  1485. value |= 0x20;
  1486. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
  1487. value &= ~0x02;
  1488. rt2800_bbp_write(rt2x00dev, 138, value);
  1489. }
  1490. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1491. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1492. if (eeprom != 0xffff && eeprom != 0x0000) {
  1493. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1494. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1495. rt2800_bbp_write(rt2x00dev, reg_id, value);
  1496. }
  1497. }
  1498. return 0;
  1499. }
  1500. EXPORT_SYMBOL_GPL(rt2800_init_bbp);
  1501. static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
  1502. bool bw40, u8 rfcsr24, u8 filter_target)
  1503. {
  1504. unsigned int i;
  1505. u8 bbp;
  1506. u8 rfcsr;
  1507. u8 passband;
  1508. u8 stopband;
  1509. u8 overtuned = 0;
  1510. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1511. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  1512. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
  1513. rt2800_bbp_write(rt2x00dev, 4, bbp);
  1514. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  1515. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
  1516. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  1517. /*
  1518. * Set power & frequency of passband test tone
  1519. */
  1520. rt2800_bbp_write(rt2x00dev, 24, 0);
  1521. for (i = 0; i < 100; i++) {
  1522. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  1523. msleep(1);
  1524. rt2800_bbp_read(rt2x00dev, 55, &passband);
  1525. if (passband)
  1526. break;
  1527. }
  1528. /*
  1529. * Set power & frequency of stopband test tone
  1530. */
  1531. rt2800_bbp_write(rt2x00dev, 24, 0x06);
  1532. for (i = 0; i < 100; i++) {
  1533. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  1534. msleep(1);
  1535. rt2800_bbp_read(rt2x00dev, 55, &stopband);
  1536. if ((passband - stopband) <= filter_target) {
  1537. rfcsr24++;
  1538. overtuned += ((passband - stopband) == filter_target);
  1539. } else
  1540. break;
  1541. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1542. }
  1543. rfcsr24 -= !!overtuned;
  1544. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1545. return rfcsr24;
  1546. }
  1547. int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
  1548. {
  1549. u8 rfcsr;
  1550. u8 bbp;
  1551. u32 reg;
  1552. u16 eeprom;
  1553. if (!rt2x00_rt(rt2x00dev, RT3070) &&
  1554. !rt2x00_rt(rt2x00dev, RT3071) &&
  1555. !rt2x00_rt(rt2x00dev, RT3090) &&
  1556. !rt2x00_rt(rt2x00dev, RT3390) &&
  1557. !rt2800_is_305x_soc(rt2x00dev))
  1558. return 0;
  1559. /*
  1560. * Init RF calibration.
  1561. */
  1562. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  1563. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
  1564. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1565. msleep(1);
  1566. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
  1567. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1568. if (rt2x00_rt(rt2x00dev, RT3070) ||
  1569. rt2x00_rt(rt2x00dev, RT3071) ||
  1570. rt2x00_rt(rt2x00dev, RT3090)) {
  1571. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1572. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  1573. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  1574. rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
  1575. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  1576. rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
  1577. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1578. rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
  1579. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1580. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  1581. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  1582. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  1583. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  1584. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  1585. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  1586. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  1587. rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
  1588. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1589. rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
  1590. } else if (rt2x00_rt(rt2x00dev, RT3390)) {
  1591. rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
  1592. rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
  1593. rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
  1594. rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
  1595. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1596. rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
  1597. rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
  1598. rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
  1599. rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
  1600. rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
  1601. rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
  1602. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1603. rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
  1604. rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
  1605. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1606. rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
  1607. rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
  1608. rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
  1609. rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
  1610. rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
  1611. rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
  1612. rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
  1613. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  1614. rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
  1615. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  1616. rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
  1617. rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
  1618. rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  1619. rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
  1620. rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
  1621. rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
  1622. rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
  1623. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  1624. rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
  1625. rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
  1626. rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
  1627. rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
  1628. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1629. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  1630. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  1631. rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
  1632. rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
  1633. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  1634. rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
  1635. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1636. rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
  1637. rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
  1638. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1639. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  1640. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  1641. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  1642. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  1643. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  1644. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  1645. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  1646. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  1647. rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
  1648. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  1649. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1650. rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
  1651. rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
  1652. rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
  1653. rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
  1654. rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
  1655. rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
  1656. return 0;
  1657. }
  1658. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
  1659. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  1660. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  1661. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  1662. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  1663. } else if (rt2x00_rt(rt2x00dev, RT3071) ||
  1664. rt2x00_rt(rt2x00dev, RT3090)) {
  1665. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  1666. rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
  1667. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  1668. rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
  1669. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  1670. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  1671. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1672. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
  1673. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1674. if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
  1675. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  1676. else
  1677. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
  1678. }
  1679. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  1680. } else if (rt2x00_rt(rt2x00dev, RT3390)) {
  1681. rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
  1682. rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
  1683. rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
  1684. }
  1685. /*
  1686. * Set RX Filter calibration for 20MHz and 40MHz
  1687. */
  1688. if (rt2x00_rt(rt2x00dev, RT3070)) {
  1689. rt2x00dev->calibration[0] =
  1690. rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
  1691. rt2x00dev->calibration[1] =
  1692. rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
  1693. } else if (rt2x00_rt(rt2x00dev, RT3071) ||
  1694. rt2x00_rt(rt2x00dev, RT3090) ||
  1695. rt2x00_rt(rt2x00dev, RT3390)) {
  1696. rt2x00dev->calibration[0] =
  1697. rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
  1698. rt2x00dev->calibration[1] =
  1699. rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
  1700. }
  1701. /*
  1702. * Set back to initial state
  1703. */
  1704. rt2800_bbp_write(rt2x00dev, 24, 0);
  1705. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  1706. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
  1707. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  1708. /*
  1709. * set BBP back to BW20
  1710. */
  1711. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  1712. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
  1713. rt2800_bbp_write(rt2x00dev, 4, bbp);
  1714. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
  1715. rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1716. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  1717. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
  1718. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  1719. rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
  1720. rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
  1721. rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
  1722. rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
  1723. rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
  1724. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1725. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  1726. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
  1727. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1728. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  1729. rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
  1730. }
  1731. rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
  1732. if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
  1733. rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
  1734. rt2x00_get_field16(eeprom,
  1735. EEPROM_TXMIXER_GAIN_BG_VAL));
  1736. rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
  1737. if (rt2x00_rt(rt2x00dev, RT3090)) {
  1738. rt2800_bbp_read(rt2x00dev, 138, &bbp);
  1739. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1740. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
  1741. rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
  1742. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
  1743. rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
  1744. rt2800_bbp_write(rt2x00dev, 138, bbp);
  1745. }
  1746. if (rt2x00_rt(rt2x00dev, RT3071) ||
  1747. rt2x00_rt(rt2x00dev, RT3090) ||
  1748. rt2x00_rt(rt2x00dev, RT3390)) {
  1749. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  1750. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  1751. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  1752. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  1753. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  1754. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  1755. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  1756. rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
  1757. rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
  1758. rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
  1759. rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
  1760. rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
  1761. rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
  1762. rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
  1763. rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
  1764. rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  1765. }
  1766. if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
  1767. rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
  1768. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
  1769. rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
  1770. rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
  1771. else
  1772. rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
  1773. rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
  1774. rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
  1775. rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
  1776. rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
  1777. }
  1778. return 0;
  1779. }
  1780. EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
  1781. int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
  1782. {
  1783. u32 reg;
  1784. rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
  1785. return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
  1786. }
  1787. EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
  1788. static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
  1789. {
  1790. u32 reg;
  1791. mutex_lock(&rt2x00dev->csr_mutex);
  1792. rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
  1793. rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
  1794. rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
  1795. rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
  1796. rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
  1797. /* Wait until the EEPROM has been loaded */
  1798. rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
  1799. /* Apparently the data is read from end to start */
  1800. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
  1801. (u32 *)&rt2x00dev->eeprom[i]);
  1802. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
  1803. (u32 *)&rt2x00dev->eeprom[i + 2]);
  1804. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
  1805. (u32 *)&rt2x00dev->eeprom[i + 4]);
  1806. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
  1807. (u32 *)&rt2x00dev->eeprom[i + 6]);
  1808. mutex_unlock(&rt2x00dev->csr_mutex);
  1809. }
  1810. void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  1811. {
  1812. unsigned int i;
  1813. for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
  1814. rt2800_efuse_read(rt2x00dev, i);
  1815. }
  1816. EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
  1817. int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1818. {
  1819. u16 word;
  1820. u8 *mac;
  1821. u8 default_lna_gain;
  1822. /*
  1823. * Start validation of the data that has been read.
  1824. */
  1825. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1826. if (!is_valid_ether_addr(mac)) {
  1827. random_ether_addr(mac);
  1828. EEPROM(rt2x00dev, "MAC: %pM\n", mac);
  1829. }
  1830. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1831. if (word == 0xffff) {
  1832. rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
  1833. rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
  1834. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
  1835. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1836. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1837. } else if (rt2x00_rt(rt2x00dev, RT2860) ||
  1838. rt2x00_rt(rt2x00dev, RT2870) ||
  1839. rt2x00_rt(rt2x00dev, RT2872)) {
  1840. /*
  1841. * There is a max of 2 RX streams for RT28x0 series
  1842. */
  1843. if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
  1844. rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
  1845. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1846. }
  1847. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1848. if (word == 0xffff) {
  1849. rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
  1850. rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
  1851. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1852. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1853. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1854. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
  1855. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
  1856. rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
  1857. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
  1858. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
  1859. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1860. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1861. }
  1862. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1863. if ((word & 0x00ff) == 0x00ff) {
  1864. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1865. rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
  1866. LED_MODE_TXRX_ACTIVITY);
  1867. rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
  1868. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1869. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
  1870. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
  1871. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
  1872. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1873. }
  1874. /*
  1875. * During the LNA validation we are going to use
  1876. * lna0 as correct value. Note that EEPROM_LNA
  1877. * is never validated.
  1878. */
  1879. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
  1880. default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
  1881. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
  1882. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
  1883. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
  1884. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
  1885. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
  1886. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
  1887. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
  1888. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
  1889. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
  1890. if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
  1891. rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
  1892. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
  1893. default_lna_gain);
  1894. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
  1895. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
  1896. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
  1897. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
  1898. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
  1899. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
  1900. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
  1901. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
  1902. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
  1903. rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
  1904. if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
  1905. rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
  1906. rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
  1907. default_lna_gain);
  1908. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
  1909. return 0;
  1910. }
  1911. EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
  1912. int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1913. {
  1914. u32 reg;
  1915. u16 value;
  1916. u16 eeprom;
  1917. /*
  1918. * Read EEPROM word for configuration.
  1919. */
  1920. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1921. /*
  1922. * Identify RF chipset.
  1923. */
  1924. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1925. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  1926. rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
  1927. value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
  1928. if (!rt2x00_rt(rt2x00dev, RT2860) &&
  1929. !rt2x00_rt(rt2x00dev, RT2870) &&
  1930. !rt2x00_rt(rt2x00dev, RT2872) &&
  1931. !rt2x00_rt(rt2x00dev, RT2883) &&
  1932. !rt2x00_rt(rt2x00dev, RT3070) &&
  1933. !rt2x00_rt(rt2x00dev, RT3071) &&
  1934. !rt2x00_rt(rt2x00dev, RT3090) &&
  1935. !rt2x00_rt(rt2x00dev, RT3390) &&
  1936. !rt2x00_rt(rt2x00dev, RT3572)) {
  1937. ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
  1938. return -ENODEV;
  1939. }
  1940. if (!rt2x00_rf(rt2x00dev, RF2820) &&
  1941. !rt2x00_rf(rt2x00dev, RF2850) &&
  1942. !rt2x00_rf(rt2x00dev, RF2720) &&
  1943. !rt2x00_rf(rt2x00dev, RF2750) &&
  1944. !rt2x00_rf(rt2x00dev, RF3020) &&
  1945. !rt2x00_rf(rt2x00dev, RF2020) &&
  1946. !rt2x00_rf(rt2x00dev, RF3021) &&
  1947. !rt2x00_rf(rt2x00dev, RF3022) &&
  1948. !rt2x00_rf(rt2x00dev, RF3052)) {
  1949. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1950. return -ENODEV;
  1951. }
  1952. /*
  1953. * Identify default antenna configuration.
  1954. */
  1955. rt2x00dev->default_ant.tx =
  1956. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
  1957. rt2x00dev->default_ant.rx =
  1958. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
  1959. /*
  1960. * Read frequency offset and RF programming sequence.
  1961. */
  1962. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  1963. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  1964. /*
  1965. * Read external LNA informations.
  1966. */
  1967. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1968. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  1969. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  1970. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  1971. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  1972. /*
  1973. * Detect if this device has an hardware controlled radio.
  1974. */
  1975. if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
  1976. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1977. /*
  1978. * Store led settings, for correct led behaviour.
  1979. */
  1980. #ifdef CONFIG_RT2X00_LIB_LEDS
  1981. rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1982. rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
  1983. rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
  1984. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
  1985. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1986. return 0;
  1987. }
  1988. EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
  1989. /*
  1990. * RF value list for rt28xx
  1991. * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
  1992. */
  1993. static const struct rf_channel rf_vals[] = {
  1994. { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
  1995. { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
  1996. { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
  1997. { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
  1998. { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
  1999. { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
  2000. { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
  2001. { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
  2002. { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
  2003. { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
  2004. { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
  2005. { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
  2006. { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
  2007. { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
  2008. /* 802.11 UNI / HyperLan 2 */
  2009. { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
  2010. { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
  2011. { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
  2012. { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
  2013. { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
  2014. { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
  2015. { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
  2016. { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
  2017. { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
  2018. { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
  2019. { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
  2020. { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
  2021. /* 802.11 HyperLan 2 */
  2022. { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
  2023. { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
  2024. { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
  2025. { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
  2026. { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
  2027. { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
  2028. { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
  2029. { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
  2030. { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
  2031. { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
  2032. { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
  2033. { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
  2034. { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
  2035. { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
  2036. { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
  2037. { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
  2038. /* 802.11 UNII */
  2039. { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
  2040. { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
  2041. { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
  2042. { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
  2043. { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
  2044. { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
  2045. { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
  2046. { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
  2047. { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
  2048. { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
  2049. { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
  2050. /* 802.11 Japan */
  2051. { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
  2052. { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
  2053. { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
  2054. { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
  2055. { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
  2056. { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
  2057. { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
  2058. };
  2059. /*
  2060. * RF value list for rt3xxx
  2061. * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
  2062. */
  2063. static const struct rf_channel rf_vals_3x[] = {
  2064. {1, 241, 2, 2 },
  2065. {2, 241, 2, 7 },
  2066. {3, 242, 2, 2 },
  2067. {4, 242, 2, 7 },
  2068. {5, 243, 2, 2 },
  2069. {6, 243, 2, 7 },
  2070. {7, 244, 2, 2 },
  2071. {8, 244, 2, 7 },
  2072. {9, 245, 2, 2 },
  2073. {10, 245, 2, 7 },
  2074. {11, 246, 2, 2 },
  2075. {12, 246, 2, 7 },
  2076. {13, 247, 2, 2 },
  2077. {14, 248, 2, 4 },
  2078. /* 802.11 UNI / HyperLan 2 */
  2079. {36, 0x56, 0, 4},
  2080. {38, 0x56, 0, 6},
  2081. {40, 0x56, 0, 8},
  2082. {44, 0x57, 0, 0},
  2083. {46, 0x57, 0, 2},
  2084. {48, 0x57, 0, 4},
  2085. {52, 0x57, 0, 8},
  2086. {54, 0x57, 0, 10},
  2087. {56, 0x58, 0, 0},
  2088. {60, 0x58, 0, 4},
  2089. {62, 0x58, 0, 6},
  2090. {64, 0x58, 0, 8},
  2091. /* 802.11 HyperLan 2 */
  2092. {100, 0x5b, 0, 8},
  2093. {102, 0x5b, 0, 10},
  2094. {104, 0x5c, 0, 0},
  2095. {108, 0x5c, 0, 4},
  2096. {110, 0x5c, 0, 6},
  2097. {112, 0x5c, 0, 8},
  2098. {116, 0x5d, 0, 0},
  2099. {118, 0x5d, 0, 2},
  2100. {120, 0x5d, 0, 4},
  2101. {124, 0x5d, 0, 8},
  2102. {126, 0x5d, 0, 10},
  2103. {128, 0x5e, 0, 0},
  2104. {132, 0x5e, 0, 4},
  2105. {134, 0x5e, 0, 6},
  2106. {136, 0x5e, 0, 8},
  2107. {140, 0x5f, 0, 0},
  2108. /* 802.11 UNII */
  2109. {149, 0x5f, 0, 9},
  2110. {151, 0x5f, 0, 11},
  2111. {153, 0x60, 0, 1},
  2112. {157, 0x60, 0, 5},
  2113. {159, 0x60, 0, 7},
  2114. {161, 0x60, 0, 9},
  2115. {165, 0x61, 0, 1},
  2116. {167, 0x61, 0, 3},
  2117. {169, 0x61, 0, 5},
  2118. {171, 0x61, 0, 7},
  2119. {173, 0x61, 0, 9},
  2120. };
  2121. int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  2122. {
  2123. struct hw_mode_spec *spec = &rt2x00dev->spec;
  2124. struct channel_info *info;
  2125. char *tx_power1;
  2126. char *tx_power2;
  2127. unsigned int i;
  2128. u16 eeprom;
  2129. /*
  2130. * Disable powersaving as default on PCI devices.
  2131. */
  2132. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  2133. rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2134. /*
  2135. * Initialize all hw fields.
  2136. */
  2137. rt2x00dev->hw->flags =
  2138. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  2139. IEEE80211_HW_SIGNAL_DBM |
  2140. IEEE80211_HW_SUPPORTS_PS |
  2141. IEEE80211_HW_PS_NULLFUNC_STACK;
  2142. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  2143. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  2144. rt2x00_eeprom_addr(rt2x00dev,
  2145. EEPROM_MAC_ADDR_0));
  2146. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  2147. /*
  2148. * Initialize hw_mode information.
  2149. */
  2150. spec->supported_bands = SUPPORT_BAND_2GHZ;
  2151. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  2152. if (rt2x00_rf(rt2x00dev, RF2820) ||
  2153. rt2x00_rf(rt2x00dev, RF2720)) {
  2154. spec->num_channels = 14;
  2155. spec->channels = rf_vals;
  2156. } else if (rt2x00_rf(rt2x00dev, RF2850) ||
  2157. rt2x00_rf(rt2x00dev, RF2750)) {
  2158. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  2159. spec->num_channels = ARRAY_SIZE(rf_vals);
  2160. spec->channels = rf_vals;
  2161. } else if (rt2x00_rf(rt2x00dev, RF3020) ||
  2162. rt2x00_rf(rt2x00dev, RF2020) ||
  2163. rt2x00_rf(rt2x00dev, RF3021) ||
  2164. rt2x00_rf(rt2x00dev, RF3022)) {
  2165. spec->num_channels = 14;
  2166. spec->channels = rf_vals_3x;
  2167. } else if (rt2x00_rf(rt2x00dev, RF3052)) {
  2168. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  2169. spec->num_channels = ARRAY_SIZE(rf_vals_3x);
  2170. spec->channels = rf_vals_3x;
  2171. }
  2172. /*
  2173. * Initialize HT information.
  2174. */
  2175. if (!rt2x00_rf(rt2x00dev, RF2020))
  2176. spec->ht.ht_supported = true;
  2177. else
  2178. spec->ht.ht_supported = false;
  2179. /*
  2180. * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
  2181. * reception problems with HT40 capable 11n APs
  2182. */
  2183. spec->ht.cap =
  2184. IEEE80211_HT_CAP_GRN_FLD |
  2185. IEEE80211_HT_CAP_SGI_20 |
  2186. IEEE80211_HT_CAP_SGI_40 |
  2187. IEEE80211_HT_CAP_TX_STBC |
  2188. IEEE80211_HT_CAP_RX_STBC;
  2189. spec->ht.ampdu_factor = 3;
  2190. spec->ht.ampdu_density = 4;
  2191. spec->ht.mcs.tx_params =
  2192. IEEE80211_HT_MCS_TX_DEFINED |
  2193. IEEE80211_HT_MCS_TX_RX_DIFF |
  2194. ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
  2195. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2196. switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
  2197. case 3:
  2198. spec->ht.mcs.rx_mask[2] = 0xff;
  2199. case 2:
  2200. spec->ht.mcs.rx_mask[1] = 0xff;
  2201. case 1:
  2202. spec->ht.mcs.rx_mask[0] = 0xff;
  2203. spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
  2204. break;
  2205. }
  2206. /*
  2207. * Create channel information array
  2208. */
  2209. info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
  2210. if (!info)
  2211. return -ENOMEM;
  2212. spec->channels_info = info;
  2213. tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
  2214. tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
  2215. for (i = 0; i < 14; i++) {
  2216. info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
  2217. info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
  2218. }
  2219. if (spec->num_channels > 14) {
  2220. tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
  2221. tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
  2222. for (i = 14; i < spec->num_channels; i++) {
  2223. info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
  2224. info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
  2225. }
  2226. }
  2227. return 0;
  2228. }
  2229. EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
  2230. /*
  2231. * IEEE80211 stack callback functions.
  2232. */
  2233. static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
  2234. u32 *iv32, u16 *iv16)
  2235. {
  2236. struct rt2x00_dev *rt2x00dev = hw->priv;
  2237. struct mac_iveiv_entry iveiv_entry;
  2238. u32 offset;
  2239. offset = MAC_IVEIV_ENTRY(hw_key_idx);
  2240. rt2800_register_multiread(rt2x00dev, offset,
  2241. &iveiv_entry, sizeof(iveiv_entry));
  2242. memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
  2243. memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
  2244. }
  2245. static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2246. {
  2247. struct rt2x00_dev *rt2x00dev = hw->priv;
  2248. u32 reg;
  2249. bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
  2250. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  2251. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
  2252. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  2253. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  2254. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
  2255. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  2256. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  2257. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
  2258. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  2259. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  2260. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
  2261. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  2262. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  2263. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
  2264. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  2265. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  2266. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
  2267. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  2268. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  2269. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
  2270. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  2271. return 0;
  2272. }
  2273. static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
  2274. const struct ieee80211_tx_queue_params *params)
  2275. {
  2276. struct rt2x00_dev *rt2x00dev = hw->priv;
  2277. struct data_queue *queue;
  2278. struct rt2x00_field32 field;
  2279. int retval;
  2280. u32 reg;
  2281. u32 offset;
  2282. /*
  2283. * First pass the configuration through rt2x00lib, that will
  2284. * update the queue settings and validate the input. After that
  2285. * we are free to update the registers based on the value
  2286. * in the queue parameter.
  2287. */
  2288. retval = rt2x00mac_conf_tx(hw, queue_idx, params);
  2289. if (retval)
  2290. return retval;
  2291. /*
  2292. * We only need to perform additional register initialization
  2293. * for WMM queues/
  2294. */
  2295. if (queue_idx >= 4)
  2296. return 0;
  2297. queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  2298. /* Update WMM TXOP register */
  2299. offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
  2300. field.bit_offset = (queue_idx & 1) * 16;
  2301. field.bit_mask = 0xffff << field.bit_offset;
  2302. rt2800_register_read(rt2x00dev, offset, &reg);
  2303. rt2x00_set_field32(&reg, field, queue->txop);
  2304. rt2800_register_write(rt2x00dev, offset, reg);
  2305. /* Update WMM registers */
  2306. field.bit_offset = queue_idx * 4;
  2307. field.bit_mask = 0xf << field.bit_offset;
  2308. rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
  2309. rt2x00_set_field32(&reg, field, queue->aifs);
  2310. rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
  2311. rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
  2312. rt2x00_set_field32(&reg, field, queue->cw_min);
  2313. rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
  2314. rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
  2315. rt2x00_set_field32(&reg, field, queue->cw_max);
  2316. rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
  2317. /* Update EDCA registers */
  2318. offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
  2319. rt2800_register_read(rt2x00dev, offset, &reg);
  2320. rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
  2321. rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
  2322. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
  2323. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
  2324. rt2800_register_write(rt2x00dev, offset, reg);
  2325. return 0;
  2326. }
  2327. static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
  2328. {
  2329. struct rt2x00_dev *rt2x00dev = hw->priv;
  2330. u64 tsf;
  2331. u32 reg;
  2332. rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
  2333. tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
  2334. rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
  2335. tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
  2336. return tsf;
  2337. }
  2338. const struct ieee80211_ops rt2800_mac80211_ops = {
  2339. .tx = rt2x00mac_tx,
  2340. .start = rt2x00mac_start,
  2341. .stop = rt2x00mac_stop,
  2342. .add_interface = rt2x00mac_add_interface,
  2343. .remove_interface = rt2x00mac_remove_interface,
  2344. .config = rt2x00mac_config,
  2345. .configure_filter = rt2x00mac_configure_filter,
  2346. .set_tim = rt2x00mac_set_tim,
  2347. .set_key = rt2x00mac_set_key,
  2348. .get_stats = rt2x00mac_get_stats,
  2349. .get_tkip_seq = rt2800_get_tkip_seq,
  2350. .set_rts_threshold = rt2800_set_rts_threshold,
  2351. .bss_info_changed = rt2x00mac_bss_info_changed,
  2352. .conf_tx = rt2800_conf_tx,
  2353. .get_tsf = rt2800_get_tsf,
  2354. .rfkill_poll = rt2x00mac_rfkill_poll,
  2355. };
  2356. EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);