r8152.c 50 KB

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  1. /*
  2. * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/signal.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/usb.h>
  18. #include <linux/crc32.h>
  19. #include <linux/if_vlan.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/list.h>
  22. #include <linux/ip.h>
  23. #include <linux/ipv6.h>
  24. /* Version Information */
  25. #define DRIVER_VERSION "v1.01.0 (2013/08/12)"
  26. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  27. #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  28. #define MODULENAME "r8152"
  29. #define R8152_PHY_ID 32
  30. #define PLA_IDR 0xc000
  31. #define PLA_RCR 0xc010
  32. #define PLA_RMS 0xc016
  33. #define PLA_RXFIFO_CTRL0 0xc0a0
  34. #define PLA_RXFIFO_CTRL1 0xc0a4
  35. #define PLA_RXFIFO_CTRL2 0xc0a8
  36. #define PLA_FMC 0xc0b4
  37. #define PLA_CFG_WOL 0xc0b6
  38. #define PLA_MAR 0xcd00
  39. #define PAL_BDC_CR 0xd1a0
  40. #define PLA_LEDSEL 0xdd90
  41. #define PLA_LED_FEATURE 0xdd92
  42. #define PLA_PHYAR 0xde00
  43. #define PLA_GPHY_INTR_IMR 0xe022
  44. #define PLA_EEE_CR 0xe040
  45. #define PLA_EEEP_CR 0xe080
  46. #define PLA_MAC_PWR_CTRL 0xe0c0
  47. #define PLA_TCR0 0xe610
  48. #define PLA_TCR1 0xe612
  49. #define PLA_TXFIFO_CTRL 0xe618
  50. #define PLA_RSTTELLY 0xe800
  51. #define PLA_CR 0xe813
  52. #define PLA_CRWECR 0xe81c
  53. #define PLA_CONFIG5 0xe822
  54. #define PLA_PHY_PWR 0xe84c
  55. #define PLA_OOB_CTRL 0xe84f
  56. #define PLA_CPCR 0xe854
  57. #define PLA_MISC_0 0xe858
  58. #define PLA_MISC_1 0xe85a
  59. #define PLA_OCP_GPHY_BASE 0xe86c
  60. #define PLA_TELLYCNT 0xe890
  61. #define PLA_SFF_STS_7 0xe8de
  62. #define PLA_PHYSTATUS 0xe908
  63. #define PLA_BP_BA 0xfc26
  64. #define PLA_BP_0 0xfc28
  65. #define PLA_BP_1 0xfc2a
  66. #define PLA_BP_2 0xfc2c
  67. #define PLA_BP_3 0xfc2e
  68. #define PLA_BP_4 0xfc30
  69. #define PLA_BP_5 0xfc32
  70. #define PLA_BP_6 0xfc34
  71. #define PLA_BP_7 0xfc36
  72. #define USB_DEV_STAT 0xb808
  73. #define USB_USB_CTRL 0xd406
  74. #define USB_PHY_CTRL 0xd408
  75. #define USB_TX_AGG 0xd40a
  76. #define USB_RX_BUF_TH 0xd40c
  77. #define USB_USB_TIMER 0xd428
  78. #define USB_PM_CTRL_STATUS 0xd432
  79. #define USB_TX_DMA 0xd434
  80. #define USB_UPS_CTRL 0xd800
  81. #define USB_BP_BA 0xfc26
  82. #define USB_BP_0 0xfc28
  83. #define USB_BP_1 0xfc2a
  84. #define USB_BP_2 0xfc2c
  85. #define USB_BP_3 0xfc2e
  86. #define USB_BP_4 0xfc30
  87. #define USB_BP_5 0xfc32
  88. #define USB_BP_6 0xfc34
  89. #define USB_BP_7 0xfc36
  90. /* OCP Registers */
  91. #define OCP_ALDPS_CONFIG 0x2010
  92. #define OCP_EEE_CONFIG1 0x2080
  93. #define OCP_EEE_CONFIG2 0x2092
  94. #define OCP_EEE_CONFIG3 0x2094
  95. #define OCP_EEE_AR 0xa41a
  96. #define OCP_EEE_DATA 0xa41c
  97. /* PLA_RCR */
  98. #define RCR_AAP 0x00000001
  99. #define RCR_APM 0x00000002
  100. #define RCR_AM 0x00000004
  101. #define RCR_AB 0x00000008
  102. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  103. /* PLA_RXFIFO_CTRL0 */
  104. #define RXFIFO_THR1_NORMAL 0x00080002
  105. #define RXFIFO_THR1_OOB 0x01800003
  106. /* PLA_RXFIFO_CTRL1 */
  107. #define RXFIFO_THR2_FULL 0x00000060
  108. #define RXFIFO_THR2_HIGH 0x00000038
  109. #define RXFIFO_THR2_OOB 0x0000004a
  110. /* PLA_RXFIFO_CTRL2 */
  111. #define RXFIFO_THR3_FULL 0x00000078
  112. #define RXFIFO_THR3_HIGH 0x00000048
  113. #define RXFIFO_THR3_OOB 0x0000005a
  114. /* PLA_TXFIFO_CTRL */
  115. #define TXFIFO_THR_NORMAL 0x00400008
  116. /* PLA_FMC */
  117. #define FMC_FCR_MCU_EN 0x0001
  118. /* PLA_EEEP_CR */
  119. #define EEEP_CR_EEEP_TX 0x0002
  120. /* PLA_TCR0 */
  121. #define TCR0_TX_EMPTY 0x0800
  122. #define TCR0_AUTO_FIFO 0x0080
  123. /* PLA_TCR1 */
  124. #define VERSION_MASK 0x7cf0
  125. /* PLA_CR */
  126. #define CR_RST 0x10
  127. #define CR_RE 0x08
  128. #define CR_TE 0x04
  129. /* PLA_CRWECR */
  130. #define CRWECR_NORAML 0x00
  131. #define CRWECR_CONFIG 0xc0
  132. /* PLA_OOB_CTRL */
  133. #define NOW_IS_OOB 0x80
  134. #define TXFIFO_EMPTY 0x20
  135. #define RXFIFO_EMPTY 0x10
  136. #define LINK_LIST_READY 0x02
  137. #define DIS_MCU_CLROOB 0x01
  138. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  139. /* PLA_MISC_1 */
  140. #define RXDY_GATED_EN 0x0008
  141. /* PLA_SFF_STS_7 */
  142. #define RE_INIT_LL 0x8000
  143. #define MCU_BORW_EN 0x4000
  144. /* PLA_CPCR */
  145. #define CPCR_RX_VLAN 0x0040
  146. /* PLA_CFG_WOL */
  147. #define MAGIC_EN 0x0001
  148. /* PAL_BDC_CR */
  149. #define ALDPS_PROXY_MODE 0x0001
  150. /* PLA_CONFIG5 */
  151. #define LAN_WAKE_EN 0x0002
  152. /* PLA_LED_FEATURE */
  153. #define LED_MODE_MASK 0x0700
  154. /* PLA_PHY_PWR */
  155. #define TX_10M_IDLE_EN 0x0080
  156. #define PFM_PWM_SWITCH 0x0040
  157. /* PLA_MAC_PWR_CTRL */
  158. #define D3_CLK_GATED_EN 0x00004000
  159. #define MCU_CLK_RATIO 0x07010f07
  160. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  161. /* PLA_GPHY_INTR_IMR */
  162. #define GPHY_STS_MSK 0x0001
  163. #define SPEED_DOWN_MSK 0x0002
  164. #define SPDWN_RXDV_MSK 0x0004
  165. #define SPDWN_LINKCHG_MSK 0x0008
  166. /* PLA_PHYAR */
  167. #define PHYAR_FLAG 0x80000000
  168. /* PLA_EEE_CR */
  169. #define EEE_RX_EN 0x0001
  170. #define EEE_TX_EN 0x0002
  171. /* USB_DEV_STAT */
  172. #define STAT_SPEED_MASK 0x0006
  173. #define STAT_SPEED_HIGH 0x0000
  174. #define STAT_SPEED_FULL 0x0001
  175. /* USB_TX_AGG */
  176. #define TX_AGG_MAX_THRESHOLD 0x03
  177. /* USB_RX_BUF_TH */
  178. #define RX_BUF_THR 0x7a120180
  179. /* USB_TX_DMA */
  180. #define TEST_MODE_DISABLE 0x00000001
  181. #define TX_SIZE_ADJUST1 0x00000100
  182. /* USB_UPS_CTRL */
  183. #define POWER_CUT 0x0100
  184. /* USB_PM_CTRL_STATUS */
  185. #define RWSUME_INDICATE 0x0001
  186. /* USB_USB_CTRL */
  187. #define RX_AGG_DISABLE 0x0010
  188. /* OCP_ALDPS_CONFIG */
  189. #define ENPWRSAVE 0x8000
  190. #define ENPDNPS 0x0200
  191. #define LINKENA 0x0100
  192. #define DIS_SDSAVE 0x0010
  193. /* OCP_EEE_CONFIG1 */
  194. #define RG_TXLPI_MSK_HFDUP 0x8000
  195. #define RG_MATCLR_EN 0x4000
  196. #define EEE_10_CAP 0x2000
  197. #define EEE_NWAY_EN 0x1000
  198. #define TX_QUIET_EN 0x0200
  199. #define RX_QUIET_EN 0x0100
  200. #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
  201. #define RG_RXLPI_MSK_HFDUP 0x0008
  202. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  203. /* OCP_EEE_CONFIG2 */
  204. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  205. #define RG_DACQUIET_EN 0x0400
  206. #define RG_LDVQUIET_EN 0x0200
  207. #define RG_CKRSEL 0x0020
  208. #define RG_EEEPRG_EN 0x0010
  209. /* OCP_EEE_CONFIG3 */
  210. #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
  211. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  212. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  213. /* OCP_EEE_AR */
  214. /* bit[15:14] function */
  215. #define FUN_ADDR 0x0000
  216. #define FUN_DATA 0x4000
  217. /* bit[4:0] device addr */
  218. #define DEVICE_ADDR 0x0007
  219. /* OCP_EEE_DATA */
  220. #define EEE_ADDR 0x003C
  221. #define EEE_DATA 0x0002
  222. enum rtl_register_content {
  223. _100bps = 0x08,
  224. _10bps = 0x04,
  225. LINK_STATUS = 0x02,
  226. FULL_DUP = 0x01,
  227. };
  228. #define RTL8152_MAX_TX 10
  229. #define RTL8152_MAX_RX 10
  230. #define INTBUFSIZE 2
  231. #define INTR_LINK 0x0004
  232. #define RTL8152_REQT_READ 0xc0
  233. #define RTL8152_REQT_WRITE 0x40
  234. #define RTL8152_REQ_GET_REGS 0x05
  235. #define RTL8152_REQ_SET_REGS 0x05
  236. #define BYTE_EN_DWORD 0xff
  237. #define BYTE_EN_WORD 0x33
  238. #define BYTE_EN_BYTE 0x11
  239. #define BYTE_EN_SIX_BYTES 0x3f
  240. #define BYTE_EN_START_MASK 0x0f
  241. #define BYTE_EN_END_MASK 0xf0
  242. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  243. #define RTL8152_TX_TIMEOUT (HZ)
  244. /* rtl8152 flags */
  245. enum rtl8152_flags {
  246. RTL8152_UNPLUG = 0,
  247. RTL8152_SET_RX_MODE,
  248. WORK_ENABLE,
  249. RTL8152_LINK_CHG,
  250. };
  251. /* Define these values to match your device */
  252. #define VENDOR_ID_REALTEK 0x0bda
  253. #define PRODUCT_ID_RTL8152 0x8152
  254. #define MCU_TYPE_PLA 0x0100
  255. #define MCU_TYPE_USB 0x0000
  256. struct rx_desc {
  257. u32 opts1;
  258. #define RX_LEN_MASK 0x7fff
  259. u32 opts2;
  260. u32 opts3;
  261. u32 opts4;
  262. u32 opts5;
  263. u32 opts6;
  264. };
  265. struct tx_desc {
  266. u32 opts1;
  267. #define TX_FS (1 << 31) /* First segment of a packet */
  268. #define TX_LS (1 << 30) /* Final segment of a packet */
  269. #define TX_LEN_MASK 0x3ffff
  270. u32 opts2;
  271. #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
  272. #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
  273. #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
  274. #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
  275. };
  276. struct r8152;
  277. struct rx_agg {
  278. struct list_head list;
  279. struct urb *urb;
  280. struct r8152 *context;
  281. void *buffer;
  282. void *head;
  283. };
  284. struct tx_agg {
  285. struct list_head list;
  286. struct urb *urb;
  287. struct r8152 *context;
  288. void *buffer;
  289. void *head;
  290. u32 skb_num;
  291. u32 skb_len;
  292. };
  293. struct r8152 {
  294. unsigned long flags;
  295. struct usb_device *udev;
  296. struct tasklet_struct tl;
  297. struct usb_interface *intf;
  298. struct net_device *netdev;
  299. struct urb *intr_urb;
  300. struct tx_agg tx_info[RTL8152_MAX_TX];
  301. struct rx_agg rx_info[RTL8152_MAX_RX];
  302. struct list_head rx_done, tx_free;
  303. struct sk_buff_head tx_queue;
  304. spinlock_t rx_lock, tx_lock;
  305. struct delayed_work schedule;
  306. struct mii_if_info mii;
  307. int intr_interval;
  308. u32 msg_enable;
  309. u16 ocp_base;
  310. u8 *intr_buff;
  311. u8 version;
  312. u8 speed;
  313. };
  314. enum rtl_version {
  315. RTL_VER_UNKNOWN = 0,
  316. RTL_VER_01,
  317. RTL_VER_02
  318. };
  319. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  320. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  321. */
  322. static const int multicast_filter_limit = 32;
  323. static unsigned int rx_buf_sz = 16384;
  324. static
  325. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  326. {
  327. int ret;
  328. void *tmp;
  329. tmp = kmalloc(size, GFP_KERNEL);
  330. if (!tmp)
  331. return -ENOMEM;
  332. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  333. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  334. value, index, tmp, size, 500);
  335. memcpy(data, tmp, size);
  336. kfree(tmp);
  337. return ret;
  338. }
  339. static
  340. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  341. {
  342. int ret;
  343. void *tmp;
  344. tmp = kmalloc(size, GFP_KERNEL);
  345. if (!tmp)
  346. return -ENOMEM;
  347. memcpy(tmp, data, size);
  348. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  349. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  350. value, index, tmp, size, 500);
  351. kfree(tmp);
  352. return ret;
  353. }
  354. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  355. void *data, u16 type)
  356. {
  357. u16 limit = 64;
  358. int ret = 0;
  359. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  360. return -ENODEV;
  361. /* both size and indix must be 4 bytes align */
  362. if ((size & 3) || !size || (index & 3) || !data)
  363. return -EPERM;
  364. if ((u32)index + (u32)size > 0xffff)
  365. return -EPERM;
  366. while (size) {
  367. if (size > limit) {
  368. ret = get_registers(tp, index, type, limit, data);
  369. if (ret < 0)
  370. break;
  371. index += limit;
  372. data += limit;
  373. size -= limit;
  374. } else {
  375. ret = get_registers(tp, index, type, size, data);
  376. if (ret < 0)
  377. break;
  378. index += size;
  379. data += size;
  380. size = 0;
  381. break;
  382. }
  383. }
  384. return ret;
  385. }
  386. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  387. u16 size, void *data, u16 type)
  388. {
  389. int ret;
  390. u16 byteen_start, byteen_end, byen;
  391. u16 limit = 512;
  392. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  393. return -ENODEV;
  394. /* both size and indix must be 4 bytes align */
  395. if ((size & 3) || !size || (index & 3) || !data)
  396. return -EPERM;
  397. if ((u32)index + (u32)size > 0xffff)
  398. return -EPERM;
  399. byteen_start = byteen & BYTE_EN_START_MASK;
  400. byteen_end = byteen & BYTE_EN_END_MASK;
  401. byen = byteen_start | (byteen_start << 4);
  402. ret = set_registers(tp, index, type | byen, 4, data);
  403. if (ret < 0)
  404. goto error1;
  405. index += 4;
  406. data += 4;
  407. size -= 4;
  408. if (size) {
  409. size -= 4;
  410. while (size) {
  411. if (size > limit) {
  412. ret = set_registers(tp, index,
  413. type | BYTE_EN_DWORD,
  414. limit, data);
  415. if (ret < 0)
  416. goto error1;
  417. index += limit;
  418. data += limit;
  419. size -= limit;
  420. } else {
  421. ret = set_registers(tp, index,
  422. type | BYTE_EN_DWORD,
  423. size, data);
  424. if (ret < 0)
  425. goto error1;
  426. index += size;
  427. data += size;
  428. size = 0;
  429. break;
  430. }
  431. }
  432. byen = byteen_end | (byteen_end >> 4);
  433. ret = set_registers(tp, index, type | byen, 4, data);
  434. if (ret < 0)
  435. goto error1;
  436. }
  437. error1:
  438. return ret;
  439. }
  440. static inline
  441. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  442. {
  443. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  444. }
  445. static inline
  446. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  447. {
  448. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  449. }
  450. static inline
  451. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  452. {
  453. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  454. }
  455. static inline
  456. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  457. {
  458. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  459. }
  460. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  461. {
  462. __le32 data;
  463. generic_ocp_read(tp, index, sizeof(data), &data, type);
  464. return __le32_to_cpu(data);
  465. }
  466. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  467. {
  468. __le32 tmp = __cpu_to_le32(data);
  469. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  470. }
  471. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  472. {
  473. u32 data;
  474. __le32 tmp;
  475. u8 shift = index & 2;
  476. index &= ~3;
  477. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  478. data = __le32_to_cpu(tmp);
  479. data >>= (shift * 8);
  480. data &= 0xffff;
  481. return (u16)data;
  482. }
  483. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  484. {
  485. u32 mask = 0xffff;
  486. __le32 tmp;
  487. u16 byen = BYTE_EN_WORD;
  488. u8 shift = index & 2;
  489. data &= mask;
  490. if (index & 2) {
  491. byen <<= shift;
  492. mask <<= (shift * 8);
  493. data <<= (shift * 8);
  494. index &= ~3;
  495. }
  496. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  497. data |= __le32_to_cpu(tmp) & ~mask;
  498. tmp = __cpu_to_le32(data);
  499. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  500. }
  501. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  502. {
  503. u32 data;
  504. __le32 tmp;
  505. u8 shift = index & 3;
  506. index &= ~3;
  507. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  508. data = __le32_to_cpu(tmp);
  509. data >>= (shift * 8);
  510. data &= 0xff;
  511. return (u8)data;
  512. }
  513. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  514. {
  515. u32 mask = 0xff;
  516. __le32 tmp;
  517. u16 byen = BYTE_EN_BYTE;
  518. u8 shift = index & 3;
  519. data &= mask;
  520. if (index & 3) {
  521. byen <<= shift;
  522. mask <<= (shift * 8);
  523. data <<= (shift * 8);
  524. index &= ~3;
  525. }
  526. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  527. data |= __le32_to_cpu(tmp) & ~mask;
  528. tmp = __cpu_to_le32(data);
  529. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  530. }
  531. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  532. {
  533. u32 ocp_data;
  534. int i;
  535. ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
  536. (value & 0xffff);
  537. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  538. for (i = 20; i > 0; i--) {
  539. udelay(25);
  540. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  541. if (!(ocp_data & PHYAR_FLAG))
  542. break;
  543. }
  544. udelay(20);
  545. }
  546. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  547. {
  548. u32 ocp_data;
  549. int i;
  550. ocp_data = (reg_addr & 0x1f) << 16;
  551. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  552. for (i = 20; i > 0; i--) {
  553. udelay(25);
  554. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  555. if (ocp_data & PHYAR_FLAG)
  556. break;
  557. }
  558. udelay(20);
  559. if (!(ocp_data & PHYAR_FLAG))
  560. return -EAGAIN;
  561. return (u16)(ocp_data & 0xffff);
  562. }
  563. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  564. {
  565. struct r8152 *tp = netdev_priv(netdev);
  566. if (phy_id != R8152_PHY_ID)
  567. return -EINVAL;
  568. return r8152_mdio_read(tp, reg);
  569. }
  570. static
  571. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  572. {
  573. struct r8152 *tp = netdev_priv(netdev);
  574. if (phy_id != R8152_PHY_ID)
  575. return;
  576. r8152_mdio_write(tp, reg, val);
  577. }
  578. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  579. {
  580. u16 ocp_base, ocp_index;
  581. ocp_base = addr & 0xf000;
  582. if (ocp_base != tp->ocp_base) {
  583. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  584. tp->ocp_base = ocp_base;
  585. }
  586. ocp_index = (addr & 0x0fff) | 0xb000;
  587. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  588. }
  589. static
  590. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  591. static inline void set_ethernet_addr(struct r8152 *tp)
  592. {
  593. struct net_device *dev = tp->netdev;
  594. u8 node_id[8] = {0};
  595. if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
  596. netif_notice(tp, probe, dev, "inet addr fail\n");
  597. else {
  598. memcpy(dev->dev_addr, node_id, dev->addr_len);
  599. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  600. }
  601. }
  602. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  603. {
  604. struct r8152 *tp = netdev_priv(netdev);
  605. struct sockaddr *addr = p;
  606. if (!is_valid_ether_addr(addr->sa_data))
  607. return -EADDRNOTAVAIL;
  608. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  609. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  610. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  611. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  612. return 0;
  613. }
  614. static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
  615. {
  616. return &dev->stats;
  617. }
  618. static void read_bulk_callback(struct urb *urb)
  619. {
  620. struct net_device *netdev;
  621. unsigned long lockflags;
  622. int status = urb->status;
  623. struct rx_agg *agg;
  624. struct r8152 *tp;
  625. int result;
  626. agg = urb->context;
  627. if (!agg)
  628. return;
  629. tp = agg->context;
  630. if (!tp)
  631. return;
  632. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  633. return;
  634. if (!test_bit(WORK_ENABLE, &tp->flags))
  635. return;
  636. netdev = tp->netdev;
  637. if (!netif_carrier_ok(netdev))
  638. return;
  639. switch (status) {
  640. case 0:
  641. if (urb->actual_length < ETH_ZLEN)
  642. break;
  643. spin_lock_irqsave(&tp->rx_lock, lockflags);
  644. list_add_tail(&agg->list, &tp->rx_done);
  645. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  646. tasklet_schedule(&tp->tl);
  647. return;
  648. case -ESHUTDOWN:
  649. set_bit(RTL8152_UNPLUG, &tp->flags);
  650. netif_device_detach(tp->netdev);
  651. return;
  652. case -ENOENT:
  653. return; /* the urb is in unlink state */
  654. case -ETIME:
  655. pr_warn_ratelimited("may be reset is needed?..\n");
  656. break;
  657. default:
  658. pr_warn_ratelimited("Rx status %d\n", status);
  659. break;
  660. }
  661. result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  662. if (result == -ENODEV) {
  663. netif_device_detach(tp->netdev);
  664. } else if (result) {
  665. spin_lock_irqsave(&tp->rx_lock, lockflags);
  666. list_add_tail(&agg->list, &tp->rx_done);
  667. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  668. tasklet_schedule(&tp->tl);
  669. }
  670. }
  671. static void write_bulk_callback(struct urb *urb)
  672. {
  673. struct net_device_stats *stats;
  674. unsigned long lockflags;
  675. struct tx_agg *agg;
  676. struct r8152 *tp;
  677. int status = urb->status;
  678. agg = urb->context;
  679. if (!agg)
  680. return;
  681. tp = agg->context;
  682. if (!tp)
  683. return;
  684. stats = rtl8152_get_stats(tp->netdev);
  685. if (status) {
  686. pr_warn_ratelimited("Tx status %d\n", status);
  687. stats->tx_errors += agg->skb_num;
  688. } else {
  689. stats->tx_packets += agg->skb_num;
  690. stats->tx_bytes += agg->skb_len;
  691. }
  692. spin_lock_irqsave(&tp->tx_lock, lockflags);
  693. list_add_tail(&agg->list, &tp->tx_free);
  694. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  695. if (!netif_carrier_ok(tp->netdev))
  696. return;
  697. if (!test_bit(WORK_ENABLE, &tp->flags))
  698. return;
  699. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  700. return;
  701. if (!skb_queue_empty(&tp->tx_queue))
  702. tasklet_schedule(&tp->tl);
  703. }
  704. static void intr_callback(struct urb *urb)
  705. {
  706. struct r8152 *tp;
  707. __u16 *d;
  708. int status = urb->status;
  709. int res;
  710. tp = urb->context;
  711. if (!tp)
  712. return;
  713. if (!test_bit(WORK_ENABLE, &tp->flags))
  714. return;
  715. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  716. return;
  717. switch (status) {
  718. case 0: /* success */
  719. break;
  720. case -ECONNRESET: /* unlink */
  721. case -ESHUTDOWN:
  722. netif_device_detach(tp->netdev);
  723. case -ENOENT:
  724. return;
  725. case -EOVERFLOW:
  726. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  727. goto resubmit;
  728. /* -EPIPE: should clear the halt */
  729. default:
  730. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  731. goto resubmit;
  732. }
  733. d = urb->transfer_buffer;
  734. if (INTR_LINK & __le16_to_cpu(d[0])) {
  735. if (!(tp->speed & LINK_STATUS)) {
  736. set_bit(RTL8152_LINK_CHG, &tp->flags);
  737. schedule_delayed_work(&tp->schedule, 0);
  738. }
  739. } else {
  740. if (tp->speed & LINK_STATUS) {
  741. set_bit(RTL8152_LINK_CHG, &tp->flags);
  742. schedule_delayed_work(&tp->schedule, 0);
  743. }
  744. }
  745. resubmit:
  746. res = usb_submit_urb(urb, GFP_ATOMIC);
  747. if (res == -ENODEV)
  748. netif_device_detach(tp->netdev);
  749. else if (res)
  750. netif_err(tp, intr, tp->netdev,
  751. "can't resubmit intr, status %d\n", res);
  752. }
  753. static inline void *rx_agg_align(void *data)
  754. {
  755. return (void *)ALIGN((uintptr_t)data, 8);
  756. }
  757. static inline void *tx_agg_align(void *data)
  758. {
  759. return (void *)ALIGN((uintptr_t)data, 4);
  760. }
  761. static void free_all_mem(struct r8152 *tp)
  762. {
  763. int i;
  764. for (i = 0; i < RTL8152_MAX_RX; i++) {
  765. if (tp->rx_info[i].urb) {
  766. usb_free_urb(tp->rx_info[i].urb);
  767. tp->rx_info[i].urb = NULL;
  768. }
  769. if (tp->rx_info[i].buffer) {
  770. kfree(tp->rx_info[i].buffer);
  771. tp->rx_info[i].buffer = NULL;
  772. tp->rx_info[i].head = NULL;
  773. }
  774. }
  775. for (i = 0; i < RTL8152_MAX_TX; i++) {
  776. if (tp->tx_info[i].urb) {
  777. usb_free_urb(tp->tx_info[i].urb);
  778. tp->tx_info[i].urb = NULL;
  779. }
  780. if (tp->tx_info[i].buffer) {
  781. kfree(tp->tx_info[i].buffer);
  782. tp->tx_info[i].buffer = NULL;
  783. tp->tx_info[i].head = NULL;
  784. }
  785. }
  786. if (tp->intr_urb) {
  787. usb_free_urb(tp->intr_urb);
  788. tp->intr_urb = NULL;
  789. }
  790. if (tp->intr_buff) {
  791. kfree(tp->intr_buff);
  792. tp->intr_buff = NULL;
  793. }
  794. }
  795. static int alloc_all_mem(struct r8152 *tp)
  796. {
  797. struct net_device *netdev = tp->netdev;
  798. struct usb_interface *intf = tp->intf;
  799. struct usb_host_interface *alt = intf->cur_altsetting;
  800. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  801. struct urb *urb;
  802. int node, i;
  803. u8 *buf;
  804. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  805. spin_lock_init(&tp->rx_lock);
  806. spin_lock_init(&tp->tx_lock);
  807. INIT_LIST_HEAD(&tp->rx_done);
  808. INIT_LIST_HEAD(&tp->tx_free);
  809. skb_queue_head_init(&tp->tx_queue);
  810. for (i = 0; i < RTL8152_MAX_RX; i++) {
  811. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  812. if (!buf)
  813. goto err1;
  814. if (buf != rx_agg_align(buf)) {
  815. kfree(buf);
  816. buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
  817. if (!buf)
  818. goto err1;
  819. }
  820. urb = usb_alloc_urb(0, GFP_KERNEL);
  821. if (!urb) {
  822. kfree(buf);
  823. goto err1;
  824. }
  825. INIT_LIST_HEAD(&tp->rx_info[i].list);
  826. tp->rx_info[i].context = tp;
  827. tp->rx_info[i].urb = urb;
  828. tp->rx_info[i].buffer = buf;
  829. tp->rx_info[i].head = rx_agg_align(buf);
  830. }
  831. for (i = 0; i < RTL8152_MAX_TX; i++) {
  832. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  833. if (!buf)
  834. goto err1;
  835. if (buf != tx_agg_align(buf)) {
  836. kfree(buf);
  837. buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
  838. if (!buf)
  839. goto err1;
  840. }
  841. urb = usb_alloc_urb(0, GFP_KERNEL);
  842. if (!urb) {
  843. kfree(buf);
  844. goto err1;
  845. }
  846. INIT_LIST_HEAD(&tp->tx_info[i].list);
  847. tp->tx_info[i].context = tp;
  848. tp->tx_info[i].urb = urb;
  849. tp->tx_info[i].buffer = buf;
  850. tp->tx_info[i].head = tx_agg_align(buf);
  851. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  852. }
  853. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  854. if (!tp->intr_urb)
  855. goto err1;
  856. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  857. if (!tp->intr_buff)
  858. goto err1;
  859. tp->intr_interval = (int)ep_intr->desc.bInterval;
  860. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  861. tp->intr_buff, INTBUFSIZE, intr_callback,
  862. tp, tp->intr_interval);
  863. return 0;
  864. err1:
  865. free_all_mem(tp);
  866. return -ENOMEM;
  867. }
  868. static void
  869. r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
  870. {
  871. memset(desc, 0, sizeof(*desc));
  872. desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
  873. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  874. __be16 protocol;
  875. u8 ip_protocol;
  876. u32 opts2 = 0;
  877. if (skb->protocol == htons(ETH_P_8021Q))
  878. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  879. else
  880. protocol = skb->protocol;
  881. switch (protocol) {
  882. case htons(ETH_P_IP):
  883. opts2 |= IPV4_CS;
  884. ip_protocol = ip_hdr(skb)->protocol;
  885. break;
  886. case htons(ETH_P_IPV6):
  887. opts2 |= IPV6_CS;
  888. ip_protocol = ipv6_hdr(skb)->nexthdr;
  889. break;
  890. default:
  891. ip_protocol = IPPROTO_RAW;
  892. break;
  893. }
  894. if (ip_protocol == IPPROTO_TCP) {
  895. opts2 |= TCP_CS;
  896. opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
  897. } else if (ip_protocol == IPPROTO_UDP) {
  898. opts2 |= UDP_CS;
  899. } else {
  900. WARN_ON_ONCE(1);
  901. }
  902. desc->opts2 = cpu_to_le32(opts2);
  903. }
  904. }
  905. static void rx_bottom(struct r8152 *tp)
  906. {
  907. struct net_device_stats *stats;
  908. struct net_device *netdev;
  909. struct rx_agg *agg;
  910. struct rx_desc *rx_desc;
  911. unsigned long lockflags;
  912. struct list_head *cursor, *next;
  913. struct sk_buff *skb;
  914. struct urb *urb;
  915. unsigned pkt_len;
  916. int len_used;
  917. u8 *rx_data;
  918. int ret;
  919. netdev = tp->netdev;
  920. stats = rtl8152_get_stats(netdev);
  921. spin_lock_irqsave(&tp->rx_lock, lockflags);
  922. list_for_each_safe(cursor, next, &tp->rx_done) {
  923. list_del_init(cursor);
  924. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  925. agg = list_entry(cursor, struct rx_agg, list);
  926. urb = agg->urb;
  927. if (urb->actual_length < ETH_ZLEN) {
  928. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  929. spin_lock_irqsave(&tp->rx_lock, lockflags);
  930. if (ret && ret != -ENODEV) {
  931. list_add_tail(&agg->list, next);
  932. tasklet_schedule(&tp->tl);
  933. }
  934. continue;
  935. }
  936. len_used = 0;
  937. rx_desc = agg->head;
  938. rx_data = agg->head;
  939. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  940. len_used += sizeof(struct rx_desc) + pkt_len;
  941. while (urb->actual_length >= len_used) {
  942. if (pkt_len < ETH_ZLEN)
  943. break;
  944. pkt_len -= 4; /* CRC */
  945. rx_data += sizeof(struct rx_desc);
  946. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  947. if (!skb) {
  948. stats->rx_dropped++;
  949. break;
  950. }
  951. memcpy(skb->data, rx_data, pkt_len);
  952. skb_put(skb, pkt_len);
  953. skb->protocol = eth_type_trans(skb, netdev);
  954. netif_rx(skb);
  955. stats->rx_packets++;
  956. stats->rx_bytes += pkt_len;
  957. rx_data = rx_agg_align(rx_data + pkt_len + 4);
  958. rx_desc = (struct rx_desc *)rx_data;
  959. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  960. len_used = (int)(rx_data - (u8 *)agg->head);
  961. len_used += sizeof(struct rx_desc) + pkt_len;
  962. }
  963. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  964. spin_lock_irqsave(&tp->rx_lock, lockflags);
  965. if (ret && ret != -ENODEV) {
  966. list_add_tail(&agg->list, next);
  967. tasklet_schedule(&tp->tl);
  968. }
  969. }
  970. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  971. }
  972. static void tx_bottom(struct r8152 *tp)
  973. {
  974. struct net_device_stats *stats;
  975. struct net_device *netdev;
  976. struct tx_agg *agg;
  977. unsigned long lockflags;
  978. u32 remain, total;
  979. u8 *tx_data;
  980. int res;
  981. netdev = tp->netdev;
  982. next_agg:
  983. agg = NULL;
  984. spin_lock_irqsave(&tp->tx_lock, lockflags);
  985. if (!skb_queue_empty(&tp->tx_queue) && !list_empty(&tp->tx_free)) {
  986. struct list_head *cursor;
  987. cursor = tp->tx_free.next;
  988. list_del_init(cursor);
  989. agg = list_entry(cursor, struct tx_agg, list);
  990. }
  991. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  992. if (!agg)
  993. return;
  994. tx_data = agg->head;
  995. agg->skb_num = agg->skb_len = 0;
  996. remain = rx_buf_sz - sizeof(struct tx_desc);
  997. total = 0;
  998. while (remain >= ETH_ZLEN) {
  999. struct tx_desc *tx_desc;
  1000. struct sk_buff *skb;
  1001. unsigned int len;
  1002. skb = skb_dequeue(&tp->tx_queue);
  1003. if (!skb)
  1004. break;
  1005. len = skb->len;
  1006. if (remain < len) {
  1007. skb_queue_head(&tp->tx_queue, skb);
  1008. break;
  1009. }
  1010. tx_data = tx_agg_align(tx_data);
  1011. tx_desc = (struct tx_desc *)tx_data;
  1012. tx_data += sizeof(*tx_desc);
  1013. r8152_tx_csum(tp, tx_desc, skb);
  1014. memcpy(tx_data, skb->data, len);
  1015. agg->skb_num++;
  1016. agg->skb_len += len;
  1017. dev_kfree_skb_any(skb);
  1018. tx_data += len;
  1019. remain = rx_buf_sz - sizeof(*tx_desc) -
  1020. (u32)(tx_agg_align(tx_data) - agg->head);
  1021. }
  1022. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1023. agg->head, (int)(tx_data - (u8 *)agg->head),
  1024. (usb_complete_t)write_bulk_callback, agg);
  1025. res = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1026. stats = rtl8152_get_stats(netdev);
  1027. if (res) {
  1028. /* Can we get/handle EPIPE here? */
  1029. if (res == -ENODEV) {
  1030. netif_device_detach(netdev);
  1031. } else {
  1032. netif_warn(tp, tx_err, netdev,
  1033. "failed tx_urb %d\n", res);
  1034. stats->tx_dropped += agg->skb_num;
  1035. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1036. list_add_tail(&agg->list, &tp->tx_free);
  1037. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1038. }
  1039. return;
  1040. }
  1041. goto next_agg;
  1042. }
  1043. static void bottom_half(unsigned long data)
  1044. {
  1045. struct r8152 *tp;
  1046. tp = (struct r8152 *)data;
  1047. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1048. return;
  1049. if (!test_bit(WORK_ENABLE, &tp->flags))
  1050. return;
  1051. if (!netif_carrier_ok(tp->netdev))
  1052. return;
  1053. rx_bottom(tp);
  1054. tx_bottom(tp);
  1055. }
  1056. static
  1057. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1058. {
  1059. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1060. agg->head, rx_buf_sz,
  1061. (usb_complete_t)read_bulk_callback, agg);
  1062. return usb_submit_urb(agg->urb, mem_flags);
  1063. }
  1064. static void rtl8152_tx_timeout(struct net_device *netdev)
  1065. {
  1066. struct r8152 *tp = netdev_priv(netdev);
  1067. int i;
  1068. netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
  1069. for (i = 0; i < RTL8152_MAX_TX; i++)
  1070. usb_unlink_urb(tp->tx_info[i].urb);
  1071. }
  1072. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1073. {
  1074. struct r8152 *tp = netdev_priv(netdev);
  1075. if (tp->speed & LINK_STATUS) {
  1076. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1077. schedule_delayed_work(&tp->schedule, 0);
  1078. }
  1079. }
  1080. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1081. {
  1082. struct r8152 *tp = netdev_priv(netdev);
  1083. u32 mc_filter[2]; /* Multicast hash filter */
  1084. __le32 tmp[2];
  1085. u32 ocp_data;
  1086. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1087. netif_stop_queue(netdev);
  1088. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1089. ocp_data &= ~RCR_ACPT_ALL;
  1090. ocp_data |= RCR_AB | RCR_APM;
  1091. if (netdev->flags & IFF_PROMISC) {
  1092. /* Unconditionally log net taps. */
  1093. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1094. ocp_data |= RCR_AM | RCR_AAP;
  1095. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1096. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1097. (netdev->flags & IFF_ALLMULTI)) {
  1098. /* Too many to filter perfectly -- accept all multicasts. */
  1099. ocp_data |= RCR_AM;
  1100. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1101. } else {
  1102. struct netdev_hw_addr *ha;
  1103. mc_filter[1] = mc_filter[0] = 0;
  1104. netdev_for_each_mc_addr(ha, netdev) {
  1105. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1106. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1107. ocp_data |= RCR_AM;
  1108. }
  1109. }
  1110. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1111. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1112. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1113. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1114. netif_wake_queue(netdev);
  1115. }
  1116. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1117. struct net_device *netdev)
  1118. {
  1119. struct r8152 *tp = netdev_priv(netdev);
  1120. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  1121. unsigned long lockflags;
  1122. struct tx_agg *agg = NULL;
  1123. struct tx_desc *tx_desc;
  1124. unsigned int len;
  1125. u8 *tx_data;
  1126. int res;
  1127. skb_tx_timestamp(skb);
  1128. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1129. if (!list_empty(&tp->tx_free) && skb_queue_empty(&tp->tx_queue)) {
  1130. struct list_head *cursor;
  1131. cursor = tp->tx_free.next;
  1132. list_del_init(cursor);
  1133. agg = list_entry(cursor, struct tx_agg, list);
  1134. }
  1135. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1136. if (!agg) {
  1137. skb_queue_tail(&tp->tx_queue, skb);
  1138. return NETDEV_TX_OK;
  1139. }
  1140. tx_desc = (struct tx_desc *)agg->head;
  1141. tx_data = agg->head + sizeof(*tx_desc);
  1142. agg->skb_num = agg->skb_len = 0;
  1143. len = skb->len;
  1144. r8152_tx_csum(tp, tx_desc, skb);
  1145. memcpy(tx_data, skb->data, len);
  1146. dev_kfree_skb_any(skb);
  1147. agg->skb_num++;
  1148. agg->skb_len += len;
  1149. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1150. agg->head, len + sizeof(*tx_desc),
  1151. (usb_complete_t)write_bulk_callback, agg);
  1152. res = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1153. if (res) {
  1154. /* Can we get/handle EPIPE here? */
  1155. if (res == -ENODEV) {
  1156. netif_device_detach(tp->netdev);
  1157. } else {
  1158. netif_warn(tp, tx_err, netdev,
  1159. "failed tx_urb %d\n", res);
  1160. stats->tx_dropped++;
  1161. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1162. list_add_tail(&agg->list, &tp->tx_free);
  1163. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1164. }
  1165. }
  1166. return NETDEV_TX_OK;
  1167. }
  1168. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1169. {
  1170. u32 ocp_data;
  1171. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1172. ocp_data &= ~FMC_FCR_MCU_EN;
  1173. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1174. ocp_data |= FMC_FCR_MCU_EN;
  1175. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1176. }
  1177. static void rtl8152_nic_reset(struct r8152 *tp)
  1178. {
  1179. int i;
  1180. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1181. for (i = 0; i < 1000; i++) {
  1182. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1183. break;
  1184. udelay(100);
  1185. }
  1186. }
  1187. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1188. {
  1189. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1190. }
  1191. static int rtl8152_enable(struct r8152 *tp)
  1192. {
  1193. u32 ocp_data;
  1194. int i, ret;
  1195. u8 speed;
  1196. speed = rtl8152_get_speed(tp);
  1197. if (speed & _10bps) {
  1198. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1199. ocp_data |= EEEP_CR_EEEP_TX;
  1200. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1201. } else {
  1202. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1203. ocp_data &= ~EEEP_CR_EEEP_TX;
  1204. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1205. }
  1206. r8152b_reset_packet_filter(tp);
  1207. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1208. ocp_data |= CR_RE | CR_TE;
  1209. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1210. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1211. ocp_data &= ~RXDY_GATED_EN;
  1212. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1213. INIT_LIST_HEAD(&tp->rx_done);
  1214. ret = 0;
  1215. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1216. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1217. ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1218. }
  1219. return ret;
  1220. }
  1221. static void rtl8152_disable(struct r8152 *tp)
  1222. {
  1223. struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
  1224. struct sk_buff *skb;
  1225. u32 ocp_data;
  1226. int i;
  1227. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1228. ocp_data &= ~RCR_ACPT_ALL;
  1229. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1230. while ((skb = skb_dequeue(&tp->tx_queue))) {
  1231. dev_kfree_skb(skb);
  1232. stats->tx_dropped++;
  1233. }
  1234. for (i = 0; i < RTL8152_MAX_TX; i++)
  1235. usb_kill_urb(tp->tx_info[i].urb);
  1236. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1237. ocp_data |= RXDY_GATED_EN;
  1238. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1239. for (i = 0; i < 1000; i++) {
  1240. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1241. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1242. break;
  1243. mdelay(1);
  1244. }
  1245. for (i = 0; i < 1000; i++) {
  1246. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1247. break;
  1248. mdelay(1);
  1249. }
  1250. for (i = 0; i < RTL8152_MAX_RX; i++)
  1251. usb_kill_urb(tp->rx_info[i].urb);
  1252. rtl8152_nic_reset(tp);
  1253. }
  1254. static void r8152b_exit_oob(struct r8152 *tp)
  1255. {
  1256. u32 ocp_data;
  1257. int i;
  1258. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1259. ocp_data &= ~RCR_ACPT_ALL;
  1260. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1261. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1262. ocp_data |= RXDY_GATED_EN;
  1263. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1264. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1265. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1266. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1267. ocp_data &= ~NOW_IS_OOB;
  1268. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1269. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1270. ocp_data &= ~MCU_BORW_EN;
  1271. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1272. for (i = 0; i < 1000; i++) {
  1273. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1274. if (ocp_data & LINK_LIST_READY)
  1275. break;
  1276. mdelay(1);
  1277. }
  1278. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1279. ocp_data |= RE_INIT_LL;
  1280. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1281. for (i = 0; i < 1000; i++) {
  1282. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1283. if (ocp_data & LINK_LIST_READY)
  1284. break;
  1285. mdelay(1);
  1286. }
  1287. rtl8152_nic_reset(tp);
  1288. /* rx share fifo credit full threshold */
  1289. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1290. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
  1291. ocp_data &= STAT_SPEED_MASK;
  1292. if (ocp_data == STAT_SPEED_FULL) {
  1293. /* rx share fifo credit near full threshold */
  1294. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1295. RXFIFO_THR2_FULL);
  1296. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1297. RXFIFO_THR3_FULL);
  1298. } else {
  1299. /* rx share fifo credit near full threshold */
  1300. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1301. RXFIFO_THR2_HIGH);
  1302. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1303. RXFIFO_THR3_HIGH);
  1304. }
  1305. /* TX share fifo free credit full threshold */
  1306. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  1307. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1308. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
  1309. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1310. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1311. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1312. ocp_data &= ~CPCR_RX_VLAN;
  1313. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1314. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1315. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  1316. ocp_data |= TCR0_AUTO_FIFO;
  1317. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  1318. }
  1319. static void r8152b_enter_oob(struct r8152 *tp)
  1320. {
  1321. u32 ocp_data;
  1322. int i;
  1323. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1324. ocp_data &= ~NOW_IS_OOB;
  1325. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1326. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  1327. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  1328. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  1329. rtl8152_disable(tp);
  1330. for (i = 0; i < 1000; i++) {
  1331. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1332. if (ocp_data & LINK_LIST_READY)
  1333. break;
  1334. mdelay(1);
  1335. }
  1336. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1337. ocp_data |= RE_INIT_LL;
  1338. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1339. for (i = 0; i < 1000; i++) {
  1340. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1341. if (ocp_data & LINK_LIST_READY)
  1342. break;
  1343. mdelay(1);
  1344. }
  1345. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1346. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1347. ocp_data |= MAGIC_EN;
  1348. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1349. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1350. ocp_data |= CPCR_RX_VLAN;
  1351. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1352. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  1353. ocp_data |= ALDPS_PROXY_MODE;
  1354. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  1355. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1356. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  1357. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1358. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
  1359. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1360. ocp_data &= ~RXDY_GATED_EN;
  1361. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1362. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1363. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  1364. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1365. }
  1366. static void r8152b_disable_aldps(struct r8152 *tp)
  1367. {
  1368. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1369. msleep(20);
  1370. }
  1371. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1372. {
  1373. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1374. LINKENA | DIS_SDSAVE);
  1375. }
  1376. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  1377. {
  1378. u16 bmcr, anar;
  1379. int ret = 0;
  1380. cancel_delayed_work_sync(&tp->schedule);
  1381. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1382. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1383. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1384. if (autoneg == AUTONEG_DISABLE) {
  1385. if (speed == SPEED_10) {
  1386. bmcr = 0;
  1387. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1388. } else if (speed == SPEED_100) {
  1389. bmcr = BMCR_SPEED100;
  1390. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1391. } else {
  1392. ret = -EINVAL;
  1393. goto out;
  1394. }
  1395. if (duplex == DUPLEX_FULL)
  1396. bmcr |= BMCR_FULLDPLX;
  1397. } else {
  1398. if (speed == SPEED_10) {
  1399. if (duplex == DUPLEX_FULL)
  1400. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1401. else
  1402. anar |= ADVERTISE_10HALF;
  1403. } else if (speed == SPEED_100) {
  1404. if (duplex == DUPLEX_FULL) {
  1405. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1406. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1407. } else {
  1408. anar |= ADVERTISE_10HALF;
  1409. anar |= ADVERTISE_100HALF;
  1410. }
  1411. } else {
  1412. ret = -EINVAL;
  1413. goto out;
  1414. }
  1415. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1416. }
  1417. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1418. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1419. out:
  1420. return ret;
  1421. }
  1422. static void rtl8152_down(struct r8152 *tp)
  1423. {
  1424. u32 ocp_data;
  1425. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1426. ocp_data &= ~POWER_CUT;
  1427. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1428. r8152b_disable_aldps(tp);
  1429. r8152b_enter_oob(tp);
  1430. r8152b_enable_aldps(tp);
  1431. }
  1432. static void set_carrier(struct r8152 *tp)
  1433. {
  1434. struct net_device *netdev = tp->netdev;
  1435. u8 speed;
  1436. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  1437. speed = rtl8152_get_speed(tp);
  1438. if (speed & LINK_STATUS) {
  1439. if (!(tp->speed & LINK_STATUS)) {
  1440. rtl8152_enable(tp);
  1441. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1442. netif_carrier_on(netdev);
  1443. }
  1444. } else {
  1445. if (tp->speed & LINK_STATUS) {
  1446. netif_carrier_off(netdev);
  1447. tasklet_disable(&tp->tl);
  1448. rtl8152_disable(tp);
  1449. tasklet_enable(&tp->tl);
  1450. }
  1451. }
  1452. tp->speed = speed;
  1453. }
  1454. static void rtl_work_func_t(struct work_struct *work)
  1455. {
  1456. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  1457. if (!test_bit(WORK_ENABLE, &tp->flags))
  1458. goto out1;
  1459. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1460. goto out1;
  1461. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  1462. set_carrier(tp);
  1463. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  1464. _rtl8152_set_rx_mode(tp->netdev);
  1465. out1:
  1466. return;
  1467. }
  1468. static int rtl8152_open(struct net_device *netdev)
  1469. {
  1470. struct r8152 *tp = netdev_priv(netdev);
  1471. int res = 0;
  1472. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  1473. if (res) {
  1474. if (res == -ENODEV)
  1475. netif_device_detach(tp->netdev);
  1476. netif_warn(tp, ifup, netdev,
  1477. "intr_urb submit failed: %d\n", res);
  1478. return res;
  1479. }
  1480. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1481. tp->speed = 0;
  1482. netif_carrier_off(netdev);
  1483. netif_start_queue(netdev);
  1484. set_bit(WORK_ENABLE, &tp->flags);
  1485. return res;
  1486. }
  1487. static int rtl8152_close(struct net_device *netdev)
  1488. {
  1489. struct r8152 *tp = netdev_priv(netdev);
  1490. int res = 0;
  1491. usb_kill_urb(tp->intr_urb);
  1492. clear_bit(WORK_ENABLE, &tp->flags);
  1493. cancel_delayed_work_sync(&tp->schedule);
  1494. netif_stop_queue(netdev);
  1495. tasklet_disable(&tp->tl);
  1496. rtl8152_disable(tp);
  1497. tasklet_enable(&tp->tl);
  1498. return res;
  1499. }
  1500. static void rtl_clear_bp(struct r8152 *tp)
  1501. {
  1502. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
  1503. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
  1504. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
  1505. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
  1506. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
  1507. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
  1508. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
  1509. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
  1510. mdelay(3);
  1511. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
  1512. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
  1513. }
  1514. static void r8152b_enable_eee(struct r8152 *tp)
  1515. {
  1516. u32 ocp_data;
  1517. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  1518. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  1519. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  1520. ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
  1521. EEE_10_CAP | EEE_NWAY_EN |
  1522. TX_QUIET_EN | RX_QUIET_EN |
  1523. SDRISETIME | RG_RXLPI_MSK_HFDUP |
  1524. SDFALLTIME);
  1525. ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
  1526. RG_LDVQUIET_EN | RG_CKRSEL |
  1527. RG_EEEPRG_EN);
  1528. ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
  1529. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
  1530. ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
  1531. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
  1532. ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
  1533. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  1534. }
  1535. static void r8152b_enable_fc(struct r8152 *tp)
  1536. {
  1537. u16 anar;
  1538. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1539. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1540. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1541. }
  1542. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1543. {
  1544. r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
  1545. r8152b_disable_aldps(tp);
  1546. }
  1547. static void r8152b_init(struct r8152 *tp)
  1548. {
  1549. u32 ocp_data;
  1550. int i;
  1551. rtl_clear_bp(tp);
  1552. if (tp->version == RTL_VER_01) {
  1553. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1554. ocp_data &= ~LED_MODE_MASK;
  1555. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1556. }
  1557. r8152b_hw_phy_cfg(tp);
  1558. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1559. ocp_data &= ~POWER_CUT;
  1560. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1561. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1562. ocp_data &= ~RWSUME_INDICATE;
  1563. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1564. r8152b_exit_oob(tp);
  1565. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1566. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1567. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1568. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1569. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1570. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1571. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1572. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1573. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1574. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1575. r8152b_enable_eee(tp);
  1576. r8152b_enable_aldps(tp);
  1577. r8152b_enable_fc(tp);
  1578. r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
  1579. BMCR_ANRESTART);
  1580. for (i = 0; i < 100; i++) {
  1581. udelay(100);
  1582. if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
  1583. break;
  1584. }
  1585. /* enable rx aggregation */
  1586. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1587. ocp_data &= ~RX_AGG_DISABLE;
  1588. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1589. }
  1590. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  1591. {
  1592. struct r8152 *tp = usb_get_intfdata(intf);
  1593. netif_device_detach(tp->netdev);
  1594. if (netif_running(tp->netdev)) {
  1595. clear_bit(WORK_ENABLE, &tp->flags);
  1596. usb_kill_urb(tp->intr_urb);
  1597. cancel_delayed_work_sync(&tp->schedule);
  1598. tasklet_disable(&tp->tl);
  1599. }
  1600. rtl8152_down(tp);
  1601. return 0;
  1602. }
  1603. static int rtl8152_resume(struct usb_interface *intf)
  1604. {
  1605. struct r8152 *tp = usb_get_intfdata(intf);
  1606. r8152b_init(tp);
  1607. netif_device_attach(tp->netdev);
  1608. if (netif_running(tp->netdev)) {
  1609. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1610. tp->speed = 0;
  1611. netif_carrier_off(tp->netdev);
  1612. set_bit(WORK_ENABLE, &tp->flags);
  1613. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  1614. tasklet_enable(&tp->tl);
  1615. }
  1616. return 0;
  1617. }
  1618. static void rtl8152_get_drvinfo(struct net_device *netdev,
  1619. struct ethtool_drvinfo *info)
  1620. {
  1621. struct r8152 *tp = netdev_priv(netdev);
  1622. strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
  1623. strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
  1624. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  1625. }
  1626. static
  1627. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  1628. {
  1629. struct r8152 *tp = netdev_priv(netdev);
  1630. if (!tp->mii.mdio_read)
  1631. return -EOPNOTSUPP;
  1632. return mii_ethtool_gset(&tp->mii, cmd);
  1633. }
  1634. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1635. {
  1636. struct r8152 *tp = netdev_priv(dev);
  1637. return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  1638. }
  1639. static struct ethtool_ops ops = {
  1640. .get_drvinfo = rtl8152_get_drvinfo,
  1641. .get_settings = rtl8152_get_settings,
  1642. .set_settings = rtl8152_set_settings,
  1643. .get_link = ethtool_op_get_link,
  1644. };
  1645. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  1646. {
  1647. struct r8152 *tp = netdev_priv(netdev);
  1648. struct mii_ioctl_data *data = if_mii(rq);
  1649. int res = 0;
  1650. switch (cmd) {
  1651. case SIOCGMIIPHY:
  1652. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  1653. break;
  1654. case SIOCGMIIREG:
  1655. data->val_out = r8152_mdio_read(tp, data->reg_num);
  1656. break;
  1657. case SIOCSMIIREG:
  1658. if (!capable(CAP_NET_ADMIN)) {
  1659. res = -EPERM;
  1660. break;
  1661. }
  1662. r8152_mdio_write(tp, data->reg_num, data->val_in);
  1663. break;
  1664. default:
  1665. res = -EOPNOTSUPP;
  1666. }
  1667. return res;
  1668. }
  1669. static const struct net_device_ops rtl8152_netdev_ops = {
  1670. .ndo_open = rtl8152_open,
  1671. .ndo_stop = rtl8152_close,
  1672. .ndo_do_ioctl = rtl8152_ioctl,
  1673. .ndo_start_xmit = rtl8152_start_xmit,
  1674. .ndo_tx_timeout = rtl8152_tx_timeout,
  1675. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  1676. .ndo_set_mac_address = rtl8152_set_mac_address,
  1677. .ndo_change_mtu = eth_change_mtu,
  1678. .ndo_validate_addr = eth_validate_addr,
  1679. };
  1680. static void r8152b_get_version(struct r8152 *tp)
  1681. {
  1682. u32 ocp_data;
  1683. u16 version;
  1684. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  1685. version = (u16)(ocp_data & VERSION_MASK);
  1686. switch (version) {
  1687. case 0x4c00:
  1688. tp->version = RTL_VER_01;
  1689. break;
  1690. case 0x4c10:
  1691. tp->version = RTL_VER_02;
  1692. break;
  1693. default:
  1694. netif_info(tp, probe, tp->netdev,
  1695. "Unknown version 0x%04x\n", version);
  1696. break;
  1697. }
  1698. }
  1699. static int rtl8152_probe(struct usb_interface *intf,
  1700. const struct usb_device_id *id)
  1701. {
  1702. struct usb_device *udev = interface_to_usbdev(intf);
  1703. struct r8152 *tp;
  1704. struct net_device *netdev;
  1705. int ret;
  1706. if (udev->actconfig->desc.bConfigurationValue != 1) {
  1707. usb_driver_set_configuration(udev, 1);
  1708. return -ENODEV;
  1709. }
  1710. netdev = alloc_etherdev(sizeof(struct r8152));
  1711. if (!netdev) {
  1712. dev_err(&intf->dev, "Out of memory");
  1713. return -ENOMEM;
  1714. }
  1715. SET_NETDEV_DEV(netdev, &intf->dev);
  1716. tp = netdev_priv(netdev);
  1717. tp->msg_enable = 0x7FFF;
  1718. tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
  1719. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  1720. tp->udev = udev;
  1721. tp->netdev = netdev;
  1722. tp->intf = intf;
  1723. netdev->netdev_ops = &rtl8152_netdev_ops;
  1724. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  1725. netdev->features |= NETIF_F_IP_CSUM;
  1726. netdev->hw_features = NETIF_F_IP_CSUM;
  1727. SET_ETHTOOL_OPS(netdev, &ops);
  1728. tp->mii.dev = netdev;
  1729. tp->mii.mdio_read = read_mii_word;
  1730. tp->mii.mdio_write = write_mii_word;
  1731. tp->mii.phy_id_mask = 0x3f;
  1732. tp->mii.reg_num_mask = 0x1f;
  1733. tp->mii.phy_id = R8152_PHY_ID;
  1734. tp->mii.supports_gmii = 0;
  1735. r8152b_get_version(tp);
  1736. r8152b_init(tp);
  1737. set_ethernet_addr(tp);
  1738. ret = alloc_all_mem(tp);
  1739. if (ret)
  1740. goto out;
  1741. usb_set_intfdata(intf, tp);
  1742. ret = register_netdev(netdev);
  1743. if (ret != 0) {
  1744. netif_err(tp, probe, netdev, "couldn't register the device");
  1745. goto out1;
  1746. }
  1747. netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
  1748. return 0;
  1749. out1:
  1750. usb_set_intfdata(intf, NULL);
  1751. out:
  1752. free_netdev(netdev);
  1753. return ret;
  1754. }
  1755. static void rtl8152_unload(struct r8152 *tp)
  1756. {
  1757. u32 ocp_data;
  1758. if (tp->version != RTL_VER_01) {
  1759. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1760. ocp_data |= POWER_CUT;
  1761. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1762. }
  1763. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1764. ocp_data &= ~RWSUME_INDICATE;
  1765. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1766. }
  1767. static void rtl8152_disconnect(struct usb_interface *intf)
  1768. {
  1769. struct r8152 *tp = usb_get_intfdata(intf);
  1770. usb_set_intfdata(intf, NULL);
  1771. if (tp) {
  1772. set_bit(RTL8152_UNPLUG, &tp->flags);
  1773. tasklet_kill(&tp->tl);
  1774. unregister_netdev(tp->netdev);
  1775. rtl8152_unload(tp);
  1776. free_all_mem(tp);
  1777. free_netdev(tp->netdev);
  1778. }
  1779. }
  1780. /* table of devices that work with this driver */
  1781. static struct usb_device_id rtl8152_table[] = {
  1782. {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
  1783. {}
  1784. };
  1785. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  1786. static struct usb_driver rtl8152_driver = {
  1787. .name = MODULENAME,
  1788. .id_table = rtl8152_table,
  1789. .probe = rtl8152_probe,
  1790. .disconnect = rtl8152_disconnect,
  1791. .suspend = rtl8152_suspend,
  1792. .resume = rtl8152_resume,
  1793. .reset_resume = rtl8152_resume,
  1794. };
  1795. module_usb_driver(rtl8152_driver);
  1796. MODULE_AUTHOR(DRIVER_AUTHOR);
  1797. MODULE_DESCRIPTION(DRIVER_DESC);
  1798. MODULE_LICENSE("GPL");