intel_display.c 94 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/i2c.h>
  27. #include <linux/kernel.h>
  28. #include "drmP.h"
  29. #include "intel_drv.h"
  30. #include "i915_drm.h"
  31. #include "i915_drv.h"
  32. #include "intel_dp.h"
  33. #include "drm_crtc_helper.h"
  34. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  35. static void intel_update_watermarks(struct drm_device *dev);
  36. typedef struct {
  37. /* given values */
  38. int n;
  39. int m1, m2;
  40. int p1, p2;
  41. /* derived values */
  42. int dot;
  43. int vco;
  44. int m;
  45. int p;
  46. } intel_clock_t;
  47. typedef struct {
  48. int min, max;
  49. } intel_range_t;
  50. typedef struct {
  51. int dot_limit;
  52. int p2_slow, p2_fast;
  53. } intel_p2_t;
  54. #define INTEL_P2_NUM 2
  55. typedef struct intel_limit intel_limit_t;
  56. struct intel_limit {
  57. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  58. intel_p2_t p2;
  59. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  60. int, int, intel_clock_t *);
  61. };
  62. #define I8XX_DOT_MIN 25000
  63. #define I8XX_DOT_MAX 350000
  64. #define I8XX_VCO_MIN 930000
  65. #define I8XX_VCO_MAX 1400000
  66. #define I8XX_N_MIN 3
  67. #define I8XX_N_MAX 16
  68. #define I8XX_M_MIN 96
  69. #define I8XX_M_MAX 140
  70. #define I8XX_M1_MIN 18
  71. #define I8XX_M1_MAX 26
  72. #define I8XX_M2_MIN 6
  73. #define I8XX_M2_MAX 16
  74. #define I8XX_P_MIN 4
  75. #define I8XX_P_MAX 128
  76. #define I8XX_P1_MIN 2
  77. #define I8XX_P1_MAX 33
  78. #define I8XX_P1_LVDS_MIN 1
  79. #define I8XX_P1_LVDS_MAX 6
  80. #define I8XX_P2_SLOW 4
  81. #define I8XX_P2_FAST 2
  82. #define I8XX_P2_LVDS_SLOW 14
  83. #define I8XX_P2_LVDS_FAST 14 /* No fast option */
  84. #define I8XX_P2_SLOW_LIMIT 165000
  85. #define I9XX_DOT_MIN 20000
  86. #define I9XX_DOT_MAX 400000
  87. #define I9XX_VCO_MIN 1400000
  88. #define I9XX_VCO_MAX 2800000
  89. #define IGD_VCO_MIN 1700000
  90. #define IGD_VCO_MAX 3500000
  91. #define I9XX_N_MIN 1
  92. #define I9XX_N_MAX 6
  93. /* IGD's Ncounter is a ring counter */
  94. #define IGD_N_MIN 3
  95. #define IGD_N_MAX 6
  96. #define I9XX_M_MIN 70
  97. #define I9XX_M_MAX 120
  98. #define IGD_M_MIN 2
  99. #define IGD_M_MAX 256
  100. #define I9XX_M1_MIN 10
  101. #define I9XX_M1_MAX 22
  102. #define I9XX_M2_MIN 5
  103. #define I9XX_M2_MAX 9
  104. /* IGD M1 is reserved, and must be 0 */
  105. #define IGD_M1_MIN 0
  106. #define IGD_M1_MAX 0
  107. #define IGD_M2_MIN 0
  108. #define IGD_M2_MAX 254
  109. #define I9XX_P_SDVO_DAC_MIN 5
  110. #define I9XX_P_SDVO_DAC_MAX 80
  111. #define I9XX_P_LVDS_MIN 7
  112. #define I9XX_P_LVDS_MAX 98
  113. #define IGD_P_LVDS_MIN 7
  114. #define IGD_P_LVDS_MAX 112
  115. #define I9XX_P1_MIN 1
  116. #define I9XX_P1_MAX 8
  117. #define I9XX_P2_SDVO_DAC_SLOW 10
  118. #define I9XX_P2_SDVO_DAC_FAST 5
  119. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  120. #define I9XX_P2_LVDS_SLOW 14
  121. #define I9XX_P2_LVDS_FAST 7
  122. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  123. /*The parameter is for SDVO on G4x platform*/
  124. #define G4X_DOT_SDVO_MIN 25000
  125. #define G4X_DOT_SDVO_MAX 270000
  126. #define G4X_VCO_MIN 1750000
  127. #define G4X_VCO_MAX 3500000
  128. #define G4X_N_SDVO_MIN 1
  129. #define G4X_N_SDVO_MAX 4
  130. #define G4X_M_SDVO_MIN 104
  131. #define G4X_M_SDVO_MAX 138
  132. #define G4X_M1_SDVO_MIN 17
  133. #define G4X_M1_SDVO_MAX 23
  134. #define G4X_M2_SDVO_MIN 5
  135. #define G4X_M2_SDVO_MAX 11
  136. #define G4X_P_SDVO_MIN 10
  137. #define G4X_P_SDVO_MAX 30
  138. #define G4X_P1_SDVO_MIN 1
  139. #define G4X_P1_SDVO_MAX 3
  140. #define G4X_P2_SDVO_SLOW 10
  141. #define G4X_P2_SDVO_FAST 10
  142. #define G4X_P2_SDVO_LIMIT 270000
  143. /*The parameter is for HDMI_DAC on G4x platform*/
  144. #define G4X_DOT_HDMI_DAC_MIN 22000
  145. #define G4X_DOT_HDMI_DAC_MAX 400000
  146. #define G4X_N_HDMI_DAC_MIN 1
  147. #define G4X_N_HDMI_DAC_MAX 4
  148. #define G4X_M_HDMI_DAC_MIN 104
  149. #define G4X_M_HDMI_DAC_MAX 138
  150. #define G4X_M1_HDMI_DAC_MIN 16
  151. #define G4X_M1_HDMI_DAC_MAX 23
  152. #define G4X_M2_HDMI_DAC_MIN 5
  153. #define G4X_M2_HDMI_DAC_MAX 11
  154. #define G4X_P_HDMI_DAC_MIN 5
  155. #define G4X_P_HDMI_DAC_MAX 80
  156. #define G4X_P1_HDMI_DAC_MIN 1
  157. #define G4X_P1_HDMI_DAC_MAX 8
  158. #define G4X_P2_HDMI_DAC_SLOW 10
  159. #define G4X_P2_HDMI_DAC_FAST 5
  160. #define G4X_P2_HDMI_DAC_LIMIT 165000
  161. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  162. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  163. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  164. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  165. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  166. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  167. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  168. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  169. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  170. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  171. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  172. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  173. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  174. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  175. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  176. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  177. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  178. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  179. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  180. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  181. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  182. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  183. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  184. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  185. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  186. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  187. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  188. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  189. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  190. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  191. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  192. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  193. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  194. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  195. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  196. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  197. /*The parameter is for DISPLAY PORT on G4x platform*/
  198. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  199. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  200. #define G4X_N_DISPLAY_PORT_MIN 1
  201. #define G4X_N_DISPLAY_PORT_MAX 2
  202. #define G4X_M_DISPLAY_PORT_MIN 97
  203. #define G4X_M_DISPLAY_PORT_MAX 108
  204. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  205. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  206. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  207. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  208. #define G4X_P_DISPLAY_PORT_MIN 10
  209. #define G4X_P_DISPLAY_PORT_MAX 20
  210. #define G4X_P1_DISPLAY_PORT_MIN 1
  211. #define G4X_P1_DISPLAY_PORT_MAX 2
  212. #define G4X_P2_DISPLAY_PORT_SLOW 10
  213. #define G4X_P2_DISPLAY_PORT_FAST 10
  214. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  215. /* IGDNG */
  216. /* as we calculate clock using (register_value + 2) for
  217. N/M1/M2, so here the range value for them is (actual_value-2).
  218. */
  219. #define IGDNG_DOT_MIN 25000
  220. #define IGDNG_DOT_MAX 350000
  221. #define IGDNG_VCO_MIN 1760000
  222. #define IGDNG_VCO_MAX 3510000
  223. #define IGDNG_N_MIN 1
  224. #define IGDNG_N_MAX 5
  225. #define IGDNG_M_MIN 79
  226. #define IGDNG_M_MAX 118
  227. #define IGDNG_M1_MIN 12
  228. #define IGDNG_M1_MAX 23
  229. #define IGDNG_M2_MIN 5
  230. #define IGDNG_M2_MAX 9
  231. #define IGDNG_P_SDVO_DAC_MIN 5
  232. #define IGDNG_P_SDVO_DAC_MAX 80
  233. #define IGDNG_P_LVDS_MIN 28
  234. #define IGDNG_P_LVDS_MAX 112
  235. #define IGDNG_P1_MIN 1
  236. #define IGDNG_P1_MAX 8
  237. #define IGDNG_P2_SDVO_DAC_SLOW 10
  238. #define IGDNG_P2_SDVO_DAC_FAST 5
  239. #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
  240. #define IGDNG_P2_LVDS_FAST 7 /* double channel */
  241. #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
  242. static bool
  243. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  244. int target, int refclk, intel_clock_t *best_clock);
  245. static bool
  246. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  247. int target, int refclk, intel_clock_t *best_clock);
  248. static bool
  249. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  250. int target, int refclk, intel_clock_t *best_clock);
  251. static bool
  252. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  253. int target, int refclk, intel_clock_t *best_clock);
  254. static const intel_limit_t intel_limits_i8xx_dvo = {
  255. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  256. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  257. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  258. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  259. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  260. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  261. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  262. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  263. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  264. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  265. .find_pll = intel_find_best_PLL,
  266. };
  267. static const intel_limit_t intel_limits_i8xx_lvds = {
  268. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  269. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  270. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  271. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  272. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  273. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  274. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  275. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  276. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  277. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  278. .find_pll = intel_find_best_PLL,
  279. };
  280. static const intel_limit_t intel_limits_i9xx_sdvo = {
  281. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  282. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  283. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  284. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  285. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  286. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  287. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  288. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  289. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  290. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  291. .find_pll = intel_find_best_PLL,
  292. };
  293. static const intel_limit_t intel_limits_i9xx_lvds = {
  294. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  295. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  296. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  297. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  298. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  299. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  300. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  301. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  302. /* The single-channel range is 25-112Mhz, and dual-channel
  303. * is 80-224Mhz. Prefer single channel as much as possible.
  304. */
  305. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  306. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  307. .find_pll = intel_find_best_PLL,
  308. };
  309. /* below parameter and function is for G4X Chipset Family*/
  310. static const intel_limit_t intel_limits_g4x_sdvo = {
  311. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  312. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  313. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  314. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  315. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  316. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  317. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  318. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  319. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  320. .p2_slow = G4X_P2_SDVO_SLOW,
  321. .p2_fast = G4X_P2_SDVO_FAST
  322. },
  323. .find_pll = intel_g4x_find_best_PLL,
  324. };
  325. static const intel_limit_t intel_limits_g4x_hdmi = {
  326. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  327. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  328. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  329. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  330. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  331. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  332. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  333. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  334. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  335. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  336. .p2_fast = G4X_P2_HDMI_DAC_FAST
  337. },
  338. .find_pll = intel_g4x_find_best_PLL,
  339. };
  340. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  341. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  342. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  343. .vco = { .min = G4X_VCO_MIN,
  344. .max = G4X_VCO_MAX },
  345. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  346. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  347. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  348. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  349. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  350. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  351. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  352. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  353. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  354. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  355. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  356. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  357. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  358. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  359. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  360. },
  361. .find_pll = intel_g4x_find_best_PLL,
  362. };
  363. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  364. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  365. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  366. .vco = { .min = G4X_VCO_MIN,
  367. .max = G4X_VCO_MAX },
  368. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  369. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  370. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  371. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  372. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  373. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  374. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  375. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  376. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  377. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  378. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  379. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  380. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  381. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  382. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  383. },
  384. .find_pll = intel_g4x_find_best_PLL,
  385. };
  386. static const intel_limit_t intel_limits_g4x_display_port = {
  387. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  388. .max = G4X_DOT_DISPLAY_PORT_MAX },
  389. .vco = { .min = G4X_VCO_MIN,
  390. .max = G4X_VCO_MAX},
  391. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  392. .max = G4X_N_DISPLAY_PORT_MAX },
  393. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  394. .max = G4X_M_DISPLAY_PORT_MAX },
  395. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  396. .max = G4X_M1_DISPLAY_PORT_MAX },
  397. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  398. .max = G4X_M2_DISPLAY_PORT_MAX },
  399. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  400. .max = G4X_P_DISPLAY_PORT_MAX },
  401. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  402. .max = G4X_P1_DISPLAY_PORT_MAX},
  403. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  404. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  405. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  406. .find_pll = intel_find_pll_g4x_dp,
  407. };
  408. static const intel_limit_t intel_limits_igd_sdvo = {
  409. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  410. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  411. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  412. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  413. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  414. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  415. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  416. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  417. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  418. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  419. .find_pll = intel_find_best_PLL,
  420. };
  421. static const intel_limit_t intel_limits_igd_lvds = {
  422. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  423. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  424. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  425. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  426. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  427. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  428. .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
  429. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  430. /* IGD only supports single-channel mode. */
  431. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  432. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  433. .find_pll = intel_find_best_PLL,
  434. };
  435. static const intel_limit_t intel_limits_igdng_sdvo = {
  436. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  437. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  438. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  439. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  440. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  441. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  442. .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
  443. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  444. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  445. .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
  446. .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
  447. .find_pll = intel_igdng_find_best_PLL,
  448. };
  449. static const intel_limit_t intel_limits_igdng_lvds = {
  450. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  451. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  452. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  453. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  454. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  455. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  456. .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
  457. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  458. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  459. .p2_slow = IGDNG_P2_LVDS_SLOW,
  460. .p2_fast = IGDNG_P2_LVDS_FAST },
  461. .find_pll = intel_igdng_find_best_PLL,
  462. };
  463. static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
  464. {
  465. const intel_limit_t *limit;
  466. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  467. limit = &intel_limits_igdng_lvds;
  468. else
  469. limit = &intel_limits_igdng_sdvo;
  470. return limit;
  471. }
  472. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  473. {
  474. struct drm_device *dev = crtc->dev;
  475. struct drm_i915_private *dev_priv = dev->dev_private;
  476. const intel_limit_t *limit;
  477. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  478. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  479. LVDS_CLKB_POWER_UP)
  480. /* LVDS with dual channel */
  481. limit = &intel_limits_g4x_dual_channel_lvds;
  482. else
  483. /* LVDS with dual channel */
  484. limit = &intel_limits_g4x_single_channel_lvds;
  485. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  486. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  487. limit = &intel_limits_g4x_hdmi;
  488. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  489. limit = &intel_limits_g4x_sdvo;
  490. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  491. limit = &intel_limits_g4x_display_port;
  492. } else /* The option is for other outputs */
  493. limit = &intel_limits_i9xx_sdvo;
  494. return limit;
  495. }
  496. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  497. {
  498. struct drm_device *dev = crtc->dev;
  499. const intel_limit_t *limit;
  500. if (IS_IGDNG(dev))
  501. limit = intel_igdng_limit(crtc);
  502. else if (IS_G4X(dev)) {
  503. limit = intel_g4x_limit(crtc);
  504. } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
  505. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  506. limit = &intel_limits_i9xx_lvds;
  507. else
  508. limit = &intel_limits_i9xx_sdvo;
  509. } else if (IS_IGD(dev)) {
  510. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  511. limit = &intel_limits_igd_lvds;
  512. else
  513. limit = &intel_limits_igd_sdvo;
  514. } else {
  515. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  516. limit = &intel_limits_i8xx_lvds;
  517. else
  518. limit = &intel_limits_i8xx_dvo;
  519. }
  520. return limit;
  521. }
  522. /* m1 is reserved as 0 in IGD, n is a ring counter */
  523. static void igd_clock(int refclk, intel_clock_t *clock)
  524. {
  525. clock->m = clock->m2 + 2;
  526. clock->p = clock->p1 * clock->p2;
  527. clock->vco = refclk * clock->m / clock->n;
  528. clock->dot = clock->vco / clock->p;
  529. }
  530. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  531. {
  532. if (IS_IGD(dev)) {
  533. igd_clock(refclk, clock);
  534. return;
  535. }
  536. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  537. clock->p = clock->p1 * clock->p2;
  538. clock->vco = refclk * clock->m / (clock->n + 2);
  539. clock->dot = clock->vco / clock->p;
  540. }
  541. /**
  542. * Returns whether any output on the specified pipe is of the specified type
  543. */
  544. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  545. {
  546. struct drm_device *dev = crtc->dev;
  547. struct drm_mode_config *mode_config = &dev->mode_config;
  548. struct drm_connector *l_entry;
  549. list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  550. if (l_entry->encoder &&
  551. l_entry->encoder->crtc == crtc) {
  552. struct intel_output *intel_output = to_intel_output(l_entry);
  553. if (intel_output->type == type)
  554. return true;
  555. }
  556. }
  557. return false;
  558. }
  559. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  560. /**
  561. * Returns whether the given set of divisors are valid for a given refclk with
  562. * the given connectors.
  563. */
  564. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  565. {
  566. const intel_limit_t *limit = intel_limit (crtc);
  567. struct drm_device *dev = crtc->dev;
  568. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  569. INTELPllInvalid ("p1 out of range\n");
  570. if (clock->p < limit->p.min || limit->p.max < clock->p)
  571. INTELPllInvalid ("p out of range\n");
  572. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  573. INTELPllInvalid ("m2 out of range\n");
  574. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  575. INTELPllInvalid ("m1 out of range\n");
  576. if (clock->m1 <= clock->m2 && !IS_IGD(dev))
  577. INTELPllInvalid ("m1 <= m2\n");
  578. if (clock->m < limit->m.min || limit->m.max < clock->m)
  579. INTELPllInvalid ("m out of range\n");
  580. if (clock->n < limit->n.min || limit->n.max < clock->n)
  581. INTELPllInvalid ("n out of range\n");
  582. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  583. INTELPllInvalid ("vco out of range\n");
  584. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  585. * connector, etc., rather than just a single range.
  586. */
  587. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  588. INTELPllInvalid ("dot out of range\n");
  589. return true;
  590. }
  591. static bool
  592. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  593. int target, int refclk, intel_clock_t *best_clock)
  594. {
  595. struct drm_device *dev = crtc->dev;
  596. struct drm_i915_private *dev_priv = dev->dev_private;
  597. intel_clock_t clock;
  598. int err = target;
  599. if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  600. (I915_READ(LVDS)) != 0) {
  601. /*
  602. * For LVDS, if the panel is on, just rely on its current
  603. * settings for dual-channel. We haven't figured out how to
  604. * reliably set up different single/dual channel state, if we
  605. * even can.
  606. */
  607. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  608. LVDS_CLKB_POWER_UP)
  609. clock.p2 = limit->p2.p2_fast;
  610. else
  611. clock.p2 = limit->p2.p2_slow;
  612. } else {
  613. if (target < limit->p2.dot_limit)
  614. clock.p2 = limit->p2.p2_slow;
  615. else
  616. clock.p2 = limit->p2.p2_fast;
  617. }
  618. memset (best_clock, 0, sizeof (*best_clock));
  619. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  620. for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
  621. /* m1 is always 0 in IGD */
  622. if (clock.m2 >= clock.m1 && !IS_IGD(dev))
  623. break;
  624. for (clock.n = limit->n.min; clock.n <= limit->n.max;
  625. clock.n++) {
  626. for (clock.p1 = limit->p1.min;
  627. clock.p1 <= limit->p1.max; clock.p1++) {
  628. int this_err;
  629. intel_clock(dev, refclk, &clock);
  630. if (!intel_PLL_is_valid(crtc, &clock))
  631. continue;
  632. this_err = abs(clock.dot - target);
  633. if (this_err < err) {
  634. *best_clock = clock;
  635. err = this_err;
  636. }
  637. }
  638. }
  639. }
  640. }
  641. return (err != target);
  642. }
  643. static bool
  644. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  645. int target, int refclk, intel_clock_t *best_clock)
  646. {
  647. struct drm_device *dev = crtc->dev;
  648. struct drm_i915_private *dev_priv = dev->dev_private;
  649. intel_clock_t clock;
  650. int max_n;
  651. bool found;
  652. /* approximately equals target * 0.00488 */
  653. int err_most = (target >> 8) + (target >> 10);
  654. found = false;
  655. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  656. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  657. LVDS_CLKB_POWER_UP)
  658. clock.p2 = limit->p2.p2_fast;
  659. else
  660. clock.p2 = limit->p2.p2_slow;
  661. } else {
  662. if (target < limit->p2.dot_limit)
  663. clock.p2 = limit->p2.p2_slow;
  664. else
  665. clock.p2 = limit->p2.p2_fast;
  666. }
  667. memset(best_clock, 0, sizeof(*best_clock));
  668. max_n = limit->n.max;
  669. /* based on hardware requriment prefer smaller n to precision */
  670. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  671. /* based on hardware requirment prefere larger m1,m2, p1 */
  672. for (clock.m1 = limit->m1.max;
  673. clock.m1 >= limit->m1.min; clock.m1--) {
  674. for (clock.m2 = limit->m2.max;
  675. clock.m2 >= limit->m2.min; clock.m2--) {
  676. for (clock.p1 = limit->p1.max;
  677. clock.p1 >= limit->p1.min; clock.p1--) {
  678. int this_err;
  679. intel_clock(dev, refclk, &clock);
  680. if (!intel_PLL_is_valid(crtc, &clock))
  681. continue;
  682. this_err = abs(clock.dot - target) ;
  683. if (this_err < err_most) {
  684. *best_clock = clock;
  685. err_most = this_err;
  686. max_n = clock.n;
  687. found = true;
  688. }
  689. }
  690. }
  691. }
  692. }
  693. return found;
  694. }
  695. static bool
  696. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  697. int target, int refclk, intel_clock_t *best_clock)
  698. {
  699. struct drm_device *dev = crtc->dev;
  700. struct drm_i915_private *dev_priv = dev->dev_private;
  701. intel_clock_t clock;
  702. int max_n;
  703. bool found;
  704. int err_most = 47;
  705. found = false;
  706. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  707. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  708. LVDS_CLKB_POWER_UP)
  709. clock.p2 = limit->p2.p2_fast;
  710. else
  711. clock.p2 = limit->p2.p2_slow;
  712. } else {
  713. if (target < limit->p2.dot_limit)
  714. clock.p2 = limit->p2.p2_slow;
  715. else
  716. clock.p2 = limit->p2.p2_fast;
  717. }
  718. memset(best_clock, 0, sizeof(*best_clock));
  719. max_n = limit->n.max;
  720. /* based on hardware requriment prefer smaller n to precision */
  721. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  722. /* based on hardware requirment prefere larger m1,m2, p1 */
  723. for (clock.m1 = limit->m1.max;
  724. clock.m1 >= limit->m1.min; clock.m1--) {
  725. for (clock.m2 = limit->m2.max;
  726. clock.m2 >= limit->m2.min; clock.m2--) {
  727. for (clock.p1 = limit->p1.max;
  728. clock.p1 >= limit->p1.min; clock.p1--) {
  729. int this_err;
  730. intel_clock(dev, refclk, &clock);
  731. if (!intel_PLL_is_valid(crtc, &clock))
  732. continue;
  733. this_err = abs((10000 - (target*10000/clock.dot)));
  734. if (this_err < err_most) {
  735. *best_clock = clock;
  736. err_most = this_err;
  737. max_n = clock.n;
  738. found = true;
  739. /* found on first matching */
  740. goto out;
  741. }
  742. }
  743. }
  744. }
  745. }
  746. out:
  747. return found;
  748. }
  749. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  750. static bool
  751. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  752. int target, int refclk, intel_clock_t *best_clock)
  753. {
  754. intel_clock_t clock;
  755. if (target < 200000) {
  756. clock.p1 = 2;
  757. clock.p2 = 10;
  758. clock.n = 2;
  759. clock.m1 = 23;
  760. clock.m2 = 8;
  761. } else {
  762. clock.p1 = 1;
  763. clock.p2 = 10;
  764. clock.n = 1;
  765. clock.m1 = 14;
  766. clock.m2 = 2;
  767. }
  768. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  769. clock.p = (clock.p1 * clock.p2);
  770. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  771. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  772. return true;
  773. }
  774. void
  775. intel_wait_for_vblank(struct drm_device *dev)
  776. {
  777. /* Wait for 20ms, i.e. one cycle at 50hz. */
  778. mdelay(20);
  779. }
  780. static int
  781. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  782. struct drm_framebuffer *old_fb)
  783. {
  784. struct drm_device *dev = crtc->dev;
  785. struct drm_i915_private *dev_priv = dev->dev_private;
  786. struct drm_i915_master_private *master_priv;
  787. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  788. struct intel_framebuffer *intel_fb;
  789. struct drm_i915_gem_object *obj_priv;
  790. struct drm_gem_object *obj;
  791. int pipe = intel_crtc->pipe;
  792. unsigned long Start, Offset;
  793. int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
  794. int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
  795. int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
  796. int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
  797. int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  798. u32 dspcntr, alignment;
  799. int ret;
  800. /* no fb bound */
  801. if (!crtc->fb) {
  802. DRM_DEBUG("No FB bound\n");
  803. return 0;
  804. }
  805. switch (pipe) {
  806. case 0:
  807. case 1:
  808. break;
  809. default:
  810. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  811. return -EINVAL;
  812. }
  813. intel_fb = to_intel_framebuffer(crtc->fb);
  814. obj = intel_fb->obj;
  815. obj_priv = obj->driver_private;
  816. switch (obj_priv->tiling_mode) {
  817. case I915_TILING_NONE:
  818. alignment = 64 * 1024;
  819. break;
  820. case I915_TILING_X:
  821. /* pin() will align the object as required by fence */
  822. alignment = 0;
  823. break;
  824. case I915_TILING_Y:
  825. /* FIXME: Is this true? */
  826. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  827. return -EINVAL;
  828. default:
  829. BUG();
  830. }
  831. mutex_lock(&dev->struct_mutex);
  832. ret = i915_gem_object_pin(obj, alignment);
  833. if (ret != 0) {
  834. mutex_unlock(&dev->struct_mutex);
  835. return ret;
  836. }
  837. ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  838. if (ret != 0) {
  839. i915_gem_object_unpin(obj);
  840. mutex_unlock(&dev->struct_mutex);
  841. return ret;
  842. }
  843. /* Pre-i965 needs to install a fence for tiled scan-out */
  844. if (!IS_I965G(dev) &&
  845. obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  846. obj_priv->tiling_mode != I915_TILING_NONE) {
  847. ret = i915_gem_object_get_fence_reg(obj);
  848. if (ret != 0) {
  849. i915_gem_object_unpin(obj);
  850. mutex_unlock(&dev->struct_mutex);
  851. return ret;
  852. }
  853. }
  854. dspcntr = I915_READ(dspcntr_reg);
  855. /* Mask out pixel format bits in case we change it */
  856. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  857. switch (crtc->fb->bits_per_pixel) {
  858. case 8:
  859. dspcntr |= DISPPLANE_8BPP;
  860. break;
  861. case 16:
  862. if (crtc->fb->depth == 15)
  863. dspcntr |= DISPPLANE_15_16BPP;
  864. else
  865. dspcntr |= DISPPLANE_16BPP;
  866. break;
  867. case 24:
  868. case 32:
  869. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  870. break;
  871. default:
  872. DRM_ERROR("Unknown color depth\n");
  873. i915_gem_object_unpin(obj);
  874. mutex_unlock(&dev->struct_mutex);
  875. return -EINVAL;
  876. }
  877. if (IS_I965G(dev)) {
  878. if (obj_priv->tiling_mode != I915_TILING_NONE)
  879. dspcntr |= DISPPLANE_TILED;
  880. else
  881. dspcntr &= ~DISPPLANE_TILED;
  882. }
  883. I915_WRITE(dspcntr_reg, dspcntr);
  884. Start = obj_priv->gtt_offset;
  885. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  886. DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
  887. I915_WRITE(dspstride, crtc->fb->pitch);
  888. if (IS_I965G(dev)) {
  889. I915_WRITE(dspbase, Offset);
  890. I915_READ(dspbase);
  891. I915_WRITE(dspsurf, Start);
  892. I915_READ(dspsurf);
  893. I915_WRITE(dsptileoff, (y << 16) | x);
  894. } else {
  895. I915_WRITE(dspbase, Start + Offset);
  896. I915_READ(dspbase);
  897. }
  898. intel_wait_for_vblank(dev);
  899. if (old_fb) {
  900. intel_fb = to_intel_framebuffer(old_fb);
  901. i915_gem_object_unpin(intel_fb->obj);
  902. }
  903. mutex_unlock(&dev->struct_mutex);
  904. if (!dev->primary->master)
  905. return 0;
  906. master_priv = dev->primary->master->driver_priv;
  907. if (!master_priv->sarea_priv)
  908. return 0;
  909. if (pipe) {
  910. master_priv->sarea_priv->pipeB_x = x;
  911. master_priv->sarea_priv->pipeB_y = y;
  912. } else {
  913. master_priv->sarea_priv->pipeA_x = x;
  914. master_priv->sarea_priv->pipeA_y = y;
  915. }
  916. return 0;
  917. }
  918. static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
  919. {
  920. struct drm_device *dev = crtc->dev;
  921. struct drm_i915_private *dev_priv = dev->dev_private;
  922. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  923. int pipe = intel_crtc->pipe;
  924. int plane = intel_crtc->plane;
  925. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  926. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  927. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  928. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  929. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  930. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  931. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  932. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  933. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  934. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  935. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  936. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  937. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  938. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  939. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  940. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  941. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  942. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  943. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  944. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  945. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  946. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  947. u32 temp;
  948. int tries = 5, j;
  949. /* XXX: When our outputs are all unaware of DPMS modes other than off
  950. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  951. */
  952. switch (mode) {
  953. case DRM_MODE_DPMS_ON:
  954. case DRM_MODE_DPMS_STANDBY:
  955. case DRM_MODE_DPMS_SUSPEND:
  956. DRM_DEBUG("crtc %d dpms on\n", pipe);
  957. /* enable PCH DPLL */
  958. temp = I915_READ(pch_dpll_reg);
  959. if ((temp & DPLL_VCO_ENABLE) == 0) {
  960. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  961. I915_READ(pch_dpll_reg);
  962. }
  963. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  964. temp = I915_READ(fdi_rx_reg);
  965. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
  966. FDI_SEL_PCDCLK |
  967. FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
  968. I915_READ(fdi_rx_reg);
  969. udelay(200);
  970. /* Enable CPU FDI TX PLL, always on for IGDNG */
  971. temp = I915_READ(fdi_tx_reg);
  972. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  973. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  974. I915_READ(fdi_tx_reg);
  975. udelay(100);
  976. }
  977. /* Enable CPU pipe */
  978. temp = I915_READ(pipeconf_reg);
  979. if ((temp & PIPEACONF_ENABLE) == 0) {
  980. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  981. I915_READ(pipeconf_reg);
  982. udelay(100);
  983. }
  984. /* configure and enable CPU plane */
  985. temp = I915_READ(dspcntr_reg);
  986. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  987. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  988. /* Flush the plane changes */
  989. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  990. }
  991. /* enable CPU FDI TX and PCH FDI RX */
  992. temp = I915_READ(fdi_tx_reg);
  993. temp |= FDI_TX_ENABLE;
  994. temp |= FDI_DP_PORT_WIDTH_X4; /* default */
  995. temp &= ~FDI_LINK_TRAIN_NONE;
  996. temp |= FDI_LINK_TRAIN_PATTERN_1;
  997. I915_WRITE(fdi_tx_reg, temp);
  998. I915_READ(fdi_tx_reg);
  999. temp = I915_READ(fdi_rx_reg);
  1000. temp &= ~FDI_LINK_TRAIN_NONE;
  1001. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1002. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1003. I915_READ(fdi_rx_reg);
  1004. udelay(150);
  1005. /* Train FDI. */
  1006. /* umask FDI RX Interrupt symbol_lock and bit_lock bit
  1007. for train result */
  1008. temp = I915_READ(fdi_rx_imr_reg);
  1009. temp &= ~FDI_RX_SYMBOL_LOCK;
  1010. temp &= ~FDI_RX_BIT_LOCK;
  1011. I915_WRITE(fdi_rx_imr_reg, temp);
  1012. I915_READ(fdi_rx_imr_reg);
  1013. udelay(150);
  1014. temp = I915_READ(fdi_rx_iir_reg);
  1015. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1016. if ((temp & FDI_RX_BIT_LOCK) == 0) {
  1017. for (j = 0; j < tries; j++) {
  1018. temp = I915_READ(fdi_rx_iir_reg);
  1019. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1020. if (temp & FDI_RX_BIT_LOCK)
  1021. break;
  1022. udelay(200);
  1023. }
  1024. if (j != tries)
  1025. I915_WRITE(fdi_rx_iir_reg,
  1026. temp | FDI_RX_BIT_LOCK);
  1027. else
  1028. DRM_DEBUG("train 1 fail\n");
  1029. } else {
  1030. I915_WRITE(fdi_rx_iir_reg,
  1031. temp | FDI_RX_BIT_LOCK);
  1032. DRM_DEBUG("train 1 ok 2!\n");
  1033. }
  1034. temp = I915_READ(fdi_tx_reg);
  1035. temp &= ~FDI_LINK_TRAIN_NONE;
  1036. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1037. I915_WRITE(fdi_tx_reg, temp);
  1038. temp = I915_READ(fdi_rx_reg);
  1039. temp &= ~FDI_LINK_TRAIN_NONE;
  1040. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1041. I915_WRITE(fdi_rx_reg, temp);
  1042. udelay(150);
  1043. temp = I915_READ(fdi_rx_iir_reg);
  1044. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1045. if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
  1046. for (j = 0; j < tries; j++) {
  1047. temp = I915_READ(fdi_rx_iir_reg);
  1048. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  1049. if (temp & FDI_RX_SYMBOL_LOCK)
  1050. break;
  1051. udelay(200);
  1052. }
  1053. if (j != tries) {
  1054. I915_WRITE(fdi_rx_iir_reg,
  1055. temp | FDI_RX_SYMBOL_LOCK);
  1056. DRM_DEBUG("train 2 ok 1!\n");
  1057. } else
  1058. DRM_DEBUG("train 2 fail\n");
  1059. } else {
  1060. I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
  1061. DRM_DEBUG("train 2 ok 2!\n");
  1062. }
  1063. DRM_DEBUG("train done\n");
  1064. /* set transcoder timing */
  1065. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1066. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1067. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1068. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1069. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1070. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1071. /* enable PCH transcoder */
  1072. temp = I915_READ(transconf_reg);
  1073. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1074. I915_READ(transconf_reg);
  1075. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1076. ;
  1077. /* enable normal */
  1078. temp = I915_READ(fdi_tx_reg);
  1079. temp &= ~FDI_LINK_TRAIN_NONE;
  1080. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1081. FDI_TX_ENHANCE_FRAME_ENABLE);
  1082. I915_READ(fdi_tx_reg);
  1083. temp = I915_READ(fdi_rx_reg);
  1084. temp &= ~FDI_LINK_TRAIN_NONE;
  1085. I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
  1086. FDI_RX_ENHANCE_FRAME_ENABLE);
  1087. I915_READ(fdi_rx_reg);
  1088. /* wait one idle pattern time */
  1089. udelay(100);
  1090. intel_crtc_load_lut(crtc);
  1091. break;
  1092. case DRM_MODE_DPMS_OFF:
  1093. DRM_DEBUG("crtc %d dpms off\n", pipe);
  1094. /* Disable the VGA plane that we never use */
  1095. I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
  1096. /* Disable display plane */
  1097. temp = I915_READ(dspcntr_reg);
  1098. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1099. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1100. /* Flush the plane changes */
  1101. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1102. I915_READ(dspbase_reg);
  1103. }
  1104. /* disable cpu pipe, disable after all planes disabled */
  1105. temp = I915_READ(pipeconf_reg);
  1106. if ((temp & PIPEACONF_ENABLE) != 0) {
  1107. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1108. I915_READ(pipeconf_reg);
  1109. /* wait for cpu pipe off, pipe state */
  1110. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
  1111. ;
  1112. } else
  1113. DRM_DEBUG("crtc %d is disabled\n", pipe);
  1114. /* IGDNG-A : disable cpu panel fitter ? */
  1115. temp = I915_READ(pf_ctl_reg);
  1116. if ((temp & PF_ENABLE) != 0) {
  1117. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1118. I915_READ(pf_ctl_reg);
  1119. }
  1120. /* disable CPU FDI tx and PCH FDI rx */
  1121. temp = I915_READ(fdi_tx_reg);
  1122. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1123. I915_READ(fdi_tx_reg);
  1124. temp = I915_READ(fdi_rx_reg);
  1125. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1126. I915_READ(fdi_rx_reg);
  1127. /* still set train pattern 1 */
  1128. temp = I915_READ(fdi_tx_reg);
  1129. temp &= ~FDI_LINK_TRAIN_NONE;
  1130. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1131. I915_WRITE(fdi_tx_reg, temp);
  1132. temp = I915_READ(fdi_rx_reg);
  1133. temp &= ~FDI_LINK_TRAIN_NONE;
  1134. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1135. I915_WRITE(fdi_rx_reg, temp);
  1136. /* disable PCH transcoder */
  1137. temp = I915_READ(transconf_reg);
  1138. if ((temp & TRANS_ENABLE) != 0) {
  1139. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1140. I915_READ(transconf_reg);
  1141. /* wait for PCH transcoder off, transcoder state */
  1142. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
  1143. ;
  1144. }
  1145. /* disable PCH DPLL */
  1146. temp = I915_READ(pch_dpll_reg);
  1147. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1148. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1149. I915_READ(pch_dpll_reg);
  1150. }
  1151. temp = I915_READ(fdi_rx_reg);
  1152. if ((temp & FDI_RX_PLL_ENABLE) != 0) {
  1153. temp &= ~FDI_SEL_PCDCLK;
  1154. temp &= ~FDI_RX_PLL_ENABLE;
  1155. I915_WRITE(fdi_rx_reg, temp);
  1156. I915_READ(fdi_rx_reg);
  1157. }
  1158. /* Wait for the clocks to turn off. */
  1159. udelay(150);
  1160. break;
  1161. }
  1162. }
  1163. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  1164. {
  1165. struct drm_device *dev = crtc->dev;
  1166. struct drm_i915_private *dev_priv = dev->dev_private;
  1167. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1168. int pipe = intel_crtc->pipe;
  1169. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1170. int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  1171. int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
  1172. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1173. u32 temp;
  1174. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1175. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1176. */
  1177. switch (mode) {
  1178. case DRM_MODE_DPMS_ON:
  1179. case DRM_MODE_DPMS_STANDBY:
  1180. case DRM_MODE_DPMS_SUSPEND:
  1181. /* Enable the DPLL */
  1182. temp = I915_READ(dpll_reg);
  1183. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1184. I915_WRITE(dpll_reg, temp);
  1185. I915_READ(dpll_reg);
  1186. /* Wait for the clocks to stabilize. */
  1187. udelay(150);
  1188. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1189. I915_READ(dpll_reg);
  1190. /* Wait for the clocks to stabilize. */
  1191. udelay(150);
  1192. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1193. I915_READ(dpll_reg);
  1194. /* Wait for the clocks to stabilize. */
  1195. udelay(150);
  1196. }
  1197. /* Enable the pipe */
  1198. temp = I915_READ(pipeconf_reg);
  1199. if ((temp & PIPEACONF_ENABLE) == 0)
  1200. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1201. /* Enable the plane */
  1202. temp = I915_READ(dspcntr_reg);
  1203. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1204. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1205. /* Flush the plane changes */
  1206. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1207. }
  1208. intel_crtc_load_lut(crtc);
  1209. /* Give the overlay scaler a chance to enable if it's on this pipe */
  1210. //intel_crtc_dpms_video(crtc, true); TODO
  1211. intel_update_watermarks(dev);
  1212. break;
  1213. case DRM_MODE_DPMS_OFF:
  1214. intel_update_watermarks(dev);
  1215. /* Give the overlay scaler a chance to disable if it's on this pipe */
  1216. //intel_crtc_dpms_video(crtc, FALSE); TODO
  1217. /* Disable the VGA plane that we never use */
  1218. I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
  1219. /* Disable display plane */
  1220. temp = I915_READ(dspcntr_reg);
  1221. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1222. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1223. /* Flush the plane changes */
  1224. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1225. I915_READ(dspbase_reg);
  1226. }
  1227. if (!IS_I9XX(dev)) {
  1228. /* Wait for vblank for the disable to take effect */
  1229. intel_wait_for_vblank(dev);
  1230. }
  1231. /* Next, disable display pipes */
  1232. temp = I915_READ(pipeconf_reg);
  1233. if ((temp & PIPEACONF_ENABLE) != 0) {
  1234. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1235. I915_READ(pipeconf_reg);
  1236. }
  1237. /* Wait for vblank for the disable to take effect. */
  1238. intel_wait_for_vblank(dev);
  1239. temp = I915_READ(dpll_reg);
  1240. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1241. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1242. I915_READ(dpll_reg);
  1243. }
  1244. /* Wait for the clocks to turn off. */
  1245. udelay(150);
  1246. break;
  1247. }
  1248. }
  1249. /**
  1250. * Sets the power management mode of the pipe and plane.
  1251. *
  1252. * This code should probably grow support for turning the cursor off and back
  1253. * on appropriately at the same time as we're turning the pipe off/on.
  1254. */
  1255. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  1256. {
  1257. struct drm_device *dev = crtc->dev;
  1258. struct drm_i915_master_private *master_priv;
  1259. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1260. int pipe = intel_crtc->pipe;
  1261. bool enabled;
  1262. if (IS_IGDNG(dev))
  1263. igdng_crtc_dpms(crtc, mode);
  1264. else
  1265. i9xx_crtc_dpms(crtc, mode);
  1266. if (!dev->primary->master)
  1267. return;
  1268. master_priv = dev->primary->master->driver_priv;
  1269. if (!master_priv->sarea_priv)
  1270. return;
  1271. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  1272. switch (pipe) {
  1273. case 0:
  1274. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  1275. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  1276. break;
  1277. case 1:
  1278. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  1279. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  1280. break;
  1281. default:
  1282. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  1283. break;
  1284. }
  1285. intel_crtc->dpms_mode = mode;
  1286. }
  1287. static void intel_crtc_prepare (struct drm_crtc *crtc)
  1288. {
  1289. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1290. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  1291. }
  1292. static void intel_crtc_commit (struct drm_crtc *crtc)
  1293. {
  1294. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1295. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1296. }
  1297. void intel_encoder_prepare (struct drm_encoder *encoder)
  1298. {
  1299. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1300. /* lvds has its own version of prepare see intel_lvds_prepare */
  1301. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  1302. }
  1303. void intel_encoder_commit (struct drm_encoder *encoder)
  1304. {
  1305. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1306. /* lvds has its own version of commit see intel_lvds_commit */
  1307. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  1308. }
  1309. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  1310. struct drm_display_mode *mode,
  1311. struct drm_display_mode *adjusted_mode)
  1312. {
  1313. struct drm_device *dev = crtc->dev;
  1314. if (IS_IGDNG(dev)) {
  1315. /* FDI link clock is fixed at 2.7G */
  1316. if (mode->clock * 3 > 27000 * 4)
  1317. return MODE_CLOCK_HIGH;
  1318. }
  1319. return true;
  1320. }
  1321. /** Returns the core display clock speed for i830 - i945 */
  1322. static int intel_get_core_clock_speed(struct drm_device *dev)
  1323. {
  1324. /* Core clock values taken from the published datasheets.
  1325. * The 830 may go up to 166 Mhz, which we should check.
  1326. */
  1327. if (IS_I945G(dev))
  1328. return 400000;
  1329. else if (IS_I915G(dev))
  1330. return 333000;
  1331. else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
  1332. return 200000;
  1333. else if (IS_I915GM(dev)) {
  1334. u16 gcfgc = 0;
  1335. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  1336. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  1337. return 133000;
  1338. else {
  1339. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  1340. case GC_DISPLAY_CLOCK_333_MHZ:
  1341. return 333000;
  1342. default:
  1343. case GC_DISPLAY_CLOCK_190_200_MHZ:
  1344. return 190000;
  1345. }
  1346. }
  1347. } else if (IS_I865G(dev))
  1348. return 266000;
  1349. else if (IS_I855(dev)) {
  1350. u16 hpllcc = 0;
  1351. /* Assume that the hardware is in the high speed state. This
  1352. * should be the default.
  1353. */
  1354. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  1355. case GC_CLOCK_133_200:
  1356. case GC_CLOCK_100_200:
  1357. return 200000;
  1358. case GC_CLOCK_166_250:
  1359. return 250000;
  1360. case GC_CLOCK_100_133:
  1361. return 133000;
  1362. }
  1363. } else /* 852, 830 */
  1364. return 133000;
  1365. return 0; /* Silence gcc warning */
  1366. }
  1367. /**
  1368. * Return the pipe currently connected to the panel fitter,
  1369. * or -1 if the panel fitter is not present or not in use
  1370. */
  1371. static int intel_panel_fitter_pipe (struct drm_device *dev)
  1372. {
  1373. struct drm_i915_private *dev_priv = dev->dev_private;
  1374. u32 pfit_control;
  1375. /* i830 doesn't have a panel fitter */
  1376. if (IS_I830(dev))
  1377. return -1;
  1378. pfit_control = I915_READ(PFIT_CONTROL);
  1379. /* See if the panel fitter is in use */
  1380. if ((pfit_control & PFIT_ENABLE) == 0)
  1381. return -1;
  1382. /* 965 can place panel fitter on either pipe */
  1383. if (IS_I965G(dev))
  1384. return (pfit_control >> 29) & 0x3;
  1385. /* older chips can only use pipe 1 */
  1386. return 1;
  1387. }
  1388. struct fdi_m_n {
  1389. u32 tu;
  1390. u32 gmch_m;
  1391. u32 gmch_n;
  1392. u32 link_m;
  1393. u32 link_n;
  1394. };
  1395. static void
  1396. fdi_reduce_ratio(u32 *num, u32 *den)
  1397. {
  1398. while (*num > 0xffffff || *den > 0xffffff) {
  1399. *num >>= 1;
  1400. *den >>= 1;
  1401. }
  1402. }
  1403. #define DATA_N 0x800000
  1404. #define LINK_N 0x80000
  1405. static void
  1406. igdng_compute_m_n(int bytes_per_pixel, int nlanes,
  1407. int pixel_clock, int link_clock,
  1408. struct fdi_m_n *m_n)
  1409. {
  1410. u64 temp;
  1411. m_n->tu = 64; /* default size */
  1412. temp = (u64) DATA_N * pixel_clock;
  1413. temp = div_u64(temp, link_clock);
  1414. m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
  1415. m_n->gmch_n = DATA_N;
  1416. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  1417. temp = (u64) LINK_N * pixel_clock;
  1418. m_n->link_m = div_u64(temp, link_clock);
  1419. m_n->link_n = LINK_N;
  1420. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  1421. }
  1422. struct intel_watermark_params {
  1423. unsigned long fifo_size;
  1424. unsigned long max_wm;
  1425. unsigned long default_wm;
  1426. unsigned long guard_size;
  1427. unsigned long cacheline_size;
  1428. };
  1429. /* IGD has different values for various configs */
  1430. static struct intel_watermark_params igd_display_wm = {
  1431. IGD_DISPLAY_FIFO,
  1432. IGD_MAX_WM,
  1433. IGD_DFT_WM,
  1434. IGD_GUARD_WM,
  1435. IGD_FIFO_LINE_SIZE
  1436. };
  1437. static struct intel_watermark_params igd_display_hplloff_wm = {
  1438. IGD_DISPLAY_FIFO,
  1439. IGD_MAX_WM,
  1440. IGD_DFT_HPLLOFF_WM,
  1441. IGD_GUARD_WM,
  1442. IGD_FIFO_LINE_SIZE
  1443. };
  1444. static struct intel_watermark_params igd_cursor_wm = {
  1445. IGD_CURSOR_FIFO,
  1446. IGD_CURSOR_MAX_WM,
  1447. IGD_CURSOR_DFT_WM,
  1448. IGD_CURSOR_GUARD_WM,
  1449. IGD_FIFO_LINE_SIZE,
  1450. };
  1451. static struct intel_watermark_params igd_cursor_hplloff_wm = {
  1452. IGD_CURSOR_FIFO,
  1453. IGD_CURSOR_MAX_WM,
  1454. IGD_CURSOR_DFT_WM,
  1455. IGD_CURSOR_GUARD_WM,
  1456. IGD_FIFO_LINE_SIZE
  1457. };
  1458. static struct intel_watermark_params i945_wm_info = {
  1459. I945_FIFO_SIZE,
  1460. I915_MAX_WM,
  1461. 1,
  1462. 2,
  1463. I915_FIFO_LINE_SIZE
  1464. };
  1465. static struct intel_watermark_params i915_wm_info = {
  1466. I915_FIFO_SIZE,
  1467. I915_MAX_WM,
  1468. 1,
  1469. 2,
  1470. I915_FIFO_LINE_SIZE
  1471. };
  1472. static struct intel_watermark_params i855_wm_info = {
  1473. I855GM_FIFO_SIZE,
  1474. I915_MAX_WM,
  1475. 1,
  1476. 2,
  1477. I830_FIFO_LINE_SIZE
  1478. };
  1479. static struct intel_watermark_params i830_wm_info = {
  1480. I830_FIFO_SIZE,
  1481. I915_MAX_WM,
  1482. 1,
  1483. 2,
  1484. I830_FIFO_LINE_SIZE
  1485. };
  1486. /**
  1487. * intel_calculate_wm - calculate watermark level
  1488. * @clock_in_khz: pixel clock
  1489. * @wm: chip FIFO params
  1490. * @pixel_size: display pixel size
  1491. * @latency_ns: memory latency for the platform
  1492. *
  1493. * Calculate the watermark level (the level at which the display plane will
  1494. * start fetching from memory again). Each chip has a different display
  1495. * FIFO size and allocation, so the caller needs to figure that out and pass
  1496. * in the correct intel_watermark_params structure.
  1497. *
  1498. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  1499. * on the pixel size. When it reaches the watermark level, it'll start
  1500. * fetching FIFO line sized based chunks from memory until the FIFO fills
  1501. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  1502. * will occur, and a display engine hang could result.
  1503. */
  1504. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  1505. struct intel_watermark_params *wm,
  1506. int pixel_size,
  1507. unsigned long latency_ns)
  1508. {
  1509. unsigned long entries_required, wm_size;
  1510. entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
  1511. entries_required /= wm->cacheline_size;
  1512. DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
  1513. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  1514. DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
  1515. if (wm_size > wm->max_wm)
  1516. wm_size = wm->max_wm;
  1517. if (wm_size == 0)
  1518. wm_size = wm->default_wm;
  1519. return wm_size;
  1520. }
  1521. struct cxsr_latency {
  1522. int is_desktop;
  1523. unsigned long fsb_freq;
  1524. unsigned long mem_freq;
  1525. unsigned long display_sr;
  1526. unsigned long display_hpll_disable;
  1527. unsigned long cursor_sr;
  1528. unsigned long cursor_hpll_disable;
  1529. };
  1530. static struct cxsr_latency cxsr_latency_table[] = {
  1531. {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  1532. {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  1533. {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  1534. {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  1535. {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  1536. {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  1537. {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  1538. {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  1539. {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  1540. {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  1541. {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  1542. {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  1543. {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  1544. {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  1545. {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  1546. {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  1547. {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  1548. {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  1549. };
  1550. static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
  1551. int mem)
  1552. {
  1553. int i;
  1554. struct cxsr_latency *latency;
  1555. if (fsb == 0 || mem == 0)
  1556. return NULL;
  1557. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  1558. latency = &cxsr_latency_table[i];
  1559. if (is_desktop == latency->is_desktop &&
  1560. fsb == latency->fsb_freq && mem == latency->mem_freq)
  1561. break;
  1562. }
  1563. if (i >= ARRAY_SIZE(cxsr_latency_table)) {
  1564. DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
  1565. return NULL;
  1566. }
  1567. return latency;
  1568. }
  1569. static void igd_disable_cxsr(struct drm_device *dev)
  1570. {
  1571. struct drm_i915_private *dev_priv = dev->dev_private;
  1572. u32 reg;
  1573. /* deactivate cxsr */
  1574. reg = I915_READ(DSPFW3);
  1575. reg &= ~(IGD_SELF_REFRESH_EN);
  1576. I915_WRITE(DSPFW3, reg);
  1577. DRM_INFO("Big FIFO is disabled\n");
  1578. }
  1579. static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
  1580. int pixel_size)
  1581. {
  1582. struct drm_i915_private *dev_priv = dev->dev_private;
  1583. u32 reg;
  1584. unsigned long wm;
  1585. struct cxsr_latency *latency;
  1586. latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
  1587. dev_priv->mem_freq);
  1588. if (!latency) {
  1589. DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
  1590. igd_disable_cxsr(dev);
  1591. return;
  1592. }
  1593. /* Display SR */
  1594. wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
  1595. latency->display_sr);
  1596. reg = I915_READ(DSPFW1);
  1597. reg &= 0x7fffff;
  1598. reg |= wm << 23;
  1599. I915_WRITE(DSPFW1, reg);
  1600. DRM_DEBUG("DSPFW1 register is %x\n", reg);
  1601. /* cursor SR */
  1602. wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
  1603. latency->cursor_sr);
  1604. reg = I915_READ(DSPFW3);
  1605. reg &= ~(0x3f << 24);
  1606. reg |= (wm & 0x3f) << 24;
  1607. I915_WRITE(DSPFW3, reg);
  1608. /* Display HPLL off SR */
  1609. wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
  1610. latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
  1611. reg = I915_READ(DSPFW3);
  1612. reg &= 0xfffffe00;
  1613. reg |= wm & 0x1ff;
  1614. I915_WRITE(DSPFW3, reg);
  1615. /* cursor HPLL off SR */
  1616. wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
  1617. latency->cursor_hpll_disable);
  1618. reg = I915_READ(DSPFW3);
  1619. reg &= ~(0x3f << 16);
  1620. reg |= (wm & 0x3f) << 16;
  1621. I915_WRITE(DSPFW3, reg);
  1622. DRM_DEBUG("DSPFW3 register is %x\n", reg);
  1623. /* activate cxsr */
  1624. reg = I915_READ(DSPFW3);
  1625. reg |= IGD_SELF_REFRESH_EN;
  1626. I915_WRITE(DSPFW3, reg);
  1627. DRM_INFO("Big FIFO is enabled\n");
  1628. return;
  1629. }
  1630. const static int latency_ns = 3000; /* default for non-igd platforms */
  1631. static int intel_get_fifo_size(struct drm_device *dev, int plane)
  1632. {
  1633. struct drm_i915_private *dev_priv = dev->dev_private;
  1634. uint32_t dsparb = I915_READ(DSPARB);
  1635. int size;
  1636. if (IS_I9XX(dev)) {
  1637. if (plane == 0)
  1638. size = dsparb & 0x7f;
  1639. else
  1640. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
  1641. (dsparb & 0x7f);
  1642. } else if (IS_I85X(dev)) {
  1643. if (plane == 0)
  1644. size = dsparb & 0x1ff;
  1645. else
  1646. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
  1647. (dsparb & 0x1ff);
  1648. size >>= 1; /* Convert to cachelines */
  1649. } else {
  1650. size = dsparb & 0x7f;
  1651. size >>= 1; /* Convert to cachelines */
  1652. }
  1653. DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
  1654. size);
  1655. return size;
  1656. }
  1657. static void i965_update_wm(struct drm_device *dev)
  1658. {
  1659. struct drm_i915_private *dev_priv = dev->dev_private;
  1660. DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
  1661. /* 965 has limitations... */
  1662. I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
  1663. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  1664. }
  1665. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  1666. int planeb_clock, int sr_hdisplay, int pixel_size)
  1667. {
  1668. struct drm_i915_private *dev_priv = dev->dev_private;
  1669. uint32_t fwater_lo;
  1670. uint32_t fwater_hi;
  1671. int total_size, cacheline_size, cwm, srwm = 1;
  1672. int planea_wm, planeb_wm;
  1673. struct intel_watermark_params planea_params, planeb_params;
  1674. unsigned long line_time_us;
  1675. int sr_clock, sr_entries = 0;
  1676. /* Create copies of the base settings for each pipe */
  1677. if (IS_I965GM(dev) || IS_I945GM(dev))
  1678. planea_params = planeb_params = i945_wm_info;
  1679. else if (IS_I9XX(dev))
  1680. planea_params = planeb_params = i915_wm_info;
  1681. else
  1682. planea_params = planeb_params = i855_wm_info;
  1683. /* Grab a couple of global values before we overwrite them */
  1684. total_size = planea_params.fifo_size;
  1685. cacheline_size = planea_params.cacheline_size;
  1686. /* Update per-plane FIFO sizes */
  1687. planea_params.fifo_size = intel_get_fifo_size(dev, 0);
  1688. planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
  1689. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  1690. pixel_size, latency_ns);
  1691. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  1692. pixel_size, latency_ns);
  1693. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  1694. /*
  1695. * Overlay gets an aggressive default since video jitter is bad.
  1696. */
  1697. cwm = 2;
  1698. /* Calc sr entries for one plane configs */
  1699. if (!planea_clock || !planeb_clock) {
  1700. /* self-refresh has much higher latency */
  1701. const static int sr_latency_ns = 6000;
  1702. sr_clock = planea_clock ? planea_clock : planeb_clock;
  1703. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  1704. /* Use ns/us then divide to preserve precision */
  1705. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  1706. pixel_size * sr_hdisplay) / 1000;
  1707. sr_entries = roundup(sr_entries / cacheline_size, 1);
  1708. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  1709. srwm = total_size - sr_entries;
  1710. if (srwm < 0)
  1711. srwm = 1;
  1712. }
  1713. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  1714. planea_wm, planeb_wm, cwm, srwm);
  1715. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  1716. fwater_hi = (cwm & 0x1f);
  1717. /* Set request length to 8 cachelines per fetch */
  1718. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  1719. fwater_hi = fwater_hi | (1 << 8);
  1720. I915_WRITE(FW_BLC, fwater_lo);
  1721. I915_WRITE(FW_BLC2, fwater_hi);
  1722. if (IS_I9XX(dev))
  1723. I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
  1724. }
  1725. static void i830_update_wm(struct drm_device *dev, int planea_clock,
  1726. int pixel_size)
  1727. {
  1728. struct drm_i915_private *dev_priv = dev->dev_private;
  1729. uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
  1730. int planea_wm;
  1731. i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
  1732. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  1733. pixel_size, latency_ns);
  1734. fwater_lo = fwater_lo | planea_wm;
  1735. I915_WRITE(FW_BLC, fwater_lo);
  1736. }
  1737. /**
  1738. * intel_update_watermarks - update FIFO watermark values based on current modes
  1739. *
  1740. * Calculate watermark values for the various WM regs based on current mode
  1741. * and plane configuration.
  1742. *
  1743. * There are several cases to deal with here:
  1744. * - normal (i.e. non-self-refresh)
  1745. * - self-refresh (SR) mode
  1746. * - lines are large relative to FIFO size (buffer can hold up to 2)
  1747. * - lines are small relative to FIFO size (buffer can hold more than 2
  1748. * lines), so need to account for TLB latency
  1749. *
  1750. * The normal calculation is:
  1751. * watermark = dotclock * bytes per pixel * latency
  1752. * where latency is platform & configuration dependent (we assume pessimal
  1753. * values here).
  1754. *
  1755. * The SR calculation is:
  1756. * watermark = (trunc(latency/line time)+1) * surface width *
  1757. * bytes per pixel
  1758. * where
  1759. * line time = htotal / dotclock
  1760. * and latency is assumed to be high, as above.
  1761. *
  1762. * The final value programmed to the register should always be rounded up,
  1763. * and include an extra 2 entries to account for clock crossings.
  1764. *
  1765. * We don't use the sprite, so we can ignore that. And on Crestline we have
  1766. * to set the non-SR watermarks to 8.
  1767. */
  1768. static void intel_update_watermarks(struct drm_device *dev)
  1769. {
  1770. struct drm_crtc *crtc;
  1771. struct intel_crtc *intel_crtc;
  1772. int sr_hdisplay = 0;
  1773. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  1774. int enabled = 0, pixel_size = 0;
  1775. if (DSPARB_HWCONTROL(dev))
  1776. return;
  1777. /* Get the clock config from both planes */
  1778. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1779. intel_crtc = to_intel_crtc(crtc);
  1780. if (crtc->enabled) {
  1781. enabled++;
  1782. if (intel_crtc->plane == 0) {
  1783. DRM_DEBUG("plane A (pipe %d) clock: %d\n",
  1784. intel_crtc->pipe, crtc->mode.clock);
  1785. planea_clock = crtc->mode.clock;
  1786. } else {
  1787. DRM_DEBUG("plane B (pipe %d) clock: %d\n",
  1788. intel_crtc->pipe, crtc->mode.clock);
  1789. planeb_clock = crtc->mode.clock;
  1790. }
  1791. sr_hdisplay = crtc->mode.hdisplay;
  1792. sr_clock = crtc->mode.clock;
  1793. if (crtc->fb)
  1794. pixel_size = crtc->fb->bits_per_pixel / 8;
  1795. else
  1796. pixel_size = 4; /* by default */
  1797. }
  1798. }
  1799. if (enabled <= 0)
  1800. return;
  1801. /* Single plane configs can enable self refresh */
  1802. if (enabled == 1 && IS_IGD(dev))
  1803. igd_enable_cxsr(dev, sr_clock, pixel_size);
  1804. else if (IS_IGD(dev))
  1805. igd_disable_cxsr(dev);
  1806. if (IS_I965G(dev))
  1807. i965_update_wm(dev);
  1808. else if (IS_I9XX(dev) || IS_MOBILE(dev))
  1809. i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
  1810. pixel_size);
  1811. else
  1812. i830_update_wm(dev, planea_clock, pixel_size);
  1813. }
  1814. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  1815. struct drm_display_mode *mode,
  1816. struct drm_display_mode *adjusted_mode,
  1817. int x, int y,
  1818. struct drm_framebuffer *old_fb)
  1819. {
  1820. struct drm_device *dev = crtc->dev;
  1821. struct drm_i915_private *dev_priv = dev->dev_private;
  1822. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1823. int pipe = intel_crtc->pipe;
  1824. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  1825. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1826. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  1827. int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  1828. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1829. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1830. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1831. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1832. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1833. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1834. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1835. int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
  1836. int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
  1837. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  1838. int refclk, num_outputs = 0;
  1839. intel_clock_t clock;
  1840. u32 dpll = 0, fp = 0, dspcntr, pipeconf;
  1841. bool ok, is_sdvo = false, is_dvo = false;
  1842. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  1843. struct drm_mode_config *mode_config = &dev->mode_config;
  1844. struct drm_connector *connector;
  1845. const intel_limit_t *limit;
  1846. int ret;
  1847. struct fdi_m_n m_n = {0};
  1848. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  1849. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  1850. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  1851. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  1852. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  1853. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1854. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1855. int lvds_reg = LVDS;
  1856. u32 temp;
  1857. int sdvo_pixel_multiply;
  1858. drm_vblank_pre_modeset(dev, pipe);
  1859. list_for_each_entry(connector, &mode_config->connector_list, head) {
  1860. struct intel_output *intel_output = to_intel_output(connector);
  1861. if (!connector->encoder || connector->encoder->crtc != crtc)
  1862. continue;
  1863. switch (intel_output->type) {
  1864. case INTEL_OUTPUT_LVDS:
  1865. is_lvds = true;
  1866. break;
  1867. case INTEL_OUTPUT_SDVO:
  1868. case INTEL_OUTPUT_HDMI:
  1869. is_sdvo = true;
  1870. if (intel_output->needs_tv_clock)
  1871. is_tv = true;
  1872. break;
  1873. case INTEL_OUTPUT_DVO:
  1874. is_dvo = true;
  1875. break;
  1876. case INTEL_OUTPUT_TVOUT:
  1877. is_tv = true;
  1878. break;
  1879. case INTEL_OUTPUT_ANALOG:
  1880. is_crt = true;
  1881. break;
  1882. case INTEL_OUTPUT_DISPLAYPORT:
  1883. is_dp = true;
  1884. break;
  1885. }
  1886. num_outputs++;
  1887. }
  1888. if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
  1889. refclk = dev_priv->lvds_ssc_freq * 1000;
  1890. DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
  1891. } else if (IS_I9XX(dev)) {
  1892. refclk = 96000;
  1893. if (IS_IGDNG(dev))
  1894. refclk = 120000; /* 120Mhz refclk */
  1895. } else {
  1896. refclk = 48000;
  1897. }
  1898. /*
  1899. * Returns a set of divisors for the desired target clock with the given
  1900. * refclk, or FALSE. The returned values represent the clock equation:
  1901. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  1902. */
  1903. limit = intel_limit(crtc);
  1904. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  1905. if (!ok) {
  1906. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  1907. drm_vblank_post_modeset(dev, pipe);
  1908. return -EINVAL;
  1909. }
  1910. /* SDVO TV has fixed PLL values depend on its clock range,
  1911. this mirrors vbios setting. */
  1912. if (is_sdvo && is_tv) {
  1913. if (adjusted_mode->clock >= 100000
  1914. && adjusted_mode->clock < 140500) {
  1915. clock.p1 = 2;
  1916. clock.p2 = 10;
  1917. clock.n = 3;
  1918. clock.m1 = 16;
  1919. clock.m2 = 8;
  1920. } else if (adjusted_mode->clock >= 140500
  1921. && adjusted_mode->clock <= 200000) {
  1922. clock.p1 = 1;
  1923. clock.p2 = 10;
  1924. clock.n = 6;
  1925. clock.m1 = 12;
  1926. clock.m2 = 8;
  1927. }
  1928. }
  1929. /* FDI link */
  1930. if (IS_IGDNG(dev))
  1931. igdng_compute_m_n(3, 4, /* lane num 4 */
  1932. adjusted_mode->clock,
  1933. 270000, /* lane clock */
  1934. &m_n);
  1935. if (IS_IGD(dev))
  1936. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  1937. else
  1938. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  1939. if (!IS_IGDNG(dev))
  1940. dpll = DPLL_VGA_MODE_DIS;
  1941. if (IS_I9XX(dev)) {
  1942. if (is_lvds)
  1943. dpll |= DPLLB_MODE_LVDS;
  1944. else
  1945. dpll |= DPLLB_MODE_DAC_SERIAL;
  1946. if (is_sdvo) {
  1947. dpll |= DPLL_DVO_HIGH_SPEED;
  1948. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  1949. if (IS_I945G(dev) || IS_I945GM(dev))
  1950. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  1951. else if (IS_IGDNG(dev))
  1952. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  1953. }
  1954. if (is_dp)
  1955. dpll |= DPLL_DVO_HIGH_SPEED;
  1956. /* compute bitmask from p1 value */
  1957. if (IS_IGD(dev))
  1958. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
  1959. else {
  1960. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  1961. /* also FPA1 */
  1962. if (IS_IGDNG(dev))
  1963. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  1964. }
  1965. switch (clock.p2) {
  1966. case 5:
  1967. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  1968. break;
  1969. case 7:
  1970. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  1971. break;
  1972. case 10:
  1973. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  1974. break;
  1975. case 14:
  1976. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  1977. break;
  1978. }
  1979. if (IS_I965G(dev) && !IS_IGDNG(dev))
  1980. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  1981. } else {
  1982. if (is_lvds) {
  1983. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  1984. } else {
  1985. if (clock.p1 == 2)
  1986. dpll |= PLL_P1_DIVIDE_BY_TWO;
  1987. else
  1988. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  1989. if (clock.p2 == 4)
  1990. dpll |= PLL_P2_DIVIDE_BY_4;
  1991. }
  1992. }
  1993. if (is_sdvo && is_tv)
  1994. dpll |= PLL_REF_INPUT_TVCLKINBC;
  1995. else if (is_tv)
  1996. /* XXX: just matching BIOS for now */
  1997. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  1998. dpll |= 3;
  1999. else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
  2000. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  2001. else
  2002. dpll |= PLL_REF_INPUT_DREFCLK;
  2003. /* setup pipeconf */
  2004. pipeconf = I915_READ(pipeconf_reg);
  2005. /* Set up the display plane register */
  2006. dspcntr = DISPPLANE_GAMMA_ENABLE;
  2007. /* IGDNG's plane is forced to pipe, bit 24 is to
  2008. enable color space conversion */
  2009. if (!IS_IGDNG(dev)) {
  2010. if (pipe == 0)
  2011. dspcntr |= DISPPLANE_SEL_PIPE_A;
  2012. else
  2013. dspcntr |= DISPPLANE_SEL_PIPE_B;
  2014. }
  2015. if (pipe == 0 && !IS_I965G(dev)) {
  2016. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  2017. * core speed.
  2018. *
  2019. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  2020. * pipe == 0 check?
  2021. */
  2022. if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
  2023. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  2024. else
  2025. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  2026. }
  2027. dspcntr |= DISPLAY_PLANE_ENABLE;
  2028. pipeconf |= PIPEACONF_ENABLE;
  2029. dpll |= DPLL_VCO_ENABLE;
  2030. /* Disable the panel fitter if it was on our pipe */
  2031. if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
  2032. I915_WRITE(PFIT_CONTROL, 0);
  2033. DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  2034. drm_mode_debug_printmodeline(mode);
  2035. /* assign to IGDNG registers */
  2036. if (IS_IGDNG(dev)) {
  2037. fp_reg = pch_fp_reg;
  2038. dpll_reg = pch_dpll_reg;
  2039. }
  2040. if (dpll & DPLL_VCO_ENABLE) {
  2041. I915_WRITE(fp_reg, fp);
  2042. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  2043. I915_READ(dpll_reg);
  2044. udelay(150);
  2045. }
  2046. if (IS_IGDNG(dev)) {
  2047. /* enable PCH clock reference source */
  2048. /* XXX need to change the setting for other outputs */
  2049. u32 temp;
  2050. temp = I915_READ(PCH_DREF_CONTROL);
  2051. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  2052. temp |= DREF_NONSPREAD_CK505_ENABLE;
  2053. temp &= ~DREF_SSC_SOURCE_MASK;
  2054. temp |= DREF_SSC_SOURCE_ENABLE;
  2055. temp &= ~DREF_SSC1_ENABLE;
  2056. /* if no eDP, disable source output to CPU */
  2057. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  2058. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  2059. I915_WRITE(PCH_DREF_CONTROL, temp);
  2060. }
  2061. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  2062. * This is an exception to the general rule that mode_set doesn't turn
  2063. * things on.
  2064. */
  2065. if (is_lvds) {
  2066. u32 lvds;
  2067. if (IS_IGDNG(dev))
  2068. lvds_reg = PCH_LVDS;
  2069. lvds = I915_READ(lvds_reg);
  2070. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
  2071. /* Set the B0-B3 data pairs corresponding to whether we're going to
  2072. * set the DPLLs for dual-channel mode or not.
  2073. */
  2074. if (clock.p2 == 7)
  2075. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  2076. else
  2077. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  2078. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  2079. * appropriately here, but we need to look more thoroughly into how
  2080. * panels behave in the two modes.
  2081. */
  2082. I915_WRITE(lvds_reg, lvds);
  2083. I915_READ(lvds_reg);
  2084. }
  2085. if (is_dp)
  2086. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  2087. I915_WRITE(fp_reg, fp);
  2088. I915_WRITE(dpll_reg, dpll);
  2089. I915_READ(dpll_reg);
  2090. /* Wait for the clocks to stabilize. */
  2091. udelay(150);
  2092. if (IS_I965G(dev) && !IS_IGDNG(dev)) {
  2093. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  2094. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  2095. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  2096. } else {
  2097. /* write it again -- the BIOS does, after all */
  2098. I915_WRITE(dpll_reg, dpll);
  2099. }
  2100. I915_READ(dpll_reg);
  2101. /* Wait for the clocks to stabilize. */
  2102. udelay(150);
  2103. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  2104. ((adjusted_mode->crtc_htotal - 1) << 16));
  2105. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  2106. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  2107. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  2108. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  2109. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  2110. ((adjusted_mode->crtc_vtotal - 1) << 16));
  2111. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  2112. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  2113. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  2114. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  2115. /* pipesrc and dspsize control the size that is scaled from, which should
  2116. * always be the user's requested size.
  2117. */
  2118. if (!IS_IGDNG(dev)) {
  2119. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  2120. (mode->hdisplay - 1));
  2121. I915_WRITE(dsppos_reg, 0);
  2122. }
  2123. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  2124. if (IS_IGDNG(dev)) {
  2125. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  2126. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  2127. I915_WRITE(link_m1_reg, m_n.link_m);
  2128. I915_WRITE(link_n1_reg, m_n.link_n);
  2129. /* enable FDI RX PLL too */
  2130. temp = I915_READ(fdi_rx_reg);
  2131. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  2132. udelay(200);
  2133. }
  2134. I915_WRITE(pipeconf_reg, pipeconf);
  2135. I915_READ(pipeconf_reg);
  2136. intel_wait_for_vblank(dev);
  2137. I915_WRITE(dspcntr_reg, dspcntr);
  2138. /* Flush the plane changes */
  2139. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  2140. intel_update_watermarks(dev);
  2141. drm_vblank_post_modeset(dev, pipe);
  2142. return ret;
  2143. }
  2144. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  2145. void intel_crtc_load_lut(struct drm_crtc *crtc)
  2146. {
  2147. struct drm_device *dev = crtc->dev;
  2148. struct drm_i915_private *dev_priv = dev->dev_private;
  2149. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2150. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  2151. int i;
  2152. /* The clocks have to be on to load the palette. */
  2153. if (!crtc->enabled)
  2154. return;
  2155. /* use legacy palette for IGDNG */
  2156. if (IS_IGDNG(dev))
  2157. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  2158. LGC_PALETTE_B;
  2159. for (i = 0; i < 256; i++) {
  2160. I915_WRITE(palreg + 4 * i,
  2161. (intel_crtc->lut_r[i] << 16) |
  2162. (intel_crtc->lut_g[i] << 8) |
  2163. intel_crtc->lut_b[i]);
  2164. }
  2165. }
  2166. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  2167. struct drm_file *file_priv,
  2168. uint32_t handle,
  2169. uint32_t width, uint32_t height)
  2170. {
  2171. struct drm_device *dev = crtc->dev;
  2172. struct drm_i915_private *dev_priv = dev->dev_private;
  2173. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2174. struct drm_gem_object *bo;
  2175. struct drm_i915_gem_object *obj_priv;
  2176. int pipe = intel_crtc->pipe;
  2177. uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
  2178. uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
  2179. uint32_t temp = I915_READ(control);
  2180. size_t addr;
  2181. int ret;
  2182. DRM_DEBUG("\n");
  2183. /* if we want to turn off the cursor ignore width and height */
  2184. if (!handle) {
  2185. DRM_DEBUG("cursor off\n");
  2186. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  2187. temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  2188. temp |= CURSOR_MODE_DISABLE;
  2189. } else {
  2190. temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  2191. }
  2192. addr = 0;
  2193. bo = NULL;
  2194. mutex_lock(&dev->struct_mutex);
  2195. goto finish;
  2196. }
  2197. /* Currently we only support 64x64 cursors */
  2198. if (width != 64 || height != 64) {
  2199. DRM_ERROR("we currently only support 64x64 cursors\n");
  2200. return -EINVAL;
  2201. }
  2202. bo = drm_gem_object_lookup(dev, file_priv, handle);
  2203. if (!bo)
  2204. return -ENOENT;
  2205. obj_priv = bo->driver_private;
  2206. if (bo->size < width * height * 4) {
  2207. DRM_ERROR("buffer is to small\n");
  2208. ret = -ENOMEM;
  2209. goto fail;
  2210. }
  2211. /* we only need to pin inside GTT if cursor is non-phy */
  2212. mutex_lock(&dev->struct_mutex);
  2213. if (!dev_priv->cursor_needs_physical) {
  2214. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  2215. if (ret) {
  2216. DRM_ERROR("failed to pin cursor bo\n");
  2217. goto fail_locked;
  2218. }
  2219. addr = obj_priv->gtt_offset;
  2220. } else {
  2221. ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  2222. if (ret) {
  2223. DRM_ERROR("failed to attach phys object\n");
  2224. goto fail_locked;
  2225. }
  2226. addr = obj_priv->phys_obj->handle->busaddr;
  2227. }
  2228. if (!IS_I9XX(dev))
  2229. I915_WRITE(CURSIZE, (height << 12) | width);
  2230. /* Hooray for CUR*CNTR differences */
  2231. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  2232. temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  2233. temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  2234. temp |= (pipe << 28); /* Connect to correct pipe */
  2235. } else {
  2236. temp &= ~(CURSOR_FORMAT_MASK);
  2237. temp |= CURSOR_ENABLE;
  2238. temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  2239. }
  2240. finish:
  2241. I915_WRITE(control, temp);
  2242. I915_WRITE(base, addr);
  2243. if (intel_crtc->cursor_bo) {
  2244. if (dev_priv->cursor_needs_physical) {
  2245. if (intel_crtc->cursor_bo != bo)
  2246. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  2247. } else
  2248. i915_gem_object_unpin(intel_crtc->cursor_bo);
  2249. drm_gem_object_unreference(intel_crtc->cursor_bo);
  2250. }
  2251. mutex_unlock(&dev->struct_mutex);
  2252. intel_crtc->cursor_addr = addr;
  2253. intel_crtc->cursor_bo = bo;
  2254. return 0;
  2255. fail:
  2256. mutex_lock(&dev->struct_mutex);
  2257. fail_locked:
  2258. drm_gem_object_unreference(bo);
  2259. mutex_unlock(&dev->struct_mutex);
  2260. return ret;
  2261. }
  2262. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  2263. {
  2264. struct drm_device *dev = crtc->dev;
  2265. struct drm_i915_private *dev_priv = dev->dev_private;
  2266. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2267. int pipe = intel_crtc->pipe;
  2268. uint32_t temp = 0;
  2269. uint32_t adder;
  2270. if (x < 0) {
  2271. temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  2272. x = -x;
  2273. }
  2274. if (y < 0) {
  2275. temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  2276. y = -y;
  2277. }
  2278. temp |= x << CURSOR_X_SHIFT;
  2279. temp |= y << CURSOR_Y_SHIFT;
  2280. adder = intel_crtc->cursor_addr;
  2281. I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
  2282. I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
  2283. return 0;
  2284. }
  2285. /** Sets the color ramps on behalf of RandR */
  2286. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  2287. u16 blue, int regno)
  2288. {
  2289. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2290. intel_crtc->lut_r[regno] = red >> 8;
  2291. intel_crtc->lut_g[regno] = green >> 8;
  2292. intel_crtc->lut_b[regno] = blue >> 8;
  2293. }
  2294. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  2295. u16 *blue, uint32_t size)
  2296. {
  2297. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2298. int i;
  2299. if (size != 256)
  2300. return;
  2301. for (i = 0; i < 256; i++) {
  2302. intel_crtc->lut_r[i] = red[i] >> 8;
  2303. intel_crtc->lut_g[i] = green[i] >> 8;
  2304. intel_crtc->lut_b[i] = blue[i] >> 8;
  2305. }
  2306. intel_crtc_load_lut(crtc);
  2307. }
  2308. /**
  2309. * Get a pipe with a simple mode set on it for doing load-based monitor
  2310. * detection.
  2311. *
  2312. * It will be up to the load-detect code to adjust the pipe as appropriate for
  2313. * its requirements. The pipe will be connected to no other outputs.
  2314. *
  2315. * Currently this code will only succeed if there is a pipe with no outputs
  2316. * configured for it. In the future, it could choose to temporarily disable
  2317. * some outputs to free up a pipe for its use.
  2318. *
  2319. * \return crtc, or NULL if no pipes are available.
  2320. */
  2321. /* VESA 640x480x72Hz mode to set on the pipe */
  2322. static struct drm_display_mode load_detect_mode = {
  2323. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  2324. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  2325. };
  2326. struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
  2327. struct drm_display_mode *mode,
  2328. int *dpms_mode)
  2329. {
  2330. struct intel_crtc *intel_crtc;
  2331. struct drm_crtc *possible_crtc;
  2332. struct drm_crtc *supported_crtc =NULL;
  2333. struct drm_encoder *encoder = &intel_output->enc;
  2334. struct drm_crtc *crtc = NULL;
  2335. struct drm_device *dev = encoder->dev;
  2336. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2337. struct drm_crtc_helper_funcs *crtc_funcs;
  2338. int i = -1;
  2339. /*
  2340. * Algorithm gets a little messy:
  2341. * - if the connector already has an assigned crtc, use it (but make
  2342. * sure it's on first)
  2343. * - try to find the first unused crtc that can drive this connector,
  2344. * and use that if we find one
  2345. * - if there are no unused crtcs available, try to use the first
  2346. * one we found that supports the connector
  2347. */
  2348. /* See if we already have a CRTC for this connector */
  2349. if (encoder->crtc) {
  2350. crtc = encoder->crtc;
  2351. /* Make sure the crtc and connector are running */
  2352. intel_crtc = to_intel_crtc(crtc);
  2353. *dpms_mode = intel_crtc->dpms_mode;
  2354. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  2355. crtc_funcs = crtc->helper_private;
  2356. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  2357. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2358. }
  2359. return crtc;
  2360. }
  2361. /* Find an unused one (if possible) */
  2362. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  2363. i++;
  2364. if (!(encoder->possible_crtcs & (1 << i)))
  2365. continue;
  2366. if (!possible_crtc->enabled) {
  2367. crtc = possible_crtc;
  2368. break;
  2369. }
  2370. if (!supported_crtc)
  2371. supported_crtc = possible_crtc;
  2372. }
  2373. /*
  2374. * If we didn't find an unused CRTC, don't use any.
  2375. */
  2376. if (!crtc) {
  2377. return NULL;
  2378. }
  2379. encoder->crtc = crtc;
  2380. intel_output->base.encoder = encoder;
  2381. intel_output->load_detect_temp = true;
  2382. intel_crtc = to_intel_crtc(crtc);
  2383. *dpms_mode = intel_crtc->dpms_mode;
  2384. if (!crtc->enabled) {
  2385. if (!mode)
  2386. mode = &load_detect_mode;
  2387. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  2388. } else {
  2389. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  2390. crtc_funcs = crtc->helper_private;
  2391. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  2392. }
  2393. /* Add this connector to the crtc */
  2394. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  2395. encoder_funcs->commit(encoder);
  2396. }
  2397. /* let the connector get through one full cycle before testing */
  2398. intel_wait_for_vblank(dev);
  2399. return crtc;
  2400. }
  2401. void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
  2402. {
  2403. struct drm_encoder *encoder = &intel_output->enc;
  2404. struct drm_device *dev = encoder->dev;
  2405. struct drm_crtc *crtc = encoder->crtc;
  2406. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2407. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2408. if (intel_output->load_detect_temp) {
  2409. encoder->crtc = NULL;
  2410. intel_output->base.encoder = NULL;
  2411. intel_output->load_detect_temp = false;
  2412. crtc->enabled = drm_helper_crtc_in_use(crtc);
  2413. drm_helper_disable_unused_functions(dev);
  2414. }
  2415. /* Switch crtc and output back off if necessary */
  2416. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  2417. if (encoder->crtc == crtc)
  2418. encoder_funcs->dpms(encoder, dpms_mode);
  2419. crtc_funcs->dpms(crtc, dpms_mode);
  2420. }
  2421. }
  2422. /* Returns the clock of the currently programmed mode of the given pipe. */
  2423. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  2424. {
  2425. struct drm_i915_private *dev_priv = dev->dev_private;
  2426. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2427. int pipe = intel_crtc->pipe;
  2428. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  2429. u32 fp;
  2430. intel_clock_t clock;
  2431. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  2432. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  2433. else
  2434. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  2435. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  2436. if (IS_IGD(dev)) {
  2437. clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  2438. clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
  2439. } else {
  2440. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  2441. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  2442. }
  2443. if (IS_I9XX(dev)) {
  2444. if (IS_IGD(dev))
  2445. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
  2446. DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
  2447. else
  2448. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  2449. DPLL_FPA01_P1_POST_DIV_SHIFT);
  2450. switch (dpll & DPLL_MODE_MASK) {
  2451. case DPLLB_MODE_DAC_SERIAL:
  2452. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  2453. 5 : 10;
  2454. break;
  2455. case DPLLB_MODE_LVDS:
  2456. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  2457. 7 : 14;
  2458. break;
  2459. default:
  2460. DRM_DEBUG("Unknown DPLL mode %08x in programmed "
  2461. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  2462. return 0;
  2463. }
  2464. /* XXX: Handle the 100Mhz refclk */
  2465. intel_clock(dev, 96000, &clock);
  2466. } else {
  2467. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  2468. if (is_lvds) {
  2469. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  2470. DPLL_FPA01_P1_POST_DIV_SHIFT);
  2471. clock.p2 = 14;
  2472. if ((dpll & PLL_REF_INPUT_MASK) ==
  2473. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  2474. /* XXX: might not be 66MHz */
  2475. intel_clock(dev, 66000, &clock);
  2476. } else
  2477. intel_clock(dev, 48000, &clock);
  2478. } else {
  2479. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  2480. clock.p1 = 2;
  2481. else {
  2482. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  2483. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  2484. }
  2485. if (dpll & PLL_P2_DIVIDE_BY_4)
  2486. clock.p2 = 4;
  2487. else
  2488. clock.p2 = 2;
  2489. intel_clock(dev, 48000, &clock);
  2490. }
  2491. }
  2492. /* XXX: It would be nice to validate the clocks, but we can't reuse
  2493. * i830PllIsValid() because it relies on the xf86_config connector
  2494. * configuration being accurate, which it isn't necessarily.
  2495. */
  2496. return clock.dot;
  2497. }
  2498. /** Returns the currently programmed mode of the given pipe. */
  2499. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  2500. struct drm_crtc *crtc)
  2501. {
  2502. struct drm_i915_private *dev_priv = dev->dev_private;
  2503. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2504. int pipe = intel_crtc->pipe;
  2505. struct drm_display_mode *mode;
  2506. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  2507. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  2508. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  2509. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  2510. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  2511. if (!mode)
  2512. return NULL;
  2513. mode->clock = intel_crtc_clock_get(dev, crtc);
  2514. mode->hdisplay = (htot & 0xffff) + 1;
  2515. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  2516. mode->hsync_start = (hsync & 0xffff) + 1;
  2517. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  2518. mode->vdisplay = (vtot & 0xffff) + 1;
  2519. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  2520. mode->vsync_start = (vsync & 0xffff) + 1;
  2521. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  2522. drm_mode_set_name(mode);
  2523. drm_mode_set_crtcinfo(mode, 0);
  2524. return mode;
  2525. }
  2526. static void intel_crtc_destroy(struct drm_crtc *crtc)
  2527. {
  2528. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2529. if (intel_crtc->mode_set.mode)
  2530. drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
  2531. drm_crtc_cleanup(crtc);
  2532. kfree(intel_crtc);
  2533. }
  2534. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  2535. .dpms = intel_crtc_dpms,
  2536. .mode_fixup = intel_crtc_mode_fixup,
  2537. .mode_set = intel_crtc_mode_set,
  2538. .mode_set_base = intel_pipe_set_base,
  2539. .prepare = intel_crtc_prepare,
  2540. .commit = intel_crtc_commit,
  2541. };
  2542. static const struct drm_crtc_funcs intel_crtc_funcs = {
  2543. .cursor_set = intel_crtc_cursor_set,
  2544. .cursor_move = intel_crtc_cursor_move,
  2545. .gamma_set = intel_crtc_gamma_set,
  2546. .set_config = drm_crtc_helper_set_config,
  2547. .destroy = intel_crtc_destroy,
  2548. };
  2549. static void intel_crtc_init(struct drm_device *dev, int pipe)
  2550. {
  2551. struct intel_crtc *intel_crtc;
  2552. int i;
  2553. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  2554. if (intel_crtc == NULL)
  2555. return;
  2556. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  2557. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  2558. intel_crtc->pipe = pipe;
  2559. intel_crtc->plane = pipe;
  2560. for (i = 0; i < 256; i++) {
  2561. intel_crtc->lut_r[i] = i;
  2562. intel_crtc->lut_g[i] = i;
  2563. intel_crtc->lut_b[i] = i;
  2564. }
  2565. intel_crtc->cursor_addr = 0;
  2566. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  2567. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  2568. intel_crtc->mode_set.crtc = &intel_crtc->base;
  2569. intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
  2570. intel_crtc->mode_set.num_connectors = 0;
  2571. if (i915_fbpercrtc) {
  2572. }
  2573. }
  2574. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  2575. struct drm_file *file_priv)
  2576. {
  2577. drm_i915_private_t *dev_priv = dev->dev_private;
  2578. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  2579. struct drm_crtc *crtc = NULL;
  2580. int pipe = -1;
  2581. if (!dev_priv) {
  2582. DRM_ERROR("called with no initialization\n");
  2583. return -EINVAL;
  2584. }
  2585. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2586. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2587. if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
  2588. pipe = intel_crtc->pipe;
  2589. break;
  2590. }
  2591. }
  2592. if (pipe == -1) {
  2593. DRM_ERROR("no such CRTC id\n");
  2594. return -EINVAL;
  2595. }
  2596. pipe_from_crtc_id->pipe = pipe;
  2597. return 0;
  2598. }
  2599. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  2600. {
  2601. struct drm_crtc *crtc = NULL;
  2602. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2603. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2604. if (intel_crtc->pipe == pipe)
  2605. break;
  2606. }
  2607. return crtc;
  2608. }
  2609. static int intel_connector_clones(struct drm_device *dev, int type_mask)
  2610. {
  2611. int index_mask = 0;
  2612. struct drm_connector *connector;
  2613. int entry = 0;
  2614. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  2615. struct intel_output *intel_output = to_intel_output(connector);
  2616. if (type_mask & (1 << intel_output->type))
  2617. index_mask |= (1 << entry);
  2618. entry++;
  2619. }
  2620. return index_mask;
  2621. }
  2622. static void intel_setup_outputs(struct drm_device *dev)
  2623. {
  2624. struct drm_i915_private *dev_priv = dev->dev_private;
  2625. struct drm_connector *connector;
  2626. intel_crt_init(dev);
  2627. /* Set up integrated LVDS */
  2628. if (IS_MOBILE(dev) && !IS_I830(dev))
  2629. intel_lvds_init(dev);
  2630. if (IS_IGDNG(dev)) {
  2631. int found;
  2632. if (I915_READ(HDMIB) & PORT_DETECTED) {
  2633. /* check SDVOB */
  2634. /* found = intel_sdvo_init(dev, HDMIB); */
  2635. found = 0;
  2636. if (!found)
  2637. intel_hdmi_init(dev, HDMIB);
  2638. }
  2639. if (I915_READ(HDMIC) & PORT_DETECTED)
  2640. intel_hdmi_init(dev, HDMIC);
  2641. if (I915_READ(HDMID) & PORT_DETECTED)
  2642. intel_hdmi_init(dev, HDMID);
  2643. } else if (IS_I9XX(dev)) {
  2644. int found;
  2645. u32 reg;
  2646. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  2647. found = intel_sdvo_init(dev, SDVOB);
  2648. if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
  2649. intel_hdmi_init(dev, SDVOB);
  2650. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  2651. intel_dp_init(dev, DP_B);
  2652. }
  2653. /* Before G4X SDVOC doesn't have its own detect register */
  2654. if (IS_G4X(dev))
  2655. reg = SDVOC;
  2656. else
  2657. reg = SDVOB;
  2658. if (I915_READ(reg) & SDVO_DETECTED) {
  2659. found = intel_sdvo_init(dev, SDVOC);
  2660. if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
  2661. intel_hdmi_init(dev, SDVOC);
  2662. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  2663. intel_dp_init(dev, DP_C);
  2664. }
  2665. if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
  2666. intel_dp_init(dev, DP_D);
  2667. } else
  2668. intel_dvo_init(dev);
  2669. if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
  2670. intel_tv_init(dev);
  2671. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  2672. struct intel_output *intel_output = to_intel_output(connector);
  2673. struct drm_encoder *encoder = &intel_output->enc;
  2674. int crtc_mask = 0, clone_mask = 0;
  2675. /* valid crtcs */
  2676. switch(intel_output->type) {
  2677. case INTEL_OUTPUT_HDMI:
  2678. crtc_mask = ((1 << 0)|
  2679. (1 << 1));
  2680. clone_mask = ((1 << INTEL_OUTPUT_HDMI));
  2681. break;
  2682. case INTEL_OUTPUT_DVO:
  2683. case INTEL_OUTPUT_SDVO:
  2684. crtc_mask = ((1 << 0)|
  2685. (1 << 1));
  2686. clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
  2687. (1 << INTEL_OUTPUT_DVO) |
  2688. (1 << INTEL_OUTPUT_SDVO));
  2689. break;
  2690. case INTEL_OUTPUT_ANALOG:
  2691. crtc_mask = ((1 << 0)|
  2692. (1 << 1));
  2693. clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
  2694. (1 << INTEL_OUTPUT_DVO) |
  2695. (1 << INTEL_OUTPUT_SDVO));
  2696. break;
  2697. case INTEL_OUTPUT_LVDS:
  2698. crtc_mask = (1 << 1);
  2699. clone_mask = (1 << INTEL_OUTPUT_LVDS);
  2700. break;
  2701. case INTEL_OUTPUT_TVOUT:
  2702. crtc_mask = ((1 << 0) |
  2703. (1 << 1));
  2704. clone_mask = (1 << INTEL_OUTPUT_TVOUT);
  2705. break;
  2706. case INTEL_OUTPUT_DISPLAYPORT:
  2707. crtc_mask = ((1 << 0) |
  2708. (1 << 1));
  2709. clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
  2710. break;
  2711. }
  2712. encoder->possible_crtcs = crtc_mask;
  2713. encoder->possible_clones = intel_connector_clones(dev, clone_mask);
  2714. }
  2715. }
  2716. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  2717. {
  2718. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  2719. struct drm_device *dev = fb->dev;
  2720. if (fb->fbdev)
  2721. intelfb_remove(dev, fb);
  2722. drm_framebuffer_cleanup(fb);
  2723. mutex_lock(&dev->struct_mutex);
  2724. drm_gem_object_unreference(intel_fb->obj);
  2725. mutex_unlock(&dev->struct_mutex);
  2726. kfree(intel_fb);
  2727. }
  2728. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  2729. struct drm_file *file_priv,
  2730. unsigned int *handle)
  2731. {
  2732. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  2733. struct drm_gem_object *object = intel_fb->obj;
  2734. return drm_gem_handle_create(file_priv, object, handle);
  2735. }
  2736. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  2737. .destroy = intel_user_framebuffer_destroy,
  2738. .create_handle = intel_user_framebuffer_create_handle,
  2739. };
  2740. int intel_framebuffer_create(struct drm_device *dev,
  2741. struct drm_mode_fb_cmd *mode_cmd,
  2742. struct drm_framebuffer **fb,
  2743. struct drm_gem_object *obj)
  2744. {
  2745. struct intel_framebuffer *intel_fb;
  2746. int ret;
  2747. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  2748. if (!intel_fb)
  2749. return -ENOMEM;
  2750. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  2751. if (ret) {
  2752. DRM_ERROR("framebuffer init failed %d\n", ret);
  2753. return ret;
  2754. }
  2755. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  2756. intel_fb->obj = obj;
  2757. *fb = &intel_fb->base;
  2758. return 0;
  2759. }
  2760. static struct drm_framebuffer *
  2761. intel_user_framebuffer_create(struct drm_device *dev,
  2762. struct drm_file *filp,
  2763. struct drm_mode_fb_cmd *mode_cmd)
  2764. {
  2765. struct drm_gem_object *obj;
  2766. struct drm_framebuffer *fb;
  2767. int ret;
  2768. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  2769. if (!obj)
  2770. return NULL;
  2771. ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
  2772. if (ret) {
  2773. mutex_lock(&dev->struct_mutex);
  2774. drm_gem_object_unreference(obj);
  2775. mutex_unlock(&dev->struct_mutex);
  2776. return NULL;
  2777. }
  2778. return fb;
  2779. }
  2780. static const struct drm_mode_config_funcs intel_mode_funcs = {
  2781. .fb_create = intel_user_framebuffer_create,
  2782. .fb_changed = intelfb_probe,
  2783. };
  2784. void intel_modeset_init(struct drm_device *dev)
  2785. {
  2786. int num_pipe;
  2787. int i;
  2788. drm_mode_config_init(dev);
  2789. dev->mode_config.min_width = 0;
  2790. dev->mode_config.min_height = 0;
  2791. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  2792. if (IS_I965G(dev)) {
  2793. dev->mode_config.max_width = 8192;
  2794. dev->mode_config.max_height = 8192;
  2795. } else if (IS_I9XX(dev)) {
  2796. dev->mode_config.max_width = 4096;
  2797. dev->mode_config.max_height = 4096;
  2798. } else {
  2799. dev->mode_config.max_width = 2048;
  2800. dev->mode_config.max_height = 2048;
  2801. }
  2802. /* set memory base */
  2803. if (IS_I9XX(dev))
  2804. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  2805. else
  2806. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  2807. if (IS_MOBILE(dev) || IS_I9XX(dev))
  2808. num_pipe = 2;
  2809. else
  2810. num_pipe = 1;
  2811. DRM_DEBUG("%d display pipe%s available.\n",
  2812. num_pipe, num_pipe > 1 ? "s" : "");
  2813. for (i = 0; i < num_pipe; i++) {
  2814. intel_crtc_init(dev, i);
  2815. }
  2816. intel_setup_outputs(dev);
  2817. }
  2818. void intel_modeset_cleanup(struct drm_device *dev)
  2819. {
  2820. drm_mode_config_cleanup(dev);
  2821. }
  2822. /* current intel driver doesn't take advantage of encoders
  2823. always give back the encoder for the connector
  2824. */
  2825. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  2826. {
  2827. struct intel_output *intel_output = to_intel_output(connector);
  2828. return &intel_output->enc;
  2829. }