mci.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566
  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  40. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  41. return false;
  42. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  43. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  44. return false;
  45. entry = kzalloc(sizeof(*entry), GFP_KERNEL);
  46. if (!entry)
  47. return false;
  48. memcpy(entry, info, 10);
  49. INC_PROF(mci, info);
  50. list_add_tail(&entry->list, &mci->info);
  51. return true;
  52. }
  53. static void ath_mci_del_profile(struct ath_common *common,
  54. struct ath_mci_profile *mci,
  55. struct ath_mci_profile_info *entry)
  56. {
  57. if (!entry)
  58. return;
  59. DEC_PROF(mci, entry);
  60. list_del(&entry->list);
  61. kfree(entry);
  62. }
  63. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  64. {
  65. struct ath_mci_profile_info *info, *tinfo;
  66. mci->aggr_limit = 0;
  67. if (list_empty(&mci->info))
  68. return;
  69. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  70. list_del(&info->list);
  71. DEC_PROF(mci, info);
  72. kfree(info);
  73. }
  74. }
  75. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  76. {
  77. struct ath_mci_profile *mci = &btcoex->mci;
  78. u32 wlan_airtime = btcoex->btcoex_period *
  79. (100 - btcoex->duty_cycle) / 100;
  80. /*
  81. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  82. * When wlan_airtime is less than 4ms, aggregation limit has to be
  83. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  84. * without collision with BT traffic.
  85. */
  86. if ((wlan_airtime <= 4) &&
  87. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  88. mci->aggr_limit = 2 * wlan_airtime;
  89. }
  90. static void ath_mci_update_scheme(struct ath_softc *sc)
  91. {
  92. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  93. struct ath_btcoex *btcoex = &sc->btcoex;
  94. struct ath_mci_profile *mci = &btcoex->mci;
  95. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  96. struct ath_mci_profile_info *info;
  97. u32 num_profile = NUM_PROF(mci);
  98. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  99. goto skip_tuning;
  100. if (num_profile == 1) {
  101. info = list_first_entry(&mci->info,
  102. struct ath_mci_profile_info,
  103. list);
  104. if (mci->num_sco) {
  105. if (info->T == 12)
  106. mci->aggr_limit = 8;
  107. else if (info->T == 6) {
  108. mci->aggr_limit = 6;
  109. btcoex->duty_cycle = 30;
  110. }
  111. ath_dbg(common, MCI,
  112. "Single SCO, aggregation limit %d 1/4 ms\n",
  113. mci->aggr_limit);
  114. } else if (mci->num_pan || mci->num_other_acl) {
  115. /*
  116. * For single PAN/FTP profile, allocate 35% for BT
  117. * to improve WLAN throughput.
  118. */
  119. btcoex->duty_cycle = 35;
  120. btcoex->btcoex_period = 53;
  121. ath_dbg(common, MCI,
  122. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  123. btcoex->duty_cycle, btcoex->btcoex_period);
  124. } else if (mci->num_hid) {
  125. btcoex->duty_cycle = 30;
  126. mci->aggr_limit = 6;
  127. ath_dbg(common, MCI,
  128. "Multiple attempt/timeout single HID "
  129. "aggregation limit 1.5 ms dutycycle 30%%\n");
  130. }
  131. } else if (num_profile == 2) {
  132. if (mci->num_hid == 2)
  133. btcoex->duty_cycle = 30;
  134. mci->aggr_limit = 6;
  135. ath_dbg(common, MCI,
  136. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  137. btcoex->duty_cycle);
  138. } else if (num_profile >= 3) {
  139. mci->aggr_limit = 4;
  140. ath_dbg(common, MCI,
  141. "Three or more profiles aggregation limit 1 ms\n");
  142. }
  143. skip_tuning:
  144. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  145. if (IS_CHAN_HT(sc->sc_ah->curchan))
  146. ath_mci_adjust_aggr_limit(btcoex);
  147. else
  148. btcoex->btcoex_period >>= 1;
  149. }
  150. ath9k_hw_btcoex_disable(sc->sc_ah);
  151. ath9k_btcoex_timer_pause(sc);
  152. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  153. return;
  154. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0);
  155. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  156. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  157. btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
  158. (100 - btcoex->duty_cycle) / 100;
  159. ath9k_hw_btcoex_enable(sc->sc_ah);
  160. ath9k_btcoex_timer_resume(sc);
  161. }
  162. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  163. {
  164. struct ath_hw *ah = sc->sc_ah;
  165. struct ath_common *common = ath9k_hw_common(ah);
  166. u32 payload[4] = {0, 0, 0, 0};
  167. switch (opcode) {
  168. case MCI_GPM_BT_CAL_REQ:
  169. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  170. ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
  171. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  172. } else {
  173. ath_dbg(common, MCI, "MCI State mismatch: %d\n",
  174. ar9003_mci_state(ah, MCI_STATE_BT, NULL));
  175. }
  176. break;
  177. case MCI_GPM_BT_CAL_DONE:
  178. ar9003_mci_state(ah, MCI_STATE_BT, NULL);
  179. break;
  180. case MCI_GPM_BT_CAL_GRANT:
  181. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  182. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  183. 16, false, true);
  184. break;
  185. default:
  186. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  187. break;
  188. }
  189. }
  190. static void ath_mci_process_profile(struct ath_softc *sc,
  191. struct ath_mci_profile_info *info)
  192. {
  193. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  194. struct ath_btcoex *btcoex = &sc->btcoex;
  195. struct ath_mci_profile *mci = &btcoex->mci;
  196. struct ath_mci_profile_info *entry = NULL;
  197. entry = ath_mci_find_profile(mci, info);
  198. if (entry)
  199. memcpy(entry, info, 10);
  200. if (info->start) {
  201. if (!entry && !ath_mci_add_profile(common, mci, info))
  202. return;
  203. } else
  204. ath_mci_del_profile(common, mci, entry);
  205. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  206. mci->aggr_limit = mci->num_sco ? 6 : 0;
  207. if (NUM_PROF(mci)) {
  208. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  209. btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
  210. } else {
  211. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  212. ATH_BTCOEX_STOMP_LOW;
  213. btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
  214. }
  215. ath_mci_update_scheme(sc);
  216. }
  217. static void ath_mci_process_status(struct ath_softc *sc,
  218. struct ath_mci_profile_status *status)
  219. {
  220. struct ath_btcoex *btcoex = &sc->btcoex;
  221. struct ath_mci_profile *mci = &btcoex->mci;
  222. struct ath_mci_profile_info info;
  223. int i = 0, old_num_mgmt = mci->num_mgmt;
  224. /* Link status type are not handled */
  225. if (status->is_link)
  226. return;
  227. info.conn_handle = status->conn_handle;
  228. if (ath_mci_find_profile(mci, &info))
  229. return;
  230. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  231. return;
  232. if (status->is_critical)
  233. __set_bit(status->conn_handle, mci->status);
  234. else
  235. __clear_bit(status->conn_handle, mci->status);
  236. mci->num_mgmt = 0;
  237. do {
  238. if (test_bit(i, mci->status))
  239. mci->num_mgmt++;
  240. } while (++i < ATH_MCI_MAX_PROFILE);
  241. if (old_num_mgmt != mci->num_mgmt)
  242. ath_mci_update_scheme(sc);
  243. }
  244. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  245. {
  246. struct ath_hw *ah = sc->sc_ah;
  247. struct ath_mci_profile_info profile_info;
  248. struct ath_mci_profile_status profile_status;
  249. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  250. u32 version;
  251. u8 major;
  252. u8 minor;
  253. u32 seq_num;
  254. switch (opcode) {
  255. case MCI_GPM_COEX_VERSION_QUERY:
  256. version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION,
  257. NULL);
  258. break;
  259. case MCI_GPM_COEX_VERSION_RESPONSE:
  260. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  261. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  262. version = (major << 8) + minor;
  263. version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION,
  264. &version);
  265. break;
  266. case MCI_GPM_COEX_STATUS_QUERY:
  267. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL);
  268. break;
  269. case MCI_GPM_COEX_BT_PROFILE_INFO:
  270. memcpy(&profile_info,
  271. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  272. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  273. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  274. ath_dbg(common, MCI,
  275. "Illegal profile type = %d, state = %d\n",
  276. profile_info.type,
  277. profile_info.start);
  278. break;
  279. }
  280. ath_mci_process_profile(sc, &profile_info);
  281. break;
  282. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  283. profile_status.is_link = *(rx_payload +
  284. MCI_GPM_COEX_B_STATUS_TYPE);
  285. profile_status.conn_handle = *(rx_payload +
  286. MCI_GPM_COEX_B_STATUS_LINKID);
  287. profile_status.is_critical = *(rx_payload +
  288. MCI_GPM_COEX_B_STATUS_STATE);
  289. seq_num = *((u32 *)(rx_payload + 12));
  290. ath_dbg(common, MCI,
  291. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
  292. profile_status.is_link, profile_status.conn_handle,
  293. profile_status.is_critical, seq_num);
  294. ath_mci_process_status(sc, &profile_status);
  295. break;
  296. default:
  297. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  298. break;
  299. }
  300. }
  301. int ath_mci_setup(struct ath_softc *sc)
  302. {
  303. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  304. struct ath_mci_coex *mci = &sc->mci_coex;
  305. struct ath_mci_buf *buf = &mci->sched_buf;
  306. buf->bf_addr = dma_alloc_coherent(sc->dev,
  307. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  308. &buf->bf_paddr, GFP_KERNEL);
  309. if (buf->bf_addr == NULL) {
  310. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  311. return -ENOMEM;
  312. }
  313. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  314. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  315. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  316. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  317. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  318. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  319. ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  320. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  321. mci->sched_buf.bf_paddr);
  322. ath_dbg(common, MCI, "MCI Initialized\n");
  323. return 0;
  324. }
  325. void ath_mci_cleanup(struct ath_softc *sc)
  326. {
  327. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  328. struct ath_hw *ah = sc->sc_ah;
  329. struct ath_mci_coex *mci = &sc->mci_coex;
  330. struct ath_mci_buf *buf = &mci->sched_buf;
  331. if (buf->bf_addr)
  332. dma_free_coherent(sc->dev,
  333. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  334. buf->bf_addr, buf->bf_paddr);
  335. ar9003_mci_cleanup(ah);
  336. ath_dbg(common, MCI, "MCI De-Initialized\n");
  337. }
  338. void ath_mci_intr(struct ath_softc *sc)
  339. {
  340. struct ath_mci_coex *mci = &sc->mci_coex;
  341. struct ath_hw *ah = sc->sc_ah;
  342. struct ath_common *common = ath9k_hw_common(ah);
  343. u32 mci_int, mci_int_rxmsg;
  344. u32 offset, subtype, opcode;
  345. u32 *pgpm;
  346. u32 more_data = MCI_GPM_MORE;
  347. bool skip_gpm = false;
  348. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  349. if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
  350. ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
  351. return;
  352. }
  353. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  354. u32 payload[4] = { 0xffffffff, 0xffffffff,
  355. 0xffffffff, 0xffffff00};
  356. /*
  357. * The following REMOTE_RESET and SYS_WAKING used to sent
  358. * only when BT wake up. Now they are always sent, as a
  359. * recovery method to reset BT MCI's RX alignment.
  360. */
  361. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  362. payload, 16, true, false);
  363. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  364. NULL, 0, true, false);
  365. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  366. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
  367. /*
  368. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  369. */
  370. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
  371. }
  372. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  373. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  374. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
  375. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  376. MCI_BT_SLEEP)
  377. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE,
  378. NULL);
  379. }
  380. }
  381. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  382. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  383. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  384. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  385. MCI_BT_AWAKE)
  386. ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
  387. NULL);
  388. }
  389. }
  390. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  391. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  392. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
  393. skip_gpm = true;
  394. }
  395. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  396. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  397. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
  398. NULL);
  399. }
  400. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  401. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  402. while (more_data == MCI_GPM_MORE) {
  403. pgpm = mci->gpm_buf.bf_addr;
  404. offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
  405. &more_data);
  406. if (offset == MCI_GPM_INVALID)
  407. break;
  408. pgpm += (offset >> 2);
  409. /*
  410. * The first dword is timer.
  411. * The real data starts from 2nd dword.
  412. */
  413. subtype = MCI_GPM_TYPE(pgpm);
  414. opcode = MCI_GPM_OPCODE(pgpm);
  415. if (skip_gpm)
  416. goto recycle;
  417. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  418. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  419. } else {
  420. switch (subtype) {
  421. case MCI_GPM_COEX_AGENT:
  422. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  423. break;
  424. default:
  425. break;
  426. }
  427. }
  428. recycle:
  429. MCI_GPM_RECYCLE(pgpm);
  430. }
  431. }
  432. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  433. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  434. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  435. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  436. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  437. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  438. int value_dbm = ar9003_mci_state(ah,
  439. MCI_STATE_CONT_RSSI_POWER, NULL);
  440. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  441. if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
  442. ath_dbg(common, MCI,
  443. "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n",
  444. ar9003_mci_state(ah,
  445. MCI_STATE_CONT_PRIORITY, NULL),
  446. value_dbm);
  447. else
  448. ath_dbg(common, MCI,
  449. "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n",
  450. ar9003_mci_state(ah,
  451. MCI_STATE_CONT_PRIORITY, NULL),
  452. value_dbm);
  453. }
  454. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  455. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  456. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  457. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  458. }
  459. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  460. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
  461. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  462. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  463. }
  464. void ath_mci_enable(struct ath_softc *sc)
  465. {
  466. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  467. if (!common->btcoex_enabled)
  468. return;
  469. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  470. sc->sc_ah->imask |= ATH9K_INT_MCI;
  471. }