qlcnic_ctx.c 35 KB

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  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. };
  40. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  41. {
  42. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  43. (0xcafe << 16);
  44. }
  45. /* Allocate mailbox registers */
  46. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  47. struct qlcnic_adapter *adapter, u32 type)
  48. {
  49. int i, size;
  50. const struct qlcnic_mailbox_metadata *mbx_tbl;
  51. mbx_tbl = qlcnic_mbx_tbl;
  52. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  53. for (i = 0; i < size; i++) {
  54. if (type == mbx_tbl[i].cmd) {
  55. mbx->req.num = mbx_tbl[i].in_args;
  56. mbx->rsp.num = mbx_tbl[i].out_args;
  57. mbx->req.arg = kcalloc(mbx->req.num,
  58. sizeof(u32), GFP_ATOMIC);
  59. if (!mbx->req.arg)
  60. return -ENOMEM;
  61. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  62. sizeof(u32), GFP_ATOMIC);
  63. if (!mbx->rsp.arg) {
  64. kfree(mbx->req.arg);
  65. mbx->req.arg = NULL;
  66. return -ENOMEM;
  67. }
  68. memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
  69. memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
  70. mbx->req.arg[0] = type;
  71. break;
  72. }
  73. }
  74. return 0;
  75. }
  76. /* Free up mailbox registers */
  77. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  78. {
  79. kfree(cmd->req.arg);
  80. cmd->req.arg = NULL;
  81. kfree(cmd->rsp.arg);
  82. cmd->rsp.arg = NULL;
  83. }
  84. static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
  85. {
  86. int i;
  87. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  88. if (adapter->npars[i].pci_func == pci_func)
  89. return i;
  90. }
  91. return -1;
  92. }
  93. static u32
  94. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  95. {
  96. u32 rsp;
  97. int timeout = 0;
  98. do {
  99. /* give atleast 1ms for firmware to respond */
  100. mdelay(1);
  101. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  102. return QLCNIC_CDRP_RSP_TIMEOUT;
  103. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
  104. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  105. return rsp;
  106. }
  107. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  108. struct qlcnic_cmd_args *cmd)
  109. {
  110. int i;
  111. u32 rsp;
  112. u32 signature;
  113. struct pci_dev *pdev = adapter->pdev;
  114. struct qlcnic_hardware_context *ahw = adapter->ahw;
  115. const char *fmt;
  116. signature = qlcnic_get_cmd_signature(ahw);
  117. /* Acquire semaphore before accessing CRB */
  118. if (qlcnic_api_lock(adapter)) {
  119. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  120. return cmd->rsp.arg[0];
  121. }
  122. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  123. for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
  124. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  125. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  126. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  127. rsp = qlcnic_poll_rsp(adapter);
  128. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  129. dev_err(&pdev->dev, "card response timeout.\n");
  130. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  131. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  132. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1));
  133. switch (cmd->rsp.arg[0]) {
  134. case QLCNIC_RCODE_INVALID_ARGS:
  135. fmt = "CDRP invalid args: [%d]\n";
  136. break;
  137. case QLCNIC_RCODE_NOT_SUPPORTED:
  138. case QLCNIC_RCODE_NOT_IMPL:
  139. fmt = "CDRP command not supported: [%d]\n";
  140. break;
  141. case QLCNIC_RCODE_NOT_PERMITTED:
  142. fmt = "CDRP requested action not permitted: [%d]\n";
  143. break;
  144. case QLCNIC_RCODE_INVALID:
  145. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  146. break;
  147. case QLCNIC_RCODE_TIMEOUT:
  148. fmt = "CDRP command timeout: [%d]\n";
  149. break;
  150. default:
  151. fmt = "CDRP command failed: [%d]\n";
  152. break;
  153. }
  154. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  155. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  156. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  157. for (i = 1; i < cmd->rsp.num; i++)
  158. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i));
  159. /* Release semaphore */
  160. qlcnic_api_unlock(adapter);
  161. return cmd->rsp.arg[0];
  162. }
  163. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  164. {
  165. struct qlcnic_cmd_args cmd;
  166. u32 arg1, arg2, arg3;
  167. char drv_string[12];
  168. int err = 0;
  169. memset(drv_string, 0, sizeof(drv_string));
  170. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  171. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  172. _QLCNIC_LINUX_SUBVERSION);
  173. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  174. if (err)
  175. return err;
  176. memcpy(&arg1, drv_string, sizeof(u32));
  177. memcpy(&arg2, drv_string + 4, sizeof(u32));
  178. memcpy(&arg3, drv_string + 8, sizeof(u32));
  179. cmd.req.arg[1] = arg1;
  180. cmd.req.arg[2] = arg2;
  181. cmd.req.arg[3] = arg3;
  182. err = qlcnic_issue_cmd(adapter, &cmd);
  183. if (err) {
  184. dev_info(&adapter->pdev->dev,
  185. "Failed to set driver version in firmware\n");
  186. return -EIO;
  187. }
  188. return 0;
  189. }
  190. int
  191. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  192. {
  193. int err = 0;
  194. struct qlcnic_cmd_args cmd;
  195. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  196. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  197. return err;
  198. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  199. if (err)
  200. return err;
  201. cmd.req.arg[1] = recv_ctx->context_id;
  202. cmd.req.arg[2] = mtu;
  203. err = qlcnic_issue_cmd(adapter, &cmd);
  204. if (err) {
  205. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  206. err = -EIO;
  207. }
  208. qlcnic_free_mbx_args(&cmd);
  209. return err;
  210. }
  211. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  212. {
  213. void *addr;
  214. struct qlcnic_hostrq_rx_ctx *prq;
  215. struct qlcnic_cardrsp_rx_ctx *prsp;
  216. struct qlcnic_hostrq_rds_ring *prq_rds;
  217. struct qlcnic_hostrq_sds_ring *prq_sds;
  218. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  219. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  220. struct qlcnic_host_rds_ring *rds_ring;
  221. struct qlcnic_host_sds_ring *sds_ring;
  222. struct qlcnic_cmd_args cmd;
  223. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  224. u64 phys_addr;
  225. u8 i, nrds_rings, nsds_rings;
  226. u16 temp_u16;
  227. size_t rq_size, rsp_size;
  228. u32 cap, reg, val, reg2;
  229. int err;
  230. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  231. nrds_rings = adapter->max_rds_rings;
  232. nsds_rings = adapter->max_sds_rings;
  233. rq_size =
  234. SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  235. nsds_rings);
  236. rsp_size =
  237. SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  238. nsds_rings);
  239. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  240. &hostrq_phys_addr, GFP_KERNEL);
  241. if (addr == NULL)
  242. return -ENOMEM;
  243. prq = addr;
  244. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  245. &cardrsp_phys_addr, GFP_KERNEL);
  246. if (addr == NULL) {
  247. err = -ENOMEM;
  248. goto out_free_rq;
  249. }
  250. prsp = addr;
  251. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  252. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  253. | QLCNIC_CAP0_VALIDOFF);
  254. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  255. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  256. prq->valid_field_offset = cpu_to_le16(temp_u16);
  257. prq->txrx_sds_binding = nsds_rings - 1;
  258. prq->capabilities[0] = cpu_to_le32(cap);
  259. prq->host_int_crb_mode =
  260. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  261. prq->host_rds_crb_mode =
  262. cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
  263. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  264. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  265. prq->rds_ring_offset = 0;
  266. val = le32_to_cpu(prq->rds_ring_offset) +
  267. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  268. prq->sds_ring_offset = cpu_to_le32(val);
  269. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  270. le32_to_cpu(prq->rds_ring_offset));
  271. for (i = 0; i < nrds_rings; i++) {
  272. rds_ring = &recv_ctx->rds_rings[i];
  273. rds_ring->producer = 0;
  274. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  275. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  276. prq_rds[i].ring_kind = cpu_to_le32(i);
  277. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  278. }
  279. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  280. le32_to_cpu(prq->sds_ring_offset));
  281. for (i = 0; i < nsds_rings; i++) {
  282. sds_ring = &recv_ctx->sds_rings[i];
  283. sds_ring->consumer = 0;
  284. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  285. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  286. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  287. prq_sds[i].msi_index = cpu_to_le16(i);
  288. }
  289. phys_addr = hostrq_phys_addr;
  290. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  291. if (err)
  292. goto out_free_rsp;
  293. cmd.req.arg[1] = MSD(phys_addr);
  294. cmd.req.arg[2] = LSD(phys_addr);
  295. cmd.req.arg[3] = rq_size;
  296. err = qlcnic_issue_cmd(adapter, &cmd);
  297. if (err) {
  298. dev_err(&adapter->pdev->dev,
  299. "Failed to create rx ctx in firmware%d\n", err);
  300. goto out_free_rsp;
  301. }
  302. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  303. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  304. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  305. rds_ring = &recv_ctx->rds_rings[i];
  306. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  307. rds_ring->crb_rcv_producer = adapter->ahw->pci_base0 + reg;
  308. }
  309. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  310. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  311. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  312. sds_ring = &recv_ctx->sds_rings[i];
  313. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  314. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  315. sds_ring->crb_sts_consumer = adapter->ahw->pci_base0 + reg;
  316. sds_ring->crb_intr_mask = adapter->ahw->pci_base0 + reg2;
  317. }
  318. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  319. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  320. recv_ctx->virt_port = prsp->virt_port;
  321. qlcnic_free_mbx_args(&cmd);
  322. out_free_rsp:
  323. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  324. cardrsp_phys_addr);
  325. out_free_rq:
  326. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  327. return err;
  328. }
  329. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  330. {
  331. int err;
  332. struct qlcnic_cmd_args cmd;
  333. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  334. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  335. if (err)
  336. return;
  337. cmd.req.arg[1] = recv_ctx->context_id;
  338. err = qlcnic_issue_cmd(adapter, &cmd);
  339. if (err)
  340. dev_err(&adapter->pdev->dev,
  341. "Failed to destroy rx ctx in firmware\n");
  342. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  343. qlcnic_free_mbx_args(&cmd);
  344. }
  345. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  346. struct qlcnic_host_tx_ring *tx_ring,
  347. int ring)
  348. {
  349. struct qlcnic_hostrq_tx_ctx *prq;
  350. struct qlcnic_hostrq_cds_ring *prq_cds;
  351. struct qlcnic_cardrsp_tx_ctx *prsp;
  352. void *rq_addr, *rsp_addr;
  353. size_t rq_size, rsp_size;
  354. u32 temp;
  355. struct qlcnic_cmd_args cmd;
  356. int err;
  357. u64 phys_addr;
  358. dma_addr_t rq_phys_addr, rsp_phys_addr;
  359. /* reset host resources */
  360. tx_ring->producer = 0;
  361. tx_ring->sw_consumer = 0;
  362. *(tx_ring->hw_consumer) = 0;
  363. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  364. rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  365. &rq_phys_addr, GFP_KERNEL | __GFP_ZERO);
  366. if (!rq_addr)
  367. return -ENOMEM;
  368. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  369. rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  370. &rsp_phys_addr, GFP_KERNEL | __GFP_ZERO);
  371. if (!rsp_addr) {
  372. err = -ENOMEM;
  373. goto out_free_rq;
  374. }
  375. prq = rq_addr;
  376. prsp = rsp_addr;
  377. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  378. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  379. QLCNIC_CAP0_LSO);
  380. prq->capabilities[0] = cpu_to_le32(temp);
  381. prq->host_int_crb_mode =
  382. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  383. prq->msi_index = 0;
  384. prq->interrupt_ctl = 0;
  385. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  386. prq_cds = &prq->cds_ring;
  387. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  388. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  389. phys_addr = rq_phys_addr;
  390. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  391. if (err)
  392. goto out_free_rsp;
  393. cmd.req.arg[1] = MSD(phys_addr);
  394. cmd.req.arg[2] = LSD(phys_addr);
  395. cmd.req.arg[3] = rq_size;
  396. err = qlcnic_issue_cmd(adapter, &cmd);
  397. if (err == QLCNIC_RCODE_SUCCESS) {
  398. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  399. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  400. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  401. } else {
  402. dev_err(&adapter->pdev->dev,
  403. "Failed to create tx ctx in firmware%d\n", err);
  404. err = -EIO;
  405. }
  406. qlcnic_free_mbx_args(&cmd);
  407. out_free_rsp:
  408. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  409. rsp_phys_addr);
  410. out_free_rq:
  411. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  412. return err;
  413. }
  414. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  415. struct qlcnic_host_tx_ring *tx_ring)
  416. {
  417. struct qlcnic_cmd_args cmd;
  418. int ret;
  419. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  420. if (ret)
  421. return;
  422. cmd.req.arg[1] = tx_ring->ctx_id;
  423. if (qlcnic_issue_cmd(adapter, &cmd))
  424. dev_err(&adapter->pdev->dev,
  425. "Failed to destroy tx ctx in firmware\n");
  426. qlcnic_free_mbx_args(&cmd);
  427. }
  428. int
  429. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  430. {
  431. int err;
  432. struct qlcnic_cmd_args cmd;
  433. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  434. if (err)
  435. return err;
  436. cmd.req.arg[1] = config;
  437. err = qlcnic_issue_cmd(adapter, &cmd);
  438. qlcnic_free_mbx_args(&cmd);
  439. return err;
  440. }
  441. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  442. {
  443. void *addr;
  444. int err, ring;
  445. struct qlcnic_recv_context *recv_ctx;
  446. struct qlcnic_host_rds_ring *rds_ring;
  447. struct qlcnic_host_sds_ring *sds_ring;
  448. struct qlcnic_host_tx_ring *tx_ring;
  449. __le32 *ptr;
  450. struct pci_dev *pdev = adapter->pdev;
  451. recv_ctx = adapter->recv_ctx;
  452. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  453. tx_ring = &adapter->tx_ring[ring];
  454. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  455. &tx_ring->hw_cons_phys_addr,
  456. GFP_KERNEL);
  457. if (ptr == NULL)
  458. return -ENOMEM;
  459. tx_ring->hw_consumer = ptr;
  460. /* cmd desc ring */
  461. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  462. &tx_ring->phys_addr,
  463. GFP_KERNEL);
  464. if (addr == NULL) {
  465. err = -ENOMEM;
  466. goto err_out_free;
  467. }
  468. tx_ring->desc_head = addr;
  469. }
  470. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  471. rds_ring = &recv_ctx->rds_rings[ring];
  472. addr = dma_alloc_coherent(&adapter->pdev->dev,
  473. RCV_DESC_RINGSIZE(rds_ring),
  474. &rds_ring->phys_addr, GFP_KERNEL);
  475. if (addr == NULL) {
  476. err = -ENOMEM;
  477. goto err_out_free;
  478. }
  479. rds_ring->desc_head = addr;
  480. }
  481. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  482. sds_ring = &recv_ctx->sds_rings[ring];
  483. addr = dma_alloc_coherent(&adapter->pdev->dev,
  484. STATUS_DESC_RINGSIZE(sds_ring),
  485. &sds_ring->phys_addr, GFP_KERNEL);
  486. if (addr == NULL) {
  487. err = -ENOMEM;
  488. goto err_out_free;
  489. }
  490. sds_ring->desc_head = addr;
  491. }
  492. return 0;
  493. err_out_free:
  494. qlcnic_free_hw_resources(adapter);
  495. return err;
  496. }
  497. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  498. {
  499. int i, err, ring;
  500. if (dev->flags & QLCNIC_NEED_FLR) {
  501. pci_reset_function(dev->pdev);
  502. dev->flags &= ~QLCNIC_NEED_FLR;
  503. }
  504. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  505. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  506. err = qlcnic_83xx_config_intrpt(dev, 1);
  507. if (err)
  508. return err;
  509. }
  510. }
  511. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  512. if (err)
  513. goto err_out;
  514. for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
  515. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  516. &dev->tx_ring[ring],
  517. ring);
  518. if (err) {
  519. qlcnic_fw_cmd_del_rx_ctx(dev);
  520. if (ring == 0)
  521. goto err_out;
  522. for (i = 0; i < ring; i++)
  523. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  524. goto err_out;
  525. }
  526. }
  527. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  528. return 0;
  529. err_out:
  530. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  531. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  532. qlcnic_83xx_config_intrpt(dev, 0);
  533. }
  534. return err;
  535. }
  536. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  537. {
  538. int ring;
  539. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  540. qlcnic_fw_cmd_del_rx_ctx(adapter);
  541. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
  542. qlcnic_fw_cmd_del_tx_ctx(adapter,
  543. &adapter->tx_ring[ring]);
  544. if (qlcnic_83xx_check(adapter) &&
  545. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  546. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  547. qlcnic_83xx_config_intrpt(adapter, 0);
  548. }
  549. /* Allow dma queues to drain after context reset */
  550. mdelay(20);
  551. }
  552. }
  553. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  554. {
  555. struct qlcnic_recv_context *recv_ctx;
  556. struct qlcnic_host_rds_ring *rds_ring;
  557. struct qlcnic_host_sds_ring *sds_ring;
  558. struct qlcnic_host_tx_ring *tx_ring;
  559. int ring;
  560. recv_ctx = adapter->recv_ctx;
  561. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  562. tx_ring = &adapter->tx_ring[ring];
  563. if (tx_ring->hw_consumer != NULL) {
  564. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  565. tx_ring->hw_consumer,
  566. tx_ring->hw_cons_phys_addr);
  567. tx_ring->hw_consumer = NULL;
  568. }
  569. if (tx_ring->desc_head != NULL) {
  570. dma_free_coherent(&adapter->pdev->dev,
  571. TX_DESC_RINGSIZE(tx_ring),
  572. tx_ring->desc_head,
  573. tx_ring->phys_addr);
  574. tx_ring->desc_head = NULL;
  575. }
  576. }
  577. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  578. rds_ring = &recv_ctx->rds_rings[ring];
  579. if (rds_ring->desc_head != NULL) {
  580. dma_free_coherent(&adapter->pdev->dev,
  581. RCV_DESC_RINGSIZE(rds_ring),
  582. rds_ring->desc_head,
  583. rds_ring->phys_addr);
  584. rds_ring->desc_head = NULL;
  585. }
  586. }
  587. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  588. sds_ring = &recv_ctx->sds_rings[ring];
  589. if (sds_ring->desc_head != NULL) {
  590. dma_free_coherent(&adapter->pdev->dev,
  591. STATUS_DESC_RINGSIZE(sds_ring),
  592. sds_ring->desc_head,
  593. sds_ring->phys_addr);
  594. sds_ring->desc_head = NULL;
  595. }
  596. }
  597. }
  598. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
  599. {
  600. int err, i;
  601. struct qlcnic_cmd_args cmd;
  602. u32 mac_low, mac_high;
  603. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  604. if (err)
  605. return err;
  606. cmd.req.arg[1] = adapter->ahw->pci_func | BIT_8;
  607. err = qlcnic_issue_cmd(adapter, &cmd);
  608. if (err == QLCNIC_RCODE_SUCCESS) {
  609. mac_low = cmd.rsp.arg[1];
  610. mac_high = cmd.rsp.arg[2];
  611. for (i = 0; i < 2; i++)
  612. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  613. for (i = 2; i < 6; i++)
  614. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  615. } else {
  616. dev_err(&adapter->pdev->dev,
  617. "Failed to get mac address%d\n", err);
  618. err = -EIO;
  619. }
  620. qlcnic_free_mbx_args(&cmd);
  621. return err;
  622. }
  623. /* Get info of a NIC partition */
  624. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  625. struct qlcnic_info *npar_info, u8 func_id)
  626. {
  627. int err;
  628. dma_addr_t nic_dma_t;
  629. const struct qlcnic_info_le *nic_info;
  630. void *nic_info_addr;
  631. struct qlcnic_cmd_args cmd;
  632. size_t nic_size = sizeof(struct qlcnic_info_le);
  633. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  634. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  635. if (!nic_info_addr)
  636. return -ENOMEM;
  637. nic_info = nic_info_addr;
  638. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  639. if (err)
  640. goto out_free_dma;
  641. cmd.req.arg[1] = MSD(nic_dma_t);
  642. cmd.req.arg[2] = LSD(nic_dma_t);
  643. cmd.req.arg[3] = (func_id << 16 | nic_size);
  644. err = qlcnic_issue_cmd(adapter, &cmd);
  645. if (err != QLCNIC_RCODE_SUCCESS) {
  646. dev_err(&adapter->pdev->dev,
  647. "Failed to get nic info%d\n", err);
  648. err = -EIO;
  649. } else {
  650. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  651. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  652. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  653. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  654. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  655. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  656. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  657. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  658. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  659. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  660. }
  661. qlcnic_free_mbx_args(&cmd);
  662. out_free_dma:
  663. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  664. nic_dma_t);
  665. return err;
  666. }
  667. /* Configure a NIC partition */
  668. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  669. struct qlcnic_info *nic)
  670. {
  671. int err = -EIO;
  672. dma_addr_t nic_dma_t;
  673. void *nic_info_addr;
  674. struct qlcnic_cmd_args cmd;
  675. struct qlcnic_info_le *nic_info;
  676. size_t nic_size = sizeof(struct qlcnic_info_le);
  677. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  678. return err;
  679. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  680. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  681. if (!nic_info_addr)
  682. return -ENOMEM;
  683. nic_info = nic_info_addr;
  684. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  685. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  686. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  687. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  688. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  689. nic_info->max_mac_filters = nic->max_mac_filters;
  690. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  691. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  692. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  693. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  694. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  695. if (err)
  696. goto out_free_dma;
  697. cmd.req.arg[1] = MSD(nic_dma_t);
  698. cmd.req.arg[2] = LSD(nic_dma_t);
  699. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  700. err = qlcnic_issue_cmd(adapter, &cmd);
  701. if (err != QLCNIC_RCODE_SUCCESS) {
  702. dev_err(&adapter->pdev->dev,
  703. "Failed to set nic info%d\n", err);
  704. err = -EIO;
  705. }
  706. qlcnic_free_mbx_args(&cmd);
  707. out_free_dma:
  708. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  709. nic_dma_t);
  710. return err;
  711. }
  712. /* Get PCI Info of a partition */
  713. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  714. struct qlcnic_pci_info *pci_info)
  715. {
  716. int err = 0, i;
  717. struct qlcnic_cmd_args cmd;
  718. dma_addr_t pci_info_dma_t;
  719. struct qlcnic_pci_info_le *npar;
  720. void *pci_info_addr;
  721. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  722. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  723. pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
  724. &pci_info_dma_t,
  725. GFP_KERNEL | __GFP_ZERO);
  726. if (!pci_info_addr)
  727. return -ENOMEM;
  728. npar = pci_info_addr;
  729. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  730. if (err)
  731. goto out_free_dma;
  732. cmd.req.arg[1] = MSD(pci_info_dma_t);
  733. cmd.req.arg[2] = LSD(pci_info_dma_t);
  734. cmd.req.arg[3] = pci_size;
  735. err = qlcnic_issue_cmd(adapter, &cmd);
  736. adapter->ahw->act_pci_func = 0;
  737. if (err == QLCNIC_RCODE_SUCCESS) {
  738. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
  739. pci_info->id = le16_to_cpu(npar->id);
  740. pci_info->active = le16_to_cpu(npar->active);
  741. pci_info->type = le16_to_cpu(npar->type);
  742. if (pci_info->type == QLCNIC_TYPE_NIC)
  743. adapter->ahw->act_pci_func++;
  744. pci_info->default_port =
  745. le16_to_cpu(npar->default_port);
  746. pci_info->tx_min_bw =
  747. le16_to_cpu(npar->tx_min_bw);
  748. pci_info->tx_max_bw =
  749. le16_to_cpu(npar->tx_max_bw);
  750. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  751. }
  752. } else {
  753. dev_err(&adapter->pdev->dev,
  754. "Failed to get PCI Info%d\n", err);
  755. err = -EIO;
  756. }
  757. qlcnic_free_mbx_args(&cmd);
  758. out_free_dma:
  759. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  760. pci_info_dma_t);
  761. return err;
  762. }
  763. /* Configure eSwitch for port mirroring */
  764. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  765. u8 enable_mirroring, u8 pci_func)
  766. {
  767. struct device *dev = &adapter->pdev->dev;
  768. struct qlcnic_cmd_args cmd;
  769. int err = -EIO;
  770. u32 arg1;
  771. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  772. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  773. return err;
  774. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  775. arg1 |= pci_func << 8;
  776. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  777. QLCNIC_CMD_SET_PORTMIRRORING);
  778. if (err)
  779. return err;
  780. cmd.req.arg[1] = arg1;
  781. err = qlcnic_issue_cmd(adapter, &cmd);
  782. if (err != QLCNIC_RCODE_SUCCESS)
  783. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  784. pci_func, id);
  785. else
  786. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  787. pci_func, id);
  788. qlcnic_free_mbx_args(&cmd);
  789. return err;
  790. }
  791. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  792. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  793. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  794. struct qlcnic_esw_stats_le *stats;
  795. dma_addr_t stats_dma_t;
  796. void *stats_addr;
  797. u32 arg1;
  798. struct qlcnic_cmd_args cmd;
  799. int err;
  800. if (esw_stats == NULL)
  801. return -ENOMEM;
  802. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  803. (func != adapter->ahw->pci_func)) {
  804. dev_err(&adapter->pdev->dev,
  805. "Not privilege to query stats for func=%d", func);
  806. return -EIO;
  807. }
  808. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  809. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  810. if (!stats_addr)
  811. return -ENOMEM;
  812. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  813. arg1 |= rx_tx << 15 | stats_size << 16;
  814. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  815. QLCNIC_CMD_GET_ESWITCH_STATS);
  816. if (err)
  817. goto out_free_dma;
  818. cmd.req.arg[1] = arg1;
  819. cmd.req.arg[2] = MSD(stats_dma_t);
  820. cmd.req.arg[3] = LSD(stats_dma_t);
  821. err = qlcnic_issue_cmd(adapter, &cmd);
  822. if (!err) {
  823. stats = stats_addr;
  824. esw_stats->context_id = le16_to_cpu(stats->context_id);
  825. esw_stats->version = le16_to_cpu(stats->version);
  826. esw_stats->size = le16_to_cpu(stats->size);
  827. esw_stats->multicast_frames =
  828. le64_to_cpu(stats->multicast_frames);
  829. esw_stats->broadcast_frames =
  830. le64_to_cpu(stats->broadcast_frames);
  831. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  832. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  833. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  834. esw_stats->errors = le64_to_cpu(stats->errors);
  835. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  836. }
  837. qlcnic_free_mbx_args(&cmd);
  838. out_free_dma:
  839. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  840. stats_dma_t);
  841. return err;
  842. }
  843. /* This routine will retrieve the MAC statistics from firmware */
  844. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  845. struct qlcnic_mac_statistics *mac_stats)
  846. {
  847. struct qlcnic_mac_statistics_le *stats;
  848. struct qlcnic_cmd_args cmd;
  849. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  850. dma_addr_t stats_dma_t;
  851. void *stats_addr;
  852. int err;
  853. if (mac_stats == NULL)
  854. return -ENOMEM;
  855. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  856. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  857. if (!stats_addr)
  858. return -ENOMEM;
  859. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  860. if (err)
  861. goto out_free_dma;
  862. cmd.req.arg[1] = stats_size << 16;
  863. cmd.req.arg[2] = MSD(stats_dma_t);
  864. cmd.req.arg[3] = LSD(stats_dma_t);
  865. err = qlcnic_issue_cmd(adapter, &cmd);
  866. if (!err) {
  867. stats = stats_addr;
  868. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  869. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  870. mac_stats->mac_tx_mcast_pkts =
  871. le64_to_cpu(stats->mac_tx_mcast_pkts);
  872. mac_stats->mac_tx_bcast_pkts =
  873. le64_to_cpu(stats->mac_tx_bcast_pkts);
  874. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  875. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  876. mac_stats->mac_rx_mcast_pkts =
  877. le64_to_cpu(stats->mac_rx_mcast_pkts);
  878. mac_stats->mac_rx_length_error =
  879. le64_to_cpu(stats->mac_rx_length_error);
  880. mac_stats->mac_rx_length_small =
  881. le64_to_cpu(stats->mac_rx_length_small);
  882. mac_stats->mac_rx_length_large =
  883. le64_to_cpu(stats->mac_rx_length_large);
  884. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  885. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  886. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  887. } else {
  888. dev_err(&adapter->pdev->dev,
  889. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  890. }
  891. qlcnic_free_mbx_args(&cmd);
  892. out_free_dma:
  893. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  894. stats_dma_t);
  895. return err;
  896. }
  897. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  898. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  899. struct __qlcnic_esw_statistics port_stats;
  900. u8 i;
  901. int ret = -EIO;
  902. if (esw_stats == NULL)
  903. return -ENOMEM;
  904. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  905. return -EIO;
  906. if (adapter->npars == NULL)
  907. return -EIO;
  908. memset(esw_stats, 0, sizeof(u64));
  909. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  910. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  911. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  912. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  913. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  914. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  915. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  916. esw_stats->context_id = eswitch;
  917. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  918. if (adapter->npars[i].phy_port != eswitch)
  919. continue;
  920. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  921. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  922. rx_tx, &port_stats))
  923. continue;
  924. esw_stats->size = port_stats.size;
  925. esw_stats->version = port_stats.version;
  926. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  927. port_stats.unicast_frames);
  928. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  929. port_stats.multicast_frames);
  930. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  931. port_stats.broadcast_frames);
  932. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  933. port_stats.dropped_frames);
  934. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  935. port_stats.errors);
  936. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  937. port_stats.local_frames);
  938. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  939. port_stats.numbytes);
  940. ret = 0;
  941. }
  942. return ret;
  943. }
  944. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  945. const u8 port, const u8 rx_tx)
  946. {
  947. int err;
  948. u32 arg1;
  949. struct qlcnic_cmd_args cmd;
  950. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  951. return -EIO;
  952. if (func_esw == QLCNIC_STATS_PORT) {
  953. if (port >= QLCNIC_MAX_PCI_FUNC)
  954. goto err_ret;
  955. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  956. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  957. goto err_ret;
  958. } else {
  959. goto err_ret;
  960. }
  961. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  962. goto err_ret;
  963. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  964. arg1 |= BIT_14 | rx_tx << 15;
  965. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  966. QLCNIC_CMD_GET_ESWITCH_STATS);
  967. if (err)
  968. return err;
  969. cmd.req.arg[1] = arg1;
  970. err = qlcnic_issue_cmd(adapter, &cmd);
  971. qlcnic_free_mbx_args(&cmd);
  972. return err;
  973. err_ret:
  974. dev_err(&adapter->pdev->dev,
  975. "Invalid args func_esw %d port %d rx_ctx %d\n",
  976. func_esw, port, rx_tx);
  977. return -EIO;
  978. }
  979. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  980. u32 *arg1, u32 *arg2)
  981. {
  982. struct device *dev = &adapter->pdev->dev;
  983. struct qlcnic_cmd_args cmd;
  984. u8 pci_func = *arg1 >> 8;
  985. int err;
  986. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  987. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  988. if (err)
  989. return err;
  990. cmd.req.arg[1] = *arg1;
  991. err = qlcnic_issue_cmd(adapter, &cmd);
  992. *arg1 = cmd.rsp.arg[1];
  993. *arg2 = cmd.rsp.arg[2];
  994. qlcnic_free_mbx_args(&cmd);
  995. if (err == QLCNIC_RCODE_SUCCESS)
  996. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  997. pci_func);
  998. else
  999. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1000. pci_func);
  1001. return err;
  1002. }
  1003. /* Configure eSwitch port
  1004. op_mode = 0 for setting default port behavior
  1005. op_mode = 1 for setting vlan id
  1006. op_mode = 2 for deleting vlan id
  1007. op_type = 0 for vlan_id
  1008. op_type = 1 for port vlan_id
  1009. */
  1010. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1011. struct qlcnic_esw_func_cfg *esw_cfg)
  1012. {
  1013. struct device *dev = &adapter->pdev->dev;
  1014. struct qlcnic_cmd_args cmd;
  1015. int err = -EIO, index;
  1016. u32 arg1, arg2 = 0;
  1017. u8 pci_func;
  1018. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1019. return err;
  1020. pci_func = esw_cfg->pci_func;
  1021. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1022. if (index < 0)
  1023. return err;
  1024. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1025. arg1 |= (pci_func << 8);
  1026. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1027. return err;
  1028. arg1 &= ~(0x0ff << 8);
  1029. arg1 |= (pci_func << 8);
  1030. arg1 &= ~(BIT_2 | BIT_3);
  1031. switch (esw_cfg->op_mode) {
  1032. case QLCNIC_PORT_DEFAULTS:
  1033. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1034. arg2 |= (BIT_0 | BIT_1);
  1035. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1036. arg2 |= (BIT_2 | BIT_3);
  1037. if (!(esw_cfg->discard_tagged))
  1038. arg1 &= ~BIT_4;
  1039. if (!(esw_cfg->promisc_mode))
  1040. arg1 &= ~BIT_6;
  1041. if (!(esw_cfg->mac_override))
  1042. arg1 &= ~BIT_7;
  1043. if (!(esw_cfg->mac_anti_spoof))
  1044. arg2 &= ~BIT_0;
  1045. if (!(esw_cfg->offload_flags & BIT_0))
  1046. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1047. if (!(esw_cfg->offload_flags & BIT_1))
  1048. arg2 &= ~BIT_2;
  1049. if (!(esw_cfg->offload_flags & BIT_2))
  1050. arg2 &= ~BIT_3;
  1051. break;
  1052. case QLCNIC_ADD_VLAN:
  1053. arg1 |= (BIT_2 | BIT_5);
  1054. arg1 |= (esw_cfg->vlan_id << 16);
  1055. break;
  1056. case QLCNIC_DEL_VLAN:
  1057. arg1 |= (BIT_3 | BIT_5);
  1058. arg1 &= ~(0x0ffff << 16);
  1059. break;
  1060. default:
  1061. return err;
  1062. }
  1063. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1064. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1065. if (err)
  1066. return err;
  1067. cmd.req.arg[1] = arg1;
  1068. cmd.req.arg[2] = arg2;
  1069. err = qlcnic_issue_cmd(adapter, &cmd);
  1070. qlcnic_free_mbx_args(&cmd);
  1071. if (err != QLCNIC_RCODE_SUCCESS)
  1072. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1073. pci_func);
  1074. else
  1075. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1076. pci_func);
  1077. return err;
  1078. }
  1079. int
  1080. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1081. struct qlcnic_esw_func_cfg *esw_cfg)
  1082. {
  1083. u32 arg1, arg2;
  1084. int index;
  1085. u8 phy_port;
  1086. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1087. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1088. if (index < 0)
  1089. return -EIO;
  1090. phy_port = adapter->npars[index].phy_port;
  1091. } else {
  1092. phy_port = adapter->ahw->physical_port;
  1093. }
  1094. arg1 = phy_port;
  1095. arg1 |= (esw_cfg->pci_func << 8);
  1096. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1097. return -EIO;
  1098. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1099. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1100. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1101. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1102. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1103. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1104. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1105. return 0;
  1106. }