clk-mux.c 4.1 KB

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  1. /*
  2. * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  3. * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  4. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Simple multiplexer clock implementation
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/module.h>
  15. #include <linux/slab.h>
  16. #include <linux/io.h>
  17. #include <linux/err.h>
  18. /*
  19. * DOC: basic adjustable multiplexer clock that cannot gate
  20. *
  21. * Traits of this clock:
  22. * prepare - clk_prepare only ensures that parents are prepared
  23. * enable - clk_enable only ensures that parents are enabled
  24. * rate - rate is only affected by parent switching. No clk_set_rate support
  25. * parent - parent is adjustable through clk_set_parent
  26. */
  27. #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  28. static u8 clk_mux_get_parent(struct clk_hw *hw)
  29. {
  30. struct clk_mux *mux = to_clk_mux(hw);
  31. int num_parents = __clk_get_num_parents(hw->clk);
  32. u32 val;
  33. /*
  34. * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  35. * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  36. * to 0x7 (index starts at one)
  37. * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  38. * val = 0x4 really means "bit 2, index starts at bit 0"
  39. */
  40. val = readl(mux->reg) >> mux->shift;
  41. val &= mux->mask;
  42. if (mux->table) {
  43. int i;
  44. for (i = 0; i < num_parents; i++)
  45. if (mux->table[i] == val)
  46. return i;
  47. return -EINVAL;
  48. }
  49. if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  50. val = ffs(val) - 1;
  51. if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  52. val--;
  53. if (val >= num_parents)
  54. return -EINVAL;
  55. return val;
  56. }
  57. static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
  58. {
  59. struct clk_mux *mux = to_clk_mux(hw);
  60. u32 val;
  61. unsigned long flags = 0;
  62. if (mux->table)
  63. index = mux->table[index];
  64. else {
  65. if (mux->flags & CLK_MUX_INDEX_BIT)
  66. index = (1 << ffs(index));
  67. if (mux->flags & CLK_MUX_INDEX_ONE)
  68. index++;
  69. }
  70. if (mux->lock)
  71. spin_lock_irqsave(mux->lock, flags);
  72. if (mux->flags & CLK_MUX_HIWORD_MASK) {
  73. val = mux->mask << (mux->shift + 16);
  74. } else {
  75. val = readl(mux->reg);
  76. val &= ~(mux->mask << mux->shift);
  77. }
  78. val |= index << mux->shift;
  79. writel(val, mux->reg);
  80. if (mux->lock)
  81. spin_unlock_irqrestore(mux->lock, flags);
  82. return 0;
  83. }
  84. const struct clk_ops clk_mux_ops = {
  85. .get_parent = clk_mux_get_parent,
  86. .set_parent = clk_mux_set_parent,
  87. };
  88. EXPORT_SYMBOL_GPL(clk_mux_ops);
  89. struct clk *clk_register_mux_table(struct device *dev, const char *name,
  90. const char **parent_names, u8 num_parents, unsigned long flags,
  91. void __iomem *reg, u8 shift, u32 mask,
  92. u8 clk_mux_flags, u32 *table, spinlock_t *lock)
  93. {
  94. struct clk_mux *mux;
  95. struct clk *clk;
  96. struct clk_init_data init;
  97. u8 width = 0;
  98. if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
  99. width = fls(mask) - ffs(mask) + 1;
  100. if (width + shift > 16) {
  101. pr_err("mux value exceeds LOWORD field\n");
  102. return ERR_PTR(-EINVAL);
  103. }
  104. }
  105. /* allocate the mux */
  106. mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
  107. if (!mux) {
  108. pr_err("%s: could not allocate mux clk\n", __func__);
  109. return ERR_PTR(-ENOMEM);
  110. }
  111. init.name = name;
  112. init.ops = &clk_mux_ops;
  113. init.flags = flags | CLK_IS_BASIC;
  114. init.parent_names = parent_names;
  115. init.num_parents = num_parents;
  116. /* struct clk_mux assignments */
  117. mux->reg = reg;
  118. mux->shift = shift;
  119. mux->mask = mask;
  120. mux->flags = clk_mux_flags;
  121. mux->lock = lock;
  122. mux->table = table;
  123. mux->hw.init = &init;
  124. clk = clk_register(dev, &mux->hw);
  125. if (IS_ERR(clk))
  126. kfree(mux);
  127. return clk;
  128. }
  129. struct clk *clk_register_mux(struct device *dev, const char *name,
  130. const char **parent_names, u8 num_parents, unsigned long flags,
  131. void __iomem *reg, u8 shift, u8 width,
  132. u8 clk_mux_flags, spinlock_t *lock)
  133. {
  134. u32 mask = BIT(width) - 1;
  135. return clk_register_mux_table(dev, name, parent_names, num_parents,
  136. flags, reg, shift, mask, clk_mux_flags,
  137. NULL, lock);
  138. }