common.c 10 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Common Codes for EXYNOS
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/bitops.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/io.h>
  17. #include <linux/device.h>
  18. #include <linux/gpio.h>
  19. #include <clocksource/samsung_pwm.h>
  20. #include <linux/sched.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/of.h>
  23. #include <linux/of_fdt.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/export.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/of_address.h>
  28. #include <linux/clocksource.h>
  29. #include <linux/clk-provider.h>
  30. #include <linux/irqchip/arm-gic.h>
  31. #include <linux/irqchip/chained_irq.h>
  32. #include <asm/proc-fns.h>
  33. #include <asm/exception.h>
  34. #include <asm/hardware/cache-l2x0.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/mach/irq.h>
  37. #include <asm/cacheflush.h>
  38. #include <mach/regs-irq.h>
  39. #include <mach/regs-pmu.h>
  40. #include <plat/cpu.h>
  41. #include <plat/pm.h>
  42. #include <plat/regs-serial.h>
  43. #include "common.h"
  44. #define L2_AUX_VAL 0x7C470001
  45. #define L2_AUX_MASK 0xC200ffff
  46. static const char name_exynos4210[] = "EXYNOS4210";
  47. static const char name_exynos4212[] = "EXYNOS4212";
  48. static const char name_exynos4412[] = "EXYNOS4412";
  49. static const char name_exynos5250[] = "EXYNOS5250";
  50. static const char name_exynos5420[] = "EXYNOS5420";
  51. static const char name_exynos5440[] = "EXYNOS5440";
  52. static void exynos4_map_io(void);
  53. static void exynos5_map_io(void);
  54. static void exynos5440_map_io(void);
  55. static int exynos_init(void);
  56. static struct cpu_table cpu_ids[] __initdata = {
  57. {
  58. .idcode = EXYNOS4210_CPU_ID,
  59. .idmask = EXYNOS4_CPU_MASK,
  60. .map_io = exynos4_map_io,
  61. .init = exynos_init,
  62. .name = name_exynos4210,
  63. }, {
  64. .idcode = EXYNOS4212_CPU_ID,
  65. .idmask = EXYNOS4_CPU_MASK,
  66. .map_io = exynos4_map_io,
  67. .init = exynos_init,
  68. .name = name_exynos4212,
  69. }, {
  70. .idcode = EXYNOS4412_CPU_ID,
  71. .idmask = EXYNOS4_CPU_MASK,
  72. .map_io = exynos4_map_io,
  73. .init = exynos_init,
  74. .name = name_exynos4412,
  75. }, {
  76. .idcode = EXYNOS5250_SOC_ID,
  77. .idmask = EXYNOS5_SOC_MASK,
  78. .map_io = exynos5_map_io,
  79. .init = exynos_init,
  80. .name = name_exynos5250,
  81. }, {
  82. .idcode = EXYNOS5420_SOC_ID,
  83. .idmask = EXYNOS5_SOC_MASK,
  84. .map_io = exynos5_map_io,
  85. .init = exynos_init,
  86. .name = name_exynos5420,
  87. }, {
  88. .idcode = EXYNOS5440_SOC_ID,
  89. .idmask = EXYNOS5_SOC_MASK,
  90. .map_io = exynos5440_map_io,
  91. .init = exynos_init,
  92. .name = name_exynos5440,
  93. },
  94. };
  95. /* Initial IO mappings */
  96. static struct map_desc exynos4_iodesc[] __initdata = {
  97. {
  98. .virtual = (unsigned long)S3C_VA_SYS,
  99. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  100. .length = SZ_64K,
  101. .type = MT_DEVICE,
  102. }, {
  103. .virtual = (unsigned long)S3C_VA_TIMER,
  104. .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
  105. .length = SZ_16K,
  106. .type = MT_DEVICE,
  107. }, {
  108. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  109. .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  110. .length = SZ_4K,
  111. .type = MT_DEVICE,
  112. }, {
  113. .virtual = (unsigned long)S5P_VA_SROMC,
  114. .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
  115. .length = SZ_4K,
  116. .type = MT_DEVICE,
  117. }, {
  118. .virtual = (unsigned long)S5P_VA_SYSTIMER,
  119. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  120. .length = SZ_4K,
  121. .type = MT_DEVICE,
  122. }, {
  123. .virtual = (unsigned long)S5P_VA_PMU,
  124. .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
  125. .length = SZ_64K,
  126. .type = MT_DEVICE,
  127. }, {
  128. .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
  129. .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  130. .length = SZ_4K,
  131. .type = MT_DEVICE,
  132. }, {
  133. .virtual = (unsigned long)S5P_VA_GIC_CPU,
  134. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  135. .length = SZ_64K,
  136. .type = MT_DEVICE,
  137. }, {
  138. .virtual = (unsigned long)S5P_VA_GIC_DIST,
  139. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  140. .length = SZ_64K,
  141. .type = MT_DEVICE,
  142. }, {
  143. .virtual = (unsigned long)S3C_VA_UART,
  144. .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
  145. .length = SZ_512K,
  146. .type = MT_DEVICE,
  147. }, {
  148. .virtual = (unsigned long)S5P_VA_CMU,
  149. .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
  150. .length = SZ_128K,
  151. .type = MT_DEVICE,
  152. }, {
  153. .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
  154. .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  155. .length = SZ_8K,
  156. .type = MT_DEVICE,
  157. }, {
  158. .virtual = (unsigned long)S5P_VA_L2CC,
  159. .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
  160. .length = SZ_4K,
  161. .type = MT_DEVICE,
  162. }, {
  163. .virtual = (unsigned long)S5P_VA_DMC0,
  164. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
  165. .length = SZ_64K,
  166. .type = MT_DEVICE,
  167. }, {
  168. .virtual = (unsigned long)S5P_VA_DMC1,
  169. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
  170. .length = SZ_64K,
  171. .type = MT_DEVICE,
  172. }, {
  173. .virtual = (unsigned long)S3C_VA_USB_HSPHY,
  174. .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
  175. .length = SZ_4K,
  176. .type = MT_DEVICE,
  177. },
  178. };
  179. static struct map_desc exynos4_iodesc0[] __initdata = {
  180. {
  181. .virtual = (unsigned long)S5P_VA_SYSRAM,
  182. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
  183. .length = SZ_4K,
  184. .type = MT_DEVICE,
  185. },
  186. };
  187. static struct map_desc exynos4_iodesc1[] __initdata = {
  188. {
  189. .virtual = (unsigned long)S5P_VA_SYSRAM,
  190. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
  191. .length = SZ_4K,
  192. .type = MT_DEVICE,
  193. },
  194. };
  195. static struct map_desc exynos4210_iodesc[] __initdata = {
  196. {
  197. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  198. .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
  199. .length = SZ_4K,
  200. .type = MT_DEVICE,
  201. },
  202. };
  203. static struct map_desc exynos4x12_iodesc[] __initdata = {
  204. {
  205. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  206. .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
  207. .length = SZ_4K,
  208. .type = MT_DEVICE,
  209. },
  210. };
  211. static struct map_desc exynos5250_iodesc[] __initdata = {
  212. {
  213. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  214. .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
  215. .length = SZ_4K,
  216. .type = MT_DEVICE,
  217. },
  218. };
  219. static struct map_desc exynos5_iodesc[] __initdata = {
  220. {
  221. .virtual = (unsigned long)S3C_VA_SYS,
  222. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
  223. .length = SZ_64K,
  224. .type = MT_DEVICE,
  225. }, {
  226. .virtual = (unsigned long)S3C_VA_TIMER,
  227. .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
  228. .length = SZ_16K,
  229. .type = MT_DEVICE,
  230. }, {
  231. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  232. .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
  233. .length = SZ_4K,
  234. .type = MT_DEVICE,
  235. }, {
  236. .virtual = (unsigned long)S5P_VA_SROMC,
  237. .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
  238. .length = SZ_4K,
  239. .type = MT_DEVICE,
  240. }, {
  241. .virtual = (unsigned long)S5P_VA_SYSRAM,
  242. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
  243. .length = SZ_4K,
  244. .type = MT_DEVICE,
  245. }, {
  246. .virtual = (unsigned long)S5P_VA_CMU,
  247. .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
  248. .length = 144 * SZ_1K,
  249. .type = MT_DEVICE,
  250. }, {
  251. .virtual = (unsigned long)S5P_VA_PMU,
  252. .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
  253. .length = SZ_64K,
  254. .type = MT_DEVICE,
  255. }, {
  256. .virtual = (unsigned long)S3C_VA_UART,
  257. .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
  258. .length = SZ_512K,
  259. .type = MT_DEVICE,
  260. },
  261. };
  262. static struct map_desc exynos5440_iodesc0[] __initdata = {
  263. {
  264. .virtual = (unsigned long)S3C_VA_UART,
  265. .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
  266. .length = SZ_512K,
  267. .type = MT_DEVICE,
  268. },
  269. };
  270. void exynos4_restart(enum reboot_mode mode, const char *cmd)
  271. {
  272. __raw_writel(0x1, S5P_SWRESET);
  273. }
  274. void exynos5_restart(enum reboot_mode mode, const char *cmd)
  275. {
  276. struct device_node *np;
  277. u32 val;
  278. void __iomem *addr;
  279. val = 0x1;
  280. addr = EXYNOS_SWRESET;
  281. if (of_machine_is_compatible("samsung,exynos5440")) {
  282. u32 status;
  283. np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
  284. addr = of_iomap(np, 0) + 0xbc;
  285. status = __raw_readl(addr);
  286. addr = of_iomap(np, 0) + 0xcc;
  287. val = __raw_readl(addr);
  288. val = (val & 0xffff0000) | (status & 0xffff);
  289. }
  290. __raw_writel(val, addr);
  291. }
  292. void __init exynos_init_late(void)
  293. {
  294. if (of_machine_is_compatible("samsung,exynos5440"))
  295. /* to be supported later */
  296. return;
  297. exynos_pm_late_initcall();
  298. }
  299. static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  300. int depth, void *data)
  301. {
  302. struct map_desc iodesc;
  303. __be32 *reg;
  304. unsigned long len;
  305. if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
  306. !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
  307. return 0;
  308. reg = of_get_flat_dt_prop(node, "reg", &len);
  309. if (reg == NULL || len != (sizeof(unsigned long) * 2))
  310. return 0;
  311. iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
  312. iodesc.length = be32_to_cpu(reg[1]) - 1;
  313. iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
  314. iodesc.type = MT_DEVICE;
  315. iotable_init(&iodesc, 1);
  316. return 1;
  317. }
  318. /*
  319. * exynos_map_io
  320. *
  321. * register the standard cpu IO areas
  322. */
  323. void __init exynos_init_io(void)
  324. {
  325. debug_ll_io_init();
  326. of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
  327. /* detect cpu id and rev. */
  328. s5p_init_cpu(S5P_VA_CHIPID);
  329. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  330. }
  331. static void __init exynos4_map_io(void)
  332. {
  333. iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
  334. if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
  335. iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
  336. else
  337. iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
  338. if (soc_is_exynos4210())
  339. iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
  340. if (soc_is_exynos4212() || soc_is_exynos4412())
  341. iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
  342. }
  343. static void __init exynos5_map_io(void)
  344. {
  345. iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
  346. if (soc_is_exynos5250())
  347. iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
  348. }
  349. static void __init exynos5440_map_io(void)
  350. {
  351. iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
  352. }
  353. void __init exynos_init_time(void)
  354. {
  355. of_clk_init(NULL);
  356. clocksource_of_init();
  357. }
  358. struct bus_type exynos_subsys = {
  359. .name = "exynos-core",
  360. .dev_name = "exynos-core",
  361. };
  362. static struct device exynos4_dev = {
  363. .bus = &exynos_subsys,
  364. };
  365. static int __init exynos_core_init(void)
  366. {
  367. return subsys_system_register(&exynos_subsys, NULL);
  368. }
  369. core_initcall(exynos_core_init);
  370. static int __init exynos4_l2x0_cache_init(void)
  371. {
  372. int ret;
  373. ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
  374. if (ret)
  375. return ret;
  376. l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  377. clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
  378. return 0;
  379. }
  380. early_initcall(exynos4_l2x0_cache_init);
  381. static int __init exynos_init(void)
  382. {
  383. printk(KERN_INFO "EXYNOS: Initializing architecture\n");
  384. return device_register(&exynos4_dev);
  385. }