system.h 4.7 KB

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  1. /* system.h: FR-V CPU control definitions
  2. *
  3. * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #ifndef _ASM_SYSTEM_H
  12. #define _ASM_SYSTEM_H
  13. #include <linux/types.h>
  14. #include <linux/linkage.h>
  15. #include <linux/kernel.h>
  16. struct thread_struct;
  17. /*
  18. * switch_to(prev, next) should switch from task `prev' to `next'
  19. * `prev' will never be the same as `next'.
  20. * The `mb' is to tell GCC not to cache `current' across this call.
  21. */
  22. extern asmlinkage
  23. struct task_struct *__switch_to(struct thread_struct *prev_thread,
  24. struct thread_struct *next_thread,
  25. struct task_struct *prev);
  26. #define switch_to(prev, next, last) \
  27. do { \
  28. (prev)->thread.sched_lr = \
  29. (unsigned long) __builtin_return_address(0); \
  30. (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
  31. mb(); \
  32. } while(0)
  33. /*
  34. * Force strict CPU ordering.
  35. */
  36. #define nop() asm volatile ("nop"::)
  37. #define mb() asm volatile ("membar" : : :"memory")
  38. #define rmb() asm volatile ("membar" : : :"memory")
  39. #define wmb() asm volatile ("membar" : : :"memory")
  40. #define read_barrier_depends() do { } while (0)
  41. #ifdef CONFIG_SMP
  42. #define smp_mb() mb()
  43. #define smp_rmb() rmb()
  44. #define smp_wmb() wmb()
  45. #define smp_read_barrier_depends() read_barrier_depends()
  46. #define set_mb(var, value) \
  47. do { xchg(&var, (value)); } while (0)
  48. #else
  49. #define smp_mb() barrier()
  50. #define smp_rmb() barrier()
  51. #define smp_wmb() barrier()
  52. #define smp_read_barrier_depends() do {} while(0)
  53. #define set_mb(var, value) \
  54. do { var = (value); barrier(); } while (0)
  55. #endif
  56. extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
  57. extern void free_initmem(void);
  58. #define arch_align_stack(x) (x)
  59. /*****************************************************************************/
  60. /*
  61. * compare and conditionally exchange value with memory
  62. * - if (*ptr == test) then orig = *ptr; *ptr = test;
  63. * - if (*ptr != test) then orig = *ptr;
  64. */
  65. extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v);
  66. #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
  67. #define cmpxchg(ptr, test, new) \
  68. ({ \
  69. __typeof__(ptr) __xg_ptr = (ptr); \
  70. __typeof__(*(ptr)) __xg_orig, __xg_tmp; \
  71. __typeof__(*(ptr)) __xg_test = (test); \
  72. __typeof__(*(ptr)) __xg_new = (new); \
  73. \
  74. switch (sizeof(__xg_orig)) { \
  75. case 4: \
  76. asm volatile( \
  77. "0: \n" \
  78. " orcc gr0,gr0,gr0,icc3 \n" \
  79. " ckeq icc3,cc7 \n" \
  80. " ld.p %M0,%1 \n" \
  81. " orcr cc7,cc7,cc3 \n" \
  82. " sub%I4cc %1,%4,%2,icc0 \n" \
  83. " bne icc0,#0,1f \n" \
  84. " cst.p %3,%M0 ,cc3,#1 \n" \
  85. " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
  86. " beq icc3,#0,0b \n" \
  87. "1: \n" \
  88. : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
  89. : "r"(__xg_new), "NPr"(__xg_test) \
  90. : "memory", "cc7", "cc3", "icc3", "icc0" \
  91. ); \
  92. break; \
  93. \
  94. default: \
  95. __xg_orig = (__typeof__(__xg_orig))0; \
  96. asm volatile("break"); \
  97. break; \
  98. } \
  99. \
  100. __xg_orig; \
  101. })
  102. #else
  103. extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
  104. #define cmpxchg(ptr, test, new) \
  105. ({ \
  106. __typeof__(ptr) __xg_ptr = (ptr); \
  107. __typeof__(*(ptr)) __xg_orig; \
  108. __typeof__(*(ptr)) __xg_test = (test); \
  109. __typeof__(*(ptr)) __xg_new = (new); \
  110. \
  111. switch (sizeof(__xg_orig)) { \
  112. case 4: __xg_orig = (__force __typeof__(*ptr)) \
  113. __cmpxchg_32((__force uint32_t *)__xg_ptr, \
  114. (__force uint32_t)__xg_test, \
  115. (__force uint32_t)__xg_new); break; \
  116. default: \
  117. __xg_orig = (__typeof__(__xg_orig))0; \
  118. asm volatile("break"); \
  119. break; \
  120. } \
  121. \
  122. __xg_orig; \
  123. })
  124. #endif
  125. #include <asm-generic/cmpxchg-local.h>
  126. static inline unsigned long __cmpxchg_local(volatile void *ptr,
  127. unsigned long old,
  128. unsigned long new, int size)
  129. {
  130. switch (size) {
  131. case 4:
  132. return cmpxchg((unsigned long *)ptr, old, new);
  133. default:
  134. return __cmpxchg_local_generic(ptr, old, new, size);
  135. }
  136. return old;
  137. }
  138. /*
  139. * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
  140. * them available.
  141. */
  142. #define cmpxchg_local(ptr, o, n) \
  143. ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
  144. (unsigned long)(n), sizeof(*(ptr))))
  145. #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
  146. #endif /* _ASM_SYSTEM_H */