intel_display.c 229 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/cpufreq.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include "drmP.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. #include "i915_trace.h"
  38. #include "drm_dp_helper.h"
  39. #include "drm_crtc_helper.h"
  40. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  41. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42. static void intel_update_watermarks(struct drm_device *dev);
  43. static void intel_increase_pllclock(struct drm_crtc *crtc);
  44. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45. typedef struct {
  46. /* given values */
  47. int n;
  48. int m1, m2;
  49. int p1, p2;
  50. /* derived values */
  51. int dot;
  52. int vco;
  53. int m;
  54. int p;
  55. } intel_clock_t;
  56. typedef struct {
  57. int min, max;
  58. } intel_range_t;
  59. typedef struct {
  60. int dot_limit;
  61. int p2_slow, p2_fast;
  62. } intel_p2_t;
  63. #define INTEL_P2_NUM 2
  64. typedef struct intel_limit intel_limit_t;
  65. struct intel_limit {
  66. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  67. intel_p2_t p2;
  68. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  69. int, int, intel_clock_t *);
  70. };
  71. /* FDI */
  72. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  73. static bool
  74. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  75. int target, int refclk, intel_clock_t *best_clock);
  76. static bool
  77. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  78. int target, int refclk, intel_clock_t *best_clock);
  79. static bool
  80. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  81. int target, int refclk, intel_clock_t *best_clock);
  82. static bool
  83. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  84. int target, int refclk, intel_clock_t *best_clock);
  85. static inline u32 /* units of 100MHz */
  86. intel_fdi_link_freq(struct drm_device *dev)
  87. {
  88. if (IS_GEN5(dev)) {
  89. struct drm_i915_private *dev_priv = dev->dev_private;
  90. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  91. } else
  92. return 27;
  93. }
  94. static const intel_limit_t intel_limits_i8xx_dvo = {
  95. .dot = { .min = 25000, .max = 350000 },
  96. .vco = { .min = 930000, .max = 1400000 },
  97. .n = { .min = 3, .max = 16 },
  98. .m = { .min = 96, .max = 140 },
  99. .m1 = { .min = 18, .max = 26 },
  100. .m2 = { .min = 6, .max = 16 },
  101. .p = { .min = 4, .max = 128 },
  102. .p1 = { .min = 2, .max = 33 },
  103. .p2 = { .dot_limit = 165000,
  104. .p2_slow = 4, .p2_fast = 2 },
  105. .find_pll = intel_find_best_PLL,
  106. };
  107. static const intel_limit_t intel_limits_i8xx_lvds = {
  108. .dot = { .min = 25000, .max = 350000 },
  109. .vco = { .min = 930000, .max = 1400000 },
  110. .n = { .min = 3, .max = 16 },
  111. .m = { .min = 96, .max = 140 },
  112. .m1 = { .min = 18, .max = 26 },
  113. .m2 = { .min = 6, .max = 16 },
  114. .p = { .min = 4, .max = 128 },
  115. .p1 = { .min = 1, .max = 6 },
  116. .p2 = { .dot_limit = 165000,
  117. .p2_slow = 14, .p2_fast = 7 },
  118. .find_pll = intel_find_best_PLL,
  119. };
  120. static const intel_limit_t intel_limits_i9xx_sdvo = {
  121. .dot = { .min = 20000, .max = 400000 },
  122. .vco = { .min = 1400000, .max = 2800000 },
  123. .n = { .min = 1, .max = 6 },
  124. .m = { .min = 70, .max = 120 },
  125. .m1 = { .min = 10, .max = 22 },
  126. .m2 = { .min = 5, .max = 9 },
  127. .p = { .min = 5, .max = 80 },
  128. .p1 = { .min = 1, .max = 8 },
  129. .p2 = { .dot_limit = 200000,
  130. .p2_slow = 10, .p2_fast = 5 },
  131. .find_pll = intel_find_best_PLL,
  132. };
  133. static const intel_limit_t intel_limits_i9xx_lvds = {
  134. .dot = { .min = 20000, .max = 400000 },
  135. .vco = { .min = 1400000, .max = 2800000 },
  136. .n = { .min = 1, .max = 6 },
  137. .m = { .min = 70, .max = 120 },
  138. .m1 = { .min = 10, .max = 22 },
  139. .m2 = { .min = 5, .max = 9 },
  140. .p = { .min = 7, .max = 98 },
  141. .p1 = { .min = 1, .max = 8 },
  142. .p2 = { .dot_limit = 112000,
  143. .p2_slow = 14, .p2_fast = 7 },
  144. .find_pll = intel_find_best_PLL,
  145. };
  146. static const intel_limit_t intel_limits_g4x_sdvo = {
  147. .dot = { .min = 25000, .max = 270000 },
  148. .vco = { .min = 1750000, .max = 3500000},
  149. .n = { .min = 1, .max = 4 },
  150. .m = { .min = 104, .max = 138 },
  151. .m1 = { .min = 17, .max = 23 },
  152. .m2 = { .min = 5, .max = 11 },
  153. .p = { .min = 10, .max = 30 },
  154. .p1 = { .min = 1, .max = 3},
  155. .p2 = { .dot_limit = 270000,
  156. .p2_slow = 10,
  157. .p2_fast = 10
  158. },
  159. .find_pll = intel_g4x_find_best_PLL,
  160. };
  161. static const intel_limit_t intel_limits_g4x_hdmi = {
  162. .dot = { .min = 22000, .max = 400000 },
  163. .vco = { .min = 1750000, .max = 3500000},
  164. .n = { .min = 1, .max = 4 },
  165. .m = { .min = 104, .max = 138 },
  166. .m1 = { .min = 16, .max = 23 },
  167. .m2 = { .min = 5, .max = 11 },
  168. .p = { .min = 5, .max = 80 },
  169. .p1 = { .min = 1, .max = 8},
  170. .p2 = { .dot_limit = 165000,
  171. .p2_slow = 10, .p2_fast = 5 },
  172. .find_pll = intel_g4x_find_best_PLL,
  173. };
  174. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  175. .dot = { .min = 20000, .max = 115000 },
  176. .vco = { .min = 1750000, .max = 3500000 },
  177. .n = { .min = 1, .max = 3 },
  178. .m = { .min = 104, .max = 138 },
  179. .m1 = { .min = 17, .max = 23 },
  180. .m2 = { .min = 5, .max = 11 },
  181. .p = { .min = 28, .max = 112 },
  182. .p1 = { .min = 2, .max = 8 },
  183. .p2 = { .dot_limit = 0,
  184. .p2_slow = 14, .p2_fast = 14
  185. },
  186. .find_pll = intel_g4x_find_best_PLL,
  187. };
  188. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  189. .dot = { .min = 80000, .max = 224000 },
  190. .vco = { .min = 1750000, .max = 3500000 },
  191. .n = { .min = 1, .max = 3 },
  192. .m = { .min = 104, .max = 138 },
  193. .m1 = { .min = 17, .max = 23 },
  194. .m2 = { .min = 5, .max = 11 },
  195. .p = { .min = 14, .max = 42 },
  196. .p1 = { .min = 2, .max = 6 },
  197. .p2 = { .dot_limit = 0,
  198. .p2_slow = 7, .p2_fast = 7
  199. },
  200. .find_pll = intel_g4x_find_best_PLL,
  201. };
  202. static const intel_limit_t intel_limits_g4x_display_port = {
  203. .dot = { .min = 161670, .max = 227000 },
  204. .vco = { .min = 1750000, .max = 3500000},
  205. .n = { .min = 1, .max = 2 },
  206. .m = { .min = 97, .max = 108 },
  207. .m1 = { .min = 0x10, .max = 0x12 },
  208. .m2 = { .min = 0x05, .max = 0x06 },
  209. .p = { .min = 10, .max = 20 },
  210. .p1 = { .min = 1, .max = 2},
  211. .p2 = { .dot_limit = 0,
  212. .p2_slow = 10, .p2_fast = 10 },
  213. .find_pll = intel_find_pll_g4x_dp,
  214. };
  215. static const intel_limit_t intel_limits_pineview_sdvo = {
  216. .dot = { .min = 20000, .max = 400000},
  217. .vco = { .min = 1700000, .max = 3500000 },
  218. /* Pineview's Ncounter is a ring counter */
  219. .n = { .min = 3, .max = 6 },
  220. .m = { .min = 2, .max = 256 },
  221. /* Pineview only has one combined m divider, which we treat as m2. */
  222. .m1 = { .min = 0, .max = 0 },
  223. .m2 = { .min = 0, .max = 254 },
  224. .p = { .min = 5, .max = 80 },
  225. .p1 = { .min = 1, .max = 8 },
  226. .p2 = { .dot_limit = 200000,
  227. .p2_slow = 10, .p2_fast = 5 },
  228. .find_pll = intel_find_best_PLL,
  229. };
  230. static const intel_limit_t intel_limits_pineview_lvds = {
  231. .dot = { .min = 20000, .max = 400000 },
  232. .vco = { .min = 1700000, .max = 3500000 },
  233. .n = { .min = 3, .max = 6 },
  234. .m = { .min = 2, .max = 256 },
  235. .m1 = { .min = 0, .max = 0 },
  236. .m2 = { .min = 0, .max = 254 },
  237. .p = { .min = 7, .max = 112 },
  238. .p1 = { .min = 1, .max = 8 },
  239. .p2 = { .dot_limit = 112000,
  240. .p2_slow = 14, .p2_fast = 14 },
  241. .find_pll = intel_find_best_PLL,
  242. };
  243. /* Ironlake / Sandybridge
  244. *
  245. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  246. * the range value for them is (actual_value - 2).
  247. */
  248. static const intel_limit_t intel_limits_ironlake_dac = {
  249. .dot = { .min = 25000, .max = 350000 },
  250. .vco = { .min = 1760000, .max = 3510000 },
  251. .n = { .min = 1, .max = 5 },
  252. .m = { .min = 79, .max = 127 },
  253. .m1 = { .min = 12, .max = 22 },
  254. .m2 = { .min = 5, .max = 9 },
  255. .p = { .min = 5, .max = 80 },
  256. .p1 = { .min = 1, .max = 8 },
  257. .p2 = { .dot_limit = 225000,
  258. .p2_slow = 10, .p2_fast = 5 },
  259. .find_pll = intel_g4x_find_best_PLL,
  260. };
  261. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  262. .dot = { .min = 25000, .max = 350000 },
  263. .vco = { .min = 1760000, .max = 3510000 },
  264. .n = { .min = 1, .max = 3 },
  265. .m = { .min = 79, .max = 118 },
  266. .m1 = { .min = 12, .max = 22 },
  267. .m2 = { .min = 5, .max = 9 },
  268. .p = { .min = 28, .max = 112 },
  269. .p1 = { .min = 2, .max = 8 },
  270. .p2 = { .dot_limit = 225000,
  271. .p2_slow = 14, .p2_fast = 14 },
  272. .find_pll = intel_g4x_find_best_PLL,
  273. };
  274. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  275. .dot = { .min = 25000, .max = 350000 },
  276. .vco = { .min = 1760000, .max = 3510000 },
  277. .n = { .min = 1, .max = 3 },
  278. .m = { .min = 79, .max = 127 },
  279. .m1 = { .min = 12, .max = 22 },
  280. .m2 = { .min = 5, .max = 9 },
  281. .p = { .min = 14, .max = 56 },
  282. .p1 = { .min = 2, .max = 8 },
  283. .p2 = { .dot_limit = 225000,
  284. .p2_slow = 7, .p2_fast = 7 },
  285. .find_pll = intel_g4x_find_best_PLL,
  286. };
  287. /* LVDS 100mhz refclk limits. */
  288. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  289. .dot = { .min = 25000, .max = 350000 },
  290. .vco = { .min = 1760000, .max = 3510000 },
  291. .n = { .min = 1, .max = 2 },
  292. .m = { .min = 79, .max = 126 },
  293. .m1 = { .min = 12, .max = 22 },
  294. .m2 = { .min = 5, .max = 9 },
  295. .p = { .min = 28, .max = 112 },
  296. .p1 = { .min = 2,.max = 8 },
  297. .p2 = { .dot_limit = 225000,
  298. .p2_slow = 14, .p2_fast = 14 },
  299. .find_pll = intel_g4x_find_best_PLL,
  300. };
  301. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  302. .dot = { .min = 25000, .max = 350000 },
  303. .vco = { .min = 1760000, .max = 3510000 },
  304. .n = { .min = 1, .max = 3 },
  305. .m = { .min = 79, .max = 126 },
  306. .m1 = { .min = 12, .max = 22 },
  307. .m2 = { .min = 5, .max = 9 },
  308. .p = { .min = 14, .max = 42 },
  309. .p1 = { .min = 2,.max = 6 },
  310. .p2 = { .dot_limit = 225000,
  311. .p2_slow = 7, .p2_fast = 7 },
  312. .find_pll = intel_g4x_find_best_PLL,
  313. };
  314. static const intel_limit_t intel_limits_ironlake_display_port = {
  315. .dot = { .min = 25000, .max = 350000 },
  316. .vco = { .min = 1760000, .max = 3510000},
  317. .n = { .min = 1, .max = 2 },
  318. .m = { .min = 81, .max = 90 },
  319. .m1 = { .min = 12, .max = 22 },
  320. .m2 = { .min = 5, .max = 9 },
  321. .p = { .min = 10, .max = 20 },
  322. .p1 = { .min = 1, .max = 2},
  323. .p2 = { .dot_limit = 0,
  324. .p2_slow = 10, .p2_fast = 10 },
  325. .find_pll = intel_find_pll_ironlake_dp,
  326. };
  327. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  328. int refclk)
  329. {
  330. struct drm_device *dev = crtc->dev;
  331. struct drm_i915_private *dev_priv = dev->dev_private;
  332. const intel_limit_t *limit;
  333. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  334. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  335. LVDS_CLKB_POWER_UP) {
  336. /* LVDS dual channel */
  337. if (refclk == 100000)
  338. limit = &intel_limits_ironlake_dual_lvds_100m;
  339. else
  340. limit = &intel_limits_ironlake_dual_lvds;
  341. } else {
  342. if (refclk == 100000)
  343. limit = &intel_limits_ironlake_single_lvds_100m;
  344. else
  345. limit = &intel_limits_ironlake_single_lvds;
  346. }
  347. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  348. HAS_eDP)
  349. limit = &intel_limits_ironlake_display_port;
  350. else
  351. limit = &intel_limits_ironlake_dac;
  352. return limit;
  353. }
  354. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  355. {
  356. struct drm_device *dev = crtc->dev;
  357. struct drm_i915_private *dev_priv = dev->dev_private;
  358. const intel_limit_t *limit;
  359. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  360. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  361. LVDS_CLKB_POWER_UP)
  362. /* LVDS with dual channel */
  363. limit = &intel_limits_g4x_dual_channel_lvds;
  364. else
  365. /* LVDS with dual channel */
  366. limit = &intel_limits_g4x_single_channel_lvds;
  367. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  368. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  369. limit = &intel_limits_g4x_hdmi;
  370. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  371. limit = &intel_limits_g4x_sdvo;
  372. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  373. limit = &intel_limits_g4x_display_port;
  374. } else /* The option is for other outputs */
  375. limit = &intel_limits_i9xx_sdvo;
  376. return limit;
  377. }
  378. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  379. {
  380. struct drm_device *dev = crtc->dev;
  381. const intel_limit_t *limit;
  382. if (HAS_PCH_SPLIT(dev))
  383. limit = intel_ironlake_limit(crtc, refclk);
  384. else if (IS_G4X(dev)) {
  385. limit = intel_g4x_limit(crtc);
  386. } else if (IS_PINEVIEW(dev)) {
  387. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  388. limit = &intel_limits_pineview_lvds;
  389. else
  390. limit = &intel_limits_pineview_sdvo;
  391. } else if (!IS_GEN2(dev)) {
  392. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  393. limit = &intel_limits_i9xx_lvds;
  394. else
  395. limit = &intel_limits_i9xx_sdvo;
  396. } else {
  397. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  398. limit = &intel_limits_i8xx_lvds;
  399. else
  400. limit = &intel_limits_i8xx_dvo;
  401. }
  402. return limit;
  403. }
  404. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  405. static void pineview_clock(int refclk, intel_clock_t *clock)
  406. {
  407. clock->m = clock->m2 + 2;
  408. clock->p = clock->p1 * clock->p2;
  409. clock->vco = refclk * clock->m / clock->n;
  410. clock->dot = clock->vco / clock->p;
  411. }
  412. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  413. {
  414. if (IS_PINEVIEW(dev)) {
  415. pineview_clock(refclk, clock);
  416. return;
  417. }
  418. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  419. clock->p = clock->p1 * clock->p2;
  420. clock->vco = refclk * clock->m / (clock->n + 2);
  421. clock->dot = clock->vco / clock->p;
  422. }
  423. /**
  424. * Returns whether any output on the specified pipe is of the specified type
  425. */
  426. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  427. {
  428. struct drm_device *dev = crtc->dev;
  429. struct drm_mode_config *mode_config = &dev->mode_config;
  430. struct intel_encoder *encoder;
  431. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  432. if (encoder->base.crtc == crtc && encoder->type == type)
  433. return true;
  434. return false;
  435. }
  436. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  437. /**
  438. * Returns whether the given set of divisors are valid for a given refclk with
  439. * the given connectors.
  440. */
  441. static bool intel_PLL_is_valid(struct drm_device *dev,
  442. const intel_limit_t *limit,
  443. const intel_clock_t *clock)
  444. {
  445. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  446. INTELPllInvalid ("p1 out of range\n");
  447. if (clock->p < limit->p.min || limit->p.max < clock->p)
  448. INTELPllInvalid ("p out of range\n");
  449. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  450. INTELPllInvalid ("m2 out of range\n");
  451. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  452. INTELPllInvalid ("m1 out of range\n");
  453. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  454. INTELPllInvalid ("m1 <= m2\n");
  455. if (clock->m < limit->m.min || limit->m.max < clock->m)
  456. INTELPllInvalid ("m out of range\n");
  457. if (clock->n < limit->n.min || limit->n.max < clock->n)
  458. INTELPllInvalid ("n out of range\n");
  459. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  460. INTELPllInvalid ("vco out of range\n");
  461. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  462. * connector, etc., rather than just a single range.
  463. */
  464. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  465. INTELPllInvalid ("dot out of range\n");
  466. return true;
  467. }
  468. static bool
  469. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  470. int target, int refclk, intel_clock_t *best_clock)
  471. {
  472. struct drm_device *dev = crtc->dev;
  473. struct drm_i915_private *dev_priv = dev->dev_private;
  474. intel_clock_t clock;
  475. int err = target;
  476. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  477. (I915_READ(LVDS)) != 0) {
  478. /*
  479. * For LVDS, if the panel is on, just rely on its current
  480. * settings for dual-channel. We haven't figured out how to
  481. * reliably set up different single/dual channel state, if we
  482. * even can.
  483. */
  484. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  485. LVDS_CLKB_POWER_UP)
  486. clock.p2 = limit->p2.p2_fast;
  487. else
  488. clock.p2 = limit->p2.p2_slow;
  489. } else {
  490. if (target < limit->p2.dot_limit)
  491. clock.p2 = limit->p2.p2_slow;
  492. else
  493. clock.p2 = limit->p2.p2_fast;
  494. }
  495. memset (best_clock, 0, sizeof (*best_clock));
  496. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  497. clock.m1++) {
  498. for (clock.m2 = limit->m2.min;
  499. clock.m2 <= limit->m2.max; clock.m2++) {
  500. /* m1 is always 0 in Pineview */
  501. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  502. break;
  503. for (clock.n = limit->n.min;
  504. clock.n <= limit->n.max; clock.n++) {
  505. for (clock.p1 = limit->p1.min;
  506. clock.p1 <= limit->p1.max; clock.p1++) {
  507. int this_err;
  508. intel_clock(dev, refclk, &clock);
  509. if (!intel_PLL_is_valid(dev, limit,
  510. &clock))
  511. continue;
  512. this_err = abs(clock.dot - target);
  513. if (this_err < err) {
  514. *best_clock = clock;
  515. err = this_err;
  516. }
  517. }
  518. }
  519. }
  520. }
  521. return (err != target);
  522. }
  523. static bool
  524. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  525. int target, int refclk, intel_clock_t *best_clock)
  526. {
  527. struct drm_device *dev = crtc->dev;
  528. struct drm_i915_private *dev_priv = dev->dev_private;
  529. intel_clock_t clock;
  530. int max_n;
  531. bool found;
  532. /* approximately equals target * 0.00585 */
  533. int err_most = (target >> 8) + (target >> 9);
  534. found = false;
  535. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  536. int lvds_reg;
  537. if (HAS_PCH_SPLIT(dev))
  538. lvds_reg = PCH_LVDS;
  539. else
  540. lvds_reg = LVDS;
  541. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  542. LVDS_CLKB_POWER_UP)
  543. clock.p2 = limit->p2.p2_fast;
  544. else
  545. clock.p2 = limit->p2.p2_slow;
  546. } else {
  547. if (target < limit->p2.dot_limit)
  548. clock.p2 = limit->p2.p2_slow;
  549. else
  550. clock.p2 = limit->p2.p2_fast;
  551. }
  552. memset(best_clock, 0, sizeof(*best_clock));
  553. max_n = limit->n.max;
  554. /* based on hardware requirement, prefer smaller n to precision */
  555. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  556. /* based on hardware requirement, prefere larger m1,m2 */
  557. for (clock.m1 = limit->m1.max;
  558. clock.m1 >= limit->m1.min; clock.m1--) {
  559. for (clock.m2 = limit->m2.max;
  560. clock.m2 >= limit->m2.min; clock.m2--) {
  561. for (clock.p1 = limit->p1.max;
  562. clock.p1 >= limit->p1.min; clock.p1--) {
  563. int this_err;
  564. intel_clock(dev, refclk, &clock);
  565. if (!intel_PLL_is_valid(dev, limit,
  566. &clock))
  567. continue;
  568. this_err = abs(clock.dot - target);
  569. if (this_err < err_most) {
  570. *best_clock = clock;
  571. err_most = this_err;
  572. max_n = clock.n;
  573. found = true;
  574. }
  575. }
  576. }
  577. }
  578. }
  579. return found;
  580. }
  581. static bool
  582. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  583. int target, int refclk, intel_clock_t *best_clock)
  584. {
  585. struct drm_device *dev = crtc->dev;
  586. intel_clock_t clock;
  587. if (target < 200000) {
  588. clock.n = 1;
  589. clock.p1 = 2;
  590. clock.p2 = 10;
  591. clock.m1 = 12;
  592. clock.m2 = 9;
  593. } else {
  594. clock.n = 2;
  595. clock.p1 = 1;
  596. clock.p2 = 10;
  597. clock.m1 = 14;
  598. clock.m2 = 8;
  599. }
  600. intel_clock(dev, refclk, &clock);
  601. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  602. return true;
  603. }
  604. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  605. static bool
  606. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  607. int target, int refclk, intel_clock_t *best_clock)
  608. {
  609. intel_clock_t clock;
  610. if (target < 200000) {
  611. clock.p1 = 2;
  612. clock.p2 = 10;
  613. clock.n = 2;
  614. clock.m1 = 23;
  615. clock.m2 = 8;
  616. } else {
  617. clock.p1 = 1;
  618. clock.p2 = 10;
  619. clock.n = 1;
  620. clock.m1 = 14;
  621. clock.m2 = 2;
  622. }
  623. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  624. clock.p = (clock.p1 * clock.p2);
  625. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  626. clock.vco = 0;
  627. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  628. return true;
  629. }
  630. /**
  631. * intel_wait_for_vblank - wait for vblank on a given pipe
  632. * @dev: drm device
  633. * @pipe: pipe to wait for
  634. *
  635. * Wait for vblank to occur on a given pipe. Needed for various bits of
  636. * mode setting code.
  637. */
  638. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  639. {
  640. struct drm_i915_private *dev_priv = dev->dev_private;
  641. int pipestat_reg = PIPESTAT(pipe);
  642. /* Clear existing vblank status. Note this will clear any other
  643. * sticky status fields as well.
  644. *
  645. * This races with i915_driver_irq_handler() with the result
  646. * that either function could miss a vblank event. Here it is not
  647. * fatal, as we will either wait upon the next vblank interrupt or
  648. * timeout. Generally speaking intel_wait_for_vblank() is only
  649. * called during modeset at which time the GPU should be idle and
  650. * should *not* be performing page flips and thus not waiting on
  651. * vblanks...
  652. * Currently, the result of us stealing a vblank from the irq
  653. * handler is that a single frame will be skipped during swapbuffers.
  654. */
  655. I915_WRITE(pipestat_reg,
  656. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  657. /* Wait for vblank interrupt bit to set */
  658. if (wait_for(I915_READ(pipestat_reg) &
  659. PIPE_VBLANK_INTERRUPT_STATUS,
  660. 50))
  661. DRM_DEBUG_KMS("vblank wait timed out\n");
  662. }
  663. /*
  664. * intel_wait_for_pipe_off - wait for pipe to turn off
  665. * @dev: drm device
  666. * @pipe: pipe to wait for
  667. *
  668. * After disabling a pipe, we can't wait for vblank in the usual way,
  669. * spinning on the vblank interrupt status bit, since we won't actually
  670. * see an interrupt when the pipe is disabled.
  671. *
  672. * On Gen4 and above:
  673. * wait for the pipe register state bit to turn off
  674. *
  675. * Otherwise:
  676. * wait for the display line value to settle (it usually
  677. * ends up stopping at the start of the next frame).
  678. *
  679. */
  680. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  681. {
  682. struct drm_i915_private *dev_priv = dev->dev_private;
  683. if (INTEL_INFO(dev)->gen >= 4) {
  684. int reg = PIPECONF(pipe);
  685. /* Wait for the Pipe State to go off */
  686. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  687. 100))
  688. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  689. } else {
  690. u32 last_line;
  691. int reg = PIPEDSL(pipe);
  692. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  693. /* Wait for the display line to settle */
  694. do {
  695. last_line = I915_READ(reg) & DSL_LINEMASK;
  696. mdelay(5);
  697. } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
  698. time_after(timeout, jiffies));
  699. if (time_after(jiffies, timeout))
  700. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  701. }
  702. }
  703. static const char *state_string(bool enabled)
  704. {
  705. return enabled ? "on" : "off";
  706. }
  707. /* Only for pre-ILK configs */
  708. static void assert_pll(struct drm_i915_private *dev_priv,
  709. enum pipe pipe, bool state)
  710. {
  711. int reg;
  712. u32 val;
  713. bool cur_state;
  714. reg = DPLL(pipe);
  715. val = I915_READ(reg);
  716. cur_state = !!(val & DPLL_VCO_ENABLE);
  717. WARN(cur_state != state,
  718. "PLL state assertion failure (expected %s, current %s)\n",
  719. state_string(state), state_string(cur_state));
  720. }
  721. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  722. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  723. /* For ILK+ */
  724. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  725. enum pipe pipe, bool state)
  726. {
  727. int reg;
  728. u32 val;
  729. bool cur_state;
  730. reg = PCH_DPLL(pipe);
  731. val = I915_READ(reg);
  732. cur_state = !!(val & DPLL_VCO_ENABLE);
  733. WARN(cur_state != state,
  734. "PCH PLL state assertion failure (expected %s, current %s)\n",
  735. state_string(state), state_string(cur_state));
  736. }
  737. #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
  738. #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
  739. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  740. enum pipe pipe, bool state)
  741. {
  742. int reg;
  743. u32 val;
  744. bool cur_state;
  745. reg = FDI_TX_CTL(pipe);
  746. val = I915_READ(reg);
  747. cur_state = !!(val & FDI_TX_ENABLE);
  748. WARN(cur_state != state,
  749. "FDI TX state assertion failure (expected %s, current %s)\n",
  750. state_string(state), state_string(cur_state));
  751. }
  752. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  753. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  754. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  755. enum pipe pipe, bool state)
  756. {
  757. int reg;
  758. u32 val;
  759. bool cur_state;
  760. reg = FDI_RX_CTL(pipe);
  761. val = I915_READ(reg);
  762. cur_state = !!(val & FDI_RX_ENABLE);
  763. WARN(cur_state != state,
  764. "FDI RX state assertion failure (expected %s, current %s)\n",
  765. state_string(state), state_string(cur_state));
  766. }
  767. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  768. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  769. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  770. enum pipe pipe)
  771. {
  772. int reg;
  773. u32 val;
  774. /* ILK FDI PLL is always enabled */
  775. if (dev_priv->info->gen == 5)
  776. return;
  777. reg = FDI_TX_CTL(pipe);
  778. val = I915_READ(reg);
  779. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  780. }
  781. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  782. enum pipe pipe)
  783. {
  784. int reg;
  785. u32 val;
  786. reg = FDI_RX_CTL(pipe);
  787. val = I915_READ(reg);
  788. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  789. }
  790. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  791. enum pipe pipe)
  792. {
  793. int pp_reg, lvds_reg;
  794. u32 val;
  795. enum pipe panel_pipe = PIPE_A;
  796. bool locked = locked;
  797. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  798. pp_reg = PCH_PP_CONTROL;
  799. lvds_reg = PCH_LVDS;
  800. } else {
  801. pp_reg = PP_CONTROL;
  802. lvds_reg = LVDS;
  803. }
  804. val = I915_READ(pp_reg);
  805. if (!(val & PANEL_POWER_ON) ||
  806. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  807. locked = false;
  808. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  809. panel_pipe = PIPE_B;
  810. WARN(panel_pipe == pipe && locked,
  811. "panel assertion failure, pipe %c regs locked\n",
  812. pipe_name(pipe));
  813. }
  814. static void assert_pipe(struct drm_i915_private *dev_priv,
  815. enum pipe pipe, bool state)
  816. {
  817. int reg;
  818. u32 val;
  819. bool cur_state;
  820. reg = PIPECONF(pipe);
  821. val = I915_READ(reg);
  822. cur_state = !!(val & PIPECONF_ENABLE);
  823. WARN(cur_state != state,
  824. "pipe %c assertion failure (expected %s, current %s)\n",
  825. pipe_name(pipe), state_string(state), state_string(cur_state));
  826. }
  827. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  828. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  829. static void assert_plane_enabled(struct drm_i915_private *dev_priv,
  830. enum plane plane)
  831. {
  832. int reg;
  833. u32 val;
  834. reg = DSPCNTR(plane);
  835. val = I915_READ(reg);
  836. WARN(!(val & DISPLAY_PLANE_ENABLE),
  837. "plane %c assertion failure, should be active but is disabled\n",
  838. plane_name(plane));
  839. }
  840. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  841. enum pipe pipe)
  842. {
  843. int reg, i;
  844. u32 val;
  845. int cur_pipe;
  846. /* Planes are fixed to pipes on ILK+ */
  847. if (HAS_PCH_SPLIT(dev_priv->dev))
  848. return;
  849. /* Need to check both planes against the pipe */
  850. for (i = 0; i < 2; i++) {
  851. reg = DSPCNTR(i);
  852. val = I915_READ(reg);
  853. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  854. DISPPLANE_SEL_PIPE_SHIFT;
  855. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  856. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  857. plane_name(i), pipe_name(pipe));
  858. }
  859. }
  860. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  861. {
  862. u32 val;
  863. bool enabled;
  864. val = I915_READ(PCH_DREF_CONTROL);
  865. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  866. DREF_SUPERSPREAD_SOURCE_MASK));
  867. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  868. }
  869. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  870. enum pipe pipe)
  871. {
  872. int reg;
  873. u32 val;
  874. bool enabled;
  875. reg = TRANSCONF(pipe);
  876. val = I915_READ(reg);
  877. enabled = !!(val & TRANS_ENABLE);
  878. WARN(enabled,
  879. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  880. pipe_name(pipe));
  881. }
  882. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  883. enum pipe pipe, int reg)
  884. {
  885. u32 val = I915_READ(reg);
  886. WARN(DP_PIPE_ENABLED(val, pipe),
  887. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  888. reg, pipe_name(pipe));
  889. }
  890. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  891. enum pipe pipe, int reg)
  892. {
  893. u32 val = I915_READ(reg);
  894. WARN(HDMI_PIPE_ENABLED(val, pipe),
  895. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  896. reg, pipe_name(pipe));
  897. }
  898. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  899. enum pipe pipe)
  900. {
  901. int reg;
  902. u32 val;
  903. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
  904. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
  905. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
  906. reg = PCH_ADPA;
  907. val = I915_READ(reg);
  908. WARN(ADPA_PIPE_ENABLED(val, pipe),
  909. "PCH VGA enabled on transcoder %c, should be disabled\n",
  910. pipe_name(pipe));
  911. reg = PCH_LVDS;
  912. val = I915_READ(reg);
  913. WARN(LVDS_PIPE_ENABLED(val, pipe),
  914. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  915. pipe_name(pipe));
  916. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
  917. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
  918. assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
  919. }
  920. /**
  921. * intel_enable_pll - enable a PLL
  922. * @dev_priv: i915 private structure
  923. * @pipe: pipe PLL to enable
  924. *
  925. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  926. * make sure the PLL reg is writable first though, since the panel write
  927. * protect mechanism may be enabled.
  928. *
  929. * Note! This is for pre-ILK only.
  930. */
  931. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  932. {
  933. int reg;
  934. u32 val;
  935. /* No really, not for ILK+ */
  936. BUG_ON(dev_priv->info->gen >= 5);
  937. /* PLL is protected by panel, make sure we can write it */
  938. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  939. assert_panel_unlocked(dev_priv, pipe);
  940. reg = DPLL(pipe);
  941. val = I915_READ(reg);
  942. val |= DPLL_VCO_ENABLE;
  943. /* We do this three times for luck */
  944. I915_WRITE(reg, val);
  945. POSTING_READ(reg);
  946. udelay(150); /* wait for warmup */
  947. I915_WRITE(reg, val);
  948. POSTING_READ(reg);
  949. udelay(150); /* wait for warmup */
  950. I915_WRITE(reg, val);
  951. POSTING_READ(reg);
  952. udelay(150); /* wait for warmup */
  953. }
  954. /**
  955. * intel_disable_pll - disable a PLL
  956. * @dev_priv: i915 private structure
  957. * @pipe: pipe PLL to disable
  958. *
  959. * Disable the PLL for @pipe, making sure the pipe is off first.
  960. *
  961. * Note! This is for pre-ILK only.
  962. */
  963. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  964. {
  965. int reg;
  966. u32 val;
  967. /* Don't disable pipe A or pipe A PLLs if needed */
  968. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  969. return;
  970. /* Make sure the pipe isn't still relying on us */
  971. assert_pipe_disabled(dev_priv, pipe);
  972. reg = DPLL(pipe);
  973. val = I915_READ(reg);
  974. val &= ~DPLL_VCO_ENABLE;
  975. I915_WRITE(reg, val);
  976. POSTING_READ(reg);
  977. }
  978. /**
  979. * intel_enable_pch_pll - enable PCH PLL
  980. * @dev_priv: i915 private structure
  981. * @pipe: pipe PLL to enable
  982. *
  983. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  984. * drives the transcoder clock.
  985. */
  986. static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
  987. enum pipe pipe)
  988. {
  989. int reg;
  990. u32 val;
  991. /* PCH only available on ILK+ */
  992. BUG_ON(dev_priv->info->gen < 5);
  993. /* PCH refclock must be enabled first */
  994. assert_pch_refclk_enabled(dev_priv);
  995. reg = PCH_DPLL(pipe);
  996. val = I915_READ(reg);
  997. val |= DPLL_VCO_ENABLE;
  998. I915_WRITE(reg, val);
  999. POSTING_READ(reg);
  1000. udelay(200);
  1001. }
  1002. static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
  1003. enum pipe pipe)
  1004. {
  1005. int reg;
  1006. u32 val;
  1007. /* PCH only available on ILK+ */
  1008. BUG_ON(dev_priv->info->gen < 5);
  1009. /* Make sure transcoder isn't still depending on us */
  1010. assert_transcoder_disabled(dev_priv, pipe);
  1011. reg = PCH_DPLL(pipe);
  1012. val = I915_READ(reg);
  1013. val &= ~DPLL_VCO_ENABLE;
  1014. I915_WRITE(reg, val);
  1015. POSTING_READ(reg);
  1016. udelay(200);
  1017. }
  1018. static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
  1019. enum pipe pipe)
  1020. {
  1021. int reg;
  1022. u32 val;
  1023. /* PCH only available on ILK+ */
  1024. BUG_ON(dev_priv->info->gen < 5);
  1025. /* Make sure PCH DPLL is enabled */
  1026. assert_pch_pll_enabled(dev_priv, pipe);
  1027. /* FDI must be feeding us bits for PCH ports */
  1028. assert_fdi_tx_enabled(dev_priv, pipe);
  1029. assert_fdi_rx_enabled(dev_priv, pipe);
  1030. reg = TRANSCONF(pipe);
  1031. val = I915_READ(reg);
  1032. if (HAS_PCH_IBX(dev_priv->dev)) {
  1033. /*
  1034. * make the BPC in transcoder be consistent with
  1035. * that in pipeconf reg.
  1036. */
  1037. val &= ~PIPE_BPC_MASK;
  1038. val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
  1039. }
  1040. I915_WRITE(reg, val | TRANS_ENABLE);
  1041. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1042. DRM_ERROR("failed to enable transcoder %d\n", pipe);
  1043. }
  1044. static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
  1045. enum pipe pipe)
  1046. {
  1047. int reg;
  1048. u32 val;
  1049. /* FDI relies on the transcoder */
  1050. assert_fdi_tx_disabled(dev_priv, pipe);
  1051. assert_fdi_rx_disabled(dev_priv, pipe);
  1052. /* Ports must be off as well */
  1053. assert_pch_ports_disabled(dev_priv, pipe);
  1054. reg = TRANSCONF(pipe);
  1055. val = I915_READ(reg);
  1056. val &= ~TRANS_ENABLE;
  1057. I915_WRITE(reg, val);
  1058. /* wait for PCH transcoder off, transcoder state */
  1059. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1060. DRM_ERROR("failed to disable transcoder\n");
  1061. }
  1062. /**
  1063. * intel_enable_pipe - enable a pipe, asserting requirements
  1064. * @dev_priv: i915 private structure
  1065. * @pipe: pipe to enable
  1066. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1067. *
  1068. * Enable @pipe, making sure that various hardware specific requirements
  1069. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1070. *
  1071. * @pipe should be %PIPE_A or %PIPE_B.
  1072. *
  1073. * Will wait until the pipe is actually running (i.e. first vblank) before
  1074. * returning.
  1075. */
  1076. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1077. bool pch_port)
  1078. {
  1079. int reg;
  1080. u32 val;
  1081. /*
  1082. * A pipe without a PLL won't actually be able to drive bits from
  1083. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1084. * need the check.
  1085. */
  1086. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1087. assert_pll_enabled(dev_priv, pipe);
  1088. else {
  1089. if (pch_port) {
  1090. /* if driving the PCH, we need FDI enabled */
  1091. assert_fdi_rx_pll_enabled(dev_priv, pipe);
  1092. assert_fdi_tx_pll_enabled(dev_priv, pipe);
  1093. }
  1094. /* FIXME: assert CPU port conditions for SNB+ */
  1095. }
  1096. reg = PIPECONF(pipe);
  1097. val = I915_READ(reg);
  1098. if (val & PIPECONF_ENABLE)
  1099. return;
  1100. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1101. intel_wait_for_vblank(dev_priv->dev, pipe);
  1102. }
  1103. /**
  1104. * intel_disable_pipe - disable a pipe, asserting requirements
  1105. * @dev_priv: i915 private structure
  1106. * @pipe: pipe to disable
  1107. *
  1108. * Disable @pipe, making sure that various hardware specific requirements
  1109. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1110. *
  1111. * @pipe should be %PIPE_A or %PIPE_B.
  1112. *
  1113. * Will wait until the pipe has shut down before returning.
  1114. */
  1115. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1116. enum pipe pipe)
  1117. {
  1118. int reg;
  1119. u32 val;
  1120. /*
  1121. * Make sure planes won't keep trying to pump pixels to us,
  1122. * or we might hang the display.
  1123. */
  1124. assert_planes_disabled(dev_priv, pipe);
  1125. /* Don't disable pipe A or pipe A PLLs if needed */
  1126. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1127. return;
  1128. reg = PIPECONF(pipe);
  1129. val = I915_READ(reg);
  1130. if ((val & PIPECONF_ENABLE) == 0)
  1131. return;
  1132. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1133. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1134. }
  1135. /**
  1136. * intel_enable_plane - enable a display plane on a given pipe
  1137. * @dev_priv: i915 private structure
  1138. * @plane: plane to enable
  1139. * @pipe: pipe being fed
  1140. *
  1141. * Enable @plane on @pipe, making sure that @pipe is running first.
  1142. */
  1143. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1144. enum plane plane, enum pipe pipe)
  1145. {
  1146. int reg;
  1147. u32 val;
  1148. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1149. assert_pipe_enabled(dev_priv, pipe);
  1150. reg = DSPCNTR(plane);
  1151. val = I915_READ(reg);
  1152. if (val & DISPLAY_PLANE_ENABLE)
  1153. return;
  1154. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1155. intel_wait_for_vblank(dev_priv->dev, pipe);
  1156. }
  1157. /*
  1158. * Plane regs are double buffered, going from enabled->disabled needs a
  1159. * trigger in order to latch. The display address reg provides this.
  1160. */
  1161. static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1162. enum plane plane)
  1163. {
  1164. u32 reg = DSPADDR(plane);
  1165. I915_WRITE(reg, I915_READ(reg));
  1166. }
  1167. /**
  1168. * intel_disable_plane - disable a display plane
  1169. * @dev_priv: i915 private structure
  1170. * @plane: plane to disable
  1171. * @pipe: pipe consuming the data
  1172. *
  1173. * Disable @plane; should be an independent operation.
  1174. */
  1175. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1176. enum plane plane, enum pipe pipe)
  1177. {
  1178. int reg;
  1179. u32 val;
  1180. reg = DSPCNTR(plane);
  1181. val = I915_READ(reg);
  1182. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1183. return;
  1184. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1185. intel_flush_display_plane(dev_priv, plane);
  1186. intel_wait_for_vblank(dev_priv->dev, pipe);
  1187. }
  1188. static void disable_pch_dp(struct drm_i915_private *dev_priv,
  1189. enum pipe pipe, int reg)
  1190. {
  1191. u32 val = I915_READ(reg);
  1192. if (DP_PIPE_ENABLED(val, pipe))
  1193. I915_WRITE(reg, val & ~DP_PORT_EN);
  1194. }
  1195. static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
  1196. enum pipe pipe, int reg)
  1197. {
  1198. u32 val = I915_READ(reg);
  1199. if (HDMI_PIPE_ENABLED(val, pipe))
  1200. I915_WRITE(reg, val & ~PORT_ENABLE);
  1201. }
  1202. /* Disable any ports connected to this transcoder */
  1203. static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
  1204. enum pipe pipe)
  1205. {
  1206. u32 reg, val;
  1207. val = I915_READ(PCH_PP_CONTROL);
  1208. I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
  1209. disable_pch_dp(dev_priv, pipe, PCH_DP_B);
  1210. disable_pch_dp(dev_priv, pipe, PCH_DP_C);
  1211. disable_pch_dp(dev_priv, pipe, PCH_DP_D);
  1212. reg = PCH_ADPA;
  1213. val = I915_READ(reg);
  1214. if (ADPA_PIPE_ENABLED(val, pipe))
  1215. I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
  1216. reg = PCH_LVDS;
  1217. val = I915_READ(reg);
  1218. if (LVDS_PIPE_ENABLED(val, pipe)) {
  1219. I915_WRITE(reg, val & ~LVDS_PORT_EN);
  1220. POSTING_READ(reg);
  1221. udelay(100);
  1222. }
  1223. disable_pch_hdmi(dev_priv, pipe, HDMIB);
  1224. disable_pch_hdmi(dev_priv, pipe, HDMIC);
  1225. disable_pch_hdmi(dev_priv, pipe, HDMID);
  1226. }
  1227. static void i8xx_disable_fbc(struct drm_device *dev)
  1228. {
  1229. struct drm_i915_private *dev_priv = dev->dev_private;
  1230. u32 fbc_ctl;
  1231. /* Disable compression */
  1232. fbc_ctl = I915_READ(FBC_CONTROL);
  1233. if ((fbc_ctl & FBC_CTL_EN) == 0)
  1234. return;
  1235. fbc_ctl &= ~FBC_CTL_EN;
  1236. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1237. /* Wait for compressing bit to clear */
  1238. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  1239. DRM_DEBUG_KMS("FBC idle timed out\n");
  1240. return;
  1241. }
  1242. DRM_DEBUG_KMS("disabled FBC\n");
  1243. }
  1244. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1245. {
  1246. struct drm_device *dev = crtc->dev;
  1247. struct drm_i915_private *dev_priv = dev->dev_private;
  1248. struct drm_framebuffer *fb = crtc->fb;
  1249. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1250. struct drm_i915_gem_object *obj = intel_fb->obj;
  1251. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1252. int cfb_pitch;
  1253. int plane, i;
  1254. u32 fbc_ctl, fbc_ctl2;
  1255. cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  1256. if (fb->pitch < cfb_pitch)
  1257. cfb_pitch = fb->pitch;
  1258. /* FBC_CTL wants 64B units */
  1259. cfb_pitch = (cfb_pitch / 64) - 1;
  1260. plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  1261. /* Clear old tags */
  1262. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  1263. I915_WRITE(FBC_TAG + (i * 4), 0);
  1264. /* Set it up... */
  1265. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  1266. fbc_ctl2 |= plane;
  1267. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  1268. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  1269. /* enable it... */
  1270. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  1271. if (IS_I945GM(dev))
  1272. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  1273. fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  1274. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  1275. fbc_ctl |= obj->fence_reg;
  1276. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1277. DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
  1278. cfb_pitch, crtc->y, intel_crtc->plane);
  1279. }
  1280. static bool i8xx_fbc_enabled(struct drm_device *dev)
  1281. {
  1282. struct drm_i915_private *dev_priv = dev->dev_private;
  1283. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  1284. }
  1285. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1286. {
  1287. struct drm_device *dev = crtc->dev;
  1288. struct drm_i915_private *dev_priv = dev->dev_private;
  1289. struct drm_framebuffer *fb = crtc->fb;
  1290. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1291. struct drm_i915_gem_object *obj = intel_fb->obj;
  1292. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1293. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1294. unsigned long stall_watermark = 200;
  1295. u32 dpfc_ctl;
  1296. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  1297. dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  1298. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  1299. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1300. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1301. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1302. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  1303. /* enable it... */
  1304. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1305. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1306. }
  1307. static void g4x_disable_fbc(struct drm_device *dev)
  1308. {
  1309. struct drm_i915_private *dev_priv = dev->dev_private;
  1310. u32 dpfc_ctl;
  1311. /* Disable compression */
  1312. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1313. if (dpfc_ctl & DPFC_CTL_EN) {
  1314. dpfc_ctl &= ~DPFC_CTL_EN;
  1315. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1316. DRM_DEBUG_KMS("disabled FBC\n");
  1317. }
  1318. }
  1319. static bool g4x_fbc_enabled(struct drm_device *dev)
  1320. {
  1321. struct drm_i915_private *dev_priv = dev->dev_private;
  1322. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1323. }
  1324. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  1325. {
  1326. struct drm_i915_private *dev_priv = dev->dev_private;
  1327. u32 blt_ecoskpd;
  1328. /* Make sure blitter notifies FBC of writes */
  1329. gen6_gt_force_wake_get(dev_priv);
  1330. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  1331. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  1332. GEN6_BLITTER_LOCK_SHIFT;
  1333. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1334. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  1335. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1336. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  1337. GEN6_BLITTER_LOCK_SHIFT);
  1338. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1339. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  1340. gen6_gt_force_wake_put(dev_priv);
  1341. }
  1342. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1343. {
  1344. struct drm_device *dev = crtc->dev;
  1345. struct drm_i915_private *dev_priv = dev->dev_private;
  1346. struct drm_framebuffer *fb = crtc->fb;
  1347. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1348. struct drm_i915_gem_object *obj = intel_fb->obj;
  1349. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1350. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1351. unsigned long stall_watermark = 200;
  1352. u32 dpfc_ctl;
  1353. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1354. dpfc_ctl &= DPFC_RESERVED;
  1355. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  1356. /* Set persistent mode for front-buffer rendering, ala X. */
  1357. dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  1358. dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  1359. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  1360. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1361. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1362. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1363. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  1364. I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  1365. /* enable it... */
  1366. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  1367. if (IS_GEN6(dev)) {
  1368. I915_WRITE(SNB_DPFC_CTL_SA,
  1369. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  1370. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  1371. sandybridge_blit_fbc_update(dev);
  1372. }
  1373. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1374. }
  1375. static void ironlake_disable_fbc(struct drm_device *dev)
  1376. {
  1377. struct drm_i915_private *dev_priv = dev->dev_private;
  1378. u32 dpfc_ctl;
  1379. /* Disable compression */
  1380. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1381. if (dpfc_ctl & DPFC_CTL_EN) {
  1382. dpfc_ctl &= ~DPFC_CTL_EN;
  1383. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1384. DRM_DEBUG_KMS("disabled FBC\n");
  1385. }
  1386. }
  1387. static bool ironlake_fbc_enabled(struct drm_device *dev)
  1388. {
  1389. struct drm_i915_private *dev_priv = dev->dev_private;
  1390. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  1391. }
  1392. bool intel_fbc_enabled(struct drm_device *dev)
  1393. {
  1394. struct drm_i915_private *dev_priv = dev->dev_private;
  1395. if (!dev_priv->display.fbc_enabled)
  1396. return false;
  1397. return dev_priv->display.fbc_enabled(dev);
  1398. }
  1399. static void intel_fbc_work_fn(struct work_struct *__work)
  1400. {
  1401. struct intel_fbc_work *work =
  1402. container_of(to_delayed_work(__work),
  1403. struct intel_fbc_work, work);
  1404. struct drm_device *dev = work->crtc->dev;
  1405. struct drm_i915_private *dev_priv = dev->dev_private;
  1406. mutex_lock(&dev->struct_mutex);
  1407. if (work == dev_priv->fbc_work) {
  1408. /* Double check that we haven't switched fb without cancelling
  1409. * the prior work.
  1410. */
  1411. if (work->crtc->fb == work->fb) {
  1412. dev_priv->display.enable_fbc(work->crtc,
  1413. work->interval);
  1414. dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
  1415. dev_priv->cfb_fb = work->crtc->fb->base.id;
  1416. dev_priv->cfb_y = work->crtc->y;
  1417. }
  1418. dev_priv->fbc_work = NULL;
  1419. }
  1420. mutex_unlock(&dev->struct_mutex);
  1421. kfree(work);
  1422. }
  1423. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  1424. {
  1425. if (dev_priv->fbc_work == NULL)
  1426. return;
  1427. DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  1428. /* Synchronisation is provided by struct_mutex and checking of
  1429. * dev_priv->fbc_work, so we can perform the cancellation
  1430. * entirely asynchronously.
  1431. */
  1432. if (cancel_delayed_work(&dev_priv->fbc_work->work))
  1433. /* tasklet was killed before being run, clean up */
  1434. kfree(dev_priv->fbc_work);
  1435. /* Mark the work as no longer wanted so that if it does
  1436. * wake-up (because the work was already running and waiting
  1437. * for our mutex), it will discover that is no longer
  1438. * necessary to run.
  1439. */
  1440. dev_priv->fbc_work = NULL;
  1441. }
  1442. static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1443. {
  1444. struct intel_fbc_work *work;
  1445. struct drm_device *dev = crtc->dev;
  1446. struct drm_i915_private *dev_priv = dev->dev_private;
  1447. if (!dev_priv->display.enable_fbc)
  1448. return;
  1449. intel_cancel_fbc_work(dev_priv);
  1450. work = kzalloc(sizeof *work, GFP_KERNEL);
  1451. if (work == NULL) {
  1452. dev_priv->display.enable_fbc(crtc, interval);
  1453. return;
  1454. }
  1455. work->crtc = crtc;
  1456. work->fb = crtc->fb;
  1457. work->interval = interval;
  1458. INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  1459. dev_priv->fbc_work = work;
  1460. DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
  1461. /* Delay the actual enabling to let pageflipping cease and the
  1462. * display to settle before starting the compression. Note that
  1463. * this delay also serves a second purpose: it allows for a
  1464. * vblank to pass after disabling the FBC before we attempt
  1465. * to modify the control registers.
  1466. *
  1467. * A more complicated solution would involve tracking vblanks
  1468. * following the termination of the page-flipping sequence
  1469. * and indeed performing the enable as a co-routine and not
  1470. * waiting synchronously upon the vblank.
  1471. */
  1472. schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  1473. }
  1474. void intel_disable_fbc(struct drm_device *dev)
  1475. {
  1476. struct drm_i915_private *dev_priv = dev->dev_private;
  1477. intel_cancel_fbc_work(dev_priv);
  1478. if (!dev_priv->display.disable_fbc)
  1479. return;
  1480. dev_priv->display.disable_fbc(dev);
  1481. dev_priv->cfb_plane = -1;
  1482. }
  1483. /**
  1484. * intel_update_fbc - enable/disable FBC as needed
  1485. * @dev: the drm_device
  1486. *
  1487. * Set up the framebuffer compression hardware at mode set time. We
  1488. * enable it if possible:
  1489. * - plane A only (on pre-965)
  1490. * - no pixel mulitply/line duplication
  1491. * - no alpha buffer discard
  1492. * - no dual wide
  1493. * - framebuffer <= 2048 in width, 1536 in height
  1494. *
  1495. * We can't assume that any compression will take place (worst case),
  1496. * so the compressed buffer has to be the same size as the uncompressed
  1497. * one. It also must reside (along with the line length buffer) in
  1498. * stolen memory.
  1499. *
  1500. * We need to enable/disable FBC on a global basis.
  1501. */
  1502. static void intel_update_fbc(struct drm_device *dev)
  1503. {
  1504. struct drm_i915_private *dev_priv = dev->dev_private;
  1505. struct drm_crtc *crtc = NULL, *tmp_crtc;
  1506. struct intel_crtc *intel_crtc;
  1507. struct drm_framebuffer *fb;
  1508. struct intel_framebuffer *intel_fb;
  1509. struct drm_i915_gem_object *obj;
  1510. DRM_DEBUG_KMS("\n");
  1511. if (!i915_powersave)
  1512. return;
  1513. if (!I915_HAS_FBC(dev))
  1514. return;
  1515. /*
  1516. * If FBC is already on, we just have to verify that we can
  1517. * keep it that way...
  1518. * Need to disable if:
  1519. * - more than one pipe is active
  1520. * - changing FBC params (stride, fence, mode)
  1521. * - new fb is too large to fit in compressed buffer
  1522. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1523. */
  1524. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  1525. if (tmp_crtc->enabled && tmp_crtc->fb) {
  1526. if (crtc) {
  1527. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  1528. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  1529. goto out_disable;
  1530. }
  1531. crtc = tmp_crtc;
  1532. }
  1533. }
  1534. if (!crtc || crtc->fb == NULL) {
  1535. DRM_DEBUG_KMS("no output, disabling\n");
  1536. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  1537. goto out_disable;
  1538. }
  1539. intel_crtc = to_intel_crtc(crtc);
  1540. fb = crtc->fb;
  1541. intel_fb = to_intel_framebuffer(fb);
  1542. obj = intel_fb->obj;
  1543. if (!i915_enable_fbc) {
  1544. DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
  1545. dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  1546. goto out_disable;
  1547. }
  1548. if (intel_fb->obj->base.size > dev_priv->cfb_size) {
  1549. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1550. "compression\n");
  1551. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1552. goto out_disable;
  1553. }
  1554. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  1555. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  1556. DRM_DEBUG_KMS("mode incompatible with compression, "
  1557. "disabling\n");
  1558. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1559. goto out_disable;
  1560. }
  1561. if ((crtc->mode.hdisplay > 2048) ||
  1562. (crtc->mode.vdisplay > 1536)) {
  1563. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1564. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1565. goto out_disable;
  1566. }
  1567. if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  1568. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1569. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1570. goto out_disable;
  1571. }
  1572. /* The use of a CPU fence is mandatory in order to detect writes
  1573. * by the CPU to the scanout and trigger updates to the FBC.
  1574. */
  1575. if (obj->tiling_mode != I915_TILING_X ||
  1576. obj->fence_reg == I915_FENCE_REG_NONE) {
  1577. DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  1578. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1579. goto out_disable;
  1580. }
  1581. /* If the kernel debugger is active, always disable compression */
  1582. if (in_dbg_master())
  1583. goto out_disable;
  1584. /* If the scanout has not changed, don't modify the FBC settings.
  1585. * Note that we make the fundamental assumption that the fb->obj
  1586. * cannot be unpinned (and have its GTT offset and fence revoked)
  1587. * without first being decoupled from the scanout and FBC disabled.
  1588. */
  1589. if (dev_priv->cfb_plane == intel_crtc->plane &&
  1590. dev_priv->cfb_fb == fb->base.id &&
  1591. dev_priv->cfb_y == crtc->y)
  1592. return;
  1593. if (intel_fbc_enabled(dev)) {
  1594. /* We update FBC along two paths, after changing fb/crtc
  1595. * configuration (modeswitching) and after page-flipping
  1596. * finishes. For the latter, we know that not only did
  1597. * we disable the FBC at the start of the page-flip
  1598. * sequence, but also more than one vblank has passed.
  1599. *
  1600. * For the former case of modeswitching, it is possible
  1601. * to switch between two FBC valid configurations
  1602. * instantaneously so we do need to disable the FBC
  1603. * before we can modify its control registers. We also
  1604. * have to wait for the next vblank for that to take
  1605. * effect. However, since we delay enabling FBC we can
  1606. * assume that a vblank has passed since disabling and
  1607. * that we can safely alter the registers in the deferred
  1608. * callback.
  1609. *
  1610. * In the scenario that we go from a valid to invalid
  1611. * and then back to valid FBC configuration we have
  1612. * no strict enforcement that a vblank occurred since
  1613. * disabling the FBC. However, along all current pipe
  1614. * disabling paths we do need to wait for a vblank at
  1615. * some point. And we wait before enabling FBC anyway.
  1616. */
  1617. DRM_DEBUG_KMS("disabling active FBC for update\n");
  1618. intel_disable_fbc(dev);
  1619. }
  1620. intel_enable_fbc(crtc, 500);
  1621. return;
  1622. out_disable:
  1623. /* Multiple disables should be harmless */
  1624. if (intel_fbc_enabled(dev)) {
  1625. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1626. intel_disable_fbc(dev);
  1627. }
  1628. }
  1629. int
  1630. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1631. struct drm_i915_gem_object *obj,
  1632. struct intel_ring_buffer *pipelined)
  1633. {
  1634. struct drm_i915_private *dev_priv = dev->dev_private;
  1635. u32 alignment;
  1636. int ret;
  1637. switch (obj->tiling_mode) {
  1638. case I915_TILING_NONE:
  1639. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1640. alignment = 128 * 1024;
  1641. else if (INTEL_INFO(dev)->gen >= 4)
  1642. alignment = 4 * 1024;
  1643. else
  1644. alignment = 64 * 1024;
  1645. break;
  1646. case I915_TILING_X:
  1647. /* pin() will align the object as required by fence */
  1648. alignment = 0;
  1649. break;
  1650. case I915_TILING_Y:
  1651. /* FIXME: Is this true? */
  1652. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1653. return -EINVAL;
  1654. default:
  1655. BUG();
  1656. }
  1657. dev_priv->mm.interruptible = false;
  1658. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1659. if (ret)
  1660. goto err_interruptible;
  1661. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1662. * fence, whereas 965+ only requires a fence if using
  1663. * framebuffer compression. For simplicity, we always install
  1664. * a fence as the cost is not that onerous.
  1665. */
  1666. if (obj->tiling_mode != I915_TILING_NONE) {
  1667. ret = i915_gem_object_get_fence(obj, pipelined);
  1668. if (ret)
  1669. goto err_unpin;
  1670. }
  1671. dev_priv->mm.interruptible = true;
  1672. return 0;
  1673. err_unpin:
  1674. i915_gem_object_unpin(obj);
  1675. err_interruptible:
  1676. dev_priv->mm.interruptible = true;
  1677. return ret;
  1678. }
  1679. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1680. int x, int y)
  1681. {
  1682. struct drm_device *dev = crtc->dev;
  1683. struct drm_i915_private *dev_priv = dev->dev_private;
  1684. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1685. struct intel_framebuffer *intel_fb;
  1686. struct drm_i915_gem_object *obj;
  1687. int plane = intel_crtc->plane;
  1688. unsigned long Start, Offset;
  1689. u32 dspcntr;
  1690. u32 reg;
  1691. switch (plane) {
  1692. case 0:
  1693. case 1:
  1694. break;
  1695. default:
  1696. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1697. return -EINVAL;
  1698. }
  1699. intel_fb = to_intel_framebuffer(fb);
  1700. obj = intel_fb->obj;
  1701. reg = DSPCNTR(plane);
  1702. dspcntr = I915_READ(reg);
  1703. /* Mask out pixel format bits in case we change it */
  1704. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1705. switch (fb->bits_per_pixel) {
  1706. case 8:
  1707. dspcntr |= DISPPLANE_8BPP;
  1708. break;
  1709. case 16:
  1710. if (fb->depth == 15)
  1711. dspcntr |= DISPPLANE_15_16BPP;
  1712. else
  1713. dspcntr |= DISPPLANE_16BPP;
  1714. break;
  1715. case 24:
  1716. case 32:
  1717. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1718. break;
  1719. default:
  1720. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1721. return -EINVAL;
  1722. }
  1723. if (INTEL_INFO(dev)->gen >= 4) {
  1724. if (obj->tiling_mode != I915_TILING_NONE)
  1725. dspcntr |= DISPPLANE_TILED;
  1726. else
  1727. dspcntr &= ~DISPPLANE_TILED;
  1728. }
  1729. I915_WRITE(reg, dspcntr);
  1730. Start = obj->gtt_offset;
  1731. Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
  1732. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1733. Start, Offset, x, y, fb->pitch);
  1734. I915_WRITE(DSPSTRIDE(plane), fb->pitch);
  1735. if (INTEL_INFO(dev)->gen >= 4) {
  1736. I915_WRITE(DSPSURF(plane), Start);
  1737. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1738. I915_WRITE(DSPADDR(plane), Offset);
  1739. } else
  1740. I915_WRITE(DSPADDR(plane), Start + Offset);
  1741. POSTING_READ(reg);
  1742. return 0;
  1743. }
  1744. static int ironlake_update_plane(struct drm_crtc *crtc,
  1745. struct drm_framebuffer *fb, int x, int y)
  1746. {
  1747. struct drm_device *dev = crtc->dev;
  1748. struct drm_i915_private *dev_priv = dev->dev_private;
  1749. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1750. struct intel_framebuffer *intel_fb;
  1751. struct drm_i915_gem_object *obj;
  1752. int plane = intel_crtc->plane;
  1753. unsigned long Start, Offset;
  1754. u32 dspcntr;
  1755. u32 reg;
  1756. switch (plane) {
  1757. case 0:
  1758. case 1:
  1759. break;
  1760. default:
  1761. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1762. return -EINVAL;
  1763. }
  1764. intel_fb = to_intel_framebuffer(fb);
  1765. obj = intel_fb->obj;
  1766. reg = DSPCNTR(plane);
  1767. dspcntr = I915_READ(reg);
  1768. /* Mask out pixel format bits in case we change it */
  1769. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1770. switch (fb->bits_per_pixel) {
  1771. case 8:
  1772. dspcntr |= DISPPLANE_8BPP;
  1773. break;
  1774. case 16:
  1775. if (fb->depth != 16)
  1776. return -EINVAL;
  1777. dspcntr |= DISPPLANE_16BPP;
  1778. break;
  1779. case 24:
  1780. case 32:
  1781. if (fb->depth == 24)
  1782. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1783. else if (fb->depth == 30)
  1784. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1785. else
  1786. return -EINVAL;
  1787. break;
  1788. default:
  1789. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1790. return -EINVAL;
  1791. }
  1792. if (obj->tiling_mode != I915_TILING_NONE)
  1793. dspcntr |= DISPPLANE_TILED;
  1794. else
  1795. dspcntr &= ~DISPPLANE_TILED;
  1796. /* must disable */
  1797. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1798. I915_WRITE(reg, dspcntr);
  1799. Start = obj->gtt_offset;
  1800. Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
  1801. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1802. Start, Offset, x, y, fb->pitch);
  1803. I915_WRITE(DSPSTRIDE(plane), fb->pitch);
  1804. I915_WRITE(DSPSURF(plane), Start);
  1805. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1806. I915_WRITE(DSPADDR(plane), Offset);
  1807. POSTING_READ(reg);
  1808. return 0;
  1809. }
  1810. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1811. static int
  1812. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1813. int x, int y, enum mode_set_atomic state)
  1814. {
  1815. struct drm_device *dev = crtc->dev;
  1816. struct drm_i915_private *dev_priv = dev->dev_private;
  1817. int ret;
  1818. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  1819. if (ret)
  1820. return ret;
  1821. intel_update_fbc(dev);
  1822. intel_increase_pllclock(crtc);
  1823. return 0;
  1824. }
  1825. static int
  1826. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1827. struct drm_framebuffer *old_fb)
  1828. {
  1829. struct drm_device *dev = crtc->dev;
  1830. struct drm_i915_master_private *master_priv;
  1831. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1832. int ret;
  1833. /* no fb bound */
  1834. if (!crtc->fb) {
  1835. DRM_ERROR("No FB bound\n");
  1836. return 0;
  1837. }
  1838. switch (intel_crtc->plane) {
  1839. case 0:
  1840. case 1:
  1841. break;
  1842. default:
  1843. DRM_ERROR("no plane for crtc\n");
  1844. return -EINVAL;
  1845. }
  1846. mutex_lock(&dev->struct_mutex);
  1847. ret = intel_pin_and_fence_fb_obj(dev,
  1848. to_intel_framebuffer(crtc->fb)->obj,
  1849. NULL);
  1850. if (ret != 0) {
  1851. mutex_unlock(&dev->struct_mutex);
  1852. DRM_ERROR("pin & fence failed\n");
  1853. return ret;
  1854. }
  1855. if (old_fb) {
  1856. struct drm_i915_private *dev_priv = dev->dev_private;
  1857. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1858. wait_event(dev_priv->pending_flip_queue,
  1859. atomic_read(&dev_priv->mm.wedged) ||
  1860. atomic_read(&obj->pending_flip) == 0);
  1861. /* Big Hammer, we also need to ensure that any pending
  1862. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1863. * current scanout is retired before unpinning the old
  1864. * framebuffer.
  1865. *
  1866. * This should only fail upon a hung GPU, in which case we
  1867. * can safely continue.
  1868. */
  1869. ret = i915_gem_object_finish_gpu(obj);
  1870. (void) ret;
  1871. }
  1872. ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
  1873. LEAVE_ATOMIC_MODE_SET);
  1874. if (ret) {
  1875. i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
  1876. mutex_unlock(&dev->struct_mutex);
  1877. DRM_ERROR("failed to update base address\n");
  1878. return ret;
  1879. }
  1880. if (old_fb) {
  1881. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1882. i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
  1883. }
  1884. mutex_unlock(&dev->struct_mutex);
  1885. if (!dev->primary->master)
  1886. return 0;
  1887. master_priv = dev->primary->master->driver_priv;
  1888. if (!master_priv->sarea_priv)
  1889. return 0;
  1890. if (intel_crtc->pipe) {
  1891. master_priv->sarea_priv->pipeB_x = x;
  1892. master_priv->sarea_priv->pipeB_y = y;
  1893. } else {
  1894. master_priv->sarea_priv->pipeA_x = x;
  1895. master_priv->sarea_priv->pipeA_y = y;
  1896. }
  1897. return 0;
  1898. }
  1899. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  1900. {
  1901. struct drm_device *dev = crtc->dev;
  1902. struct drm_i915_private *dev_priv = dev->dev_private;
  1903. u32 dpa_ctl;
  1904. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1905. dpa_ctl = I915_READ(DP_A);
  1906. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1907. if (clock < 200000) {
  1908. u32 temp;
  1909. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1910. /* workaround for 160Mhz:
  1911. 1) program 0x4600c bits 15:0 = 0x8124
  1912. 2) program 0x46010 bit 0 = 1
  1913. 3) program 0x46034 bit 24 = 1
  1914. 4) program 0x64000 bit 14 = 1
  1915. */
  1916. temp = I915_READ(0x4600c);
  1917. temp &= 0xffff0000;
  1918. I915_WRITE(0x4600c, temp | 0x8124);
  1919. temp = I915_READ(0x46010);
  1920. I915_WRITE(0x46010, temp | 1);
  1921. temp = I915_READ(0x46034);
  1922. I915_WRITE(0x46034, temp | (1 << 24));
  1923. } else {
  1924. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1925. }
  1926. I915_WRITE(DP_A, dpa_ctl);
  1927. POSTING_READ(DP_A);
  1928. udelay(500);
  1929. }
  1930. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  1931. {
  1932. struct drm_device *dev = crtc->dev;
  1933. struct drm_i915_private *dev_priv = dev->dev_private;
  1934. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1935. int pipe = intel_crtc->pipe;
  1936. u32 reg, temp;
  1937. /* enable normal train */
  1938. reg = FDI_TX_CTL(pipe);
  1939. temp = I915_READ(reg);
  1940. if (IS_IVYBRIDGE(dev)) {
  1941. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  1942. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  1943. } else {
  1944. temp &= ~FDI_LINK_TRAIN_NONE;
  1945. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  1946. }
  1947. I915_WRITE(reg, temp);
  1948. reg = FDI_RX_CTL(pipe);
  1949. temp = I915_READ(reg);
  1950. if (HAS_PCH_CPT(dev)) {
  1951. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1952. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1953. } else {
  1954. temp &= ~FDI_LINK_TRAIN_NONE;
  1955. temp |= FDI_LINK_TRAIN_NONE;
  1956. }
  1957. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1958. /* wait one idle pattern time */
  1959. POSTING_READ(reg);
  1960. udelay(1000);
  1961. /* IVB wants error correction enabled */
  1962. if (IS_IVYBRIDGE(dev))
  1963. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  1964. FDI_FE_ERRC_ENABLE);
  1965. }
  1966. /* The FDI link training functions for ILK/Ibexpeak. */
  1967. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1968. {
  1969. struct drm_device *dev = crtc->dev;
  1970. struct drm_i915_private *dev_priv = dev->dev_private;
  1971. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1972. int pipe = intel_crtc->pipe;
  1973. int plane = intel_crtc->plane;
  1974. u32 reg, temp, tries;
  1975. /* FDI needs bits from pipe & plane first */
  1976. assert_pipe_enabled(dev_priv, pipe);
  1977. assert_plane_enabled(dev_priv, plane);
  1978. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1979. for train result */
  1980. reg = FDI_RX_IMR(pipe);
  1981. temp = I915_READ(reg);
  1982. temp &= ~FDI_RX_SYMBOL_LOCK;
  1983. temp &= ~FDI_RX_BIT_LOCK;
  1984. I915_WRITE(reg, temp);
  1985. I915_READ(reg);
  1986. udelay(150);
  1987. /* enable CPU FDI TX and PCH FDI RX */
  1988. reg = FDI_TX_CTL(pipe);
  1989. temp = I915_READ(reg);
  1990. temp &= ~(7 << 19);
  1991. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1992. temp &= ~FDI_LINK_TRAIN_NONE;
  1993. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1994. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  1995. reg = FDI_RX_CTL(pipe);
  1996. temp = I915_READ(reg);
  1997. temp &= ~FDI_LINK_TRAIN_NONE;
  1998. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1999. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2000. POSTING_READ(reg);
  2001. udelay(150);
  2002. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2003. if (HAS_PCH_IBX(dev)) {
  2004. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2005. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2006. FDI_RX_PHASE_SYNC_POINTER_EN);
  2007. }
  2008. reg = FDI_RX_IIR(pipe);
  2009. for (tries = 0; tries < 5; tries++) {
  2010. temp = I915_READ(reg);
  2011. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2012. if ((temp & FDI_RX_BIT_LOCK)) {
  2013. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2014. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2015. break;
  2016. }
  2017. }
  2018. if (tries == 5)
  2019. DRM_ERROR("FDI train 1 fail!\n");
  2020. /* Train 2 */
  2021. reg = FDI_TX_CTL(pipe);
  2022. temp = I915_READ(reg);
  2023. temp &= ~FDI_LINK_TRAIN_NONE;
  2024. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2025. I915_WRITE(reg, temp);
  2026. reg = FDI_RX_CTL(pipe);
  2027. temp = I915_READ(reg);
  2028. temp &= ~FDI_LINK_TRAIN_NONE;
  2029. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2030. I915_WRITE(reg, temp);
  2031. POSTING_READ(reg);
  2032. udelay(150);
  2033. reg = FDI_RX_IIR(pipe);
  2034. for (tries = 0; tries < 5; tries++) {
  2035. temp = I915_READ(reg);
  2036. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2037. if (temp & FDI_RX_SYMBOL_LOCK) {
  2038. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2039. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2040. break;
  2041. }
  2042. }
  2043. if (tries == 5)
  2044. DRM_ERROR("FDI train 2 fail!\n");
  2045. DRM_DEBUG_KMS("FDI train done\n");
  2046. }
  2047. static const int snb_b_fdi_train_param [] = {
  2048. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2049. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2050. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2051. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2052. };
  2053. /* The FDI link training functions for SNB/Cougarpoint. */
  2054. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2055. {
  2056. struct drm_device *dev = crtc->dev;
  2057. struct drm_i915_private *dev_priv = dev->dev_private;
  2058. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2059. int pipe = intel_crtc->pipe;
  2060. u32 reg, temp, i;
  2061. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2062. for train result */
  2063. reg = FDI_RX_IMR(pipe);
  2064. temp = I915_READ(reg);
  2065. temp &= ~FDI_RX_SYMBOL_LOCK;
  2066. temp &= ~FDI_RX_BIT_LOCK;
  2067. I915_WRITE(reg, temp);
  2068. POSTING_READ(reg);
  2069. udelay(150);
  2070. /* enable CPU FDI TX and PCH FDI RX */
  2071. reg = FDI_TX_CTL(pipe);
  2072. temp = I915_READ(reg);
  2073. temp &= ~(7 << 19);
  2074. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2075. temp &= ~FDI_LINK_TRAIN_NONE;
  2076. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2077. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2078. /* SNB-B */
  2079. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2080. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2081. reg = FDI_RX_CTL(pipe);
  2082. temp = I915_READ(reg);
  2083. if (HAS_PCH_CPT(dev)) {
  2084. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2085. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2086. } else {
  2087. temp &= ~FDI_LINK_TRAIN_NONE;
  2088. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2089. }
  2090. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2091. POSTING_READ(reg);
  2092. udelay(150);
  2093. for (i = 0; i < 4; i++ ) {
  2094. reg = FDI_TX_CTL(pipe);
  2095. temp = I915_READ(reg);
  2096. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2097. temp |= snb_b_fdi_train_param[i];
  2098. I915_WRITE(reg, temp);
  2099. POSTING_READ(reg);
  2100. udelay(500);
  2101. reg = FDI_RX_IIR(pipe);
  2102. temp = I915_READ(reg);
  2103. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2104. if (temp & FDI_RX_BIT_LOCK) {
  2105. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2106. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2107. break;
  2108. }
  2109. }
  2110. if (i == 4)
  2111. DRM_ERROR("FDI train 1 fail!\n");
  2112. /* Train 2 */
  2113. reg = FDI_TX_CTL(pipe);
  2114. temp = I915_READ(reg);
  2115. temp &= ~FDI_LINK_TRAIN_NONE;
  2116. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2117. if (IS_GEN6(dev)) {
  2118. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2119. /* SNB-B */
  2120. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2121. }
  2122. I915_WRITE(reg, temp);
  2123. reg = FDI_RX_CTL(pipe);
  2124. temp = I915_READ(reg);
  2125. if (HAS_PCH_CPT(dev)) {
  2126. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2127. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2128. } else {
  2129. temp &= ~FDI_LINK_TRAIN_NONE;
  2130. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2131. }
  2132. I915_WRITE(reg, temp);
  2133. POSTING_READ(reg);
  2134. udelay(150);
  2135. for (i = 0; i < 4; i++ ) {
  2136. reg = FDI_TX_CTL(pipe);
  2137. temp = I915_READ(reg);
  2138. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2139. temp |= snb_b_fdi_train_param[i];
  2140. I915_WRITE(reg, temp);
  2141. POSTING_READ(reg);
  2142. udelay(500);
  2143. reg = FDI_RX_IIR(pipe);
  2144. temp = I915_READ(reg);
  2145. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2146. if (temp & FDI_RX_SYMBOL_LOCK) {
  2147. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2148. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2149. break;
  2150. }
  2151. }
  2152. if (i == 4)
  2153. DRM_ERROR("FDI train 2 fail!\n");
  2154. DRM_DEBUG_KMS("FDI train done.\n");
  2155. }
  2156. /* Manual link training for Ivy Bridge A0 parts */
  2157. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2158. {
  2159. struct drm_device *dev = crtc->dev;
  2160. struct drm_i915_private *dev_priv = dev->dev_private;
  2161. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2162. int pipe = intel_crtc->pipe;
  2163. u32 reg, temp, i;
  2164. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2165. for train result */
  2166. reg = FDI_RX_IMR(pipe);
  2167. temp = I915_READ(reg);
  2168. temp &= ~FDI_RX_SYMBOL_LOCK;
  2169. temp &= ~FDI_RX_BIT_LOCK;
  2170. I915_WRITE(reg, temp);
  2171. POSTING_READ(reg);
  2172. udelay(150);
  2173. /* enable CPU FDI TX and PCH FDI RX */
  2174. reg = FDI_TX_CTL(pipe);
  2175. temp = I915_READ(reg);
  2176. temp &= ~(7 << 19);
  2177. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2178. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2179. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2180. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2181. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2182. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2183. reg = FDI_RX_CTL(pipe);
  2184. temp = I915_READ(reg);
  2185. temp &= ~FDI_LINK_TRAIN_AUTO;
  2186. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2187. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2188. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2189. POSTING_READ(reg);
  2190. udelay(150);
  2191. for (i = 0; i < 4; i++ ) {
  2192. reg = FDI_TX_CTL(pipe);
  2193. temp = I915_READ(reg);
  2194. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2195. temp |= snb_b_fdi_train_param[i];
  2196. I915_WRITE(reg, temp);
  2197. POSTING_READ(reg);
  2198. udelay(500);
  2199. reg = FDI_RX_IIR(pipe);
  2200. temp = I915_READ(reg);
  2201. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2202. if (temp & FDI_RX_BIT_LOCK ||
  2203. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2204. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2205. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2206. break;
  2207. }
  2208. }
  2209. if (i == 4)
  2210. DRM_ERROR("FDI train 1 fail!\n");
  2211. /* Train 2 */
  2212. reg = FDI_TX_CTL(pipe);
  2213. temp = I915_READ(reg);
  2214. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2215. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2216. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2217. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2218. I915_WRITE(reg, temp);
  2219. reg = FDI_RX_CTL(pipe);
  2220. temp = I915_READ(reg);
  2221. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2222. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2223. I915_WRITE(reg, temp);
  2224. POSTING_READ(reg);
  2225. udelay(150);
  2226. for (i = 0; i < 4; i++ ) {
  2227. reg = FDI_TX_CTL(pipe);
  2228. temp = I915_READ(reg);
  2229. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2230. temp |= snb_b_fdi_train_param[i];
  2231. I915_WRITE(reg, temp);
  2232. POSTING_READ(reg);
  2233. udelay(500);
  2234. reg = FDI_RX_IIR(pipe);
  2235. temp = I915_READ(reg);
  2236. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2237. if (temp & FDI_RX_SYMBOL_LOCK) {
  2238. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2239. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2240. break;
  2241. }
  2242. }
  2243. if (i == 4)
  2244. DRM_ERROR("FDI train 2 fail!\n");
  2245. DRM_DEBUG_KMS("FDI train done.\n");
  2246. }
  2247. static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
  2248. {
  2249. struct drm_device *dev = crtc->dev;
  2250. struct drm_i915_private *dev_priv = dev->dev_private;
  2251. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2252. int pipe = intel_crtc->pipe;
  2253. u32 reg, temp;
  2254. /* Write the TU size bits so error detection works */
  2255. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2256. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2257. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2258. reg = FDI_RX_CTL(pipe);
  2259. temp = I915_READ(reg);
  2260. temp &= ~((0x7 << 19) | (0x7 << 16));
  2261. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2262. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2263. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2264. POSTING_READ(reg);
  2265. udelay(200);
  2266. /* Switch from Rawclk to PCDclk */
  2267. temp = I915_READ(reg);
  2268. I915_WRITE(reg, temp | FDI_PCDCLK);
  2269. POSTING_READ(reg);
  2270. udelay(200);
  2271. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2272. reg = FDI_TX_CTL(pipe);
  2273. temp = I915_READ(reg);
  2274. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2275. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2276. POSTING_READ(reg);
  2277. udelay(100);
  2278. }
  2279. }
  2280. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2281. {
  2282. struct drm_device *dev = crtc->dev;
  2283. struct drm_i915_private *dev_priv = dev->dev_private;
  2284. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2285. int pipe = intel_crtc->pipe;
  2286. u32 reg, temp;
  2287. /* disable CPU FDI tx and PCH FDI rx */
  2288. reg = FDI_TX_CTL(pipe);
  2289. temp = I915_READ(reg);
  2290. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2291. POSTING_READ(reg);
  2292. reg = FDI_RX_CTL(pipe);
  2293. temp = I915_READ(reg);
  2294. temp &= ~(0x7 << 16);
  2295. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2296. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2297. POSTING_READ(reg);
  2298. udelay(100);
  2299. /* Ironlake workaround, disable clock pointer after downing FDI */
  2300. if (HAS_PCH_IBX(dev)) {
  2301. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2302. I915_WRITE(FDI_RX_CHICKEN(pipe),
  2303. I915_READ(FDI_RX_CHICKEN(pipe) &
  2304. ~FDI_RX_PHASE_SYNC_POINTER_EN));
  2305. }
  2306. /* still set train pattern 1 */
  2307. reg = FDI_TX_CTL(pipe);
  2308. temp = I915_READ(reg);
  2309. temp &= ~FDI_LINK_TRAIN_NONE;
  2310. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2311. I915_WRITE(reg, temp);
  2312. reg = FDI_RX_CTL(pipe);
  2313. temp = I915_READ(reg);
  2314. if (HAS_PCH_CPT(dev)) {
  2315. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2316. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2317. } else {
  2318. temp &= ~FDI_LINK_TRAIN_NONE;
  2319. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2320. }
  2321. /* BPC in FDI rx is consistent with that in PIPECONF */
  2322. temp &= ~(0x07 << 16);
  2323. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2324. I915_WRITE(reg, temp);
  2325. POSTING_READ(reg);
  2326. udelay(100);
  2327. }
  2328. /*
  2329. * When we disable a pipe, we need to clear any pending scanline wait events
  2330. * to avoid hanging the ring, which we assume we are waiting on.
  2331. */
  2332. static void intel_clear_scanline_wait(struct drm_device *dev)
  2333. {
  2334. struct drm_i915_private *dev_priv = dev->dev_private;
  2335. struct intel_ring_buffer *ring;
  2336. u32 tmp;
  2337. if (IS_GEN2(dev))
  2338. /* Can't break the hang on i8xx */
  2339. return;
  2340. ring = LP_RING(dev_priv);
  2341. tmp = I915_READ_CTL(ring);
  2342. if (tmp & RING_WAIT)
  2343. I915_WRITE_CTL(ring, tmp);
  2344. }
  2345. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2346. {
  2347. struct drm_i915_gem_object *obj;
  2348. struct drm_i915_private *dev_priv;
  2349. if (crtc->fb == NULL)
  2350. return;
  2351. obj = to_intel_framebuffer(crtc->fb)->obj;
  2352. dev_priv = crtc->dev->dev_private;
  2353. wait_event(dev_priv->pending_flip_queue,
  2354. atomic_read(&obj->pending_flip) == 0);
  2355. }
  2356. static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
  2357. {
  2358. struct drm_device *dev = crtc->dev;
  2359. struct drm_mode_config *mode_config = &dev->mode_config;
  2360. struct intel_encoder *encoder;
  2361. /*
  2362. * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
  2363. * must be driven by its own crtc; no sharing is possible.
  2364. */
  2365. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  2366. if (encoder->base.crtc != crtc)
  2367. continue;
  2368. switch (encoder->type) {
  2369. case INTEL_OUTPUT_EDP:
  2370. if (!intel_encoder_is_pch_edp(&encoder->base))
  2371. return false;
  2372. continue;
  2373. }
  2374. }
  2375. return true;
  2376. }
  2377. /*
  2378. * Enable PCH resources required for PCH ports:
  2379. * - PCH PLLs
  2380. * - FDI training & RX/TX
  2381. * - update transcoder timings
  2382. * - DP transcoding bits
  2383. * - transcoder
  2384. */
  2385. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2386. {
  2387. struct drm_device *dev = crtc->dev;
  2388. struct drm_i915_private *dev_priv = dev->dev_private;
  2389. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2390. int pipe = intel_crtc->pipe;
  2391. u32 reg, temp;
  2392. /* For PCH output, training FDI link */
  2393. dev_priv->display.fdi_link_train(crtc);
  2394. intel_enable_pch_pll(dev_priv, pipe);
  2395. if (HAS_PCH_CPT(dev)) {
  2396. /* Be sure PCH DPLL SEL is set */
  2397. temp = I915_READ(PCH_DPLL_SEL);
  2398. if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
  2399. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  2400. else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
  2401. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2402. I915_WRITE(PCH_DPLL_SEL, temp);
  2403. }
  2404. /* set transcoder timing, panel must allow it */
  2405. assert_panel_unlocked(dev_priv, pipe);
  2406. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2407. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2408. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2409. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2410. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2411. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2412. intel_fdi_normal_train(crtc);
  2413. /* For PCH DP, enable TRANS_DP_CTL */
  2414. if (HAS_PCH_CPT(dev) &&
  2415. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  2416. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
  2417. reg = TRANS_DP_CTL(pipe);
  2418. temp = I915_READ(reg);
  2419. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2420. TRANS_DP_SYNC_MASK |
  2421. TRANS_DP_BPC_MASK);
  2422. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2423. TRANS_DP_ENH_FRAMING);
  2424. temp |= bpc << 9; /* same format but at 11:9 */
  2425. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2426. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2427. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2428. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2429. switch (intel_trans_dp_port_sel(crtc)) {
  2430. case PCH_DP_B:
  2431. temp |= TRANS_DP_PORT_SEL_B;
  2432. break;
  2433. case PCH_DP_C:
  2434. temp |= TRANS_DP_PORT_SEL_C;
  2435. break;
  2436. case PCH_DP_D:
  2437. temp |= TRANS_DP_PORT_SEL_D;
  2438. break;
  2439. default:
  2440. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  2441. temp |= TRANS_DP_PORT_SEL_B;
  2442. break;
  2443. }
  2444. I915_WRITE(reg, temp);
  2445. }
  2446. intel_enable_transcoder(dev_priv, pipe);
  2447. }
  2448. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2449. {
  2450. struct drm_device *dev = crtc->dev;
  2451. struct drm_i915_private *dev_priv = dev->dev_private;
  2452. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2453. int pipe = intel_crtc->pipe;
  2454. int plane = intel_crtc->plane;
  2455. u32 temp;
  2456. bool is_pch_port;
  2457. if (intel_crtc->active)
  2458. return;
  2459. intel_crtc->active = true;
  2460. intel_update_watermarks(dev);
  2461. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2462. temp = I915_READ(PCH_LVDS);
  2463. if ((temp & LVDS_PORT_EN) == 0)
  2464. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2465. }
  2466. is_pch_port = intel_crtc_driving_pch(crtc);
  2467. if (is_pch_port)
  2468. ironlake_fdi_pll_enable(crtc);
  2469. else
  2470. ironlake_fdi_disable(crtc);
  2471. /* Enable panel fitting for LVDS */
  2472. if (dev_priv->pch_pf_size &&
  2473. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
  2474. /* Force use of hard-coded filter coefficients
  2475. * as some pre-programmed values are broken,
  2476. * e.g. x201.
  2477. */
  2478. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2479. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2480. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2481. }
  2482. /*
  2483. * On ILK+ LUT must be loaded before the pipe is running but with
  2484. * clocks enabled
  2485. */
  2486. intel_crtc_load_lut(crtc);
  2487. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2488. intel_enable_plane(dev_priv, plane, pipe);
  2489. if (is_pch_port)
  2490. ironlake_pch_enable(crtc);
  2491. mutex_lock(&dev->struct_mutex);
  2492. intel_update_fbc(dev);
  2493. mutex_unlock(&dev->struct_mutex);
  2494. intel_crtc_update_cursor(crtc, true);
  2495. }
  2496. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2497. {
  2498. struct drm_device *dev = crtc->dev;
  2499. struct drm_i915_private *dev_priv = dev->dev_private;
  2500. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2501. int pipe = intel_crtc->pipe;
  2502. int plane = intel_crtc->plane;
  2503. u32 reg, temp;
  2504. if (!intel_crtc->active)
  2505. return;
  2506. intel_crtc_wait_for_pending_flips(crtc);
  2507. drm_vblank_off(dev, pipe);
  2508. intel_crtc_update_cursor(crtc, false);
  2509. intel_disable_plane(dev_priv, plane, pipe);
  2510. if (dev_priv->cfb_plane == plane)
  2511. intel_disable_fbc(dev);
  2512. intel_disable_pipe(dev_priv, pipe);
  2513. /* Disable PF */
  2514. I915_WRITE(PF_CTL(pipe), 0);
  2515. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2516. ironlake_fdi_disable(crtc);
  2517. /* This is a horrible layering violation; we should be doing this in
  2518. * the connector/encoder ->prepare instead, but we don't always have
  2519. * enough information there about the config to know whether it will
  2520. * actually be necessary or just cause undesired flicker.
  2521. */
  2522. intel_disable_pch_ports(dev_priv, pipe);
  2523. intel_disable_transcoder(dev_priv, pipe);
  2524. if (HAS_PCH_CPT(dev)) {
  2525. /* disable TRANS_DP_CTL */
  2526. reg = TRANS_DP_CTL(pipe);
  2527. temp = I915_READ(reg);
  2528. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2529. temp |= TRANS_DP_PORT_SEL_NONE;
  2530. I915_WRITE(reg, temp);
  2531. /* disable DPLL_SEL */
  2532. temp = I915_READ(PCH_DPLL_SEL);
  2533. switch (pipe) {
  2534. case 0:
  2535. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  2536. break;
  2537. case 1:
  2538. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2539. break;
  2540. case 2:
  2541. /* FIXME: manage transcoder PLLs? */
  2542. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  2543. break;
  2544. default:
  2545. BUG(); /* wtf */
  2546. }
  2547. I915_WRITE(PCH_DPLL_SEL, temp);
  2548. }
  2549. /* disable PCH DPLL */
  2550. intel_disable_pch_pll(dev_priv, pipe);
  2551. /* Switch from PCDclk to Rawclk */
  2552. reg = FDI_RX_CTL(pipe);
  2553. temp = I915_READ(reg);
  2554. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2555. /* Disable CPU FDI TX PLL */
  2556. reg = FDI_TX_CTL(pipe);
  2557. temp = I915_READ(reg);
  2558. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2559. POSTING_READ(reg);
  2560. udelay(100);
  2561. reg = FDI_RX_CTL(pipe);
  2562. temp = I915_READ(reg);
  2563. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2564. /* Wait for the clocks to turn off. */
  2565. POSTING_READ(reg);
  2566. udelay(100);
  2567. intel_crtc->active = false;
  2568. intel_update_watermarks(dev);
  2569. mutex_lock(&dev->struct_mutex);
  2570. intel_update_fbc(dev);
  2571. intel_clear_scanline_wait(dev);
  2572. mutex_unlock(&dev->struct_mutex);
  2573. }
  2574. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  2575. {
  2576. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2577. int pipe = intel_crtc->pipe;
  2578. int plane = intel_crtc->plane;
  2579. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2580. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2581. */
  2582. switch (mode) {
  2583. case DRM_MODE_DPMS_ON:
  2584. case DRM_MODE_DPMS_STANDBY:
  2585. case DRM_MODE_DPMS_SUSPEND:
  2586. DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
  2587. ironlake_crtc_enable(crtc);
  2588. break;
  2589. case DRM_MODE_DPMS_OFF:
  2590. DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
  2591. ironlake_crtc_disable(crtc);
  2592. break;
  2593. }
  2594. }
  2595. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2596. {
  2597. if (!enable && intel_crtc->overlay) {
  2598. struct drm_device *dev = intel_crtc->base.dev;
  2599. struct drm_i915_private *dev_priv = dev->dev_private;
  2600. mutex_lock(&dev->struct_mutex);
  2601. dev_priv->mm.interruptible = false;
  2602. (void) intel_overlay_switch_off(intel_crtc->overlay);
  2603. dev_priv->mm.interruptible = true;
  2604. mutex_unlock(&dev->struct_mutex);
  2605. }
  2606. /* Let userspace switch the overlay on again. In most cases userspace
  2607. * has to recompute where to put it anyway.
  2608. */
  2609. }
  2610. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  2611. {
  2612. struct drm_device *dev = crtc->dev;
  2613. struct drm_i915_private *dev_priv = dev->dev_private;
  2614. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2615. int pipe = intel_crtc->pipe;
  2616. int plane = intel_crtc->plane;
  2617. if (intel_crtc->active)
  2618. return;
  2619. intel_crtc->active = true;
  2620. intel_update_watermarks(dev);
  2621. intel_enable_pll(dev_priv, pipe);
  2622. intel_enable_pipe(dev_priv, pipe, false);
  2623. intel_enable_plane(dev_priv, plane, pipe);
  2624. intel_crtc_load_lut(crtc);
  2625. intel_update_fbc(dev);
  2626. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2627. intel_crtc_dpms_overlay(intel_crtc, true);
  2628. intel_crtc_update_cursor(crtc, true);
  2629. }
  2630. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2631. {
  2632. struct drm_device *dev = crtc->dev;
  2633. struct drm_i915_private *dev_priv = dev->dev_private;
  2634. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2635. int pipe = intel_crtc->pipe;
  2636. int plane = intel_crtc->plane;
  2637. if (!intel_crtc->active)
  2638. return;
  2639. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2640. intel_crtc_wait_for_pending_flips(crtc);
  2641. drm_vblank_off(dev, pipe);
  2642. intel_crtc_dpms_overlay(intel_crtc, false);
  2643. intel_crtc_update_cursor(crtc, false);
  2644. if (dev_priv->cfb_plane == plane)
  2645. intel_disable_fbc(dev);
  2646. intel_disable_plane(dev_priv, plane, pipe);
  2647. intel_disable_pipe(dev_priv, pipe);
  2648. intel_disable_pll(dev_priv, pipe);
  2649. intel_crtc->active = false;
  2650. intel_update_fbc(dev);
  2651. intel_update_watermarks(dev);
  2652. intel_clear_scanline_wait(dev);
  2653. }
  2654. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  2655. {
  2656. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2657. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2658. */
  2659. switch (mode) {
  2660. case DRM_MODE_DPMS_ON:
  2661. case DRM_MODE_DPMS_STANDBY:
  2662. case DRM_MODE_DPMS_SUSPEND:
  2663. i9xx_crtc_enable(crtc);
  2664. break;
  2665. case DRM_MODE_DPMS_OFF:
  2666. i9xx_crtc_disable(crtc);
  2667. break;
  2668. }
  2669. }
  2670. /**
  2671. * Sets the power management mode of the pipe and plane.
  2672. */
  2673. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2674. {
  2675. struct drm_device *dev = crtc->dev;
  2676. struct drm_i915_private *dev_priv = dev->dev_private;
  2677. struct drm_i915_master_private *master_priv;
  2678. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2679. int pipe = intel_crtc->pipe;
  2680. bool enabled;
  2681. if (intel_crtc->dpms_mode == mode)
  2682. return;
  2683. intel_crtc->dpms_mode = mode;
  2684. dev_priv->display.dpms(crtc, mode);
  2685. if (!dev->primary->master)
  2686. return;
  2687. master_priv = dev->primary->master->driver_priv;
  2688. if (!master_priv->sarea_priv)
  2689. return;
  2690. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2691. switch (pipe) {
  2692. case 0:
  2693. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2694. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2695. break;
  2696. case 1:
  2697. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2698. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2699. break;
  2700. default:
  2701. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  2702. break;
  2703. }
  2704. }
  2705. static void intel_crtc_disable(struct drm_crtc *crtc)
  2706. {
  2707. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2708. struct drm_device *dev = crtc->dev;
  2709. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2710. if (crtc->fb) {
  2711. mutex_lock(&dev->struct_mutex);
  2712. i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
  2713. mutex_unlock(&dev->struct_mutex);
  2714. }
  2715. }
  2716. /* Prepare for a mode set.
  2717. *
  2718. * Note we could be a lot smarter here. We need to figure out which outputs
  2719. * will be enabled, which disabled (in short, how the config will changes)
  2720. * and perform the minimum necessary steps to accomplish that, e.g. updating
  2721. * watermarks, FBC configuration, making sure PLLs are programmed correctly,
  2722. * panel fitting is in the proper state, etc.
  2723. */
  2724. static void i9xx_crtc_prepare(struct drm_crtc *crtc)
  2725. {
  2726. i9xx_crtc_disable(crtc);
  2727. }
  2728. static void i9xx_crtc_commit(struct drm_crtc *crtc)
  2729. {
  2730. i9xx_crtc_enable(crtc);
  2731. }
  2732. static void ironlake_crtc_prepare(struct drm_crtc *crtc)
  2733. {
  2734. ironlake_crtc_disable(crtc);
  2735. }
  2736. static void ironlake_crtc_commit(struct drm_crtc *crtc)
  2737. {
  2738. ironlake_crtc_enable(crtc);
  2739. }
  2740. void intel_encoder_prepare (struct drm_encoder *encoder)
  2741. {
  2742. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2743. /* lvds has its own version of prepare see intel_lvds_prepare */
  2744. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2745. }
  2746. void intel_encoder_commit (struct drm_encoder *encoder)
  2747. {
  2748. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2749. /* lvds has its own version of commit see intel_lvds_commit */
  2750. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2751. }
  2752. void intel_encoder_destroy(struct drm_encoder *encoder)
  2753. {
  2754. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2755. drm_encoder_cleanup(encoder);
  2756. kfree(intel_encoder);
  2757. }
  2758. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2759. struct drm_display_mode *mode,
  2760. struct drm_display_mode *adjusted_mode)
  2761. {
  2762. struct drm_device *dev = crtc->dev;
  2763. if (HAS_PCH_SPLIT(dev)) {
  2764. /* FDI link clock is fixed at 2.7G */
  2765. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  2766. return false;
  2767. }
  2768. /* XXX some encoders set the crtcinfo, others don't.
  2769. * Obviously we need some form of conflict resolution here...
  2770. */
  2771. if (adjusted_mode->crtc_htotal == 0)
  2772. drm_mode_set_crtcinfo(adjusted_mode, 0);
  2773. return true;
  2774. }
  2775. static int i945_get_display_clock_speed(struct drm_device *dev)
  2776. {
  2777. return 400000;
  2778. }
  2779. static int i915_get_display_clock_speed(struct drm_device *dev)
  2780. {
  2781. return 333000;
  2782. }
  2783. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2784. {
  2785. return 200000;
  2786. }
  2787. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2788. {
  2789. u16 gcfgc = 0;
  2790. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2791. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2792. return 133000;
  2793. else {
  2794. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2795. case GC_DISPLAY_CLOCK_333_MHZ:
  2796. return 333000;
  2797. default:
  2798. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2799. return 190000;
  2800. }
  2801. }
  2802. }
  2803. static int i865_get_display_clock_speed(struct drm_device *dev)
  2804. {
  2805. return 266000;
  2806. }
  2807. static int i855_get_display_clock_speed(struct drm_device *dev)
  2808. {
  2809. u16 hpllcc = 0;
  2810. /* Assume that the hardware is in the high speed state. This
  2811. * should be the default.
  2812. */
  2813. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2814. case GC_CLOCK_133_200:
  2815. case GC_CLOCK_100_200:
  2816. return 200000;
  2817. case GC_CLOCK_166_250:
  2818. return 250000;
  2819. case GC_CLOCK_100_133:
  2820. return 133000;
  2821. }
  2822. /* Shouldn't happen */
  2823. return 0;
  2824. }
  2825. static int i830_get_display_clock_speed(struct drm_device *dev)
  2826. {
  2827. return 133000;
  2828. }
  2829. struct fdi_m_n {
  2830. u32 tu;
  2831. u32 gmch_m;
  2832. u32 gmch_n;
  2833. u32 link_m;
  2834. u32 link_n;
  2835. };
  2836. static void
  2837. fdi_reduce_ratio(u32 *num, u32 *den)
  2838. {
  2839. while (*num > 0xffffff || *den > 0xffffff) {
  2840. *num >>= 1;
  2841. *den >>= 1;
  2842. }
  2843. }
  2844. static void
  2845. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2846. int link_clock, struct fdi_m_n *m_n)
  2847. {
  2848. m_n->tu = 64; /* default size */
  2849. /* BUG_ON(pixel_clock > INT_MAX / 36); */
  2850. m_n->gmch_m = bits_per_pixel * pixel_clock;
  2851. m_n->gmch_n = link_clock * nlanes * 8;
  2852. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2853. m_n->link_m = pixel_clock;
  2854. m_n->link_n = link_clock;
  2855. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2856. }
  2857. struct intel_watermark_params {
  2858. unsigned long fifo_size;
  2859. unsigned long max_wm;
  2860. unsigned long default_wm;
  2861. unsigned long guard_size;
  2862. unsigned long cacheline_size;
  2863. };
  2864. /* Pineview has different values for various configs */
  2865. static const struct intel_watermark_params pineview_display_wm = {
  2866. PINEVIEW_DISPLAY_FIFO,
  2867. PINEVIEW_MAX_WM,
  2868. PINEVIEW_DFT_WM,
  2869. PINEVIEW_GUARD_WM,
  2870. PINEVIEW_FIFO_LINE_SIZE
  2871. };
  2872. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  2873. PINEVIEW_DISPLAY_FIFO,
  2874. PINEVIEW_MAX_WM,
  2875. PINEVIEW_DFT_HPLLOFF_WM,
  2876. PINEVIEW_GUARD_WM,
  2877. PINEVIEW_FIFO_LINE_SIZE
  2878. };
  2879. static const struct intel_watermark_params pineview_cursor_wm = {
  2880. PINEVIEW_CURSOR_FIFO,
  2881. PINEVIEW_CURSOR_MAX_WM,
  2882. PINEVIEW_CURSOR_DFT_WM,
  2883. PINEVIEW_CURSOR_GUARD_WM,
  2884. PINEVIEW_FIFO_LINE_SIZE,
  2885. };
  2886. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2887. PINEVIEW_CURSOR_FIFO,
  2888. PINEVIEW_CURSOR_MAX_WM,
  2889. PINEVIEW_CURSOR_DFT_WM,
  2890. PINEVIEW_CURSOR_GUARD_WM,
  2891. PINEVIEW_FIFO_LINE_SIZE
  2892. };
  2893. static const struct intel_watermark_params g4x_wm_info = {
  2894. G4X_FIFO_SIZE,
  2895. G4X_MAX_WM,
  2896. G4X_MAX_WM,
  2897. 2,
  2898. G4X_FIFO_LINE_SIZE,
  2899. };
  2900. static const struct intel_watermark_params g4x_cursor_wm_info = {
  2901. I965_CURSOR_FIFO,
  2902. I965_CURSOR_MAX_WM,
  2903. I965_CURSOR_DFT_WM,
  2904. 2,
  2905. G4X_FIFO_LINE_SIZE,
  2906. };
  2907. static const struct intel_watermark_params i965_cursor_wm_info = {
  2908. I965_CURSOR_FIFO,
  2909. I965_CURSOR_MAX_WM,
  2910. I965_CURSOR_DFT_WM,
  2911. 2,
  2912. I915_FIFO_LINE_SIZE,
  2913. };
  2914. static const struct intel_watermark_params i945_wm_info = {
  2915. I945_FIFO_SIZE,
  2916. I915_MAX_WM,
  2917. 1,
  2918. 2,
  2919. I915_FIFO_LINE_SIZE
  2920. };
  2921. static const struct intel_watermark_params i915_wm_info = {
  2922. I915_FIFO_SIZE,
  2923. I915_MAX_WM,
  2924. 1,
  2925. 2,
  2926. I915_FIFO_LINE_SIZE
  2927. };
  2928. static const struct intel_watermark_params i855_wm_info = {
  2929. I855GM_FIFO_SIZE,
  2930. I915_MAX_WM,
  2931. 1,
  2932. 2,
  2933. I830_FIFO_LINE_SIZE
  2934. };
  2935. static const struct intel_watermark_params i830_wm_info = {
  2936. I830_FIFO_SIZE,
  2937. I915_MAX_WM,
  2938. 1,
  2939. 2,
  2940. I830_FIFO_LINE_SIZE
  2941. };
  2942. static const struct intel_watermark_params ironlake_display_wm_info = {
  2943. ILK_DISPLAY_FIFO,
  2944. ILK_DISPLAY_MAXWM,
  2945. ILK_DISPLAY_DFTWM,
  2946. 2,
  2947. ILK_FIFO_LINE_SIZE
  2948. };
  2949. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  2950. ILK_CURSOR_FIFO,
  2951. ILK_CURSOR_MAXWM,
  2952. ILK_CURSOR_DFTWM,
  2953. 2,
  2954. ILK_FIFO_LINE_SIZE
  2955. };
  2956. static const struct intel_watermark_params ironlake_display_srwm_info = {
  2957. ILK_DISPLAY_SR_FIFO,
  2958. ILK_DISPLAY_MAX_SRWM,
  2959. ILK_DISPLAY_DFT_SRWM,
  2960. 2,
  2961. ILK_FIFO_LINE_SIZE
  2962. };
  2963. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  2964. ILK_CURSOR_SR_FIFO,
  2965. ILK_CURSOR_MAX_SRWM,
  2966. ILK_CURSOR_DFT_SRWM,
  2967. 2,
  2968. ILK_FIFO_LINE_SIZE
  2969. };
  2970. static const struct intel_watermark_params sandybridge_display_wm_info = {
  2971. SNB_DISPLAY_FIFO,
  2972. SNB_DISPLAY_MAXWM,
  2973. SNB_DISPLAY_DFTWM,
  2974. 2,
  2975. SNB_FIFO_LINE_SIZE
  2976. };
  2977. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  2978. SNB_CURSOR_FIFO,
  2979. SNB_CURSOR_MAXWM,
  2980. SNB_CURSOR_DFTWM,
  2981. 2,
  2982. SNB_FIFO_LINE_SIZE
  2983. };
  2984. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  2985. SNB_DISPLAY_SR_FIFO,
  2986. SNB_DISPLAY_MAX_SRWM,
  2987. SNB_DISPLAY_DFT_SRWM,
  2988. 2,
  2989. SNB_FIFO_LINE_SIZE
  2990. };
  2991. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  2992. SNB_CURSOR_SR_FIFO,
  2993. SNB_CURSOR_MAX_SRWM,
  2994. SNB_CURSOR_DFT_SRWM,
  2995. 2,
  2996. SNB_FIFO_LINE_SIZE
  2997. };
  2998. /**
  2999. * intel_calculate_wm - calculate watermark level
  3000. * @clock_in_khz: pixel clock
  3001. * @wm: chip FIFO params
  3002. * @pixel_size: display pixel size
  3003. * @latency_ns: memory latency for the platform
  3004. *
  3005. * Calculate the watermark level (the level at which the display plane will
  3006. * start fetching from memory again). Each chip has a different display
  3007. * FIFO size and allocation, so the caller needs to figure that out and pass
  3008. * in the correct intel_watermark_params structure.
  3009. *
  3010. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  3011. * on the pixel size. When it reaches the watermark level, it'll start
  3012. * fetching FIFO line sized based chunks from memory until the FIFO fills
  3013. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  3014. * will occur, and a display engine hang could result.
  3015. */
  3016. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  3017. const struct intel_watermark_params *wm,
  3018. int fifo_size,
  3019. int pixel_size,
  3020. unsigned long latency_ns)
  3021. {
  3022. long entries_required, wm_size;
  3023. /*
  3024. * Note: we need to make sure we don't overflow for various clock &
  3025. * latency values.
  3026. * clocks go from a few thousand to several hundred thousand.
  3027. * latency is usually a few thousand
  3028. */
  3029. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  3030. 1000;
  3031. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  3032. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  3033. wm_size = fifo_size - (entries_required + wm->guard_size);
  3034. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  3035. /* Don't promote wm_size to unsigned... */
  3036. if (wm_size > (long)wm->max_wm)
  3037. wm_size = wm->max_wm;
  3038. if (wm_size <= 0)
  3039. wm_size = wm->default_wm;
  3040. return wm_size;
  3041. }
  3042. struct cxsr_latency {
  3043. int is_desktop;
  3044. int is_ddr3;
  3045. unsigned long fsb_freq;
  3046. unsigned long mem_freq;
  3047. unsigned long display_sr;
  3048. unsigned long display_hpll_disable;
  3049. unsigned long cursor_sr;
  3050. unsigned long cursor_hpll_disable;
  3051. };
  3052. static const struct cxsr_latency cxsr_latency_table[] = {
  3053. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  3054. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  3055. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  3056. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  3057. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  3058. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  3059. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  3060. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  3061. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  3062. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  3063. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  3064. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  3065. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  3066. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  3067. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  3068. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  3069. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  3070. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  3071. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  3072. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  3073. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  3074. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  3075. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  3076. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  3077. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  3078. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  3079. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  3080. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  3081. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  3082. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  3083. };
  3084. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  3085. int is_ddr3,
  3086. int fsb,
  3087. int mem)
  3088. {
  3089. const struct cxsr_latency *latency;
  3090. int i;
  3091. if (fsb == 0 || mem == 0)
  3092. return NULL;
  3093. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  3094. latency = &cxsr_latency_table[i];
  3095. if (is_desktop == latency->is_desktop &&
  3096. is_ddr3 == latency->is_ddr3 &&
  3097. fsb == latency->fsb_freq && mem == latency->mem_freq)
  3098. return latency;
  3099. }
  3100. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  3101. return NULL;
  3102. }
  3103. static void pineview_disable_cxsr(struct drm_device *dev)
  3104. {
  3105. struct drm_i915_private *dev_priv = dev->dev_private;
  3106. /* deactivate cxsr */
  3107. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  3108. }
  3109. /*
  3110. * Latency for FIFO fetches is dependent on several factors:
  3111. * - memory configuration (speed, channels)
  3112. * - chipset
  3113. * - current MCH state
  3114. * It can be fairly high in some situations, so here we assume a fairly
  3115. * pessimal value. It's a tradeoff between extra memory fetches (if we
  3116. * set this value too high, the FIFO will fetch frequently to stay full)
  3117. * and power consumption (set it too low to save power and we might see
  3118. * FIFO underruns and display "flicker").
  3119. *
  3120. * A value of 5us seems to be a good balance; safe for very low end
  3121. * platforms but not overly aggressive on lower latency configs.
  3122. */
  3123. static const int latency_ns = 5000;
  3124. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  3125. {
  3126. struct drm_i915_private *dev_priv = dev->dev_private;
  3127. uint32_t dsparb = I915_READ(DSPARB);
  3128. int size;
  3129. size = dsparb & 0x7f;
  3130. if (plane)
  3131. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  3132. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3133. plane ? "B" : "A", size);
  3134. return size;
  3135. }
  3136. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  3137. {
  3138. struct drm_i915_private *dev_priv = dev->dev_private;
  3139. uint32_t dsparb = I915_READ(DSPARB);
  3140. int size;
  3141. size = dsparb & 0x1ff;
  3142. if (plane)
  3143. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  3144. size >>= 1; /* Convert to cachelines */
  3145. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3146. plane ? "B" : "A", size);
  3147. return size;
  3148. }
  3149. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  3150. {
  3151. struct drm_i915_private *dev_priv = dev->dev_private;
  3152. uint32_t dsparb = I915_READ(DSPARB);
  3153. int size;
  3154. size = dsparb & 0x7f;
  3155. size >>= 2; /* Convert to cachelines */
  3156. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3157. plane ? "B" : "A",
  3158. size);
  3159. return size;
  3160. }
  3161. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  3162. {
  3163. struct drm_i915_private *dev_priv = dev->dev_private;
  3164. uint32_t dsparb = I915_READ(DSPARB);
  3165. int size;
  3166. size = dsparb & 0x7f;
  3167. size >>= 1; /* Convert to cachelines */
  3168. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3169. plane ? "B" : "A", size);
  3170. return size;
  3171. }
  3172. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  3173. {
  3174. struct drm_crtc *crtc, *enabled = NULL;
  3175. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3176. if (crtc->enabled && crtc->fb) {
  3177. if (enabled)
  3178. return NULL;
  3179. enabled = crtc;
  3180. }
  3181. }
  3182. return enabled;
  3183. }
  3184. static void pineview_update_wm(struct drm_device *dev)
  3185. {
  3186. struct drm_i915_private *dev_priv = dev->dev_private;
  3187. struct drm_crtc *crtc;
  3188. const struct cxsr_latency *latency;
  3189. u32 reg;
  3190. unsigned long wm;
  3191. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  3192. dev_priv->fsb_freq, dev_priv->mem_freq);
  3193. if (!latency) {
  3194. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  3195. pineview_disable_cxsr(dev);
  3196. return;
  3197. }
  3198. crtc = single_enabled_crtc(dev);
  3199. if (crtc) {
  3200. int clock = crtc->mode.clock;
  3201. int pixel_size = crtc->fb->bits_per_pixel / 8;
  3202. /* Display SR */
  3203. wm = intel_calculate_wm(clock, &pineview_display_wm,
  3204. pineview_display_wm.fifo_size,
  3205. pixel_size, latency->display_sr);
  3206. reg = I915_READ(DSPFW1);
  3207. reg &= ~DSPFW_SR_MASK;
  3208. reg |= wm << DSPFW_SR_SHIFT;
  3209. I915_WRITE(DSPFW1, reg);
  3210. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  3211. /* cursor SR */
  3212. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  3213. pineview_display_wm.fifo_size,
  3214. pixel_size, latency->cursor_sr);
  3215. reg = I915_READ(DSPFW3);
  3216. reg &= ~DSPFW_CURSOR_SR_MASK;
  3217. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  3218. I915_WRITE(DSPFW3, reg);
  3219. /* Display HPLL off SR */
  3220. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  3221. pineview_display_hplloff_wm.fifo_size,
  3222. pixel_size, latency->display_hpll_disable);
  3223. reg = I915_READ(DSPFW3);
  3224. reg &= ~DSPFW_HPLL_SR_MASK;
  3225. reg |= wm & DSPFW_HPLL_SR_MASK;
  3226. I915_WRITE(DSPFW3, reg);
  3227. /* cursor HPLL off SR */
  3228. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  3229. pineview_display_hplloff_wm.fifo_size,
  3230. pixel_size, latency->cursor_hpll_disable);
  3231. reg = I915_READ(DSPFW3);
  3232. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  3233. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  3234. I915_WRITE(DSPFW3, reg);
  3235. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  3236. /* activate cxsr */
  3237. I915_WRITE(DSPFW3,
  3238. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  3239. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  3240. } else {
  3241. pineview_disable_cxsr(dev);
  3242. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  3243. }
  3244. }
  3245. static bool g4x_compute_wm0(struct drm_device *dev,
  3246. int plane,
  3247. const struct intel_watermark_params *display,
  3248. int display_latency_ns,
  3249. const struct intel_watermark_params *cursor,
  3250. int cursor_latency_ns,
  3251. int *plane_wm,
  3252. int *cursor_wm)
  3253. {
  3254. struct drm_crtc *crtc;
  3255. int htotal, hdisplay, clock, pixel_size;
  3256. int line_time_us, line_count;
  3257. int entries, tlb_miss;
  3258. crtc = intel_get_crtc_for_plane(dev, plane);
  3259. if (crtc->fb == NULL || !crtc->enabled) {
  3260. *cursor_wm = cursor->guard_size;
  3261. *plane_wm = display->guard_size;
  3262. return false;
  3263. }
  3264. htotal = crtc->mode.htotal;
  3265. hdisplay = crtc->mode.hdisplay;
  3266. clock = crtc->mode.clock;
  3267. pixel_size = crtc->fb->bits_per_pixel / 8;
  3268. /* Use the small buffer method to calculate plane watermark */
  3269. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  3270. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  3271. if (tlb_miss > 0)
  3272. entries += tlb_miss;
  3273. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  3274. *plane_wm = entries + display->guard_size;
  3275. if (*plane_wm > (int)display->max_wm)
  3276. *plane_wm = display->max_wm;
  3277. /* Use the large buffer method to calculate cursor watermark */
  3278. line_time_us = ((htotal * 1000) / clock);
  3279. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  3280. entries = line_count * 64 * pixel_size;
  3281. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  3282. if (tlb_miss > 0)
  3283. entries += tlb_miss;
  3284. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3285. *cursor_wm = entries + cursor->guard_size;
  3286. if (*cursor_wm > (int)cursor->max_wm)
  3287. *cursor_wm = (int)cursor->max_wm;
  3288. return true;
  3289. }
  3290. /*
  3291. * Check the wm result.
  3292. *
  3293. * If any calculated watermark values is larger than the maximum value that
  3294. * can be programmed into the associated watermark register, that watermark
  3295. * must be disabled.
  3296. */
  3297. static bool g4x_check_srwm(struct drm_device *dev,
  3298. int display_wm, int cursor_wm,
  3299. const struct intel_watermark_params *display,
  3300. const struct intel_watermark_params *cursor)
  3301. {
  3302. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  3303. display_wm, cursor_wm);
  3304. if (display_wm > display->max_wm) {
  3305. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  3306. display_wm, display->max_wm);
  3307. return false;
  3308. }
  3309. if (cursor_wm > cursor->max_wm) {
  3310. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  3311. cursor_wm, cursor->max_wm);
  3312. return false;
  3313. }
  3314. if (!(display_wm || cursor_wm)) {
  3315. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  3316. return false;
  3317. }
  3318. return true;
  3319. }
  3320. static bool g4x_compute_srwm(struct drm_device *dev,
  3321. int plane,
  3322. int latency_ns,
  3323. const struct intel_watermark_params *display,
  3324. const struct intel_watermark_params *cursor,
  3325. int *display_wm, int *cursor_wm)
  3326. {
  3327. struct drm_crtc *crtc;
  3328. int hdisplay, htotal, pixel_size, clock;
  3329. unsigned long line_time_us;
  3330. int line_count, line_size;
  3331. int small, large;
  3332. int entries;
  3333. if (!latency_ns) {
  3334. *display_wm = *cursor_wm = 0;
  3335. return false;
  3336. }
  3337. crtc = intel_get_crtc_for_plane(dev, plane);
  3338. hdisplay = crtc->mode.hdisplay;
  3339. htotal = crtc->mode.htotal;
  3340. clock = crtc->mode.clock;
  3341. pixel_size = crtc->fb->bits_per_pixel / 8;
  3342. line_time_us = (htotal * 1000) / clock;
  3343. line_count = (latency_ns / line_time_us + 1000) / 1000;
  3344. line_size = hdisplay * pixel_size;
  3345. /* Use the minimum of the small and large buffer method for primary */
  3346. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  3347. large = line_count * line_size;
  3348. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  3349. *display_wm = entries + display->guard_size;
  3350. /* calculate the self-refresh watermark for display cursor */
  3351. entries = line_count * pixel_size * 64;
  3352. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3353. *cursor_wm = entries + cursor->guard_size;
  3354. return g4x_check_srwm(dev,
  3355. *display_wm, *cursor_wm,
  3356. display, cursor);
  3357. }
  3358. #define single_plane_enabled(mask) is_power_of_2(mask)
  3359. static void g4x_update_wm(struct drm_device *dev)
  3360. {
  3361. static const int sr_latency_ns = 12000;
  3362. struct drm_i915_private *dev_priv = dev->dev_private;
  3363. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  3364. int plane_sr, cursor_sr;
  3365. unsigned int enabled = 0;
  3366. if (g4x_compute_wm0(dev, 0,
  3367. &g4x_wm_info, latency_ns,
  3368. &g4x_cursor_wm_info, latency_ns,
  3369. &planea_wm, &cursora_wm))
  3370. enabled |= 1;
  3371. if (g4x_compute_wm0(dev, 1,
  3372. &g4x_wm_info, latency_ns,
  3373. &g4x_cursor_wm_info, latency_ns,
  3374. &planeb_wm, &cursorb_wm))
  3375. enabled |= 2;
  3376. plane_sr = cursor_sr = 0;
  3377. if (single_plane_enabled(enabled) &&
  3378. g4x_compute_srwm(dev, ffs(enabled) - 1,
  3379. sr_latency_ns,
  3380. &g4x_wm_info,
  3381. &g4x_cursor_wm_info,
  3382. &plane_sr, &cursor_sr))
  3383. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  3384. else
  3385. I915_WRITE(FW_BLC_SELF,
  3386. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  3387. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  3388. planea_wm, cursora_wm,
  3389. planeb_wm, cursorb_wm,
  3390. plane_sr, cursor_sr);
  3391. I915_WRITE(DSPFW1,
  3392. (plane_sr << DSPFW_SR_SHIFT) |
  3393. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  3394. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  3395. planea_wm);
  3396. I915_WRITE(DSPFW2,
  3397. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  3398. (cursora_wm << DSPFW_CURSORA_SHIFT));
  3399. /* HPLL off in SR has some issues on G4x... disable it */
  3400. I915_WRITE(DSPFW3,
  3401. (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  3402. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  3403. }
  3404. static void i965_update_wm(struct drm_device *dev)
  3405. {
  3406. struct drm_i915_private *dev_priv = dev->dev_private;
  3407. struct drm_crtc *crtc;
  3408. int srwm = 1;
  3409. int cursor_sr = 16;
  3410. /* Calc sr entries for one plane configs */
  3411. crtc = single_enabled_crtc(dev);
  3412. if (crtc) {
  3413. /* self-refresh has much higher latency */
  3414. static const int sr_latency_ns = 12000;
  3415. int clock = crtc->mode.clock;
  3416. int htotal = crtc->mode.htotal;
  3417. int hdisplay = crtc->mode.hdisplay;
  3418. int pixel_size = crtc->fb->bits_per_pixel / 8;
  3419. unsigned long line_time_us;
  3420. int entries;
  3421. line_time_us = ((htotal * 1000) / clock);
  3422. /* Use ns/us then divide to preserve precision */
  3423. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3424. pixel_size * hdisplay;
  3425. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  3426. srwm = I965_FIFO_SIZE - entries;
  3427. if (srwm < 0)
  3428. srwm = 1;
  3429. srwm &= 0x1ff;
  3430. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  3431. entries, srwm);
  3432. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3433. pixel_size * 64;
  3434. entries = DIV_ROUND_UP(entries,
  3435. i965_cursor_wm_info.cacheline_size);
  3436. cursor_sr = i965_cursor_wm_info.fifo_size -
  3437. (entries + i965_cursor_wm_info.guard_size);
  3438. if (cursor_sr > i965_cursor_wm_info.max_wm)
  3439. cursor_sr = i965_cursor_wm_info.max_wm;
  3440. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  3441. "cursor %d\n", srwm, cursor_sr);
  3442. if (IS_CRESTLINE(dev))
  3443. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  3444. } else {
  3445. /* Turn off self refresh if both pipes are enabled */
  3446. if (IS_CRESTLINE(dev))
  3447. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  3448. & ~FW_BLC_SELF_EN);
  3449. }
  3450. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  3451. srwm);
  3452. /* 965 has limitations... */
  3453. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  3454. (8 << 16) | (8 << 8) | (8 << 0));
  3455. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  3456. /* update cursor SR watermark */
  3457. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  3458. }
  3459. static void i9xx_update_wm(struct drm_device *dev)
  3460. {
  3461. struct drm_i915_private *dev_priv = dev->dev_private;
  3462. const struct intel_watermark_params *wm_info;
  3463. uint32_t fwater_lo;
  3464. uint32_t fwater_hi;
  3465. int cwm, srwm = 1;
  3466. int fifo_size;
  3467. int planea_wm, planeb_wm;
  3468. struct drm_crtc *crtc, *enabled = NULL;
  3469. if (IS_I945GM(dev))
  3470. wm_info = &i945_wm_info;
  3471. else if (!IS_GEN2(dev))
  3472. wm_info = &i915_wm_info;
  3473. else
  3474. wm_info = &i855_wm_info;
  3475. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  3476. crtc = intel_get_crtc_for_plane(dev, 0);
  3477. if (crtc->enabled && crtc->fb) {
  3478. planea_wm = intel_calculate_wm(crtc->mode.clock,
  3479. wm_info, fifo_size,
  3480. crtc->fb->bits_per_pixel / 8,
  3481. latency_ns);
  3482. enabled = crtc;
  3483. } else
  3484. planea_wm = fifo_size - wm_info->guard_size;
  3485. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  3486. crtc = intel_get_crtc_for_plane(dev, 1);
  3487. if (crtc->enabled && crtc->fb) {
  3488. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  3489. wm_info, fifo_size,
  3490. crtc->fb->bits_per_pixel / 8,
  3491. latency_ns);
  3492. if (enabled == NULL)
  3493. enabled = crtc;
  3494. else
  3495. enabled = NULL;
  3496. } else
  3497. planeb_wm = fifo_size - wm_info->guard_size;
  3498. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  3499. /*
  3500. * Overlay gets an aggressive default since video jitter is bad.
  3501. */
  3502. cwm = 2;
  3503. /* Play safe and disable self-refresh before adjusting watermarks. */
  3504. if (IS_I945G(dev) || IS_I945GM(dev))
  3505. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  3506. else if (IS_I915GM(dev))
  3507. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  3508. /* Calc sr entries for one plane configs */
  3509. if (HAS_FW_BLC(dev) && enabled) {
  3510. /* self-refresh has much higher latency */
  3511. static const int sr_latency_ns = 6000;
  3512. int clock = enabled->mode.clock;
  3513. int htotal = enabled->mode.htotal;
  3514. int hdisplay = enabled->mode.hdisplay;
  3515. int pixel_size = enabled->fb->bits_per_pixel / 8;
  3516. unsigned long line_time_us;
  3517. int entries;
  3518. line_time_us = (htotal * 1000) / clock;
  3519. /* Use ns/us then divide to preserve precision */
  3520. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3521. pixel_size * hdisplay;
  3522. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  3523. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  3524. srwm = wm_info->fifo_size - entries;
  3525. if (srwm < 0)
  3526. srwm = 1;
  3527. if (IS_I945G(dev) || IS_I945GM(dev))
  3528. I915_WRITE(FW_BLC_SELF,
  3529. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  3530. else if (IS_I915GM(dev))
  3531. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  3532. }
  3533. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  3534. planea_wm, planeb_wm, cwm, srwm);
  3535. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  3536. fwater_hi = (cwm & 0x1f);
  3537. /* Set request length to 8 cachelines per fetch */
  3538. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  3539. fwater_hi = fwater_hi | (1 << 8);
  3540. I915_WRITE(FW_BLC, fwater_lo);
  3541. I915_WRITE(FW_BLC2, fwater_hi);
  3542. if (HAS_FW_BLC(dev)) {
  3543. if (enabled) {
  3544. if (IS_I945G(dev) || IS_I945GM(dev))
  3545. I915_WRITE(FW_BLC_SELF,
  3546. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  3547. else if (IS_I915GM(dev))
  3548. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  3549. DRM_DEBUG_KMS("memory self refresh enabled\n");
  3550. } else
  3551. DRM_DEBUG_KMS("memory self refresh disabled\n");
  3552. }
  3553. }
  3554. static void i830_update_wm(struct drm_device *dev)
  3555. {
  3556. struct drm_i915_private *dev_priv = dev->dev_private;
  3557. struct drm_crtc *crtc;
  3558. uint32_t fwater_lo;
  3559. int planea_wm;
  3560. crtc = single_enabled_crtc(dev);
  3561. if (crtc == NULL)
  3562. return;
  3563. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  3564. dev_priv->display.get_fifo_size(dev, 0),
  3565. crtc->fb->bits_per_pixel / 8,
  3566. latency_ns);
  3567. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  3568. fwater_lo |= (3<<8) | planea_wm;
  3569. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  3570. I915_WRITE(FW_BLC, fwater_lo);
  3571. }
  3572. #define ILK_LP0_PLANE_LATENCY 700
  3573. #define ILK_LP0_CURSOR_LATENCY 1300
  3574. /*
  3575. * Check the wm result.
  3576. *
  3577. * If any calculated watermark values is larger than the maximum value that
  3578. * can be programmed into the associated watermark register, that watermark
  3579. * must be disabled.
  3580. */
  3581. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  3582. int fbc_wm, int display_wm, int cursor_wm,
  3583. const struct intel_watermark_params *display,
  3584. const struct intel_watermark_params *cursor)
  3585. {
  3586. struct drm_i915_private *dev_priv = dev->dev_private;
  3587. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  3588. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  3589. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  3590. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  3591. fbc_wm, SNB_FBC_MAX_SRWM, level);
  3592. /* fbc has it's own way to disable FBC WM */
  3593. I915_WRITE(DISP_ARB_CTL,
  3594. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  3595. return false;
  3596. }
  3597. if (display_wm > display->max_wm) {
  3598. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  3599. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  3600. return false;
  3601. }
  3602. if (cursor_wm > cursor->max_wm) {
  3603. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  3604. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  3605. return false;
  3606. }
  3607. if (!(fbc_wm || display_wm || cursor_wm)) {
  3608. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  3609. return false;
  3610. }
  3611. return true;
  3612. }
  3613. /*
  3614. * Compute watermark values of WM[1-3],
  3615. */
  3616. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  3617. int latency_ns,
  3618. const struct intel_watermark_params *display,
  3619. const struct intel_watermark_params *cursor,
  3620. int *fbc_wm, int *display_wm, int *cursor_wm)
  3621. {
  3622. struct drm_crtc *crtc;
  3623. unsigned long line_time_us;
  3624. int hdisplay, htotal, pixel_size, clock;
  3625. int line_count, line_size;
  3626. int small, large;
  3627. int entries;
  3628. if (!latency_ns) {
  3629. *fbc_wm = *display_wm = *cursor_wm = 0;
  3630. return false;
  3631. }
  3632. crtc = intel_get_crtc_for_plane(dev, plane);
  3633. hdisplay = crtc->mode.hdisplay;
  3634. htotal = crtc->mode.htotal;
  3635. clock = crtc->mode.clock;
  3636. pixel_size = crtc->fb->bits_per_pixel / 8;
  3637. line_time_us = (htotal * 1000) / clock;
  3638. line_count = (latency_ns / line_time_us + 1000) / 1000;
  3639. line_size = hdisplay * pixel_size;
  3640. /* Use the minimum of the small and large buffer method for primary */
  3641. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  3642. large = line_count * line_size;
  3643. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  3644. *display_wm = entries + display->guard_size;
  3645. /*
  3646. * Spec says:
  3647. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  3648. */
  3649. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  3650. /* calculate the self-refresh watermark for display cursor */
  3651. entries = line_count * pixel_size * 64;
  3652. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3653. *cursor_wm = entries + cursor->guard_size;
  3654. return ironlake_check_srwm(dev, level,
  3655. *fbc_wm, *display_wm, *cursor_wm,
  3656. display, cursor);
  3657. }
  3658. static void ironlake_update_wm(struct drm_device *dev)
  3659. {
  3660. struct drm_i915_private *dev_priv = dev->dev_private;
  3661. int fbc_wm, plane_wm, cursor_wm;
  3662. unsigned int enabled;
  3663. enabled = 0;
  3664. if (g4x_compute_wm0(dev, 0,
  3665. &ironlake_display_wm_info,
  3666. ILK_LP0_PLANE_LATENCY,
  3667. &ironlake_cursor_wm_info,
  3668. ILK_LP0_CURSOR_LATENCY,
  3669. &plane_wm, &cursor_wm)) {
  3670. I915_WRITE(WM0_PIPEA_ILK,
  3671. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3672. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  3673. " plane %d, " "cursor: %d\n",
  3674. plane_wm, cursor_wm);
  3675. enabled |= 1;
  3676. }
  3677. if (g4x_compute_wm0(dev, 1,
  3678. &ironlake_display_wm_info,
  3679. ILK_LP0_PLANE_LATENCY,
  3680. &ironlake_cursor_wm_info,
  3681. ILK_LP0_CURSOR_LATENCY,
  3682. &plane_wm, &cursor_wm)) {
  3683. I915_WRITE(WM0_PIPEB_ILK,
  3684. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3685. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  3686. " plane %d, cursor: %d\n",
  3687. plane_wm, cursor_wm);
  3688. enabled |= 2;
  3689. }
  3690. /*
  3691. * Calculate and update the self-refresh watermark only when one
  3692. * display plane is used.
  3693. */
  3694. I915_WRITE(WM3_LP_ILK, 0);
  3695. I915_WRITE(WM2_LP_ILK, 0);
  3696. I915_WRITE(WM1_LP_ILK, 0);
  3697. if (!single_plane_enabled(enabled))
  3698. return;
  3699. enabled = ffs(enabled) - 1;
  3700. /* WM1 */
  3701. if (!ironlake_compute_srwm(dev, 1, enabled,
  3702. ILK_READ_WM1_LATENCY() * 500,
  3703. &ironlake_display_srwm_info,
  3704. &ironlake_cursor_srwm_info,
  3705. &fbc_wm, &plane_wm, &cursor_wm))
  3706. return;
  3707. I915_WRITE(WM1_LP_ILK,
  3708. WM1_LP_SR_EN |
  3709. (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3710. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3711. (plane_wm << WM1_LP_SR_SHIFT) |
  3712. cursor_wm);
  3713. /* WM2 */
  3714. if (!ironlake_compute_srwm(dev, 2, enabled,
  3715. ILK_READ_WM2_LATENCY() * 500,
  3716. &ironlake_display_srwm_info,
  3717. &ironlake_cursor_srwm_info,
  3718. &fbc_wm, &plane_wm, &cursor_wm))
  3719. return;
  3720. I915_WRITE(WM2_LP_ILK,
  3721. WM2_LP_EN |
  3722. (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3723. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3724. (plane_wm << WM1_LP_SR_SHIFT) |
  3725. cursor_wm);
  3726. /*
  3727. * WM3 is unsupported on ILK, probably because we don't have latency
  3728. * data for that power state
  3729. */
  3730. }
  3731. static void sandybridge_update_wm(struct drm_device *dev)
  3732. {
  3733. struct drm_i915_private *dev_priv = dev->dev_private;
  3734. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  3735. int fbc_wm, plane_wm, cursor_wm;
  3736. unsigned int enabled;
  3737. enabled = 0;
  3738. if (g4x_compute_wm0(dev, 0,
  3739. &sandybridge_display_wm_info, latency,
  3740. &sandybridge_cursor_wm_info, latency,
  3741. &plane_wm, &cursor_wm)) {
  3742. I915_WRITE(WM0_PIPEA_ILK,
  3743. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3744. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  3745. " plane %d, " "cursor: %d\n",
  3746. plane_wm, cursor_wm);
  3747. enabled |= 1;
  3748. }
  3749. if (g4x_compute_wm0(dev, 1,
  3750. &sandybridge_display_wm_info, latency,
  3751. &sandybridge_cursor_wm_info, latency,
  3752. &plane_wm, &cursor_wm)) {
  3753. I915_WRITE(WM0_PIPEB_ILK,
  3754. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3755. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  3756. " plane %d, cursor: %d\n",
  3757. plane_wm, cursor_wm);
  3758. enabled |= 2;
  3759. }
  3760. /*
  3761. * Calculate and update the self-refresh watermark only when one
  3762. * display plane is used.
  3763. *
  3764. * SNB support 3 levels of watermark.
  3765. *
  3766. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  3767. * and disabled in the descending order
  3768. *
  3769. */
  3770. I915_WRITE(WM3_LP_ILK, 0);
  3771. I915_WRITE(WM2_LP_ILK, 0);
  3772. I915_WRITE(WM1_LP_ILK, 0);
  3773. if (!single_plane_enabled(enabled))
  3774. return;
  3775. enabled = ffs(enabled) - 1;
  3776. /* WM1 */
  3777. if (!ironlake_compute_srwm(dev, 1, enabled,
  3778. SNB_READ_WM1_LATENCY() * 500,
  3779. &sandybridge_display_srwm_info,
  3780. &sandybridge_cursor_srwm_info,
  3781. &fbc_wm, &plane_wm, &cursor_wm))
  3782. return;
  3783. I915_WRITE(WM1_LP_ILK,
  3784. WM1_LP_SR_EN |
  3785. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3786. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3787. (plane_wm << WM1_LP_SR_SHIFT) |
  3788. cursor_wm);
  3789. /* WM2 */
  3790. if (!ironlake_compute_srwm(dev, 2, enabled,
  3791. SNB_READ_WM2_LATENCY() * 500,
  3792. &sandybridge_display_srwm_info,
  3793. &sandybridge_cursor_srwm_info,
  3794. &fbc_wm, &plane_wm, &cursor_wm))
  3795. return;
  3796. I915_WRITE(WM2_LP_ILK,
  3797. WM2_LP_EN |
  3798. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3799. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3800. (plane_wm << WM1_LP_SR_SHIFT) |
  3801. cursor_wm);
  3802. /* WM3 */
  3803. if (!ironlake_compute_srwm(dev, 3, enabled,
  3804. SNB_READ_WM3_LATENCY() * 500,
  3805. &sandybridge_display_srwm_info,
  3806. &sandybridge_cursor_srwm_info,
  3807. &fbc_wm, &plane_wm, &cursor_wm))
  3808. return;
  3809. I915_WRITE(WM3_LP_ILK,
  3810. WM3_LP_EN |
  3811. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3812. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3813. (plane_wm << WM1_LP_SR_SHIFT) |
  3814. cursor_wm);
  3815. }
  3816. /**
  3817. * intel_update_watermarks - update FIFO watermark values based on current modes
  3818. *
  3819. * Calculate watermark values for the various WM regs based on current mode
  3820. * and plane configuration.
  3821. *
  3822. * There are several cases to deal with here:
  3823. * - normal (i.e. non-self-refresh)
  3824. * - self-refresh (SR) mode
  3825. * - lines are large relative to FIFO size (buffer can hold up to 2)
  3826. * - lines are small relative to FIFO size (buffer can hold more than 2
  3827. * lines), so need to account for TLB latency
  3828. *
  3829. * The normal calculation is:
  3830. * watermark = dotclock * bytes per pixel * latency
  3831. * where latency is platform & configuration dependent (we assume pessimal
  3832. * values here).
  3833. *
  3834. * The SR calculation is:
  3835. * watermark = (trunc(latency/line time)+1) * surface width *
  3836. * bytes per pixel
  3837. * where
  3838. * line time = htotal / dotclock
  3839. * surface width = hdisplay for normal plane and 64 for cursor
  3840. * and latency is assumed to be high, as above.
  3841. *
  3842. * The final value programmed to the register should always be rounded up,
  3843. * and include an extra 2 entries to account for clock crossings.
  3844. *
  3845. * We don't use the sprite, so we can ignore that. And on Crestline we have
  3846. * to set the non-SR watermarks to 8.
  3847. */
  3848. static void intel_update_watermarks(struct drm_device *dev)
  3849. {
  3850. struct drm_i915_private *dev_priv = dev->dev_private;
  3851. if (dev_priv->display.update_wm)
  3852. dev_priv->display.update_wm(dev);
  3853. }
  3854. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3855. {
  3856. return dev_priv->lvds_use_ssc && i915_panel_use_ssc
  3857. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3858. }
  3859. /**
  3860. * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
  3861. * @crtc: CRTC structure
  3862. *
  3863. * A pipe may be connected to one or more outputs. Based on the depth of the
  3864. * attached framebuffer, choose a good color depth to use on the pipe.
  3865. *
  3866. * If possible, match the pipe depth to the fb depth. In some cases, this
  3867. * isn't ideal, because the connected output supports a lesser or restricted
  3868. * set of depths. Resolve that here:
  3869. * LVDS typically supports only 6bpc, so clamp down in that case
  3870. * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
  3871. * Displays may support a restricted set as well, check EDID and clamp as
  3872. * appropriate.
  3873. *
  3874. * RETURNS:
  3875. * Dithering requirement (i.e. false if display bpc and pipe bpc match,
  3876. * true if they don't match).
  3877. */
  3878. static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
  3879. unsigned int *pipe_bpp)
  3880. {
  3881. struct drm_device *dev = crtc->dev;
  3882. struct drm_i915_private *dev_priv = dev->dev_private;
  3883. struct drm_encoder *encoder;
  3884. struct drm_connector *connector;
  3885. unsigned int display_bpc = UINT_MAX, bpc;
  3886. /* Walk the encoders & connectors on this crtc, get min bpc */
  3887. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3888. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3889. if (encoder->crtc != crtc)
  3890. continue;
  3891. if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
  3892. unsigned int lvds_bpc;
  3893. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
  3894. LVDS_A3_POWER_UP)
  3895. lvds_bpc = 8;
  3896. else
  3897. lvds_bpc = 6;
  3898. if (lvds_bpc < display_bpc) {
  3899. DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
  3900. display_bpc = lvds_bpc;
  3901. }
  3902. continue;
  3903. }
  3904. if (intel_encoder->type == INTEL_OUTPUT_EDP) {
  3905. /* Use VBT settings if we have an eDP panel */
  3906. unsigned int edp_bpc = dev_priv->edp.bpp / 3;
  3907. if (edp_bpc < display_bpc) {
  3908. DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
  3909. display_bpc = edp_bpc;
  3910. }
  3911. continue;
  3912. }
  3913. /* Not one of the known troublemakers, check the EDID */
  3914. list_for_each_entry(connector, &dev->mode_config.connector_list,
  3915. head) {
  3916. if (connector->encoder != encoder)
  3917. continue;
  3918. if (connector->display_info.bpc < display_bpc) {
  3919. DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
  3920. display_bpc = connector->display_info.bpc;
  3921. }
  3922. }
  3923. /*
  3924. * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  3925. * through, clamp it down. (Note: >12bpc will be caught below.)
  3926. */
  3927. if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
  3928. if (display_bpc > 8 && display_bpc < 12) {
  3929. DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
  3930. display_bpc = 12;
  3931. } else {
  3932. DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
  3933. display_bpc = 8;
  3934. }
  3935. }
  3936. }
  3937. /*
  3938. * We could just drive the pipe at the highest bpc all the time and
  3939. * enable dithering as needed, but that costs bandwidth. So choose
  3940. * the minimum value that expresses the full color range of the fb but
  3941. * also stays within the max display bpc discovered above.
  3942. */
  3943. switch (crtc->fb->depth) {
  3944. case 8:
  3945. bpc = 8; /* since we go through a colormap */
  3946. break;
  3947. case 15:
  3948. case 16:
  3949. bpc = 6; /* min is 18bpp */
  3950. break;
  3951. case 24:
  3952. bpc = min((unsigned int)8, display_bpc);
  3953. break;
  3954. case 30:
  3955. bpc = min((unsigned int)10, display_bpc);
  3956. break;
  3957. case 48:
  3958. bpc = min((unsigned int)12, display_bpc);
  3959. break;
  3960. default:
  3961. DRM_DEBUG("unsupported depth, assuming 24 bits\n");
  3962. bpc = min((unsigned int)8, display_bpc);
  3963. break;
  3964. }
  3965. DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
  3966. bpc, display_bpc);
  3967. *pipe_bpp = bpc * 3;
  3968. return display_bpc != bpc;
  3969. }
  3970. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  3971. struct drm_display_mode *mode,
  3972. struct drm_display_mode *adjusted_mode,
  3973. int x, int y,
  3974. struct drm_framebuffer *old_fb)
  3975. {
  3976. struct drm_device *dev = crtc->dev;
  3977. struct drm_i915_private *dev_priv = dev->dev_private;
  3978. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3979. int pipe = intel_crtc->pipe;
  3980. int plane = intel_crtc->plane;
  3981. int refclk, num_connectors = 0;
  3982. intel_clock_t clock, reduced_clock;
  3983. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  3984. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  3985. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  3986. struct drm_mode_config *mode_config = &dev->mode_config;
  3987. struct intel_encoder *encoder;
  3988. const intel_limit_t *limit;
  3989. int ret;
  3990. u32 temp;
  3991. u32 lvds_sync = 0;
  3992. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  3993. if (encoder->base.crtc != crtc)
  3994. continue;
  3995. switch (encoder->type) {
  3996. case INTEL_OUTPUT_LVDS:
  3997. is_lvds = true;
  3998. break;
  3999. case INTEL_OUTPUT_SDVO:
  4000. case INTEL_OUTPUT_HDMI:
  4001. is_sdvo = true;
  4002. if (encoder->needs_tv_clock)
  4003. is_tv = true;
  4004. break;
  4005. case INTEL_OUTPUT_DVO:
  4006. is_dvo = true;
  4007. break;
  4008. case INTEL_OUTPUT_TVOUT:
  4009. is_tv = true;
  4010. break;
  4011. case INTEL_OUTPUT_ANALOG:
  4012. is_crt = true;
  4013. break;
  4014. case INTEL_OUTPUT_DISPLAYPORT:
  4015. is_dp = true;
  4016. break;
  4017. }
  4018. num_connectors++;
  4019. }
  4020. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4021. refclk = dev_priv->lvds_ssc_freq * 1000;
  4022. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4023. refclk / 1000);
  4024. } else if (!IS_GEN2(dev)) {
  4025. refclk = 96000;
  4026. } else {
  4027. refclk = 48000;
  4028. }
  4029. /*
  4030. * Returns a set of divisors for the desired target clock with the given
  4031. * refclk, or FALSE. The returned values represent the clock equation:
  4032. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4033. */
  4034. limit = intel_limit(crtc, refclk);
  4035. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  4036. if (!ok) {
  4037. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4038. return -EINVAL;
  4039. }
  4040. /* Ensure that the cursor is valid for the new mode before changing... */
  4041. intel_crtc_update_cursor(crtc, true);
  4042. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4043. has_reduced_clock = limit->find_pll(limit, crtc,
  4044. dev_priv->lvds_downclock,
  4045. refclk,
  4046. &reduced_clock);
  4047. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  4048. /*
  4049. * If the different P is found, it means that we can't
  4050. * switch the display clock by using the FP0/FP1.
  4051. * In such case we will disable the LVDS downclock
  4052. * feature.
  4053. */
  4054. DRM_DEBUG_KMS("Different P is found for "
  4055. "LVDS clock/downclock\n");
  4056. has_reduced_clock = 0;
  4057. }
  4058. }
  4059. /* SDVO TV has fixed PLL values depend on its clock range,
  4060. this mirrors vbios setting. */
  4061. if (is_sdvo && is_tv) {
  4062. if (adjusted_mode->clock >= 100000
  4063. && adjusted_mode->clock < 140500) {
  4064. clock.p1 = 2;
  4065. clock.p2 = 10;
  4066. clock.n = 3;
  4067. clock.m1 = 16;
  4068. clock.m2 = 8;
  4069. } else if (adjusted_mode->clock >= 140500
  4070. && adjusted_mode->clock <= 200000) {
  4071. clock.p1 = 1;
  4072. clock.p2 = 10;
  4073. clock.n = 6;
  4074. clock.m1 = 12;
  4075. clock.m2 = 8;
  4076. }
  4077. }
  4078. if (IS_PINEVIEW(dev)) {
  4079. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  4080. if (has_reduced_clock)
  4081. fp2 = (1 << reduced_clock.n) << 16 |
  4082. reduced_clock.m1 << 8 | reduced_clock.m2;
  4083. } else {
  4084. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4085. if (has_reduced_clock)
  4086. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4087. reduced_clock.m2;
  4088. }
  4089. dpll = DPLL_VGA_MODE_DIS;
  4090. if (!IS_GEN2(dev)) {
  4091. if (is_lvds)
  4092. dpll |= DPLLB_MODE_LVDS;
  4093. else
  4094. dpll |= DPLLB_MODE_DAC_SERIAL;
  4095. if (is_sdvo) {
  4096. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4097. if (pixel_multiplier > 1) {
  4098. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  4099. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  4100. }
  4101. dpll |= DPLL_DVO_HIGH_SPEED;
  4102. }
  4103. if (is_dp)
  4104. dpll |= DPLL_DVO_HIGH_SPEED;
  4105. /* compute bitmask from p1 value */
  4106. if (IS_PINEVIEW(dev))
  4107. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  4108. else {
  4109. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4110. if (IS_G4X(dev) && has_reduced_clock)
  4111. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4112. }
  4113. switch (clock.p2) {
  4114. case 5:
  4115. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4116. break;
  4117. case 7:
  4118. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4119. break;
  4120. case 10:
  4121. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4122. break;
  4123. case 14:
  4124. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4125. break;
  4126. }
  4127. if (INTEL_INFO(dev)->gen >= 4)
  4128. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  4129. } else {
  4130. if (is_lvds) {
  4131. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4132. } else {
  4133. if (clock.p1 == 2)
  4134. dpll |= PLL_P1_DIVIDE_BY_TWO;
  4135. else
  4136. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4137. if (clock.p2 == 4)
  4138. dpll |= PLL_P2_DIVIDE_BY_4;
  4139. }
  4140. }
  4141. if (is_sdvo && is_tv)
  4142. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4143. else if (is_tv)
  4144. /* XXX: just matching BIOS for now */
  4145. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4146. dpll |= 3;
  4147. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4148. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4149. else
  4150. dpll |= PLL_REF_INPUT_DREFCLK;
  4151. /* setup pipeconf */
  4152. pipeconf = I915_READ(PIPECONF(pipe));
  4153. /* Set up the display plane register */
  4154. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4155. /* Ironlake's plane is forced to pipe, bit 24 is to
  4156. enable color space conversion */
  4157. if (pipe == 0)
  4158. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4159. else
  4160. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4161. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  4162. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  4163. * core speed.
  4164. *
  4165. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  4166. * pipe == 0 check?
  4167. */
  4168. if (mode->clock >
  4169. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  4170. pipeconf |= PIPECONF_DOUBLE_WIDE;
  4171. else
  4172. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  4173. }
  4174. dpll |= DPLL_VCO_ENABLE;
  4175. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  4176. drm_mode_debug_printmodeline(mode);
  4177. I915_WRITE(FP0(pipe), fp);
  4178. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  4179. POSTING_READ(DPLL(pipe));
  4180. udelay(150);
  4181. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  4182. * This is an exception to the general rule that mode_set doesn't turn
  4183. * things on.
  4184. */
  4185. if (is_lvds) {
  4186. temp = I915_READ(LVDS);
  4187. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  4188. if (pipe == 1) {
  4189. temp |= LVDS_PIPEB_SELECT;
  4190. } else {
  4191. temp &= ~LVDS_PIPEB_SELECT;
  4192. }
  4193. /* set the corresponsding LVDS_BORDER bit */
  4194. temp |= dev_priv->lvds_border_bits;
  4195. /* Set the B0-B3 data pairs corresponding to whether we're going to
  4196. * set the DPLLs for dual-channel mode or not.
  4197. */
  4198. if (clock.p2 == 7)
  4199. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  4200. else
  4201. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4202. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4203. * appropriately here, but we need to look more thoroughly into how
  4204. * panels behave in the two modes.
  4205. */
  4206. /* set the dithering flag on LVDS as needed */
  4207. if (INTEL_INFO(dev)->gen >= 4) {
  4208. if (dev_priv->lvds_dither)
  4209. temp |= LVDS_ENABLE_DITHER;
  4210. else
  4211. temp &= ~LVDS_ENABLE_DITHER;
  4212. }
  4213. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4214. lvds_sync |= LVDS_HSYNC_POLARITY;
  4215. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4216. lvds_sync |= LVDS_VSYNC_POLARITY;
  4217. if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
  4218. != lvds_sync) {
  4219. char flags[2] = "-+";
  4220. DRM_INFO("Changing LVDS panel from "
  4221. "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
  4222. flags[!(temp & LVDS_HSYNC_POLARITY)],
  4223. flags[!(temp & LVDS_VSYNC_POLARITY)],
  4224. flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
  4225. flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
  4226. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4227. temp |= lvds_sync;
  4228. }
  4229. I915_WRITE(LVDS, temp);
  4230. }
  4231. if (is_dp) {
  4232. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4233. }
  4234. I915_WRITE(DPLL(pipe), dpll);
  4235. /* Wait for the clocks to stabilize. */
  4236. POSTING_READ(DPLL(pipe));
  4237. udelay(150);
  4238. if (INTEL_INFO(dev)->gen >= 4) {
  4239. temp = 0;
  4240. if (is_sdvo) {
  4241. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  4242. if (temp > 1)
  4243. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4244. else
  4245. temp = 0;
  4246. }
  4247. I915_WRITE(DPLL_MD(pipe), temp);
  4248. } else {
  4249. /* The pixel multiplier can only be updated once the
  4250. * DPLL is enabled and the clocks are stable.
  4251. *
  4252. * So write it again.
  4253. */
  4254. I915_WRITE(DPLL(pipe), dpll);
  4255. }
  4256. intel_crtc->lowfreq_avail = false;
  4257. if (is_lvds && has_reduced_clock && i915_powersave) {
  4258. I915_WRITE(FP1(pipe), fp2);
  4259. intel_crtc->lowfreq_avail = true;
  4260. if (HAS_PIPE_CXSR(dev)) {
  4261. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4262. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4263. }
  4264. } else {
  4265. I915_WRITE(FP1(pipe), fp);
  4266. if (HAS_PIPE_CXSR(dev)) {
  4267. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4268. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4269. }
  4270. }
  4271. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4272. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4273. /* the chip adds 2 halflines automatically */
  4274. adjusted_mode->crtc_vdisplay -= 1;
  4275. adjusted_mode->crtc_vtotal -= 1;
  4276. adjusted_mode->crtc_vblank_start -= 1;
  4277. adjusted_mode->crtc_vblank_end -= 1;
  4278. adjusted_mode->crtc_vsync_end -= 1;
  4279. adjusted_mode->crtc_vsync_start -= 1;
  4280. } else
  4281. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  4282. I915_WRITE(HTOTAL(pipe),
  4283. (adjusted_mode->crtc_hdisplay - 1) |
  4284. ((adjusted_mode->crtc_htotal - 1) << 16));
  4285. I915_WRITE(HBLANK(pipe),
  4286. (adjusted_mode->crtc_hblank_start - 1) |
  4287. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4288. I915_WRITE(HSYNC(pipe),
  4289. (adjusted_mode->crtc_hsync_start - 1) |
  4290. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4291. I915_WRITE(VTOTAL(pipe),
  4292. (adjusted_mode->crtc_vdisplay - 1) |
  4293. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4294. I915_WRITE(VBLANK(pipe),
  4295. (adjusted_mode->crtc_vblank_start - 1) |
  4296. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4297. I915_WRITE(VSYNC(pipe),
  4298. (adjusted_mode->crtc_vsync_start - 1) |
  4299. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4300. /* pipesrc and dspsize control the size that is scaled from,
  4301. * which should always be the user's requested size.
  4302. */
  4303. I915_WRITE(DSPSIZE(plane),
  4304. ((mode->vdisplay - 1) << 16) |
  4305. (mode->hdisplay - 1));
  4306. I915_WRITE(DSPPOS(plane), 0);
  4307. I915_WRITE(PIPESRC(pipe),
  4308. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4309. I915_WRITE(PIPECONF(pipe), pipeconf);
  4310. POSTING_READ(PIPECONF(pipe));
  4311. intel_enable_pipe(dev_priv, pipe, false);
  4312. intel_wait_for_vblank(dev, pipe);
  4313. I915_WRITE(DSPCNTR(plane), dspcntr);
  4314. POSTING_READ(DSPCNTR(plane));
  4315. intel_enable_plane(dev_priv, plane, pipe);
  4316. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  4317. intel_update_watermarks(dev);
  4318. return ret;
  4319. }
  4320. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4321. struct drm_display_mode *mode,
  4322. struct drm_display_mode *adjusted_mode,
  4323. int x, int y,
  4324. struct drm_framebuffer *old_fb)
  4325. {
  4326. struct drm_device *dev = crtc->dev;
  4327. struct drm_i915_private *dev_priv = dev->dev_private;
  4328. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4329. int pipe = intel_crtc->pipe;
  4330. int plane = intel_crtc->plane;
  4331. int refclk, num_connectors = 0;
  4332. intel_clock_t clock, reduced_clock;
  4333. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  4334. bool ok, has_reduced_clock = false, is_sdvo = false;
  4335. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  4336. struct intel_encoder *has_edp_encoder = NULL;
  4337. struct drm_mode_config *mode_config = &dev->mode_config;
  4338. struct intel_encoder *encoder;
  4339. const intel_limit_t *limit;
  4340. int ret;
  4341. struct fdi_m_n m_n = {0};
  4342. u32 temp;
  4343. u32 lvds_sync = 0;
  4344. int target_clock, pixel_multiplier, lane, link_bw, factor;
  4345. unsigned int pipe_bpp;
  4346. bool dither;
  4347. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4348. if (encoder->base.crtc != crtc)
  4349. continue;
  4350. switch (encoder->type) {
  4351. case INTEL_OUTPUT_LVDS:
  4352. is_lvds = true;
  4353. break;
  4354. case INTEL_OUTPUT_SDVO:
  4355. case INTEL_OUTPUT_HDMI:
  4356. is_sdvo = true;
  4357. if (encoder->needs_tv_clock)
  4358. is_tv = true;
  4359. break;
  4360. case INTEL_OUTPUT_TVOUT:
  4361. is_tv = true;
  4362. break;
  4363. case INTEL_OUTPUT_ANALOG:
  4364. is_crt = true;
  4365. break;
  4366. case INTEL_OUTPUT_DISPLAYPORT:
  4367. is_dp = true;
  4368. break;
  4369. case INTEL_OUTPUT_EDP:
  4370. has_edp_encoder = encoder;
  4371. break;
  4372. }
  4373. num_connectors++;
  4374. }
  4375. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4376. refclk = dev_priv->lvds_ssc_freq * 1000;
  4377. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4378. refclk / 1000);
  4379. } else {
  4380. refclk = 96000;
  4381. if (!has_edp_encoder ||
  4382. intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4383. refclk = 120000; /* 120Mhz refclk */
  4384. }
  4385. /*
  4386. * Returns a set of divisors for the desired target clock with the given
  4387. * refclk, or FALSE. The returned values represent the clock equation:
  4388. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4389. */
  4390. limit = intel_limit(crtc, refclk);
  4391. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  4392. if (!ok) {
  4393. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4394. return -EINVAL;
  4395. }
  4396. /* Ensure that the cursor is valid for the new mode before changing... */
  4397. intel_crtc_update_cursor(crtc, true);
  4398. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4399. has_reduced_clock = limit->find_pll(limit, crtc,
  4400. dev_priv->lvds_downclock,
  4401. refclk,
  4402. &reduced_clock);
  4403. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  4404. /*
  4405. * If the different P is found, it means that we can't
  4406. * switch the display clock by using the FP0/FP1.
  4407. * In such case we will disable the LVDS downclock
  4408. * feature.
  4409. */
  4410. DRM_DEBUG_KMS("Different P is found for "
  4411. "LVDS clock/downclock\n");
  4412. has_reduced_clock = 0;
  4413. }
  4414. }
  4415. /* SDVO TV has fixed PLL values depend on its clock range,
  4416. this mirrors vbios setting. */
  4417. if (is_sdvo && is_tv) {
  4418. if (adjusted_mode->clock >= 100000
  4419. && adjusted_mode->clock < 140500) {
  4420. clock.p1 = 2;
  4421. clock.p2 = 10;
  4422. clock.n = 3;
  4423. clock.m1 = 16;
  4424. clock.m2 = 8;
  4425. } else if (adjusted_mode->clock >= 140500
  4426. && adjusted_mode->clock <= 200000) {
  4427. clock.p1 = 1;
  4428. clock.p2 = 10;
  4429. clock.n = 6;
  4430. clock.m1 = 12;
  4431. clock.m2 = 8;
  4432. }
  4433. }
  4434. /* FDI link */
  4435. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4436. lane = 0;
  4437. /* CPU eDP doesn't require FDI link, so just set DP M/N
  4438. according to current link config */
  4439. if (has_edp_encoder &&
  4440. !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4441. target_clock = mode->clock;
  4442. intel_edp_link_config(has_edp_encoder,
  4443. &lane, &link_bw);
  4444. } else {
  4445. /* [e]DP over FDI requires target mode clock
  4446. instead of link clock */
  4447. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4448. target_clock = mode->clock;
  4449. else
  4450. target_clock = adjusted_mode->clock;
  4451. /* FDI is a binary signal running at ~2.7GHz, encoding
  4452. * each output octet as 10 bits. The actual frequency
  4453. * is stored as a divider into a 100MHz clock, and the
  4454. * mode pixel clock is stored in units of 1KHz.
  4455. * Hence the bw of each lane in terms of the mode signal
  4456. * is:
  4457. */
  4458. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4459. }
  4460. /* determine panel color depth */
  4461. temp = I915_READ(PIPECONF(pipe));
  4462. temp &= ~PIPE_BPC_MASK;
  4463. dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
  4464. switch (pipe_bpp) {
  4465. case 18:
  4466. temp |= PIPE_6BPC;
  4467. break;
  4468. case 24:
  4469. temp |= PIPE_8BPC;
  4470. break;
  4471. case 30:
  4472. temp |= PIPE_10BPC;
  4473. break;
  4474. case 36:
  4475. temp |= PIPE_12BPC;
  4476. break;
  4477. default:
  4478. WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
  4479. temp |= PIPE_8BPC;
  4480. pipe_bpp = 24;
  4481. break;
  4482. }
  4483. intel_crtc->bpp = pipe_bpp;
  4484. I915_WRITE(PIPECONF(pipe), temp);
  4485. if (!lane) {
  4486. /*
  4487. * Account for spread spectrum to avoid
  4488. * oversubscribing the link. Max center spread
  4489. * is 2.5%; use 5% for safety's sake.
  4490. */
  4491. u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
  4492. lane = bps / (link_bw * 8) + 1;
  4493. }
  4494. intel_crtc->fdi_lanes = lane;
  4495. if (pixel_multiplier > 1)
  4496. link_bw *= pixel_multiplier;
  4497. ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
  4498. &m_n);
  4499. /* Ironlake: try to setup display ref clock before DPLL
  4500. * enabling. This is only under driver's control after
  4501. * PCH B stepping, previous chipset stepping should be
  4502. * ignoring this setting.
  4503. */
  4504. temp = I915_READ(PCH_DREF_CONTROL);
  4505. /* Always enable nonspread source */
  4506. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  4507. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  4508. temp &= ~DREF_SSC_SOURCE_MASK;
  4509. temp |= DREF_SSC_SOURCE_ENABLE;
  4510. I915_WRITE(PCH_DREF_CONTROL, temp);
  4511. POSTING_READ(PCH_DREF_CONTROL);
  4512. udelay(200);
  4513. if (has_edp_encoder) {
  4514. if (intel_panel_use_ssc(dev_priv)) {
  4515. temp |= DREF_SSC1_ENABLE;
  4516. I915_WRITE(PCH_DREF_CONTROL, temp);
  4517. POSTING_READ(PCH_DREF_CONTROL);
  4518. udelay(200);
  4519. }
  4520. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4521. /* Enable CPU source on CPU attached eDP */
  4522. if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4523. if (intel_panel_use_ssc(dev_priv))
  4524. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4525. else
  4526. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4527. } else {
  4528. /* Enable SSC on PCH eDP if needed */
  4529. if (intel_panel_use_ssc(dev_priv)) {
  4530. DRM_ERROR("enabling SSC on PCH\n");
  4531. temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
  4532. }
  4533. }
  4534. I915_WRITE(PCH_DREF_CONTROL, temp);
  4535. POSTING_READ(PCH_DREF_CONTROL);
  4536. udelay(200);
  4537. }
  4538. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4539. if (has_reduced_clock)
  4540. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4541. reduced_clock.m2;
  4542. /* Enable autotuning of the PLL clock (if permissible) */
  4543. factor = 21;
  4544. if (is_lvds) {
  4545. if ((intel_panel_use_ssc(dev_priv) &&
  4546. dev_priv->lvds_ssc_freq == 100) ||
  4547. (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
  4548. factor = 25;
  4549. } else if (is_sdvo && is_tv)
  4550. factor = 20;
  4551. if (clock.m1 < factor * clock.n)
  4552. fp |= FP_CB_TUNE;
  4553. dpll = 0;
  4554. if (is_lvds)
  4555. dpll |= DPLLB_MODE_LVDS;
  4556. else
  4557. dpll |= DPLLB_MODE_DAC_SERIAL;
  4558. if (is_sdvo) {
  4559. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4560. if (pixel_multiplier > 1) {
  4561. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4562. }
  4563. dpll |= DPLL_DVO_HIGH_SPEED;
  4564. }
  4565. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4566. dpll |= DPLL_DVO_HIGH_SPEED;
  4567. /* compute bitmask from p1 value */
  4568. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4569. /* also FPA1 */
  4570. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4571. switch (clock.p2) {
  4572. case 5:
  4573. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4574. break;
  4575. case 7:
  4576. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4577. break;
  4578. case 10:
  4579. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4580. break;
  4581. case 14:
  4582. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4583. break;
  4584. }
  4585. if (is_sdvo && is_tv)
  4586. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4587. else if (is_tv)
  4588. /* XXX: just matching BIOS for now */
  4589. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4590. dpll |= 3;
  4591. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4592. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4593. else
  4594. dpll |= PLL_REF_INPUT_DREFCLK;
  4595. /* setup pipeconf */
  4596. pipeconf = I915_READ(PIPECONF(pipe));
  4597. /* Set up the display plane register */
  4598. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4599. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  4600. drm_mode_debug_printmodeline(mode);
  4601. /* PCH eDP needs FDI, but CPU eDP does not */
  4602. if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4603. I915_WRITE(PCH_FP0(pipe), fp);
  4604. I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  4605. POSTING_READ(PCH_DPLL(pipe));
  4606. udelay(150);
  4607. }
  4608. /* enable transcoder DPLL */
  4609. if (HAS_PCH_CPT(dev)) {
  4610. temp = I915_READ(PCH_DPLL_SEL);
  4611. switch (pipe) {
  4612. case 0:
  4613. temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
  4614. break;
  4615. case 1:
  4616. temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
  4617. break;
  4618. case 2:
  4619. /* FIXME: manage transcoder PLLs? */
  4620. temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
  4621. break;
  4622. default:
  4623. BUG();
  4624. }
  4625. I915_WRITE(PCH_DPLL_SEL, temp);
  4626. POSTING_READ(PCH_DPLL_SEL);
  4627. udelay(150);
  4628. }
  4629. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  4630. * This is an exception to the general rule that mode_set doesn't turn
  4631. * things on.
  4632. */
  4633. if (is_lvds) {
  4634. temp = I915_READ(PCH_LVDS);
  4635. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  4636. if (pipe == 1) {
  4637. if (HAS_PCH_CPT(dev))
  4638. temp |= PORT_TRANS_B_SEL_CPT;
  4639. else
  4640. temp |= LVDS_PIPEB_SELECT;
  4641. } else {
  4642. if (HAS_PCH_CPT(dev))
  4643. temp &= ~PORT_TRANS_SEL_MASK;
  4644. else
  4645. temp &= ~LVDS_PIPEB_SELECT;
  4646. }
  4647. /* set the corresponsding LVDS_BORDER bit */
  4648. temp |= dev_priv->lvds_border_bits;
  4649. /* Set the B0-B3 data pairs corresponding to whether we're going to
  4650. * set the DPLLs for dual-channel mode or not.
  4651. */
  4652. if (clock.p2 == 7)
  4653. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  4654. else
  4655. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4656. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4657. * appropriately here, but we need to look more thoroughly into how
  4658. * panels behave in the two modes.
  4659. */
  4660. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4661. lvds_sync |= LVDS_HSYNC_POLARITY;
  4662. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4663. lvds_sync |= LVDS_VSYNC_POLARITY;
  4664. if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
  4665. != lvds_sync) {
  4666. char flags[2] = "-+";
  4667. DRM_INFO("Changing LVDS panel from "
  4668. "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
  4669. flags[!(temp & LVDS_HSYNC_POLARITY)],
  4670. flags[!(temp & LVDS_VSYNC_POLARITY)],
  4671. flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
  4672. flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
  4673. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4674. temp |= lvds_sync;
  4675. }
  4676. I915_WRITE(PCH_LVDS, temp);
  4677. }
  4678. pipeconf &= ~PIPECONF_DITHER_EN;
  4679. pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
  4680. if ((is_lvds && dev_priv->lvds_dither) || dither) {
  4681. pipeconf |= PIPECONF_DITHER_EN;
  4682. pipeconf |= PIPECONF_DITHER_TYPE_ST1;
  4683. }
  4684. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4685. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4686. } else {
  4687. /* For non-DP output, clear any trans DP clock recovery setting.*/
  4688. I915_WRITE(TRANSDATA_M1(pipe), 0);
  4689. I915_WRITE(TRANSDATA_N1(pipe), 0);
  4690. I915_WRITE(TRANSDPLINK_M1(pipe), 0);
  4691. I915_WRITE(TRANSDPLINK_N1(pipe), 0);
  4692. }
  4693. if (!has_edp_encoder ||
  4694. intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4695. I915_WRITE(PCH_DPLL(pipe), dpll);
  4696. /* Wait for the clocks to stabilize. */
  4697. POSTING_READ(PCH_DPLL(pipe));
  4698. udelay(150);
  4699. /* The pixel multiplier can only be updated once the
  4700. * DPLL is enabled and the clocks are stable.
  4701. *
  4702. * So write it again.
  4703. */
  4704. I915_WRITE(PCH_DPLL(pipe), dpll);
  4705. }
  4706. intel_crtc->lowfreq_avail = false;
  4707. if (is_lvds && has_reduced_clock && i915_powersave) {
  4708. I915_WRITE(PCH_FP1(pipe), fp2);
  4709. intel_crtc->lowfreq_avail = true;
  4710. if (HAS_PIPE_CXSR(dev)) {
  4711. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4712. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4713. }
  4714. } else {
  4715. I915_WRITE(PCH_FP1(pipe), fp);
  4716. if (HAS_PIPE_CXSR(dev)) {
  4717. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4718. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4719. }
  4720. }
  4721. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4722. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4723. /* the chip adds 2 halflines automatically */
  4724. adjusted_mode->crtc_vdisplay -= 1;
  4725. adjusted_mode->crtc_vtotal -= 1;
  4726. adjusted_mode->crtc_vblank_start -= 1;
  4727. adjusted_mode->crtc_vblank_end -= 1;
  4728. adjusted_mode->crtc_vsync_end -= 1;
  4729. adjusted_mode->crtc_vsync_start -= 1;
  4730. } else
  4731. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  4732. I915_WRITE(HTOTAL(pipe),
  4733. (adjusted_mode->crtc_hdisplay - 1) |
  4734. ((adjusted_mode->crtc_htotal - 1) << 16));
  4735. I915_WRITE(HBLANK(pipe),
  4736. (adjusted_mode->crtc_hblank_start - 1) |
  4737. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4738. I915_WRITE(HSYNC(pipe),
  4739. (adjusted_mode->crtc_hsync_start - 1) |
  4740. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4741. I915_WRITE(VTOTAL(pipe),
  4742. (adjusted_mode->crtc_vdisplay - 1) |
  4743. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4744. I915_WRITE(VBLANK(pipe),
  4745. (adjusted_mode->crtc_vblank_start - 1) |
  4746. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4747. I915_WRITE(VSYNC(pipe),
  4748. (adjusted_mode->crtc_vsync_start - 1) |
  4749. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4750. /* pipesrc controls the size that is scaled from, which should
  4751. * always be the user's requested size.
  4752. */
  4753. I915_WRITE(PIPESRC(pipe),
  4754. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4755. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  4756. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  4757. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  4758. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  4759. if (has_edp_encoder &&
  4760. !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4761. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  4762. }
  4763. I915_WRITE(PIPECONF(pipe), pipeconf);
  4764. POSTING_READ(PIPECONF(pipe));
  4765. intel_wait_for_vblank(dev, pipe);
  4766. if (IS_GEN5(dev)) {
  4767. /* enable address swizzle for tiling buffer */
  4768. temp = I915_READ(DISP_ARB_CTL);
  4769. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  4770. }
  4771. I915_WRITE(DSPCNTR(plane), dspcntr);
  4772. POSTING_READ(DSPCNTR(plane));
  4773. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  4774. intel_update_watermarks(dev);
  4775. return ret;
  4776. }
  4777. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  4778. struct drm_display_mode *mode,
  4779. struct drm_display_mode *adjusted_mode,
  4780. int x, int y,
  4781. struct drm_framebuffer *old_fb)
  4782. {
  4783. struct drm_device *dev = crtc->dev;
  4784. struct drm_i915_private *dev_priv = dev->dev_private;
  4785. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4786. int pipe = intel_crtc->pipe;
  4787. int ret;
  4788. drm_vblank_pre_modeset(dev, pipe);
  4789. ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  4790. x, y, old_fb);
  4791. drm_vblank_post_modeset(dev, pipe);
  4792. return ret;
  4793. }
  4794. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  4795. void intel_crtc_load_lut(struct drm_crtc *crtc)
  4796. {
  4797. struct drm_device *dev = crtc->dev;
  4798. struct drm_i915_private *dev_priv = dev->dev_private;
  4799. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4800. int palreg = PALETTE(intel_crtc->pipe);
  4801. int i;
  4802. /* The clocks have to be on to load the palette. */
  4803. if (!crtc->enabled)
  4804. return;
  4805. /* use legacy palette for Ironlake */
  4806. if (HAS_PCH_SPLIT(dev))
  4807. palreg = LGC_PALETTE(intel_crtc->pipe);
  4808. for (i = 0; i < 256; i++) {
  4809. I915_WRITE(palreg + 4 * i,
  4810. (intel_crtc->lut_r[i] << 16) |
  4811. (intel_crtc->lut_g[i] << 8) |
  4812. intel_crtc->lut_b[i]);
  4813. }
  4814. }
  4815. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  4816. {
  4817. struct drm_device *dev = crtc->dev;
  4818. struct drm_i915_private *dev_priv = dev->dev_private;
  4819. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4820. bool visible = base != 0;
  4821. u32 cntl;
  4822. if (intel_crtc->cursor_visible == visible)
  4823. return;
  4824. cntl = I915_READ(_CURACNTR);
  4825. if (visible) {
  4826. /* On these chipsets we can only modify the base whilst
  4827. * the cursor is disabled.
  4828. */
  4829. I915_WRITE(_CURABASE, base);
  4830. cntl &= ~(CURSOR_FORMAT_MASK);
  4831. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  4832. cntl |= CURSOR_ENABLE |
  4833. CURSOR_GAMMA_ENABLE |
  4834. CURSOR_FORMAT_ARGB;
  4835. } else
  4836. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  4837. I915_WRITE(_CURACNTR, cntl);
  4838. intel_crtc->cursor_visible = visible;
  4839. }
  4840. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  4841. {
  4842. struct drm_device *dev = crtc->dev;
  4843. struct drm_i915_private *dev_priv = dev->dev_private;
  4844. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4845. int pipe = intel_crtc->pipe;
  4846. bool visible = base != 0;
  4847. if (intel_crtc->cursor_visible != visible) {
  4848. uint32_t cntl = I915_READ(CURCNTR(pipe));
  4849. if (base) {
  4850. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  4851. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  4852. cntl |= pipe << 28; /* Connect to correct pipe */
  4853. } else {
  4854. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  4855. cntl |= CURSOR_MODE_DISABLE;
  4856. }
  4857. I915_WRITE(CURCNTR(pipe), cntl);
  4858. intel_crtc->cursor_visible = visible;
  4859. }
  4860. /* and commit changes on next vblank */
  4861. I915_WRITE(CURBASE(pipe), base);
  4862. }
  4863. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  4864. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  4865. bool on)
  4866. {
  4867. struct drm_device *dev = crtc->dev;
  4868. struct drm_i915_private *dev_priv = dev->dev_private;
  4869. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4870. int pipe = intel_crtc->pipe;
  4871. int x = intel_crtc->cursor_x;
  4872. int y = intel_crtc->cursor_y;
  4873. u32 base, pos;
  4874. bool visible;
  4875. pos = 0;
  4876. if (on && crtc->enabled && crtc->fb) {
  4877. base = intel_crtc->cursor_addr;
  4878. if (x > (int) crtc->fb->width)
  4879. base = 0;
  4880. if (y > (int) crtc->fb->height)
  4881. base = 0;
  4882. } else
  4883. base = 0;
  4884. if (x < 0) {
  4885. if (x + intel_crtc->cursor_width < 0)
  4886. base = 0;
  4887. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  4888. x = -x;
  4889. }
  4890. pos |= x << CURSOR_X_SHIFT;
  4891. if (y < 0) {
  4892. if (y + intel_crtc->cursor_height < 0)
  4893. base = 0;
  4894. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  4895. y = -y;
  4896. }
  4897. pos |= y << CURSOR_Y_SHIFT;
  4898. visible = base != 0;
  4899. if (!visible && !intel_crtc->cursor_visible)
  4900. return;
  4901. I915_WRITE(CURPOS(pipe), pos);
  4902. if (IS_845G(dev) || IS_I865G(dev))
  4903. i845_update_cursor(crtc, base);
  4904. else
  4905. i9xx_update_cursor(crtc, base);
  4906. if (visible)
  4907. intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
  4908. }
  4909. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  4910. struct drm_file *file,
  4911. uint32_t handle,
  4912. uint32_t width, uint32_t height)
  4913. {
  4914. struct drm_device *dev = crtc->dev;
  4915. struct drm_i915_private *dev_priv = dev->dev_private;
  4916. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4917. struct drm_i915_gem_object *obj;
  4918. uint32_t addr;
  4919. int ret;
  4920. DRM_DEBUG_KMS("\n");
  4921. /* if we want to turn off the cursor ignore width and height */
  4922. if (!handle) {
  4923. DRM_DEBUG_KMS("cursor off\n");
  4924. addr = 0;
  4925. obj = NULL;
  4926. mutex_lock(&dev->struct_mutex);
  4927. goto finish;
  4928. }
  4929. /* Currently we only support 64x64 cursors */
  4930. if (width != 64 || height != 64) {
  4931. DRM_ERROR("we currently only support 64x64 cursors\n");
  4932. return -EINVAL;
  4933. }
  4934. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  4935. if (&obj->base == NULL)
  4936. return -ENOENT;
  4937. if (obj->base.size < width * height * 4) {
  4938. DRM_ERROR("buffer is to small\n");
  4939. ret = -ENOMEM;
  4940. goto fail;
  4941. }
  4942. /* we only need to pin inside GTT if cursor is non-phy */
  4943. mutex_lock(&dev->struct_mutex);
  4944. if (!dev_priv->info->cursor_needs_physical) {
  4945. if (obj->tiling_mode) {
  4946. DRM_ERROR("cursor cannot be tiled\n");
  4947. ret = -EINVAL;
  4948. goto fail_locked;
  4949. }
  4950. ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
  4951. if (ret) {
  4952. DRM_ERROR("failed to move cursor bo into the GTT\n");
  4953. goto fail_locked;
  4954. }
  4955. ret = i915_gem_object_put_fence(obj);
  4956. if (ret) {
  4957. DRM_ERROR("failed to release fence for cursor");
  4958. goto fail_unpin;
  4959. }
  4960. addr = obj->gtt_offset;
  4961. } else {
  4962. int align = IS_I830(dev) ? 16 * 1024 : 256;
  4963. ret = i915_gem_attach_phys_object(dev, obj,
  4964. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  4965. align);
  4966. if (ret) {
  4967. DRM_ERROR("failed to attach phys object\n");
  4968. goto fail_locked;
  4969. }
  4970. addr = obj->phys_obj->handle->busaddr;
  4971. }
  4972. if (IS_GEN2(dev))
  4973. I915_WRITE(CURSIZE, (height << 12) | width);
  4974. finish:
  4975. if (intel_crtc->cursor_bo) {
  4976. if (dev_priv->info->cursor_needs_physical) {
  4977. if (intel_crtc->cursor_bo != obj)
  4978. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  4979. } else
  4980. i915_gem_object_unpin(intel_crtc->cursor_bo);
  4981. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  4982. }
  4983. mutex_unlock(&dev->struct_mutex);
  4984. intel_crtc->cursor_addr = addr;
  4985. intel_crtc->cursor_bo = obj;
  4986. intel_crtc->cursor_width = width;
  4987. intel_crtc->cursor_height = height;
  4988. intel_crtc_update_cursor(crtc, true);
  4989. return 0;
  4990. fail_unpin:
  4991. i915_gem_object_unpin(obj);
  4992. fail_locked:
  4993. mutex_unlock(&dev->struct_mutex);
  4994. fail:
  4995. drm_gem_object_unreference_unlocked(&obj->base);
  4996. return ret;
  4997. }
  4998. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  4999. {
  5000. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5001. intel_crtc->cursor_x = x;
  5002. intel_crtc->cursor_y = y;
  5003. intel_crtc_update_cursor(crtc, true);
  5004. return 0;
  5005. }
  5006. /** Sets the color ramps on behalf of RandR */
  5007. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  5008. u16 blue, int regno)
  5009. {
  5010. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5011. intel_crtc->lut_r[regno] = red >> 8;
  5012. intel_crtc->lut_g[regno] = green >> 8;
  5013. intel_crtc->lut_b[regno] = blue >> 8;
  5014. }
  5015. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  5016. u16 *blue, int regno)
  5017. {
  5018. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5019. *red = intel_crtc->lut_r[regno] << 8;
  5020. *green = intel_crtc->lut_g[regno] << 8;
  5021. *blue = intel_crtc->lut_b[regno] << 8;
  5022. }
  5023. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5024. u16 *blue, uint32_t start, uint32_t size)
  5025. {
  5026. int end = (start + size > 256) ? 256 : start + size, i;
  5027. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5028. for (i = start; i < end; i++) {
  5029. intel_crtc->lut_r[i] = red[i] >> 8;
  5030. intel_crtc->lut_g[i] = green[i] >> 8;
  5031. intel_crtc->lut_b[i] = blue[i] >> 8;
  5032. }
  5033. intel_crtc_load_lut(crtc);
  5034. }
  5035. /**
  5036. * Get a pipe with a simple mode set on it for doing load-based monitor
  5037. * detection.
  5038. *
  5039. * It will be up to the load-detect code to adjust the pipe as appropriate for
  5040. * its requirements. The pipe will be connected to no other encoders.
  5041. *
  5042. * Currently this code will only succeed if there is a pipe with no encoders
  5043. * configured for it. In the future, it could choose to temporarily disable
  5044. * some outputs to free up a pipe for its use.
  5045. *
  5046. * \return crtc, or NULL if no pipes are available.
  5047. */
  5048. /* VESA 640x480x72Hz mode to set on the pipe */
  5049. static struct drm_display_mode load_detect_mode = {
  5050. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5051. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5052. };
  5053. static struct drm_framebuffer *
  5054. intel_framebuffer_create(struct drm_device *dev,
  5055. struct drm_mode_fb_cmd *mode_cmd,
  5056. struct drm_i915_gem_object *obj)
  5057. {
  5058. struct intel_framebuffer *intel_fb;
  5059. int ret;
  5060. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  5061. if (!intel_fb) {
  5062. drm_gem_object_unreference_unlocked(&obj->base);
  5063. return ERR_PTR(-ENOMEM);
  5064. }
  5065. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  5066. if (ret) {
  5067. drm_gem_object_unreference_unlocked(&obj->base);
  5068. kfree(intel_fb);
  5069. return ERR_PTR(ret);
  5070. }
  5071. return &intel_fb->base;
  5072. }
  5073. static u32
  5074. intel_framebuffer_pitch_for_width(int width, int bpp)
  5075. {
  5076. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  5077. return ALIGN(pitch, 64);
  5078. }
  5079. static u32
  5080. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  5081. {
  5082. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  5083. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  5084. }
  5085. static struct drm_framebuffer *
  5086. intel_framebuffer_create_for_mode(struct drm_device *dev,
  5087. struct drm_display_mode *mode,
  5088. int depth, int bpp)
  5089. {
  5090. struct drm_i915_gem_object *obj;
  5091. struct drm_mode_fb_cmd mode_cmd;
  5092. obj = i915_gem_alloc_object(dev,
  5093. intel_framebuffer_size_for_mode(mode, bpp));
  5094. if (obj == NULL)
  5095. return ERR_PTR(-ENOMEM);
  5096. mode_cmd.width = mode->hdisplay;
  5097. mode_cmd.height = mode->vdisplay;
  5098. mode_cmd.depth = depth;
  5099. mode_cmd.bpp = bpp;
  5100. mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
  5101. return intel_framebuffer_create(dev, &mode_cmd, obj);
  5102. }
  5103. static struct drm_framebuffer *
  5104. mode_fits_in_fbdev(struct drm_device *dev,
  5105. struct drm_display_mode *mode)
  5106. {
  5107. struct drm_i915_private *dev_priv = dev->dev_private;
  5108. struct drm_i915_gem_object *obj;
  5109. struct drm_framebuffer *fb;
  5110. if (dev_priv->fbdev == NULL)
  5111. return NULL;
  5112. obj = dev_priv->fbdev->ifb.obj;
  5113. if (obj == NULL)
  5114. return NULL;
  5115. fb = &dev_priv->fbdev->ifb.base;
  5116. if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
  5117. fb->bits_per_pixel))
  5118. return NULL;
  5119. if (obj->base.size < mode->vdisplay * fb->pitch)
  5120. return NULL;
  5121. return fb;
  5122. }
  5123. bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  5124. struct drm_connector *connector,
  5125. struct drm_display_mode *mode,
  5126. struct intel_load_detect_pipe *old)
  5127. {
  5128. struct intel_crtc *intel_crtc;
  5129. struct drm_crtc *possible_crtc;
  5130. struct drm_encoder *encoder = &intel_encoder->base;
  5131. struct drm_crtc *crtc = NULL;
  5132. struct drm_device *dev = encoder->dev;
  5133. struct drm_framebuffer *old_fb;
  5134. int i = -1;
  5135. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5136. connector->base.id, drm_get_connector_name(connector),
  5137. encoder->base.id, drm_get_encoder_name(encoder));
  5138. /*
  5139. * Algorithm gets a little messy:
  5140. *
  5141. * - if the connector already has an assigned crtc, use it (but make
  5142. * sure it's on first)
  5143. *
  5144. * - try to find the first unused crtc that can drive this connector,
  5145. * and use that if we find one
  5146. */
  5147. /* See if we already have a CRTC for this connector */
  5148. if (encoder->crtc) {
  5149. crtc = encoder->crtc;
  5150. intel_crtc = to_intel_crtc(crtc);
  5151. old->dpms_mode = intel_crtc->dpms_mode;
  5152. old->load_detect_temp = false;
  5153. /* Make sure the crtc and connector are running */
  5154. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  5155. struct drm_encoder_helper_funcs *encoder_funcs;
  5156. struct drm_crtc_helper_funcs *crtc_funcs;
  5157. crtc_funcs = crtc->helper_private;
  5158. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  5159. encoder_funcs = encoder->helper_private;
  5160. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  5161. }
  5162. return true;
  5163. }
  5164. /* Find an unused one (if possible) */
  5165. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  5166. i++;
  5167. if (!(encoder->possible_crtcs & (1 << i)))
  5168. continue;
  5169. if (!possible_crtc->enabled) {
  5170. crtc = possible_crtc;
  5171. break;
  5172. }
  5173. }
  5174. /*
  5175. * If we didn't find an unused CRTC, don't use any.
  5176. */
  5177. if (!crtc) {
  5178. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  5179. return false;
  5180. }
  5181. encoder->crtc = crtc;
  5182. connector->encoder = encoder;
  5183. intel_crtc = to_intel_crtc(crtc);
  5184. old->dpms_mode = intel_crtc->dpms_mode;
  5185. old->load_detect_temp = true;
  5186. old->release_fb = NULL;
  5187. if (!mode)
  5188. mode = &load_detect_mode;
  5189. old_fb = crtc->fb;
  5190. /* We need a framebuffer large enough to accommodate all accesses
  5191. * that the plane may generate whilst we perform load detection.
  5192. * We can not rely on the fbcon either being present (we get called
  5193. * during its initialisation to detect all boot displays, or it may
  5194. * not even exist) or that it is large enough to satisfy the
  5195. * requested mode.
  5196. */
  5197. crtc->fb = mode_fits_in_fbdev(dev, mode);
  5198. if (crtc->fb == NULL) {
  5199. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5200. crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5201. old->release_fb = crtc->fb;
  5202. } else
  5203. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5204. if (IS_ERR(crtc->fb)) {
  5205. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5206. crtc->fb = old_fb;
  5207. return false;
  5208. }
  5209. if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
  5210. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5211. if (old->release_fb)
  5212. old->release_fb->funcs->destroy(old->release_fb);
  5213. crtc->fb = old_fb;
  5214. return false;
  5215. }
  5216. /* let the connector get through one full cycle before testing */
  5217. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5218. return true;
  5219. }
  5220. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  5221. struct drm_connector *connector,
  5222. struct intel_load_detect_pipe *old)
  5223. {
  5224. struct drm_encoder *encoder = &intel_encoder->base;
  5225. struct drm_device *dev = encoder->dev;
  5226. struct drm_crtc *crtc = encoder->crtc;
  5227. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  5228. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  5229. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5230. connector->base.id, drm_get_connector_name(connector),
  5231. encoder->base.id, drm_get_encoder_name(encoder));
  5232. if (old->load_detect_temp) {
  5233. connector->encoder = NULL;
  5234. drm_helper_disable_unused_functions(dev);
  5235. if (old->release_fb)
  5236. old->release_fb->funcs->destroy(old->release_fb);
  5237. return;
  5238. }
  5239. /* Switch crtc and encoder back off if necessary */
  5240. if (old->dpms_mode != DRM_MODE_DPMS_ON) {
  5241. encoder_funcs->dpms(encoder, old->dpms_mode);
  5242. crtc_funcs->dpms(crtc, old->dpms_mode);
  5243. }
  5244. }
  5245. /* Returns the clock of the currently programmed mode of the given pipe. */
  5246. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  5247. {
  5248. struct drm_i915_private *dev_priv = dev->dev_private;
  5249. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5250. int pipe = intel_crtc->pipe;
  5251. u32 dpll = I915_READ(DPLL(pipe));
  5252. u32 fp;
  5253. intel_clock_t clock;
  5254. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5255. fp = I915_READ(FP0(pipe));
  5256. else
  5257. fp = I915_READ(FP1(pipe));
  5258. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5259. if (IS_PINEVIEW(dev)) {
  5260. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5261. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5262. } else {
  5263. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5264. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5265. }
  5266. if (!IS_GEN2(dev)) {
  5267. if (IS_PINEVIEW(dev))
  5268. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5269. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5270. else
  5271. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5272. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5273. switch (dpll & DPLL_MODE_MASK) {
  5274. case DPLLB_MODE_DAC_SERIAL:
  5275. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5276. 5 : 10;
  5277. break;
  5278. case DPLLB_MODE_LVDS:
  5279. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5280. 7 : 14;
  5281. break;
  5282. default:
  5283. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5284. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5285. return 0;
  5286. }
  5287. /* XXX: Handle the 100Mhz refclk */
  5288. intel_clock(dev, 96000, &clock);
  5289. } else {
  5290. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5291. if (is_lvds) {
  5292. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5293. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5294. clock.p2 = 14;
  5295. if ((dpll & PLL_REF_INPUT_MASK) ==
  5296. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5297. /* XXX: might not be 66MHz */
  5298. intel_clock(dev, 66000, &clock);
  5299. } else
  5300. intel_clock(dev, 48000, &clock);
  5301. } else {
  5302. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5303. clock.p1 = 2;
  5304. else {
  5305. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5306. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5307. }
  5308. if (dpll & PLL_P2_DIVIDE_BY_4)
  5309. clock.p2 = 4;
  5310. else
  5311. clock.p2 = 2;
  5312. intel_clock(dev, 48000, &clock);
  5313. }
  5314. }
  5315. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5316. * i830PllIsValid() because it relies on the xf86_config connector
  5317. * configuration being accurate, which it isn't necessarily.
  5318. */
  5319. return clock.dot;
  5320. }
  5321. /** Returns the currently programmed mode of the given pipe. */
  5322. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5323. struct drm_crtc *crtc)
  5324. {
  5325. struct drm_i915_private *dev_priv = dev->dev_private;
  5326. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5327. int pipe = intel_crtc->pipe;
  5328. struct drm_display_mode *mode;
  5329. int htot = I915_READ(HTOTAL(pipe));
  5330. int hsync = I915_READ(HSYNC(pipe));
  5331. int vtot = I915_READ(VTOTAL(pipe));
  5332. int vsync = I915_READ(VSYNC(pipe));
  5333. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5334. if (!mode)
  5335. return NULL;
  5336. mode->clock = intel_crtc_clock_get(dev, crtc);
  5337. mode->hdisplay = (htot & 0xffff) + 1;
  5338. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5339. mode->hsync_start = (hsync & 0xffff) + 1;
  5340. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5341. mode->vdisplay = (vtot & 0xffff) + 1;
  5342. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5343. mode->vsync_start = (vsync & 0xffff) + 1;
  5344. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5345. drm_mode_set_name(mode);
  5346. drm_mode_set_crtcinfo(mode, 0);
  5347. return mode;
  5348. }
  5349. #define GPU_IDLE_TIMEOUT 500 /* ms */
  5350. /* When this timer fires, we've been idle for awhile */
  5351. static void intel_gpu_idle_timer(unsigned long arg)
  5352. {
  5353. struct drm_device *dev = (struct drm_device *)arg;
  5354. drm_i915_private_t *dev_priv = dev->dev_private;
  5355. if (!list_empty(&dev_priv->mm.active_list)) {
  5356. /* Still processing requests, so just re-arm the timer. */
  5357. mod_timer(&dev_priv->idle_timer, jiffies +
  5358. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  5359. return;
  5360. }
  5361. dev_priv->busy = false;
  5362. queue_work(dev_priv->wq, &dev_priv->idle_work);
  5363. }
  5364. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  5365. static void intel_crtc_idle_timer(unsigned long arg)
  5366. {
  5367. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  5368. struct drm_crtc *crtc = &intel_crtc->base;
  5369. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  5370. struct intel_framebuffer *intel_fb;
  5371. intel_fb = to_intel_framebuffer(crtc->fb);
  5372. if (intel_fb && intel_fb->obj->active) {
  5373. /* The framebuffer is still being accessed by the GPU. */
  5374. mod_timer(&intel_crtc->idle_timer, jiffies +
  5375. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  5376. return;
  5377. }
  5378. intel_crtc->busy = false;
  5379. queue_work(dev_priv->wq, &dev_priv->idle_work);
  5380. }
  5381. static void intel_increase_pllclock(struct drm_crtc *crtc)
  5382. {
  5383. struct drm_device *dev = crtc->dev;
  5384. drm_i915_private_t *dev_priv = dev->dev_private;
  5385. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5386. int pipe = intel_crtc->pipe;
  5387. int dpll_reg = DPLL(pipe);
  5388. int dpll;
  5389. if (HAS_PCH_SPLIT(dev))
  5390. return;
  5391. if (!dev_priv->lvds_downclock_avail)
  5392. return;
  5393. dpll = I915_READ(dpll_reg);
  5394. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  5395. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  5396. /* Unlock panel regs */
  5397. I915_WRITE(PP_CONTROL,
  5398. I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
  5399. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  5400. I915_WRITE(dpll_reg, dpll);
  5401. intel_wait_for_vblank(dev, pipe);
  5402. dpll = I915_READ(dpll_reg);
  5403. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  5404. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  5405. /* ...and lock them again */
  5406. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  5407. }
  5408. /* Schedule downclock */
  5409. mod_timer(&intel_crtc->idle_timer, jiffies +
  5410. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  5411. }
  5412. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  5413. {
  5414. struct drm_device *dev = crtc->dev;
  5415. drm_i915_private_t *dev_priv = dev->dev_private;
  5416. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5417. int pipe = intel_crtc->pipe;
  5418. int dpll_reg = DPLL(pipe);
  5419. int dpll = I915_READ(dpll_reg);
  5420. if (HAS_PCH_SPLIT(dev))
  5421. return;
  5422. if (!dev_priv->lvds_downclock_avail)
  5423. return;
  5424. /*
  5425. * Since this is called by a timer, we should never get here in
  5426. * the manual case.
  5427. */
  5428. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  5429. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  5430. /* Unlock panel regs */
  5431. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  5432. PANEL_UNLOCK_REGS);
  5433. dpll |= DISPLAY_RATE_SELECT_FPA1;
  5434. I915_WRITE(dpll_reg, dpll);
  5435. intel_wait_for_vblank(dev, pipe);
  5436. dpll = I915_READ(dpll_reg);
  5437. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  5438. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  5439. /* ...and lock them again */
  5440. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  5441. }
  5442. }
  5443. /**
  5444. * intel_idle_update - adjust clocks for idleness
  5445. * @work: work struct
  5446. *
  5447. * Either the GPU or display (or both) went idle. Check the busy status
  5448. * here and adjust the CRTC and GPU clocks as necessary.
  5449. */
  5450. static void intel_idle_update(struct work_struct *work)
  5451. {
  5452. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  5453. idle_work);
  5454. struct drm_device *dev = dev_priv->dev;
  5455. struct drm_crtc *crtc;
  5456. struct intel_crtc *intel_crtc;
  5457. if (!i915_powersave)
  5458. return;
  5459. mutex_lock(&dev->struct_mutex);
  5460. i915_update_gfx_val(dev_priv);
  5461. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5462. /* Skip inactive CRTCs */
  5463. if (!crtc->fb)
  5464. continue;
  5465. intel_crtc = to_intel_crtc(crtc);
  5466. if (!intel_crtc->busy)
  5467. intel_decrease_pllclock(crtc);
  5468. }
  5469. mutex_unlock(&dev->struct_mutex);
  5470. }
  5471. /**
  5472. * intel_mark_busy - mark the GPU and possibly the display busy
  5473. * @dev: drm device
  5474. * @obj: object we're operating on
  5475. *
  5476. * Callers can use this function to indicate that the GPU is busy processing
  5477. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  5478. * buffer), we'll also mark the display as busy, so we know to increase its
  5479. * clock frequency.
  5480. */
  5481. void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
  5482. {
  5483. drm_i915_private_t *dev_priv = dev->dev_private;
  5484. struct drm_crtc *crtc = NULL;
  5485. struct intel_framebuffer *intel_fb;
  5486. struct intel_crtc *intel_crtc;
  5487. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  5488. return;
  5489. if (!dev_priv->busy)
  5490. dev_priv->busy = true;
  5491. else
  5492. mod_timer(&dev_priv->idle_timer, jiffies +
  5493. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  5494. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5495. if (!crtc->fb)
  5496. continue;
  5497. intel_crtc = to_intel_crtc(crtc);
  5498. intel_fb = to_intel_framebuffer(crtc->fb);
  5499. if (intel_fb->obj == obj) {
  5500. if (!intel_crtc->busy) {
  5501. /* Non-busy -> busy, upclock */
  5502. intel_increase_pllclock(crtc);
  5503. intel_crtc->busy = true;
  5504. } else {
  5505. /* Busy -> busy, put off timer */
  5506. mod_timer(&intel_crtc->idle_timer, jiffies +
  5507. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  5508. }
  5509. }
  5510. }
  5511. }
  5512. static void intel_crtc_destroy(struct drm_crtc *crtc)
  5513. {
  5514. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5515. struct drm_device *dev = crtc->dev;
  5516. struct intel_unpin_work *work;
  5517. unsigned long flags;
  5518. spin_lock_irqsave(&dev->event_lock, flags);
  5519. work = intel_crtc->unpin_work;
  5520. intel_crtc->unpin_work = NULL;
  5521. spin_unlock_irqrestore(&dev->event_lock, flags);
  5522. if (work) {
  5523. cancel_work_sync(&work->work);
  5524. kfree(work);
  5525. }
  5526. drm_crtc_cleanup(crtc);
  5527. kfree(intel_crtc);
  5528. }
  5529. static void intel_unpin_work_fn(struct work_struct *__work)
  5530. {
  5531. struct intel_unpin_work *work =
  5532. container_of(__work, struct intel_unpin_work, work);
  5533. mutex_lock(&work->dev->struct_mutex);
  5534. i915_gem_object_unpin(work->old_fb_obj);
  5535. drm_gem_object_unreference(&work->pending_flip_obj->base);
  5536. drm_gem_object_unreference(&work->old_fb_obj->base);
  5537. intel_update_fbc(work->dev);
  5538. mutex_unlock(&work->dev->struct_mutex);
  5539. kfree(work);
  5540. }
  5541. static void do_intel_finish_page_flip(struct drm_device *dev,
  5542. struct drm_crtc *crtc)
  5543. {
  5544. drm_i915_private_t *dev_priv = dev->dev_private;
  5545. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5546. struct intel_unpin_work *work;
  5547. struct drm_i915_gem_object *obj;
  5548. struct drm_pending_vblank_event *e;
  5549. struct timeval tnow, tvbl;
  5550. unsigned long flags;
  5551. /* Ignore early vblank irqs */
  5552. if (intel_crtc == NULL)
  5553. return;
  5554. do_gettimeofday(&tnow);
  5555. spin_lock_irqsave(&dev->event_lock, flags);
  5556. work = intel_crtc->unpin_work;
  5557. if (work == NULL || !work->pending) {
  5558. spin_unlock_irqrestore(&dev->event_lock, flags);
  5559. return;
  5560. }
  5561. intel_crtc->unpin_work = NULL;
  5562. if (work->event) {
  5563. e = work->event;
  5564. e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
  5565. /* Called before vblank count and timestamps have
  5566. * been updated for the vblank interval of flip
  5567. * completion? Need to increment vblank count and
  5568. * add one videorefresh duration to returned timestamp
  5569. * to account for this. We assume this happened if we
  5570. * get called over 0.9 frame durations after the last
  5571. * timestamped vblank.
  5572. *
  5573. * This calculation can not be used with vrefresh rates
  5574. * below 5Hz (10Hz to be on the safe side) without
  5575. * promoting to 64 integers.
  5576. */
  5577. if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
  5578. 9 * crtc->framedur_ns) {
  5579. e->event.sequence++;
  5580. tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
  5581. crtc->framedur_ns);
  5582. }
  5583. e->event.tv_sec = tvbl.tv_sec;
  5584. e->event.tv_usec = tvbl.tv_usec;
  5585. list_add_tail(&e->base.link,
  5586. &e->base.file_priv->event_list);
  5587. wake_up_interruptible(&e->base.file_priv->event_wait);
  5588. }
  5589. drm_vblank_put(dev, intel_crtc->pipe);
  5590. spin_unlock_irqrestore(&dev->event_lock, flags);
  5591. obj = work->old_fb_obj;
  5592. atomic_clear_mask(1 << intel_crtc->plane,
  5593. &obj->pending_flip.counter);
  5594. if (atomic_read(&obj->pending_flip) == 0)
  5595. wake_up(&dev_priv->pending_flip_queue);
  5596. schedule_work(&work->work);
  5597. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  5598. }
  5599. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  5600. {
  5601. drm_i915_private_t *dev_priv = dev->dev_private;
  5602. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  5603. do_intel_finish_page_flip(dev, crtc);
  5604. }
  5605. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  5606. {
  5607. drm_i915_private_t *dev_priv = dev->dev_private;
  5608. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  5609. do_intel_finish_page_flip(dev, crtc);
  5610. }
  5611. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  5612. {
  5613. drm_i915_private_t *dev_priv = dev->dev_private;
  5614. struct intel_crtc *intel_crtc =
  5615. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  5616. unsigned long flags;
  5617. spin_lock_irqsave(&dev->event_lock, flags);
  5618. if (intel_crtc->unpin_work) {
  5619. if ((++intel_crtc->unpin_work->pending) > 1)
  5620. DRM_ERROR("Prepared flip multiple times\n");
  5621. } else {
  5622. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  5623. }
  5624. spin_unlock_irqrestore(&dev->event_lock, flags);
  5625. }
  5626. static int intel_gen2_queue_flip(struct drm_device *dev,
  5627. struct drm_crtc *crtc,
  5628. struct drm_framebuffer *fb,
  5629. struct drm_i915_gem_object *obj)
  5630. {
  5631. struct drm_i915_private *dev_priv = dev->dev_private;
  5632. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5633. unsigned long offset;
  5634. u32 flip_mask;
  5635. int ret;
  5636. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5637. if (ret)
  5638. goto out;
  5639. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  5640. offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
  5641. ret = BEGIN_LP_RING(6);
  5642. if (ret)
  5643. goto out;
  5644. /* Can't queue multiple flips, so wait for the previous
  5645. * one to finish before executing the next.
  5646. */
  5647. if (intel_crtc->plane)
  5648. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5649. else
  5650. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5651. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  5652. OUT_RING(MI_NOOP);
  5653. OUT_RING(MI_DISPLAY_FLIP |
  5654. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5655. OUT_RING(fb->pitch);
  5656. OUT_RING(obj->gtt_offset + offset);
  5657. OUT_RING(MI_NOOP);
  5658. ADVANCE_LP_RING();
  5659. out:
  5660. return ret;
  5661. }
  5662. static int intel_gen3_queue_flip(struct drm_device *dev,
  5663. struct drm_crtc *crtc,
  5664. struct drm_framebuffer *fb,
  5665. struct drm_i915_gem_object *obj)
  5666. {
  5667. struct drm_i915_private *dev_priv = dev->dev_private;
  5668. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5669. unsigned long offset;
  5670. u32 flip_mask;
  5671. int ret;
  5672. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5673. if (ret)
  5674. goto out;
  5675. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  5676. offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
  5677. ret = BEGIN_LP_RING(6);
  5678. if (ret)
  5679. goto out;
  5680. if (intel_crtc->plane)
  5681. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5682. else
  5683. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5684. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  5685. OUT_RING(MI_NOOP);
  5686. OUT_RING(MI_DISPLAY_FLIP_I915 |
  5687. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5688. OUT_RING(fb->pitch);
  5689. OUT_RING(obj->gtt_offset + offset);
  5690. OUT_RING(MI_NOOP);
  5691. ADVANCE_LP_RING();
  5692. out:
  5693. return ret;
  5694. }
  5695. static int intel_gen4_queue_flip(struct drm_device *dev,
  5696. struct drm_crtc *crtc,
  5697. struct drm_framebuffer *fb,
  5698. struct drm_i915_gem_object *obj)
  5699. {
  5700. struct drm_i915_private *dev_priv = dev->dev_private;
  5701. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5702. uint32_t pf, pipesrc;
  5703. int ret;
  5704. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5705. if (ret)
  5706. goto out;
  5707. ret = BEGIN_LP_RING(4);
  5708. if (ret)
  5709. goto out;
  5710. /* i965+ uses the linear or tiled offsets from the
  5711. * Display Registers (which do not change across a page-flip)
  5712. * so we need only reprogram the base address.
  5713. */
  5714. OUT_RING(MI_DISPLAY_FLIP |
  5715. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5716. OUT_RING(fb->pitch);
  5717. OUT_RING(obj->gtt_offset | obj->tiling_mode);
  5718. /* XXX Enabling the panel-fitter across page-flip is so far
  5719. * untested on non-native modes, so ignore it for now.
  5720. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  5721. */
  5722. pf = 0;
  5723. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5724. OUT_RING(pf | pipesrc);
  5725. ADVANCE_LP_RING();
  5726. out:
  5727. return ret;
  5728. }
  5729. static int intel_gen6_queue_flip(struct drm_device *dev,
  5730. struct drm_crtc *crtc,
  5731. struct drm_framebuffer *fb,
  5732. struct drm_i915_gem_object *obj)
  5733. {
  5734. struct drm_i915_private *dev_priv = dev->dev_private;
  5735. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5736. uint32_t pf, pipesrc;
  5737. int ret;
  5738. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  5739. if (ret)
  5740. goto out;
  5741. ret = BEGIN_LP_RING(4);
  5742. if (ret)
  5743. goto out;
  5744. OUT_RING(MI_DISPLAY_FLIP |
  5745. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5746. OUT_RING(fb->pitch | obj->tiling_mode);
  5747. OUT_RING(obj->gtt_offset);
  5748. pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  5749. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5750. OUT_RING(pf | pipesrc);
  5751. ADVANCE_LP_RING();
  5752. out:
  5753. return ret;
  5754. }
  5755. /*
  5756. * On gen7 we currently use the blit ring because (in early silicon at least)
  5757. * the render ring doesn't give us interrpts for page flip completion, which
  5758. * means clients will hang after the first flip is queued. Fortunately the
  5759. * blit ring generates interrupts properly, so use it instead.
  5760. */
  5761. static int intel_gen7_queue_flip(struct drm_device *dev,
  5762. struct drm_crtc *crtc,
  5763. struct drm_framebuffer *fb,
  5764. struct drm_i915_gem_object *obj)
  5765. {
  5766. struct drm_i915_private *dev_priv = dev->dev_private;
  5767. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5768. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  5769. int ret;
  5770. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5771. if (ret)
  5772. goto out;
  5773. ret = intel_ring_begin(ring, 4);
  5774. if (ret)
  5775. goto out;
  5776. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
  5777. intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
  5778. intel_ring_emit(ring, (obj->gtt_offset));
  5779. intel_ring_emit(ring, (MI_NOOP));
  5780. intel_ring_advance(ring);
  5781. out:
  5782. return ret;
  5783. }
  5784. static int intel_default_queue_flip(struct drm_device *dev,
  5785. struct drm_crtc *crtc,
  5786. struct drm_framebuffer *fb,
  5787. struct drm_i915_gem_object *obj)
  5788. {
  5789. return -ENODEV;
  5790. }
  5791. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  5792. struct drm_framebuffer *fb,
  5793. struct drm_pending_vblank_event *event)
  5794. {
  5795. struct drm_device *dev = crtc->dev;
  5796. struct drm_i915_private *dev_priv = dev->dev_private;
  5797. struct intel_framebuffer *intel_fb;
  5798. struct drm_i915_gem_object *obj;
  5799. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5800. struct intel_unpin_work *work;
  5801. unsigned long flags;
  5802. int ret;
  5803. work = kzalloc(sizeof *work, GFP_KERNEL);
  5804. if (work == NULL)
  5805. return -ENOMEM;
  5806. work->event = event;
  5807. work->dev = crtc->dev;
  5808. intel_fb = to_intel_framebuffer(crtc->fb);
  5809. work->old_fb_obj = intel_fb->obj;
  5810. INIT_WORK(&work->work, intel_unpin_work_fn);
  5811. /* We borrow the event spin lock for protecting unpin_work */
  5812. spin_lock_irqsave(&dev->event_lock, flags);
  5813. if (intel_crtc->unpin_work) {
  5814. spin_unlock_irqrestore(&dev->event_lock, flags);
  5815. kfree(work);
  5816. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  5817. return -EBUSY;
  5818. }
  5819. intel_crtc->unpin_work = work;
  5820. spin_unlock_irqrestore(&dev->event_lock, flags);
  5821. intel_fb = to_intel_framebuffer(fb);
  5822. obj = intel_fb->obj;
  5823. mutex_lock(&dev->struct_mutex);
  5824. /* Reference the objects for the scheduled work. */
  5825. drm_gem_object_reference(&work->old_fb_obj->base);
  5826. drm_gem_object_reference(&obj->base);
  5827. crtc->fb = fb;
  5828. ret = drm_vblank_get(dev, intel_crtc->pipe);
  5829. if (ret)
  5830. goto cleanup_objs;
  5831. work->pending_flip_obj = obj;
  5832. work->enable_stall_check = true;
  5833. /* Block clients from rendering to the new back buffer until
  5834. * the flip occurs and the object is no longer visible.
  5835. */
  5836. atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5837. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  5838. if (ret)
  5839. goto cleanup_pending;
  5840. intel_disable_fbc(dev);
  5841. mutex_unlock(&dev->struct_mutex);
  5842. trace_i915_flip_request(intel_crtc->plane, obj);
  5843. return 0;
  5844. cleanup_pending:
  5845. atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5846. cleanup_objs:
  5847. drm_gem_object_unreference(&work->old_fb_obj->base);
  5848. drm_gem_object_unreference(&obj->base);
  5849. mutex_unlock(&dev->struct_mutex);
  5850. spin_lock_irqsave(&dev->event_lock, flags);
  5851. intel_crtc->unpin_work = NULL;
  5852. spin_unlock_irqrestore(&dev->event_lock, flags);
  5853. kfree(work);
  5854. return ret;
  5855. }
  5856. static void intel_sanitize_modesetting(struct drm_device *dev,
  5857. int pipe, int plane)
  5858. {
  5859. struct drm_i915_private *dev_priv = dev->dev_private;
  5860. u32 reg, val;
  5861. if (HAS_PCH_SPLIT(dev))
  5862. return;
  5863. /* Who knows what state these registers were left in by the BIOS or
  5864. * grub?
  5865. *
  5866. * If we leave the registers in a conflicting state (e.g. with the
  5867. * display plane reading from the other pipe than the one we intend
  5868. * to use) then when we attempt to teardown the active mode, we will
  5869. * not disable the pipes and planes in the correct order -- leaving
  5870. * a plane reading from a disabled pipe and possibly leading to
  5871. * undefined behaviour.
  5872. */
  5873. reg = DSPCNTR(plane);
  5874. val = I915_READ(reg);
  5875. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  5876. return;
  5877. if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
  5878. return;
  5879. /* This display plane is active and attached to the other CPU pipe. */
  5880. pipe = !pipe;
  5881. /* Disable the plane and wait for it to stop reading from the pipe. */
  5882. intel_disable_plane(dev_priv, plane, pipe);
  5883. intel_disable_pipe(dev_priv, pipe);
  5884. }
  5885. static void intel_crtc_reset(struct drm_crtc *crtc)
  5886. {
  5887. struct drm_device *dev = crtc->dev;
  5888. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5889. /* Reset flags back to the 'unknown' status so that they
  5890. * will be correctly set on the initial modeset.
  5891. */
  5892. intel_crtc->dpms_mode = -1;
  5893. /* We need to fix up any BIOS configuration that conflicts with
  5894. * our expectations.
  5895. */
  5896. intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
  5897. }
  5898. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  5899. .dpms = intel_crtc_dpms,
  5900. .mode_fixup = intel_crtc_mode_fixup,
  5901. .mode_set = intel_crtc_mode_set,
  5902. .mode_set_base = intel_pipe_set_base,
  5903. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  5904. .load_lut = intel_crtc_load_lut,
  5905. .disable = intel_crtc_disable,
  5906. };
  5907. static const struct drm_crtc_funcs intel_crtc_funcs = {
  5908. .reset = intel_crtc_reset,
  5909. .cursor_set = intel_crtc_cursor_set,
  5910. .cursor_move = intel_crtc_cursor_move,
  5911. .gamma_set = intel_crtc_gamma_set,
  5912. .set_config = drm_crtc_helper_set_config,
  5913. .destroy = intel_crtc_destroy,
  5914. .page_flip = intel_crtc_page_flip,
  5915. };
  5916. static void intel_crtc_init(struct drm_device *dev, int pipe)
  5917. {
  5918. drm_i915_private_t *dev_priv = dev->dev_private;
  5919. struct intel_crtc *intel_crtc;
  5920. int i;
  5921. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  5922. if (intel_crtc == NULL)
  5923. return;
  5924. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  5925. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  5926. for (i = 0; i < 256; i++) {
  5927. intel_crtc->lut_r[i] = i;
  5928. intel_crtc->lut_g[i] = i;
  5929. intel_crtc->lut_b[i] = i;
  5930. }
  5931. /* Swap pipes & planes for FBC on pre-965 */
  5932. intel_crtc->pipe = pipe;
  5933. intel_crtc->plane = pipe;
  5934. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  5935. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  5936. intel_crtc->plane = !pipe;
  5937. }
  5938. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  5939. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  5940. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  5941. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  5942. intel_crtc_reset(&intel_crtc->base);
  5943. intel_crtc->active = true; /* force the pipe off on setup_init_config */
  5944. intel_crtc->bpp = 24; /* default for pre-Ironlake */
  5945. if (HAS_PCH_SPLIT(dev)) {
  5946. intel_helper_funcs.prepare = ironlake_crtc_prepare;
  5947. intel_helper_funcs.commit = ironlake_crtc_commit;
  5948. } else {
  5949. intel_helper_funcs.prepare = i9xx_crtc_prepare;
  5950. intel_helper_funcs.commit = i9xx_crtc_commit;
  5951. }
  5952. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  5953. intel_crtc->busy = false;
  5954. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  5955. (unsigned long)intel_crtc);
  5956. }
  5957. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  5958. struct drm_file *file)
  5959. {
  5960. drm_i915_private_t *dev_priv = dev->dev_private;
  5961. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  5962. struct drm_mode_object *drmmode_obj;
  5963. struct intel_crtc *crtc;
  5964. if (!dev_priv) {
  5965. DRM_ERROR("called with no initialization\n");
  5966. return -EINVAL;
  5967. }
  5968. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  5969. DRM_MODE_OBJECT_CRTC);
  5970. if (!drmmode_obj) {
  5971. DRM_ERROR("no such CRTC id\n");
  5972. return -EINVAL;
  5973. }
  5974. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  5975. pipe_from_crtc_id->pipe = crtc->pipe;
  5976. return 0;
  5977. }
  5978. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  5979. {
  5980. struct intel_encoder *encoder;
  5981. int index_mask = 0;
  5982. int entry = 0;
  5983. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  5984. if (type_mask & encoder->clone_mask)
  5985. index_mask |= (1 << entry);
  5986. entry++;
  5987. }
  5988. return index_mask;
  5989. }
  5990. static bool has_edp_a(struct drm_device *dev)
  5991. {
  5992. struct drm_i915_private *dev_priv = dev->dev_private;
  5993. if (!IS_MOBILE(dev))
  5994. return false;
  5995. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  5996. return false;
  5997. if (IS_GEN5(dev) &&
  5998. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  5999. return false;
  6000. return true;
  6001. }
  6002. static void intel_setup_outputs(struct drm_device *dev)
  6003. {
  6004. struct drm_i915_private *dev_priv = dev->dev_private;
  6005. struct intel_encoder *encoder;
  6006. bool dpd_is_edp = false;
  6007. bool has_lvds = false;
  6008. if (IS_MOBILE(dev) && !IS_I830(dev))
  6009. has_lvds = intel_lvds_init(dev);
  6010. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  6011. /* disable the panel fitter on everything but LVDS */
  6012. I915_WRITE(PFIT_CONTROL, 0);
  6013. }
  6014. if (HAS_PCH_SPLIT(dev)) {
  6015. dpd_is_edp = intel_dpd_is_edp(dev);
  6016. if (has_edp_a(dev))
  6017. intel_dp_init(dev, DP_A);
  6018. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  6019. intel_dp_init(dev, PCH_DP_D);
  6020. }
  6021. intel_crt_init(dev);
  6022. if (HAS_PCH_SPLIT(dev)) {
  6023. int found;
  6024. if (I915_READ(HDMIB) & PORT_DETECTED) {
  6025. /* PCH SDVOB multiplex with HDMIB */
  6026. found = intel_sdvo_init(dev, PCH_SDVOB);
  6027. if (!found)
  6028. intel_hdmi_init(dev, HDMIB);
  6029. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  6030. intel_dp_init(dev, PCH_DP_B);
  6031. }
  6032. if (I915_READ(HDMIC) & PORT_DETECTED)
  6033. intel_hdmi_init(dev, HDMIC);
  6034. if (I915_READ(HDMID) & PORT_DETECTED)
  6035. intel_hdmi_init(dev, HDMID);
  6036. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  6037. intel_dp_init(dev, PCH_DP_C);
  6038. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  6039. intel_dp_init(dev, PCH_DP_D);
  6040. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  6041. bool found = false;
  6042. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6043. DRM_DEBUG_KMS("probing SDVOB\n");
  6044. found = intel_sdvo_init(dev, SDVOB);
  6045. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  6046. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  6047. intel_hdmi_init(dev, SDVOB);
  6048. }
  6049. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  6050. DRM_DEBUG_KMS("probing DP_B\n");
  6051. intel_dp_init(dev, DP_B);
  6052. }
  6053. }
  6054. /* Before G4X SDVOC doesn't have its own detect register */
  6055. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6056. DRM_DEBUG_KMS("probing SDVOC\n");
  6057. found = intel_sdvo_init(dev, SDVOC);
  6058. }
  6059. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  6060. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  6061. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  6062. intel_hdmi_init(dev, SDVOC);
  6063. }
  6064. if (SUPPORTS_INTEGRATED_DP(dev)) {
  6065. DRM_DEBUG_KMS("probing DP_C\n");
  6066. intel_dp_init(dev, DP_C);
  6067. }
  6068. }
  6069. if (SUPPORTS_INTEGRATED_DP(dev) &&
  6070. (I915_READ(DP_D) & DP_DETECTED)) {
  6071. DRM_DEBUG_KMS("probing DP_D\n");
  6072. intel_dp_init(dev, DP_D);
  6073. }
  6074. } else if (IS_GEN2(dev))
  6075. intel_dvo_init(dev);
  6076. if (SUPPORTS_TV(dev))
  6077. intel_tv_init(dev);
  6078. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6079. encoder->base.possible_crtcs = encoder->crtc_mask;
  6080. encoder->base.possible_clones =
  6081. intel_encoder_clones(dev, encoder->clone_mask);
  6082. }
  6083. intel_panel_setup_backlight(dev);
  6084. /* disable all the possible outputs/crtcs before entering KMS mode */
  6085. drm_helper_disable_unused_functions(dev);
  6086. }
  6087. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  6088. {
  6089. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6090. drm_framebuffer_cleanup(fb);
  6091. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  6092. kfree(intel_fb);
  6093. }
  6094. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  6095. struct drm_file *file,
  6096. unsigned int *handle)
  6097. {
  6098. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6099. struct drm_i915_gem_object *obj = intel_fb->obj;
  6100. return drm_gem_handle_create(file, &obj->base, handle);
  6101. }
  6102. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  6103. .destroy = intel_user_framebuffer_destroy,
  6104. .create_handle = intel_user_framebuffer_create_handle,
  6105. };
  6106. int intel_framebuffer_init(struct drm_device *dev,
  6107. struct intel_framebuffer *intel_fb,
  6108. struct drm_mode_fb_cmd *mode_cmd,
  6109. struct drm_i915_gem_object *obj)
  6110. {
  6111. int ret;
  6112. if (obj->tiling_mode == I915_TILING_Y)
  6113. return -EINVAL;
  6114. if (mode_cmd->pitch & 63)
  6115. return -EINVAL;
  6116. switch (mode_cmd->bpp) {
  6117. case 8:
  6118. case 16:
  6119. /* Only pre-ILK can handle 5:5:5 */
  6120. if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
  6121. return -EINVAL;
  6122. break;
  6123. case 24:
  6124. case 32:
  6125. break;
  6126. default:
  6127. return -EINVAL;
  6128. }
  6129. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  6130. if (ret) {
  6131. DRM_ERROR("framebuffer init failed %d\n", ret);
  6132. return ret;
  6133. }
  6134. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  6135. intel_fb->obj = obj;
  6136. return 0;
  6137. }
  6138. static struct drm_framebuffer *
  6139. intel_user_framebuffer_create(struct drm_device *dev,
  6140. struct drm_file *filp,
  6141. struct drm_mode_fb_cmd *mode_cmd)
  6142. {
  6143. struct drm_i915_gem_object *obj;
  6144. obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
  6145. if (&obj->base == NULL)
  6146. return ERR_PTR(-ENOENT);
  6147. return intel_framebuffer_create(dev, mode_cmd, obj);
  6148. }
  6149. static const struct drm_mode_config_funcs intel_mode_funcs = {
  6150. .fb_create = intel_user_framebuffer_create,
  6151. .output_poll_changed = intel_fb_output_poll_changed,
  6152. };
  6153. static struct drm_i915_gem_object *
  6154. intel_alloc_context_page(struct drm_device *dev)
  6155. {
  6156. struct drm_i915_gem_object *ctx;
  6157. int ret;
  6158. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  6159. ctx = i915_gem_alloc_object(dev, 4096);
  6160. if (!ctx) {
  6161. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  6162. return NULL;
  6163. }
  6164. ret = i915_gem_object_pin(ctx, 4096, true);
  6165. if (ret) {
  6166. DRM_ERROR("failed to pin power context: %d\n", ret);
  6167. goto err_unref;
  6168. }
  6169. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  6170. if (ret) {
  6171. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  6172. goto err_unpin;
  6173. }
  6174. return ctx;
  6175. err_unpin:
  6176. i915_gem_object_unpin(ctx);
  6177. err_unref:
  6178. drm_gem_object_unreference(&ctx->base);
  6179. mutex_unlock(&dev->struct_mutex);
  6180. return NULL;
  6181. }
  6182. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  6183. {
  6184. struct drm_i915_private *dev_priv = dev->dev_private;
  6185. u16 rgvswctl;
  6186. rgvswctl = I915_READ16(MEMSWCTL);
  6187. if (rgvswctl & MEMCTL_CMD_STS) {
  6188. DRM_DEBUG("gpu busy, RCS change rejected\n");
  6189. return false; /* still busy with another command */
  6190. }
  6191. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  6192. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  6193. I915_WRITE16(MEMSWCTL, rgvswctl);
  6194. POSTING_READ16(MEMSWCTL);
  6195. rgvswctl |= MEMCTL_CMD_STS;
  6196. I915_WRITE16(MEMSWCTL, rgvswctl);
  6197. return true;
  6198. }
  6199. void ironlake_enable_drps(struct drm_device *dev)
  6200. {
  6201. struct drm_i915_private *dev_priv = dev->dev_private;
  6202. u32 rgvmodectl = I915_READ(MEMMODECTL);
  6203. u8 fmax, fmin, fstart, vstart;
  6204. /* Enable temp reporting */
  6205. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  6206. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  6207. /* 100ms RC evaluation intervals */
  6208. I915_WRITE(RCUPEI, 100000);
  6209. I915_WRITE(RCDNEI, 100000);
  6210. /* Set max/min thresholds to 90ms and 80ms respectively */
  6211. I915_WRITE(RCBMAXAVG, 90000);
  6212. I915_WRITE(RCBMINAVG, 80000);
  6213. I915_WRITE(MEMIHYST, 1);
  6214. /* Set up min, max, and cur for interrupt handling */
  6215. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  6216. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  6217. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  6218. MEMMODE_FSTART_SHIFT;
  6219. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  6220. PXVFREQ_PX_SHIFT;
  6221. dev_priv->fmax = fmax; /* IPS callback will increase this */
  6222. dev_priv->fstart = fstart;
  6223. dev_priv->max_delay = fstart;
  6224. dev_priv->min_delay = fmin;
  6225. dev_priv->cur_delay = fstart;
  6226. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  6227. fmax, fmin, fstart);
  6228. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  6229. /*
  6230. * Interrupts will be enabled in ironlake_irq_postinstall
  6231. */
  6232. I915_WRITE(VIDSTART, vstart);
  6233. POSTING_READ(VIDSTART);
  6234. rgvmodectl |= MEMMODE_SWMODE_EN;
  6235. I915_WRITE(MEMMODECTL, rgvmodectl);
  6236. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  6237. DRM_ERROR("stuck trying to change perf mode\n");
  6238. msleep(1);
  6239. ironlake_set_drps(dev, fstart);
  6240. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  6241. I915_READ(0x112e0);
  6242. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  6243. dev_priv->last_count2 = I915_READ(0x112f4);
  6244. getrawmonotonic(&dev_priv->last_time2);
  6245. }
  6246. void ironlake_disable_drps(struct drm_device *dev)
  6247. {
  6248. struct drm_i915_private *dev_priv = dev->dev_private;
  6249. u16 rgvswctl = I915_READ16(MEMSWCTL);
  6250. /* Ack interrupts, disable EFC interrupt */
  6251. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  6252. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  6253. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  6254. I915_WRITE(DEIIR, DE_PCU_EVENT);
  6255. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  6256. /* Go back to the starting frequency */
  6257. ironlake_set_drps(dev, dev_priv->fstart);
  6258. msleep(1);
  6259. rgvswctl |= MEMCTL_CMD_STS;
  6260. I915_WRITE(MEMSWCTL, rgvswctl);
  6261. msleep(1);
  6262. }
  6263. void gen6_set_rps(struct drm_device *dev, u8 val)
  6264. {
  6265. struct drm_i915_private *dev_priv = dev->dev_private;
  6266. u32 swreq;
  6267. swreq = (val & 0x3ff) << 25;
  6268. I915_WRITE(GEN6_RPNSWREQ, swreq);
  6269. }
  6270. void gen6_disable_rps(struct drm_device *dev)
  6271. {
  6272. struct drm_i915_private *dev_priv = dev->dev_private;
  6273. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  6274. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  6275. I915_WRITE(GEN6_PMIER, 0);
  6276. spin_lock_irq(&dev_priv->rps_lock);
  6277. dev_priv->pm_iir = 0;
  6278. spin_unlock_irq(&dev_priv->rps_lock);
  6279. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  6280. }
  6281. static unsigned long intel_pxfreq(u32 vidfreq)
  6282. {
  6283. unsigned long freq;
  6284. int div = (vidfreq & 0x3f0000) >> 16;
  6285. int post = (vidfreq & 0x3000) >> 12;
  6286. int pre = (vidfreq & 0x7);
  6287. if (!pre)
  6288. return 0;
  6289. freq = ((div * 133333) / ((1<<post) * pre));
  6290. return freq;
  6291. }
  6292. void intel_init_emon(struct drm_device *dev)
  6293. {
  6294. struct drm_i915_private *dev_priv = dev->dev_private;
  6295. u32 lcfuse;
  6296. u8 pxw[16];
  6297. int i;
  6298. /* Disable to program */
  6299. I915_WRITE(ECR, 0);
  6300. POSTING_READ(ECR);
  6301. /* Program energy weights for various events */
  6302. I915_WRITE(SDEW, 0x15040d00);
  6303. I915_WRITE(CSIEW0, 0x007f0000);
  6304. I915_WRITE(CSIEW1, 0x1e220004);
  6305. I915_WRITE(CSIEW2, 0x04000004);
  6306. for (i = 0; i < 5; i++)
  6307. I915_WRITE(PEW + (i * 4), 0);
  6308. for (i = 0; i < 3; i++)
  6309. I915_WRITE(DEW + (i * 4), 0);
  6310. /* Program P-state weights to account for frequency power adjustment */
  6311. for (i = 0; i < 16; i++) {
  6312. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  6313. unsigned long freq = intel_pxfreq(pxvidfreq);
  6314. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  6315. PXVFREQ_PX_SHIFT;
  6316. unsigned long val;
  6317. val = vid * vid;
  6318. val *= (freq / 1000);
  6319. val *= 255;
  6320. val /= (127*127*900);
  6321. if (val > 0xff)
  6322. DRM_ERROR("bad pxval: %ld\n", val);
  6323. pxw[i] = val;
  6324. }
  6325. /* Render standby states get 0 weight */
  6326. pxw[14] = 0;
  6327. pxw[15] = 0;
  6328. for (i = 0; i < 4; i++) {
  6329. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  6330. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  6331. I915_WRITE(PXW + (i * 4), val);
  6332. }
  6333. /* Adjust magic regs to magic values (more experimental results) */
  6334. I915_WRITE(OGW0, 0);
  6335. I915_WRITE(OGW1, 0);
  6336. I915_WRITE(EG0, 0x00007f00);
  6337. I915_WRITE(EG1, 0x0000000e);
  6338. I915_WRITE(EG2, 0x000e0000);
  6339. I915_WRITE(EG3, 0x68000300);
  6340. I915_WRITE(EG4, 0x42000000);
  6341. I915_WRITE(EG5, 0x00140031);
  6342. I915_WRITE(EG6, 0);
  6343. I915_WRITE(EG7, 0);
  6344. for (i = 0; i < 8; i++)
  6345. I915_WRITE(PXWL + (i * 4), 0);
  6346. /* Enable PMON + select events */
  6347. I915_WRITE(ECR, 0x80000019);
  6348. lcfuse = I915_READ(LCFUSE02);
  6349. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  6350. }
  6351. void gen6_enable_rps(struct drm_i915_private *dev_priv)
  6352. {
  6353. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  6354. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  6355. u32 pcu_mbox, rc6_mask = 0;
  6356. int cur_freq, min_freq, max_freq;
  6357. int i;
  6358. /* Here begins a magic sequence of register writes to enable
  6359. * auto-downclocking.
  6360. *
  6361. * Perhaps there might be some value in exposing these to
  6362. * userspace...
  6363. */
  6364. I915_WRITE(GEN6_RC_STATE, 0);
  6365. mutex_lock(&dev_priv->dev->struct_mutex);
  6366. gen6_gt_force_wake_get(dev_priv);
  6367. /* disable the counters and set deterministic thresholds */
  6368. I915_WRITE(GEN6_RC_CONTROL, 0);
  6369. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  6370. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  6371. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  6372. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  6373. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  6374. for (i = 0; i < I915_NUM_RINGS; i++)
  6375. I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
  6376. I915_WRITE(GEN6_RC_SLEEP, 0);
  6377. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  6378. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  6379. I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
  6380. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  6381. if (i915_enable_rc6)
  6382. rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
  6383. GEN6_RC_CTL_RC6_ENABLE;
  6384. I915_WRITE(GEN6_RC_CONTROL,
  6385. rc6_mask |
  6386. GEN6_RC_CTL_EI_MODE(1) |
  6387. GEN6_RC_CTL_HW_ENABLE);
  6388. I915_WRITE(GEN6_RPNSWREQ,
  6389. GEN6_FREQUENCY(10) |
  6390. GEN6_OFFSET(0) |
  6391. GEN6_AGGRESSIVE_TURBO);
  6392. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  6393. GEN6_FREQUENCY(12));
  6394. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  6395. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  6396. 18 << 24 |
  6397. 6 << 16);
  6398. I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
  6399. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
  6400. I915_WRITE(GEN6_RP_UP_EI, 100000);
  6401. I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
  6402. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  6403. I915_WRITE(GEN6_RP_CONTROL,
  6404. GEN6_RP_MEDIA_TURBO |
  6405. GEN6_RP_USE_NORMAL_FREQ |
  6406. GEN6_RP_MEDIA_IS_GFX |
  6407. GEN6_RP_ENABLE |
  6408. GEN6_RP_UP_BUSY_AVG |
  6409. GEN6_RP_DOWN_IDLE_CONT);
  6410. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6411. 500))
  6412. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  6413. I915_WRITE(GEN6_PCODE_DATA, 0);
  6414. I915_WRITE(GEN6_PCODE_MAILBOX,
  6415. GEN6_PCODE_READY |
  6416. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  6417. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6418. 500))
  6419. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  6420. min_freq = (rp_state_cap & 0xff0000) >> 16;
  6421. max_freq = rp_state_cap & 0xff;
  6422. cur_freq = (gt_perf_status & 0xff00) >> 8;
  6423. /* Check for overclock support */
  6424. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6425. 500))
  6426. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  6427. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
  6428. pcu_mbox = I915_READ(GEN6_PCODE_DATA);
  6429. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  6430. 500))
  6431. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  6432. if (pcu_mbox & (1<<31)) { /* OC supported */
  6433. max_freq = pcu_mbox & 0xff;
  6434. DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
  6435. }
  6436. /* In units of 100MHz */
  6437. dev_priv->max_delay = max_freq;
  6438. dev_priv->min_delay = min_freq;
  6439. dev_priv->cur_delay = cur_freq;
  6440. /* requires MSI enabled */
  6441. I915_WRITE(GEN6_PMIER,
  6442. GEN6_PM_MBOX_EVENT |
  6443. GEN6_PM_THERMAL_EVENT |
  6444. GEN6_PM_RP_DOWN_TIMEOUT |
  6445. GEN6_PM_RP_UP_THRESHOLD |
  6446. GEN6_PM_RP_DOWN_THRESHOLD |
  6447. GEN6_PM_RP_UP_EI_EXPIRED |
  6448. GEN6_PM_RP_DOWN_EI_EXPIRED);
  6449. spin_lock_irq(&dev_priv->rps_lock);
  6450. WARN_ON(dev_priv->pm_iir != 0);
  6451. I915_WRITE(GEN6_PMIMR, 0);
  6452. spin_unlock_irq(&dev_priv->rps_lock);
  6453. /* enable all PM interrupts */
  6454. I915_WRITE(GEN6_PMINTRMSK, 0);
  6455. gen6_gt_force_wake_put(dev_priv);
  6456. mutex_unlock(&dev_priv->dev->struct_mutex);
  6457. }
  6458. void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
  6459. {
  6460. int min_freq = 15;
  6461. int gpu_freq, ia_freq, max_ia_freq;
  6462. int scaling_factor = 180;
  6463. max_ia_freq = cpufreq_quick_get_max(0);
  6464. /*
  6465. * Default to measured freq if none found, PCU will ensure we don't go
  6466. * over
  6467. */
  6468. if (!max_ia_freq)
  6469. max_ia_freq = tsc_khz;
  6470. /* Convert from kHz to MHz */
  6471. max_ia_freq /= 1000;
  6472. mutex_lock(&dev_priv->dev->struct_mutex);
  6473. /*
  6474. * For each potential GPU frequency, load a ring frequency we'd like
  6475. * to use for memory access. We do this by specifying the IA frequency
  6476. * the PCU should use as a reference to determine the ring frequency.
  6477. */
  6478. for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
  6479. gpu_freq--) {
  6480. int diff = dev_priv->max_delay - gpu_freq;
  6481. /*
  6482. * For GPU frequencies less than 750MHz, just use the lowest
  6483. * ring freq.
  6484. */
  6485. if (gpu_freq < min_freq)
  6486. ia_freq = 800;
  6487. else
  6488. ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  6489. ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  6490. I915_WRITE(GEN6_PCODE_DATA,
  6491. (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
  6492. gpu_freq);
  6493. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  6494. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  6495. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  6496. GEN6_PCODE_READY) == 0, 10)) {
  6497. DRM_ERROR("pcode write of freq table timed out\n");
  6498. continue;
  6499. }
  6500. }
  6501. mutex_unlock(&dev_priv->dev->struct_mutex);
  6502. }
  6503. static void ironlake_init_clock_gating(struct drm_device *dev)
  6504. {
  6505. struct drm_i915_private *dev_priv = dev->dev_private;
  6506. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  6507. /* Required for FBC */
  6508. dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
  6509. DPFCRUNIT_CLOCK_GATE_DISABLE |
  6510. DPFDUNIT_CLOCK_GATE_DISABLE;
  6511. /* Required for CxSR */
  6512. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  6513. I915_WRITE(PCH_3DCGDIS0,
  6514. MARIUNIT_CLOCK_GATE_DISABLE |
  6515. SVSMUNIT_CLOCK_GATE_DISABLE);
  6516. I915_WRITE(PCH_3DCGDIS1,
  6517. VFMUNIT_CLOCK_GATE_DISABLE);
  6518. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  6519. /*
  6520. * According to the spec the following bits should be set in
  6521. * order to enable memory self-refresh
  6522. * The bit 22/21 of 0x42004
  6523. * The bit 5 of 0x42020
  6524. * The bit 15 of 0x45000
  6525. */
  6526. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6527. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  6528. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  6529. I915_WRITE(ILK_DSPCLK_GATE,
  6530. (I915_READ(ILK_DSPCLK_GATE) |
  6531. ILK_DPARB_CLK_GATE));
  6532. I915_WRITE(DISP_ARB_CTL,
  6533. (I915_READ(DISP_ARB_CTL) |
  6534. DISP_FBC_WM_DIS));
  6535. I915_WRITE(WM3_LP_ILK, 0);
  6536. I915_WRITE(WM2_LP_ILK, 0);
  6537. I915_WRITE(WM1_LP_ILK, 0);
  6538. /*
  6539. * Based on the document from hardware guys the following bits
  6540. * should be set unconditionally in order to enable FBC.
  6541. * The bit 22 of 0x42000
  6542. * The bit 22 of 0x42004
  6543. * The bit 7,8,9 of 0x42020.
  6544. */
  6545. if (IS_IRONLAKE_M(dev)) {
  6546. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  6547. I915_READ(ILK_DISPLAY_CHICKEN1) |
  6548. ILK_FBCQ_DIS);
  6549. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6550. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6551. ILK_DPARB_GATE);
  6552. I915_WRITE(ILK_DSPCLK_GATE,
  6553. I915_READ(ILK_DSPCLK_GATE) |
  6554. ILK_DPFC_DIS1 |
  6555. ILK_DPFC_DIS2 |
  6556. ILK_CLK_FBC);
  6557. }
  6558. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6559. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6560. ILK_ELPIN_409_SELECT);
  6561. I915_WRITE(_3D_CHICKEN2,
  6562. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  6563. _3D_CHICKEN2_WM_READ_PIPELINED);
  6564. }
  6565. static void gen6_init_clock_gating(struct drm_device *dev)
  6566. {
  6567. struct drm_i915_private *dev_priv = dev->dev_private;
  6568. int pipe;
  6569. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  6570. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  6571. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6572. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6573. ILK_ELPIN_409_SELECT);
  6574. I915_WRITE(WM3_LP_ILK, 0);
  6575. I915_WRITE(WM2_LP_ILK, 0);
  6576. I915_WRITE(WM1_LP_ILK, 0);
  6577. /*
  6578. * According to the spec the following bits should be
  6579. * set in order to enable memory self-refresh and fbc:
  6580. * The bit21 and bit22 of 0x42000
  6581. * The bit21 and bit22 of 0x42004
  6582. * The bit5 and bit7 of 0x42020
  6583. * The bit14 of 0x70180
  6584. * The bit14 of 0x71180
  6585. */
  6586. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  6587. I915_READ(ILK_DISPLAY_CHICKEN1) |
  6588. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  6589. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  6590. I915_READ(ILK_DISPLAY_CHICKEN2) |
  6591. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  6592. I915_WRITE(ILK_DSPCLK_GATE,
  6593. I915_READ(ILK_DSPCLK_GATE) |
  6594. ILK_DPARB_CLK_GATE |
  6595. ILK_DPFD_CLK_GATE);
  6596. for_each_pipe(pipe)
  6597. I915_WRITE(DSPCNTR(pipe),
  6598. I915_READ(DSPCNTR(pipe)) |
  6599. DISPPLANE_TRICKLE_FEED_DISABLE);
  6600. }
  6601. static void ivybridge_init_clock_gating(struct drm_device *dev)
  6602. {
  6603. struct drm_i915_private *dev_priv = dev->dev_private;
  6604. int pipe;
  6605. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  6606. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  6607. I915_WRITE(WM3_LP_ILK, 0);
  6608. I915_WRITE(WM2_LP_ILK, 0);
  6609. I915_WRITE(WM1_LP_ILK, 0);
  6610. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  6611. for_each_pipe(pipe)
  6612. I915_WRITE(DSPCNTR(pipe),
  6613. I915_READ(DSPCNTR(pipe)) |
  6614. DISPPLANE_TRICKLE_FEED_DISABLE);
  6615. }
  6616. static void g4x_init_clock_gating(struct drm_device *dev)
  6617. {
  6618. struct drm_i915_private *dev_priv = dev->dev_private;
  6619. uint32_t dspclk_gate;
  6620. I915_WRITE(RENCLK_GATE_D1, 0);
  6621. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  6622. GS_UNIT_CLOCK_GATE_DISABLE |
  6623. CL_UNIT_CLOCK_GATE_DISABLE);
  6624. I915_WRITE(RAMCLK_GATE_D, 0);
  6625. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  6626. OVRUNIT_CLOCK_GATE_DISABLE |
  6627. OVCUNIT_CLOCK_GATE_DISABLE;
  6628. if (IS_GM45(dev))
  6629. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  6630. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  6631. }
  6632. static void crestline_init_clock_gating(struct drm_device *dev)
  6633. {
  6634. struct drm_i915_private *dev_priv = dev->dev_private;
  6635. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  6636. I915_WRITE(RENCLK_GATE_D2, 0);
  6637. I915_WRITE(DSPCLK_GATE_D, 0);
  6638. I915_WRITE(RAMCLK_GATE_D, 0);
  6639. I915_WRITE16(DEUC, 0);
  6640. }
  6641. static void broadwater_init_clock_gating(struct drm_device *dev)
  6642. {
  6643. struct drm_i915_private *dev_priv = dev->dev_private;
  6644. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  6645. I965_RCC_CLOCK_GATE_DISABLE |
  6646. I965_RCPB_CLOCK_GATE_DISABLE |
  6647. I965_ISC_CLOCK_GATE_DISABLE |
  6648. I965_FBC_CLOCK_GATE_DISABLE);
  6649. I915_WRITE(RENCLK_GATE_D2, 0);
  6650. }
  6651. static void gen3_init_clock_gating(struct drm_device *dev)
  6652. {
  6653. struct drm_i915_private *dev_priv = dev->dev_private;
  6654. u32 dstate = I915_READ(D_STATE);
  6655. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  6656. DSTATE_DOT_CLOCK_GATING;
  6657. I915_WRITE(D_STATE, dstate);
  6658. }
  6659. static void i85x_init_clock_gating(struct drm_device *dev)
  6660. {
  6661. struct drm_i915_private *dev_priv = dev->dev_private;
  6662. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  6663. }
  6664. static void i830_init_clock_gating(struct drm_device *dev)
  6665. {
  6666. struct drm_i915_private *dev_priv = dev->dev_private;
  6667. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  6668. }
  6669. static void ibx_init_clock_gating(struct drm_device *dev)
  6670. {
  6671. struct drm_i915_private *dev_priv = dev->dev_private;
  6672. /*
  6673. * On Ibex Peak and Cougar Point, we need to disable clock
  6674. * gating for the panel power sequencer or it will fail to
  6675. * start up when no ports are active.
  6676. */
  6677. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  6678. }
  6679. static void cpt_init_clock_gating(struct drm_device *dev)
  6680. {
  6681. struct drm_i915_private *dev_priv = dev->dev_private;
  6682. /*
  6683. * On Ibex Peak and Cougar Point, we need to disable clock
  6684. * gating for the panel power sequencer or it will fail to
  6685. * start up when no ports are active.
  6686. */
  6687. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  6688. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  6689. DPLS_EDP_PPS_FIX_DIS);
  6690. }
  6691. static void ironlake_teardown_rc6(struct drm_device *dev)
  6692. {
  6693. struct drm_i915_private *dev_priv = dev->dev_private;
  6694. if (dev_priv->renderctx) {
  6695. i915_gem_object_unpin(dev_priv->renderctx);
  6696. drm_gem_object_unreference(&dev_priv->renderctx->base);
  6697. dev_priv->renderctx = NULL;
  6698. }
  6699. if (dev_priv->pwrctx) {
  6700. i915_gem_object_unpin(dev_priv->pwrctx);
  6701. drm_gem_object_unreference(&dev_priv->pwrctx->base);
  6702. dev_priv->pwrctx = NULL;
  6703. }
  6704. }
  6705. static void ironlake_disable_rc6(struct drm_device *dev)
  6706. {
  6707. struct drm_i915_private *dev_priv = dev->dev_private;
  6708. if (I915_READ(PWRCTXA)) {
  6709. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  6710. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  6711. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  6712. 50);
  6713. I915_WRITE(PWRCTXA, 0);
  6714. POSTING_READ(PWRCTXA);
  6715. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  6716. POSTING_READ(RSTDBYCTL);
  6717. }
  6718. ironlake_teardown_rc6(dev);
  6719. }
  6720. static int ironlake_setup_rc6(struct drm_device *dev)
  6721. {
  6722. struct drm_i915_private *dev_priv = dev->dev_private;
  6723. if (dev_priv->renderctx == NULL)
  6724. dev_priv->renderctx = intel_alloc_context_page(dev);
  6725. if (!dev_priv->renderctx)
  6726. return -ENOMEM;
  6727. if (dev_priv->pwrctx == NULL)
  6728. dev_priv->pwrctx = intel_alloc_context_page(dev);
  6729. if (!dev_priv->pwrctx) {
  6730. ironlake_teardown_rc6(dev);
  6731. return -ENOMEM;
  6732. }
  6733. return 0;
  6734. }
  6735. void ironlake_enable_rc6(struct drm_device *dev)
  6736. {
  6737. struct drm_i915_private *dev_priv = dev->dev_private;
  6738. int ret;
  6739. /* rc6 disabled by default due to repeated reports of hanging during
  6740. * boot and resume.
  6741. */
  6742. if (!i915_enable_rc6)
  6743. return;
  6744. mutex_lock(&dev->struct_mutex);
  6745. ret = ironlake_setup_rc6(dev);
  6746. if (ret) {
  6747. mutex_unlock(&dev->struct_mutex);
  6748. return;
  6749. }
  6750. /*
  6751. * GPU can automatically power down the render unit if given a page
  6752. * to save state.
  6753. */
  6754. ret = BEGIN_LP_RING(6);
  6755. if (ret) {
  6756. ironlake_teardown_rc6(dev);
  6757. mutex_unlock(&dev->struct_mutex);
  6758. return;
  6759. }
  6760. OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  6761. OUT_RING(MI_SET_CONTEXT);
  6762. OUT_RING(dev_priv->renderctx->gtt_offset |
  6763. MI_MM_SPACE_GTT |
  6764. MI_SAVE_EXT_STATE_EN |
  6765. MI_RESTORE_EXT_STATE_EN |
  6766. MI_RESTORE_INHIBIT);
  6767. OUT_RING(MI_SUSPEND_FLUSH);
  6768. OUT_RING(MI_NOOP);
  6769. OUT_RING(MI_FLUSH);
  6770. ADVANCE_LP_RING();
  6771. /*
  6772. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  6773. * does an implicit flush, combined with MI_FLUSH above, it should be
  6774. * safe to assume that renderctx is valid
  6775. */
  6776. ret = intel_wait_ring_idle(LP_RING(dev_priv));
  6777. if (ret) {
  6778. DRM_ERROR("failed to enable ironlake power power savings\n");
  6779. ironlake_teardown_rc6(dev);
  6780. mutex_unlock(&dev->struct_mutex);
  6781. return;
  6782. }
  6783. I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
  6784. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  6785. mutex_unlock(&dev->struct_mutex);
  6786. }
  6787. void intel_init_clock_gating(struct drm_device *dev)
  6788. {
  6789. struct drm_i915_private *dev_priv = dev->dev_private;
  6790. dev_priv->display.init_clock_gating(dev);
  6791. if (dev_priv->display.init_pch_clock_gating)
  6792. dev_priv->display.init_pch_clock_gating(dev);
  6793. }
  6794. /* Set up chip specific display functions */
  6795. static void intel_init_display(struct drm_device *dev)
  6796. {
  6797. struct drm_i915_private *dev_priv = dev->dev_private;
  6798. /* We always want a DPMS function */
  6799. if (HAS_PCH_SPLIT(dev)) {
  6800. dev_priv->display.dpms = ironlake_crtc_dpms;
  6801. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  6802. dev_priv->display.update_plane = ironlake_update_plane;
  6803. } else {
  6804. dev_priv->display.dpms = i9xx_crtc_dpms;
  6805. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  6806. dev_priv->display.update_plane = i9xx_update_plane;
  6807. }
  6808. if (I915_HAS_FBC(dev)) {
  6809. if (HAS_PCH_SPLIT(dev)) {
  6810. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  6811. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  6812. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  6813. } else if (IS_GM45(dev)) {
  6814. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  6815. dev_priv->display.enable_fbc = g4x_enable_fbc;
  6816. dev_priv->display.disable_fbc = g4x_disable_fbc;
  6817. } else if (IS_CRESTLINE(dev)) {
  6818. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  6819. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  6820. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  6821. }
  6822. /* 855GM needs testing */
  6823. }
  6824. /* Returns the core display clock speed */
  6825. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  6826. dev_priv->display.get_display_clock_speed =
  6827. i945_get_display_clock_speed;
  6828. else if (IS_I915G(dev))
  6829. dev_priv->display.get_display_clock_speed =
  6830. i915_get_display_clock_speed;
  6831. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  6832. dev_priv->display.get_display_clock_speed =
  6833. i9xx_misc_get_display_clock_speed;
  6834. else if (IS_I915GM(dev))
  6835. dev_priv->display.get_display_clock_speed =
  6836. i915gm_get_display_clock_speed;
  6837. else if (IS_I865G(dev))
  6838. dev_priv->display.get_display_clock_speed =
  6839. i865_get_display_clock_speed;
  6840. else if (IS_I85X(dev))
  6841. dev_priv->display.get_display_clock_speed =
  6842. i855_get_display_clock_speed;
  6843. else /* 852, 830 */
  6844. dev_priv->display.get_display_clock_speed =
  6845. i830_get_display_clock_speed;
  6846. /* For FIFO watermark updates */
  6847. if (HAS_PCH_SPLIT(dev)) {
  6848. if (HAS_PCH_IBX(dev))
  6849. dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
  6850. else if (HAS_PCH_CPT(dev))
  6851. dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
  6852. if (IS_GEN5(dev)) {
  6853. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  6854. dev_priv->display.update_wm = ironlake_update_wm;
  6855. else {
  6856. DRM_DEBUG_KMS("Failed to get proper latency. "
  6857. "Disable CxSR\n");
  6858. dev_priv->display.update_wm = NULL;
  6859. }
  6860. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  6861. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  6862. } else if (IS_GEN6(dev)) {
  6863. if (SNB_READ_WM0_LATENCY()) {
  6864. dev_priv->display.update_wm = sandybridge_update_wm;
  6865. } else {
  6866. DRM_DEBUG_KMS("Failed to read display plane latency. "
  6867. "Disable CxSR\n");
  6868. dev_priv->display.update_wm = NULL;
  6869. }
  6870. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  6871. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  6872. } else if (IS_IVYBRIDGE(dev)) {
  6873. /* FIXME: detect B0+ stepping and use auto training */
  6874. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  6875. if (SNB_READ_WM0_LATENCY()) {
  6876. dev_priv->display.update_wm = sandybridge_update_wm;
  6877. } else {
  6878. DRM_DEBUG_KMS("Failed to read display plane latency. "
  6879. "Disable CxSR\n");
  6880. dev_priv->display.update_wm = NULL;
  6881. }
  6882. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  6883. } else
  6884. dev_priv->display.update_wm = NULL;
  6885. } else if (IS_PINEVIEW(dev)) {
  6886. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  6887. dev_priv->is_ddr3,
  6888. dev_priv->fsb_freq,
  6889. dev_priv->mem_freq)) {
  6890. DRM_INFO("failed to find known CxSR latency "
  6891. "(found ddr%s fsb freq %d, mem freq %d), "
  6892. "disabling CxSR\n",
  6893. (dev_priv->is_ddr3 == 1) ? "3": "2",
  6894. dev_priv->fsb_freq, dev_priv->mem_freq);
  6895. /* Disable CxSR and never update its watermark again */
  6896. pineview_disable_cxsr(dev);
  6897. dev_priv->display.update_wm = NULL;
  6898. } else
  6899. dev_priv->display.update_wm = pineview_update_wm;
  6900. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  6901. } else if (IS_G4X(dev)) {
  6902. dev_priv->display.update_wm = g4x_update_wm;
  6903. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  6904. } else if (IS_GEN4(dev)) {
  6905. dev_priv->display.update_wm = i965_update_wm;
  6906. if (IS_CRESTLINE(dev))
  6907. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  6908. else if (IS_BROADWATER(dev))
  6909. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  6910. } else if (IS_GEN3(dev)) {
  6911. dev_priv->display.update_wm = i9xx_update_wm;
  6912. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  6913. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  6914. } else if (IS_I865G(dev)) {
  6915. dev_priv->display.update_wm = i830_update_wm;
  6916. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  6917. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  6918. } else if (IS_I85X(dev)) {
  6919. dev_priv->display.update_wm = i9xx_update_wm;
  6920. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  6921. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  6922. } else {
  6923. dev_priv->display.update_wm = i830_update_wm;
  6924. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  6925. if (IS_845G(dev))
  6926. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  6927. else
  6928. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  6929. }
  6930. /* Default just returns -ENODEV to indicate unsupported */
  6931. dev_priv->display.queue_flip = intel_default_queue_flip;
  6932. switch (INTEL_INFO(dev)->gen) {
  6933. case 2:
  6934. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  6935. break;
  6936. case 3:
  6937. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  6938. break;
  6939. case 4:
  6940. case 5:
  6941. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  6942. break;
  6943. case 6:
  6944. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  6945. break;
  6946. case 7:
  6947. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  6948. break;
  6949. }
  6950. }
  6951. /*
  6952. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  6953. * resume, or other times. This quirk makes sure that's the case for
  6954. * affected systems.
  6955. */
  6956. static void quirk_pipea_force (struct drm_device *dev)
  6957. {
  6958. struct drm_i915_private *dev_priv = dev->dev_private;
  6959. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  6960. DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
  6961. }
  6962. /*
  6963. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  6964. */
  6965. static void quirk_ssc_force_disable(struct drm_device *dev)
  6966. {
  6967. struct drm_i915_private *dev_priv = dev->dev_private;
  6968. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  6969. }
  6970. struct intel_quirk {
  6971. int device;
  6972. int subsystem_vendor;
  6973. int subsystem_device;
  6974. void (*hook)(struct drm_device *dev);
  6975. };
  6976. struct intel_quirk intel_quirks[] = {
  6977. /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
  6978. { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
  6979. /* HP Mini needs pipe A force quirk (LP: #322104) */
  6980. { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
  6981. /* Thinkpad R31 needs pipe A force quirk */
  6982. { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
  6983. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  6984. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  6985. /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
  6986. { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
  6987. /* ThinkPad X40 needs pipe A force quirk */
  6988. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  6989. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  6990. /* 855 & before need to leave pipe A & dpll A up */
  6991. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6992. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6993. /* Lenovo U160 cannot use SSC on LVDS */
  6994. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  6995. };
  6996. static void intel_init_quirks(struct drm_device *dev)
  6997. {
  6998. struct pci_dev *d = dev->pdev;
  6999. int i;
  7000. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  7001. struct intel_quirk *q = &intel_quirks[i];
  7002. if (d->device == q->device &&
  7003. (d->subsystem_vendor == q->subsystem_vendor ||
  7004. q->subsystem_vendor == PCI_ANY_ID) &&
  7005. (d->subsystem_device == q->subsystem_device ||
  7006. q->subsystem_device == PCI_ANY_ID))
  7007. q->hook(dev);
  7008. }
  7009. }
  7010. /* Disable the VGA plane that we never use */
  7011. static void i915_disable_vga(struct drm_device *dev)
  7012. {
  7013. struct drm_i915_private *dev_priv = dev->dev_private;
  7014. u8 sr1;
  7015. u32 vga_reg;
  7016. if (HAS_PCH_SPLIT(dev))
  7017. vga_reg = CPU_VGACNTRL;
  7018. else
  7019. vga_reg = VGACNTRL;
  7020. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  7021. outb(1, VGA_SR_INDEX);
  7022. sr1 = inb(VGA_SR_DATA);
  7023. outb(sr1 | 1<<5, VGA_SR_DATA);
  7024. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  7025. udelay(300);
  7026. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  7027. POSTING_READ(vga_reg);
  7028. }
  7029. void intel_modeset_init(struct drm_device *dev)
  7030. {
  7031. struct drm_i915_private *dev_priv = dev->dev_private;
  7032. int i;
  7033. drm_mode_config_init(dev);
  7034. dev->mode_config.min_width = 0;
  7035. dev->mode_config.min_height = 0;
  7036. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  7037. intel_init_quirks(dev);
  7038. intel_init_display(dev);
  7039. if (IS_GEN2(dev)) {
  7040. dev->mode_config.max_width = 2048;
  7041. dev->mode_config.max_height = 2048;
  7042. } else if (IS_GEN3(dev)) {
  7043. dev->mode_config.max_width = 4096;
  7044. dev->mode_config.max_height = 4096;
  7045. } else {
  7046. dev->mode_config.max_width = 8192;
  7047. dev->mode_config.max_height = 8192;
  7048. }
  7049. dev->mode_config.fb_base = dev->agp->base;
  7050. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  7051. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  7052. for (i = 0; i < dev_priv->num_pipe; i++) {
  7053. intel_crtc_init(dev, i);
  7054. }
  7055. /* Just disable it once at startup */
  7056. i915_disable_vga(dev);
  7057. intel_setup_outputs(dev);
  7058. intel_init_clock_gating(dev);
  7059. if (IS_IRONLAKE_M(dev)) {
  7060. ironlake_enable_drps(dev);
  7061. intel_init_emon(dev);
  7062. }
  7063. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  7064. gen6_enable_rps(dev_priv);
  7065. gen6_update_ring_freq(dev_priv);
  7066. }
  7067. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  7068. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  7069. (unsigned long)dev);
  7070. }
  7071. void intel_modeset_gem_init(struct drm_device *dev)
  7072. {
  7073. if (IS_IRONLAKE_M(dev))
  7074. ironlake_enable_rc6(dev);
  7075. intel_setup_overlay(dev);
  7076. }
  7077. void intel_modeset_cleanup(struct drm_device *dev)
  7078. {
  7079. struct drm_i915_private *dev_priv = dev->dev_private;
  7080. struct drm_crtc *crtc;
  7081. struct intel_crtc *intel_crtc;
  7082. drm_kms_helper_poll_fini(dev);
  7083. mutex_lock(&dev->struct_mutex);
  7084. intel_unregister_dsm_handler();
  7085. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7086. /* Skip inactive CRTCs */
  7087. if (!crtc->fb)
  7088. continue;
  7089. intel_crtc = to_intel_crtc(crtc);
  7090. intel_increase_pllclock(crtc);
  7091. }
  7092. intel_disable_fbc(dev);
  7093. if (IS_IRONLAKE_M(dev))
  7094. ironlake_disable_drps(dev);
  7095. if (IS_GEN6(dev) || IS_GEN7(dev))
  7096. gen6_disable_rps(dev);
  7097. if (IS_IRONLAKE_M(dev))
  7098. ironlake_disable_rc6(dev);
  7099. mutex_unlock(&dev->struct_mutex);
  7100. /* Disable the irq before mode object teardown, for the irq might
  7101. * enqueue unpin/hotplug work. */
  7102. drm_irq_uninstall(dev);
  7103. cancel_work_sync(&dev_priv->hotplug_work);
  7104. /* flush any delayed tasks or pending work */
  7105. flush_scheduled_work();
  7106. /* Shut off idle work before the crtcs get freed. */
  7107. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7108. intel_crtc = to_intel_crtc(crtc);
  7109. del_timer_sync(&intel_crtc->idle_timer);
  7110. }
  7111. del_timer_sync(&dev_priv->idle_timer);
  7112. cancel_work_sync(&dev_priv->idle_work);
  7113. drm_mode_config_cleanup(dev);
  7114. }
  7115. /*
  7116. * Return which encoder is currently attached for connector.
  7117. */
  7118. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  7119. {
  7120. return &intel_attached_encoder(connector)->base;
  7121. }
  7122. void intel_connector_attach_encoder(struct intel_connector *connector,
  7123. struct intel_encoder *encoder)
  7124. {
  7125. connector->encoder = encoder;
  7126. drm_mode_connector_attach_encoder(&connector->base,
  7127. &encoder->base);
  7128. }
  7129. /*
  7130. * set vga decode state - true == enable VGA decode
  7131. */
  7132. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  7133. {
  7134. struct drm_i915_private *dev_priv = dev->dev_private;
  7135. u16 gmch_ctrl;
  7136. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  7137. if (state)
  7138. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  7139. else
  7140. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  7141. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  7142. return 0;
  7143. }
  7144. #ifdef CONFIG_DEBUG_FS
  7145. #include <linux/seq_file.h>
  7146. struct intel_display_error_state {
  7147. struct intel_cursor_error_state {
  7148. u32 control;
  7149. u32 position;
  7150. u32 base;
  7151. u32 size;
  7152. } cursor[2];
  7153. struct intel_pipe_error_state {
  7154. u32 conf;
  7155. u32 source;
  7156. u32 htotal;
  7157. u32 hblank;
  7158. u32 hsync;
  7159. u32 vtotal;
  7160. u32 vblank;
  7161. u32 vsync;
  7162. } pipe[2];
  7163. struct intel_plane_error_state {
  7164. u32 control;
  7165. u32 stride;
  7166. u32 size;
  7167. u32 pos;
  7168. u32 addr;
  7169. u32 surface;
  7170. u32 tile_offset;
  7171. } plane[2];
  7172. };
  7173. struct intel_display_error_state *
  7174. intel_display_capture_error_state(struct drm_device *dev)
  7175. {
  7176. drm_i915_private_t *dev_priv = dev->dev_private;
  7177. struct intel_display_error_state *error;
  7178. int i;
  7179. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  7180. if (error == NULL)
  7181. return NULL;
  7182. for (i = 0; i < 2; i++) {
  7183. error->cursor[i].control = I915_READ(CURCNTR(i));
  7184. error->cursor[i].position = I915_READ(CURPOS(i));
  7185. error->cursor[i].base = I915_READ(CURBASE(i));
  7186. error->plane[i].control = I915_READ(DSPCNTR(i));
  7187. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  7188. error->plane[i].size = I915_READ(DSPSIZE(i));
  7189. error->plane[i].pos= I915_READ(DSPPOS(i));
  7190. error->plane[i].addr = I915_READ(DSPADDR(i));
  7191. if (INTEL_INFO(dev)->gen >= 4) {
  7192. error->plane[i].surface = I915_READ(DSPSURF(i));
  7193. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  7194. }
  7195. error->pipe[i].conf = I915_READ(PIPECONF(i));
  7196. error->pipe[i].source = I915_READ(PIPESRC(i));
  7197. error->pipe[i].htotal = I915_READ(HTOTAL(i));
  7198. error->pipe[i].hblank = I915_READ(HBLANK(i));
  7199. error->pipe[i].hsync = I915_READ(HSYNC(i));
  7200. error->pipe[i].vtotal = I915_READ(VTOTAL(i));
  7201. error->pipe[i].vblank = I915_READ(VBLANK(i));
  7202. error->pipe[i].vsync = I915_READ(VSYNC(i));
  7203. }
  7204. return error;
  7205. }
  7206. void
  7207. intel_display_print_error_state(struct seq_file *m,
  7208. struct drm_device *dev,
  7209. struct intel_display_error_state *error)
  7210. {
  7211. int i;
  7212. for (i = 0; i < 2; i++) {
  7213. seq_printf(m, "Pipe [%d]:\n", i);
  7214. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  7215. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  7216. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  7217. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  7218. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  7219. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  7220. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  7221. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  7222. seq_printf(m, "Plane [%d]:\n", i);
  7223. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  7224. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  7225. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  7226. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  7227. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  7228. if (INTEL_INFO(dev)->gen >= 4) {
  7229. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  7230. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  7231. }
  7232. seq_printf(m, "Cursor [%d]:\n", i);
  7233. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  7234. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  7235. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  7236. }
  7237. }
  7238. #endif