adc.c 12 KB

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  1. /* arch/arm/plat-samsung/adc.c
  2. *
  3. * Copyright (c) 2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
  6. *
  7. * Samsung ADC device core
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/sched.h>
  17. #include <linux/list.h>
  18. #include <linux/slab.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <plat/regs-adc.h>
  25. #include <plat/adc.h>
  26. /* This driver is designed to control the usage of the ADC block between
  27. * the touchscreen and any other drivers that may need to use it, such as
  28. * the hwmon driver.
  29. *
  30. * Priority will be given to the touchscreen driver, but as this itself is
  31. * rate limited it should not starve other requests which are processed in
  32. * order that they are received.
  33. *
  34. * Each user registers to get a client block which uniquely identifies it
  35. * and stores information such as the necessary functions to callback when
  36. * action is required.
  37. */
  38. enum s3c_cpu_type {
  39. TYPE_ADCV1, /* S3C24XX */
  40. TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
  41. TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
  42. };
  43. struct s3c_adc_client {
  44. struct platform_device *pdev;
  45. struct list_head pend;
  46. wait_queue_head_t *wait;
  47. unsigned int nr_samples;
  48. int result;
  49. unsigned char is_ts;
  50. unsigned char channel;
  51. void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
  52. void (*convert_cb)(struct s3c_adc_client *c,
  53. unsigned val1, unsigned val2,
  54. unsigned *samples_left);
  55. };
  56. struct adc_device {
  57. struct platform_device *pdev;
  58. struct platform_device *owner;
  59. struct clk *clk;
  60. struct s3c_adc_client *cur;
  61. struct s3c_adc_client *ts_pend;
  62. void __iomem *regs;
  63. spinlock_t lock;
  64. unsigned int prescale;
  65. int irq;
  66. struct regulator *vdd;
  67. };
  68. static struct adc_device *adc_dev;
  69. static LIST_HEAD(adc_pending); /* protected by adc_device.lock */
  70. #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
  71. static inline void s3c_adc_convert(struct adc_device *adc)
  72. {
  73. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  74. con |= S3C2410_ADCCON_ENABLE_START;
  75. writel(con, adc->regs + S3C2410_ADCCON);
  76. }
  77. static inline void s3c_adc_select(struct adc_device *adc,
  78. struct s3c_adc_client *client)
  79. {
  80. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  81. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  82. client->select_cb(client, 1);
  83. if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
  84. con &= ~S3C2410_ADCCON_MUXMASK;
  85. con &= ~S3C2410_ADCCON_STDBM;
  86. con &= ~S3C2410_ADCCON_STARTMASK;
  87. if (!client->is_ts) {
  88. if (cpu == TYPE_ADCV3)
  89. writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
  90. else
  91. con |= S3C2410_ADCCON_SELMUX(client->channel);
  92. }
  93. writel(con, adc->regs + S3C2410_ADCCON);
  94. }
  95. static void s3c_adc_dbgshow(struct adc_device *adc)
  96. {
  97. adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
  98. readl(adc->regs + S3C2410_ADCCON),
  99. readl(adc->regs + S3C2410_ADCTSC),
  100. readl(adc->regs + S3C2410_ADCDLY));
  101. }
  102. static void s3c_adc_try(struct adc_device *adc)
  103. {
  104. struct s3c_adc_client *next = adc->ts_pend;
  105. if (!next && !list_empty(&adc_pending)) {
  106. next = list_first_entry(&adc_pending,
  107. struct s3c_adc_client, pend);
  108. list_del(&next->pend);
  109. } else
  110. adc->ts_pend = NULL;
  111. if (next) {
  112. adc_dbg(adc, "new client is %p\n", next);
  113. adc->cur = next;
  114. s3c_adc_select(adc, next);
  115. s3c_adc_convert(adc);
  116. s3c_adc_dbgshow(adc);
  117. }
  118. }
  119. int s3c_adc_start(struct s3c_adc_client *client,
  120. unsigned int channel, unsigned int nr_samples)
  121. {
  122. struct adc_device *adc = adc_dev;
  123. unsigned long flags;
  124. if (!adc) {
  125. printk(KERN_ERR "%s: failed to find adc\n", __func__);
  126. return -EINVAL;
  127. }
  128. if (client->is_ts && adc->ts_pend)
  129. return -EAGAIN;
  130. spin_lock_irqsave(&adc->lock, flags);
  131. client->channel = channel;
  132. client->nr_samples = nr_samples;
  133. if (client->is_ts)
  134. adc->ts_pend = client;
  135. else
  136. list_add_tail(&client->pend, &adc_pending);
  137. if (!adc->cur)
  138. s3c_adc_try(adc);
  139. spin_unlock_irqrestore(&adc->lock, flags);
  140. return 0;
  141. }
  142. EXPORT_SYMBOL_GPL(s3c_adc_start);
  143. static void s3c_convert_done(struct s3c_adc_client *client,
  144. unsigned v, unsigned u, unsigned *left)
  145. {
  146. client->result = v;
  147. wake_up(client->wait);
  148. }
  149. int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
  150. {
  151. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
  152. int ret;
  153. client->convert_cb = s3c_convert_done;
  154. client->wait = &wake;
  155. client->result = -1;
  156. ret = s3c_adc_start(client, ch, 1);
  157. if (ret < 0)
  158. goto err;
  159. ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
  160. if (client->result < 0) {
  161. ret = -ETIMEDOUT;
  162. goto err;
  163. }
  164. client->convert_cb = NULL;
  165. return client->result;
  166. err:
  167. return ret;
  168. }
  169. EXPORT_SYMBOL_GPL(s3c_adc_read);
  170. static void s3c_adc_default_select(struct s3c_adc_client *client,
  171. unsigned select)
  172. {
  173. }
  174. struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
  175. void (*select)(struct s3c_adc_client *client,
  176. unsigned int selected),
  177. void (*conv)(struct s3c_adc_client *client,
  178. unsigned d0, unsigned d1,
  179. unsigned *samples_left),
  180. unsigned int is_ts)
  181. {
  182. struct s3c_adc_client *client;
  183. WARN_ON(!pdev);
  184. if (!select)
  185. select = s3c_adc_default_select;
  186. if (!pdev)
  187. return ERR_PTR(-EINVAL);
  188. client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
  189. if (!client) {
  190. dev_err(&pdev->dev, "no memory for adc client\n");
  191. return ERR_PTR(-ENOMEM);
  192. }
  193. client->pdev = pdev;
  194. client->is_ts = is_ts;
  195. client->select_cb = select;
  196. client->convert_cb = conv;
  197. return client;
  198. }
  199. EXPORT_SYMBOL_GPL(s3c_adc_register);
  200. void s3c_adc_release(struct s3c_adc_client *client)
  201. {
  202. unsigned long flags;
  203. spin_lock_irqsave(&adc_dev->lock, flags);
  204. /* We should really check that nothing is in progress. */
  205. if (adc_dev->cur == client)
  206. adc_dev->cur = NULL;
  207. if (adc_dev->ts_pend == client)
  208. adc_dev->ts_pend = NULL;
  209. else {
  210. struct list_head *p, *n;
  211. struct s3c_adc_client *tmp;
  212. list_for_each_safe(p, n, &adc_pending) {
  213. tmp = list_entry(p, struct s3c_adc_client, pend);
  214. if (tmp == client)
  215. list_del(&tmp->pend);
  216. }
  217. }
  218. if (adc_dev->cur == NULL)
  219. s3c_adc_try(adc_dev);
  220. spin_unlock_irqrestore(&adc_dev->lock, flags);
  221. kfree(client);
  222. }
  223. EXPORT_SYMBOL_GPL(s3c_adc_release);
  224. static irqreturn_t s3c_adc_irq(int irq, void *pw)
  225. {
  226. struct adc_device *adc = pw;
  227. struct s3c_adc_client *client = adc->cur;
  228. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  229. unsigned data0, data1;
  230. if (!client) {
  231. dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
  232. goto exit;
  233. }
  234. data0 = readl(adc->regs + S3C2410_ADCDAT0);
  235. data1 = readl(adc->regs + S3C2410_ADCDAT1);
  236. adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
  237. client->nr_samples--;
  238. if (cpu != TYPE_ADCV1) {
  239. /* S3C64XX/S5P ADC resolution is 12-bit */
  240. data0 &= 0xfff;
  241. data1 &= 0xfff;
  242. } else {
  243. data0 &= 0x3ff;
  244. data1 &= 0x3ff;
  245. }
  246. if (client->convert_cb)
  247. (client->convert_cb)(client, data0, data1, &client->nr_samples);
  248. if (client->nr_samples > 0) {
  249. /* fire another conversion for this */
  250. client->select_cb(client, 1);
  251. s3c_adc_convert(adc);
  252. } else {
  253. spin_lock(&adc->lock);
  254. (client->select_cb)(client, 0);
  255. adc->cur = NULL;
  256. s3c_adc_try(adc);
  257. spin_unlock(&adc->lock);
  258. }
  259. exit:
  260. if (cpu != TYPE_ADCV1) {
  261. /* Clear ADC interrupt */
  262. writel(0, adc->regs + S3C64XX_ADCCLRINT);
  263. }
  264. return IRQ_HANDLED;
  265. }
  266. static int s3c_adc_probe(struct platform_device *pdev)
  267. {
  268. struct device *dev = &pdev->dev;
  269. struct adc_device *adc;
  270. struct resource *regs;
  271. int ret;
  272. unsigned tmp;
  273. adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
  274. if (adc == NULL) {
  275. dev_err(dev, "failed to allocate adc_device\n");
  276. return -ENOMEM;
  277. }
  278. spin_lock_init(&adc->lock);
  279. adc->pdev = pdev;
  280. adc->prescale = S3C2410_ADCCON_PRSCVL(49);
  281. adc->vdd = regulator_get(dev, "vdd");
  282. if (IS_ERR(adc->vdd)) {
  283. dev_err(dev, "operating without regulator \"vdd\" .\n");
  284. ret = PTR_ERR(adc->vdd);
  285. goto err_alloc;
  286. }
  287. adc->irq = platform_get_irq(pdev, 1);
  288. if (adc->irq <= 0) {
  289. dev_err(dev, "failed to get adc irq\n");
  290. ret = -ENOENT;
  291. goto err_reg;
  292. }
  293. ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
  294. if (ret < 0) {
  295. dev_err(dev, "failed to attach adc irq\n");
  296. goto err_reg;
  297. }
  298. adc->clk = clk_get(dev, "adc");
  299. if (IS_ERR(adc->clk)) {
  300. dev_err(dev, "failed to get adc clock\n");
  301. ret = PTR_ERR(adc->clk);
  302. goto err_irq;
  303. }
  304. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  305. if (!regs) {
  306. dev_err(dev, "failed to find registers\n");
  307. ret = -ENXIO;
  308. goto err_clk;
  309. }
  310. adc->regs = ioremap(regs->start, resource_size(regs));
  311. if (!adc->regs) {
  312. dev_err(dev, "failed to map registers\n");
  313. ret = -ENXIO;
  314. goto err_clk;
  315. }
  316. ret = regulator_enable(adc->vdd);
  317. if (ret)
  318. goto err_ioremap;
  319. clk_enable(adc->clk);
  320. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  321. if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
  322. /* Enable 12-bit ADC resolution */
  323. tmp |= S3C64XX_ADCCON_RESSEL;
  324. }
  325. writel(tmp, adc->regs + S3C2410_ADCCON);
  326. dev_info(dev, "attached adc driver\n");
  327. platform_set_drvdata(pdev, adc);
  328. adc_dev = adc;
  329. return 0;
  330. err_ioremap:
  331. iounmap(adc->regs);
  332. err_clk:
  333. clk_put(adc->clk);
  334. err_irq:
  335. free_irq(adc->irq, adc);
  336. err_reg:
  337. regulator_put(adc->vdd);
  338. err_alloc:
  339. kfree(adc);
  340. return ret;
  341. }
  342. static int __devexit s3c_adc_remove(struct platform_device *pdev)
  343. {
  344. struct adc_device *adc = platform_get_drvdata(pdev);
  345. iounmap(adc->regs);
  346. free_irq(adc->irq, adc);
  347. clk_disable(adc->clk);
  348. regulator_disable(adc->vdd);
  349. regulator_put(adc->vdd);
  350. clk_put(adc->clk);
  351. kfree(adc);
  352. return 0;
  353. }
  354. #ifdef CONFIG_PM
  355. static int s3c_adc_suspend(struct device *dev)
  356. {
  357. struct platform_device *pdev = container_of(dev,
  358. struct platform_device, dev);
  359. struct adc_device *adc = platform_get_drvdata(pdev);
  360. unsigned long flags;
  361. u32 con;
  362. spin_lock_irqsave(&adc->lock, flags);
  363. con = readl(adc->regs + S3C2410_ADCCON);
  364. con |= S3C2410_ADCCON_STDBM;
  365. writel(con, adc->regs + S3C2410_ADCCON);
  366. disable_irq(adc->irq);
  367. spin_unlock_irqrestore(&adc->lock, flags);
  368. clk_disable(adc->clk);
  369. regulator_disable(adc->vdd);
  370. return 0;
  371. }
  372. static int s3c_adc_resume(struct device *dev)
  373. {
  374. struct platform_device *pdev = container_of(dev,
  375. struct platform_device, dev);
  376. struct adc_device *adc = platform_get_drvdata(pdev);
  377. int ret;
  378. unsigned long tmp;
  379. ret = regulator_enable(adc->vdd);
  380. if (ret)
  381. return ret;
  382. clk_enable(adc->clk);
  383. enable_irq(adc->irq);
  384. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  385. /* Enable 12-bit ADC resolution */
  386. if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
  387. tmp |= S3C64XX_ADCCON_RESSEL;
  388. writel(tmp, adc->regs + S3C2410_ADCCON);
  389. return 0;
  390. }
  391. #else
  392. #define s3c_adc_suspend NULL
  393. #define s3c_adc_resume NULL
  394. #endif
  395. static struct platform_device_id s3c_adc_driver_ids[] = {
  396. {
  397. .name = "s3c24xx-adc",
  398. .driver_data = TYPE_ADCV1,
  399. }, {
  400. .name = "s3c64xx-adc",
  401. .driver_data = TYPE_ADCV2,
  402. }, {
  403. .name = "samsung-adc-v3",
  404. .driver_data = TYPE_ADCV3,
  405. },
  406. { }
  407. };
  408. MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
  409. static const struct dev_pm_ops adc_pm_ops = {
  410. .suspend = s3c_adc_suspend,
  411. .resume = s3c_adc_resume,
  412. };
  413. static struct platform_driver s3c_adc_driver = {
  414. .id_table = s3c_adc_driver_ids,
  415. .driver = {
  416. .name = "s3c-adc",
  417. .owner = THIS_MODULE,
  418. .pm = &adc_pm_ops,
  419. },
  420. .probe = s3c_adc_probe,
  421. .remove = __devexit_p(s3c_adc_remove),
  422. };
  423. static int __init adc_init(void)
  424. {
  425. int ret;
  426. ret = platform_driver_register(&s3c_adc_driver);
  427. if (ret)
  428. printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
  429. return ret;
  430. }
  431. module_init(adc_init);