dma-s3c2443.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179
  1. /* linux/arch/arm/mach-s3c2443/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2443 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-dma.h>
  25. #include <mach/regs-lcd.h>
  26. #include <mach/regs-sdi.h>
  27. #include <plat/regs-spi.h>
  28. #define MAP(x) { \
  29. [0] = (x) | DMA_CH_VALID, \
  30. [1] = (x) | DMA_CH_VALID, \
  31. [2] = (x) | DMA_CH_VALID, \
  32. [3] = (x) | DMA_CH_VALID, \
  33. [4] = (x) | DMA_CH_VALID, \
  34. [5] = (x) | DMA_CH_VALID, \
  35. }
  36. static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
  37. [DMACH_XD0] = {
  38. .name = "xdreq0",
  39. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  40. },
  41. [DMACH_XD1] = {
  42. .name = "xdreq1",
  43. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  44. },
  45. [DMACH_SDI] = { /* only on S3C2443 */
  46. .name = "sdi",
  47. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  48. },
  49. [DMACH_SPI0_RX] = {
  50. .name = "spi0-rx",
  51. .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
  52. },
  53. [DMACH_SPI0_TX] = {
  54. .name = "spi0-tx",
  55. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  56. },
  57. [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
  58. .name = "spi1-rx",
  59. .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
  60. },
  61. [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
  62. .name = "spi1-tx",
  63. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  64. },
  65. [DMACH_UART0] = {
  66. .name = "uart0",
  67. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  68. },
  69. [DMACH_UART1] = {
  70. .name = "uart1",
  71. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  72. },
  73. [DMACH_UART2] = {
  74. .name = "uart2",
  75. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  76. },
  77. [DMACH_UART3] = {
  78. .name = "uart3",
  79. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  80. },
  81. [DMACH_UART0_SRC2] = {
  82. .name = "uart0",
  83. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  84. },
  85. [DMACH_UART1_SRC2] = {
  86. .name = "uart1",
  87. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  88. },
  89. [DMACH_UART2_SRC2] = {
  90. .name = "uart2",
  91. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  92. },
  93. [DMACH_UART3_SRC2] = {
  94. .name = "uart3",
  95. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  96. },
  97. [DMACH_TIMER] = {
  98. .name = "timer",
  99. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  100. },
  101. [DMACH_I2S_IN] = {
  102. .name = "i2s-sdi",
  103. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  104. },
  105. [DMACH_I2S_OUT] = {
  106. .name = "i2s-sdo",
  107. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  108. },
  109. [DMACH_PCM_IN] = {
  110. .name = "pcm-in",
  111. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  112. },
  113. [DMACH_PCM_OUT] = {
  114. .name = "pcm-out",
  115. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  116. },
  117. [DMACH_MIC_IN] = {
  118. .name = "mic-in",
  119. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  120. },
  121. };
  122. static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
  123. struct s3c24xx_dma_map *map)
  124. {
  125. writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
  126. chan->regs + S3C2443_DMA_DMAREQSEL);
  127. }
  128. static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
  129. .select = s3c2443_dma_select,
  130. .dcon_mask = 0,
  131. .map = s3c2443_dma_mappings,
  132. .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
  133. };
  134. static int __init s3c2443_dma_add(struct device *dev,
  135. struct subsys_interface *sif)
  136. {
  137. s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
  138. return s3c24xx_dma_init_map(&s3c2443_dma_sel);
  139. }
  140. #ifdef CONFIG_CPU_S3C2416
  141. /* S3C2416 DMA contains the same selection table as the S3C2443 */
  142. static struct subsys_interface s3c2416_dma_interface = {
  143. .name = "s3c2416_dma",
  144. .subsys = &s3c2416_subsys,
  145. .add_dev = s3c2443_dma_add,
  146. };
  147. static int __init s3c2416_dma_init(void)
  148. {
  149. return subsys_interface_register(&s3c2416_dma_interface);
  150. }
  151. arch_initcall(s3c2416_dma_init);
  152. #endif
  153. #ifdef CONFIG_CPU_S3C2443
  154. static struct subsys_interface s3c2443_dma_interface = {
  155. .name = "s3c2443_dma",
  156. .subsys = &s3c2443_subsys,
  157. .add_dev = s3c2443_dma_add,
  158. };
  159. static int __init s3c2443_dma_init(void)
  160. {
  161. return subsys_interface_register(&s3c2443_dma_interface);
  162. }
  163. arch_initcall(s3c2443_dma_init);
  164. #endif