dma-s3c2440.c 4.7 KB

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  1. /* linux/arch/arm/mach-s3c2440/dma.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2440 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_core.h>
  18. #include <mach/map.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-dma.h>
  25. #include <mach/regs-lcd.h>
  26. #include <mach/regs-sdi.h>
  27. #include <plat/regs-spi.h>
  28. static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  29. [DMACH_XD0] = {
  30. .name = "xdreq0",
  31. .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  32. },
  33. [DMACH_XD1] = {
  34. .name = "xdreq1",
  35. .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  36. },
  37. [DMACH_SDI] = {
  38. .name = "sdi",
  39. .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  40. .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  41. .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  42. .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  43. },
  44. [DMACH_SPI0] = {
  45. .name = "spi0",
  46. .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  47. },
  48. [DMACH_SPI1] = {
  49. .name = "spi1",
  50. .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  51. },
  52. [DMACH_UART0] = {
  53. .name = "uart0",
  54. .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  55. },
  56. [DMACH_UART1] = {
  57. .name = "uart1",
  58. .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  59. },
  60. [DMACH_UART2] = {
  61. .name = "uart2",
  62. .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  63. },
  64. [DMACH_TIMER] = {
  65. .name = "timer",
  66. .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  67. .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  68. .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  69. },
  70. [DMACH_I2S_IN] = {
  71. .name = "i2s-sdi",
  72. .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  73. .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  74. },
  75. [DMACH_I2S_OUT] = {
  76. .name = "i2s-sdo",
  77. .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  78. .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  79. },
  80. [DMACH_PCM_IN] = {
  81. .name = "pcm-in",
  82. .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  83. .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  84. },
  85. [DMACH_PCM_OUT] = {
  86. .name = "pcm-out",
  87. .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  88. .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  89. },
  90. [DMACH_MIC_IN] = {
  91. .name = "mic-in",
  92. .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
  93. .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
  94. },
  95. [DMACH_USB_EP1] = {
  96. .name = "usb-ep1",
  97. .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
  98. },
  99. [DMACH_USB_EP2] = {
  100. .name = "usb-ep2",
  101. .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
  102. },
  103. [DMACH_USB_EP3] = {
  104. .name = "usb-ep3",
  105. .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
  106. },
  107. [DMACH_USB_EP4] = {
  108. .name = "usb-ep4",
  109. .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
  110. },
  111. };
  112. static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
  113. struct s3c24xx_dma_map *map)
  114. {
  115. chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
  116. }
  117. static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
  118. .select = s3c2440_dma_select,
  119. .dcon_mask = 7 << 24,
  120. .map = s3c2440_dma_mappings,
  121. .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
  122. };
  123. static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
  124. .channels = {
  125. [DMACH_SDI] = {
  126. .list = {
  127. [0] = 3 | DMA_CH_VALID,
  128. [1] = 2 | DMA_CH_VALID,
  129. [2] = 1 | DMA_CH_VALID,
  130. [3] = 0 | DMA_CH_VALID,
  131. },
  132. },
  133. [DMACH_I2S_IN] = {
  134. .list = {
  135. [0] = 1 | DMA_CH_VALID,
  136. [1] = 2 | DMA_CH_VALID,
  137. },
  138. },
  139. [DMACH_I2S_OUT] = {
  140. .list = {
  141. [0] = 2 | DMA_CH_VALID,
  142. [1] = 1 | DMA_CH_VALID,
  143. },
  144. },
  145. [DMACH_PCM_IN] = {
  146. .list = {
  147. [0] = 2 | DMA_CH_VALID,
  148. [1] = 1 | DMA_CH_VALID,
  149. },
  150. },
  151. [DMACH_PCM_OUT] = {
  152. .list = {
  153. [0] = 1 | DMA_CH_VALID,
  154. [1] = 3 | DMA_CH_VALID,
  155. },
  156. },
  157. [DMACH_MIC_IN] = {
  158. .list = {
  159. [0] = 3 | DMA_CH_VALID,
  160. [1] = 2 | DMA_CH_VALID,
  161. },
  162. },
  163. },
  164. };
  165. static int __init s3c2440_dma_add(struct device *dev,
  166. struct subsys_interface *sif)
  167. {
  168. s3c2410_dma_init();
  169. s3c24xx_dma_order_set(&s3c2440_dma_order);
  170. return s3c24xx_dma_init_map(&s3c2440_dma_sel);
  171. }
  172. static struct subsys_interface s3c2440_dma_interface = {
  173. .name = "s3c2440_dma",
  174. .subsys = &s3c2440_subsys,
  175. .add_dev = s3c2440_dma_add,
  176. };
  177. static int __init s3c2440_dma_init(void)
  178. {
  179. return subsys_interface_register(&s3c2440_dma_interface);
  180. }
  181. arch_initcall(s3c2440_dma_init);