da8xx-fb.c 36 KB

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  1. /*
  2. * Copyright (C) 2008-2009 MontaVista Software Inc.
  3. * Copyright (C) 2008-2009 Texas Instruments Inc
  4. *
  5. * Based on the LCD driver for TI Avalanche processors written by
  6. * Ajay Singh and Shalom Hai.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option)any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/fb.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/device.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/clk.h>
  31. #include <linux/cpufreq.h>
  32. #include <linux/console.h>
  33. #include <linux/spinlock.h>
  34. #include <linux/slab.h>
  35. #include <linux/lcm.h>
  36. #include <video/da8xx-fb.h>
  37. #include <asm/div64.h>
  38. #define DRIVER_NAME "da8xx_lcdc"
  39. #define LCD_VERSION_1 1
  40. #define LCD_VERSION_2 2
  41. /* LCD Status Register */
  42. #define LCD_END_OF_FRAME1 BIT(9)
  43. #define LCD_END_OF_FRAME0 BIT(8)
  44. #define LCD_PL_LOAD_DONE BIT(6)
  45. #define LCD_FIFO_UNDERFLOW BIT(5)
  46. #define LCD_SYNC_LOST BIT(2)
  47. /* LCD DMA Control Register */
  48. #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
  49. #define LCD_DMA_BURST_1 0x0
  50. #define LCD_DMA_BURST_2 0x1
  51. #define LCD_DMA_BURST_4 0x2
  52. #define LCD_DMA_BURST_8 0x3
  53. #define LCD_DMA_BURST_16 0x4
  54. #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
  55. #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
  56. #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
  57. #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
  58. /* LCD Control Register */
  59. #define LCD_CLK_DIVISOR(x) ((x) << 8)
  60. #define LCD_RASTER_MODE 0x01
  61. /* LCD Raster Control Register */
  62. #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
  63. #define PALETTE_AND_DATA 0x00
  64. #define PALETTE_ONLY 0x01
  65. #define DATA_ONLY 0x02
  66. #define LCD_MONO_8BIT_MODE BIT(9)
  67. #define LCD_RASTER_ORDER BIT(8)
  68. #define LCD_TFT_MODE BIT(7)
  69. #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
  70. #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
  71. #define LCD_V1_PL_INT_ENA BIT(4)
  72. #define LCD_V2_PL_INT_ENA BIT(6)
  73. #define LCD_MONOCHROME_MODE BIT(1)
  74. #define LCD_RASTER_ENABLE BIT(0)
  75. #define LCD_TFT_ALT_ENABLE BIT(23)
  76. #define LCD_STN_565_ENABLE BIT(24)
  77. #define LCD_V2_DMA_CLK_EN BIT(2)
  78. #define LCD_V2_LIDD_CLK_EN BIT(1)
  79. #define LCD_V2_CORE_CLK_EN BIT(0)
  80. #define LCD_V2_LPP_B10 26
  81. /* LCD Raster Timing 2 Register */
  82. #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
  83. #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
  84. #define LCD_SYNC_CTRL BIT(25)
  85. #define LCD_SYNC_EDGE BIT(24)
  86. #define LCD_INVERT_PIXEL_CLOCK BIT(22)
  87. #define LCD_INVERT_LINE_CLOCK BIT(21)
  88. #define LCD_INVERT_FRAME_CLOCK BIT(20)
  89. /* LCD Block */
  90. #define LCD_PID_REG 0x0
  91. #define LCD_CTRL_REG 0x4
  92. #define LCD_STAT_REG 0x8
  93. #define LCD_RASTER_CTRL_REG 0x28
  94. #define LCD_RASTER_TIMING_0_REG 0x2C
  95. #define LCD_RASTER_TIMING_1_REG 0x30
  96. #define LCD_RASTER_TIMING_2_REG 0x34
  97. #define LCD_DMA_CTRL_REG 0x40
  98. #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
  99. #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
  100. #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
  101. #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
  102. /* Interrupt Registers available only in Version 2 */
  103. #define LCD_RAW_STAT_REG 0x58
  104. #define LCD_MASKED_STAT_REG 0x5c
  105. #define LCD_INT_ENABLE_SET_REG 0x60
  106. #define LCD_INT_ENABLE_CLR_REG 0x64
  107. #define LCD_END_OF_INT_IND_REG 0x68
  108. /* Clock registers available only on Version 2 */
  109. #define LCD_CLK_ENABLE_REG 0x6c
  110. #define LCD_CLK_RESET_REG 0x70
  111. #define LCD_CLK_MAIN_RESET BIT(3)
  112. #define LCD_NUM_BUFFERS 2
  113. #define WSI_TIMEOUT 50
  114. #define PALETTE_SIZE 256
  115. #define LEFT_MARGIN 64
  116. #define RIGHT_MARGIN 64
  117. #define UPPER_MARGIN 32
  118. #define LOWER_MARGIN 32
  119. static resource_size_t da8xx_fb_reg_base;
  120. static struct resource *lcdc_regs;
  121. static unsigned int lcd_revision;
  122. static irq_handler_t lcdc_irq_handler;
  123. static inline unsigned int lcdc_read(unsigned int addr)
  124. {
  125. return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
  126. }
  127. static inline void lcdc_write(unsigned int val, unsigned int addr)
  128. {
  129. __raw_writel(val, da8xx_fb_reg_base + (addr));
  130. }
  131. struct da8xx_fb_par {
  132. resource_size_t p_palette_base;
  133. unsigned char *v_palette_base;
  134. dma_addr_t vram_phys;
  135. unsigned long vram_size;
  136. void *vram_virt;
  137. unsigned int dma_start;
  138. unsigned int dma_end;
  139. struct clk *lcdc_clk;
  140. int irq;
  141. unsigned short pseudo_palette[16];
  142. unsigned int palette_sz;
  143. unsigned int pxl_clk;
  144. int blank;
  145. wait_queue_head_t vsync_wait;
  146. int vsync_flag;
  147. int vsync_timeout;
  148. spinlock_t lock_for_chan_update;
  149. /*
  150. * LCDC has 2 ping pong DMA channels, channel 0
  151. * and channel 1.
  152. */
  153. unsigned int which_dma_channel_done;
  154. #ifdef CONFIG_CPU_FREQ
  155. struct notifier_block freq_transition;
  156. unsigned int lcd_fck_rate;
  157. #endif
  158. void (*panel_power_ctrl)(int);
  159. };
  160. /* Variable Screen Information */
  161. static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
  162. .xoffset = 0,
  163. .yoffset = 0,
  164. .transp = {0, 0, 0},
  165. .nonstd = 0,
  166. .activate = 0,
  167. .height = -1,
  168. .width = -1,
  169. .accel_flags = 0,
  170. .left_margin = LEFT_MARGIN,
  171. .right_margin = RIGHT_MARGIN,
  172. .upper_margin = UPPER_MARGIN,
  173. .lower_margin = LOWER_MARGIN,
  174. .sync = 0,
  175. .vmode = FB_VMODE_NONINTERLACED
  176. };
  177. static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
  178. .id = "DA8xx FB Drv",
  179. .type = FB_TYPE_PACKED_PIXELS,
  180. .type_aux = 0,
  181. .visual = FB_VISUAL_PSEUDOCOLOR,
  182. .xpanstep = 0,
  183. .ypanstep = 1,
  184. .ywrapstep = 0,
  185. .accel = FB_ACCEL_NONE
  186. };
  187. struct da8xx_panel {
  188. const char name[25]; /* Full name <vendor>_<model> */
  189. unsigned short width;
  190. unsigned short height;
  191. int hfp; /* Horizontal front porch */
  192. int hbp; /* Horizontal back porch */
  193. int hsw; /* Horizontal Sync Pulse Width */
  194. int vfp; /* Vertical front porch */
  195. int vbp; /* Vertical back porch */
  196. int vsw; /* Vertical Sync Pulse Width */
  197. unsigned int pxl_clk; /* Pixel clock */
  198. unsigned char invert_pxl_clk; /* Invert Pixel clock */
  199. };
  200. static struct da8xx_panel known_lcd_panels[] = {
  201. /* Sharp LCD035Q3DG01 */
  202. [0] = {
  203. .name = "Sharp_LCD035Q3DG01",
  204. .width = 320,
  205. .height = 240,
  206. .hfp = 8,
  207. .hbp = 6,
  208. .hsw = 0,
  209. .vfp = 2,
  210. .vbp = 2,
  211. .vsw = 0,
  212. .pxl_clk = 4608000,
  213. .invert_pxl_clk = 1,
  214. },
  215. /* Sharp LK043T1DG01 */
  216. [1] = {
  217. .name = "Sharp_LK043T1DG01",
  218. .width = 480,
  219. .height = 272,
  220. .hfp = 2,
  221. .hbp = 2,
  222. .hsw = 41,
  223. .vfp = 2,
  224. .vbp = 2,
  225. .vsw = 10,
  226. .pxl_clk = 7833600,
  227. .invert_pxl_clk = 0,
  228. },
  229. [2] = {
  230. /* Hitachi SP10Q010 */
  231. .name = "SP10Q010",
  232. .width = 320,
  233. .height = 240,
  234. .hfp = 10,
  235. .hbp = 10,
  236. .hsw = 10,
  237. .vfp = 10,
  238. .vbp = 10,
  239. .vsw = 10,
  240. .pxl_clk = 7833600,
  241. .invert_pxl_clk = 0,
  242. },
  243. };
  244. /* Enable the Raster Engine of the LCD Controller */
  245. static inline void lcd_enable_raster(void)
  246. {
  247. u32 reg;
  248. /* Bring LCDC out of reset */
  249. if (lcd_revision == LCD_VERSION_2)
  250. lcdc_write(0, LCD_CLK_RESET_REG);
  251. reg = lcdc_read(LCD_RASTER_CTRL_REG);
  252. if (!(reg & LCD_RASTER_ENABLE))
  253. lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
  254. }
  255. /* Disable the Raster Engine of the LCD Controller */
  256. static inline void lcd_disable_raster(void)
  257. {
  258. u32 reg;
  259. reg = lcdc_read(LCD_RASTER_CTRL_REG);
  260. if (reg & LCD_RASTER_ENABLE)
  261. lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
  262. if (lcd_revision == LCD_VERSION_2)
  263. /* Write 1 to reset LCDC */
  264. lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
  265. }
  266. static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
  267. {
  268. u32 start;
  269. u32 end;
  270. u32 reg_ras;
  271. u32 reg_dma;
  272. u32 reg_int;
  273. /* init reg to clear PLM (loading mode) fields */
  274. reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
  275. reg_ras &= ~(3 << 20);
  276. reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
  277. if (load_mode == LOAD_DATA) {
  278. start = par->dma_start;
  279. end = par->dma_end;
  280. reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
  281. if (lcd_revision == LCD_VERSION_1) {
  282. reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
  283. } else {
  284. reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
  285. LCD_V2_END_OF_FRAME0_INT_ENA |
  286. LCD_V2_END_OF_FRAME1_INT_ENA;
  287. lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
  288. }
  289. reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
  290. lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
  291. lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
  292. lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
  293. lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
  294. } else if (load_mode == LOAD_PALETTE) {
  295. start = par->p_palette_base;
  296. end = start + par->palette_sz - 1;
  297. reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
  298. if (lcd_revision == LCD_VERSION_1) {
  299. reg_ras |= LCD_V1_PL_INT_ENA;
  300. } else {
  301. reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
  302. LCD_V2_PL_INT_ENA;
  303. lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
  304. }
  305. lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
  306. lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
  307. }
  308. lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
  309. lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
  310. /*
  311. * The Raster enable bit must be set after all other control fields are
  312. * set.
  313. */
  314. lcd_enable_raster();
  315. }
  316. /* Configure the Burst Size of DMA */
  317. static int lcd_cfg_dma(int burst_size)
  318. {
  319. u32 reg;
  320. reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
  321. switch (burst_size) {
  322. case 1:
  323. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
  324. break;
  325. case 2:
  326. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
  327. break;
  328. case 4:
  329. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
  330. break;
  331. case 8:
  332. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
  333. break;
  334. case 16:
  335. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
  336. break;
  337. default:
  338. return -EINVAL;
  339. }
  340. lcdc_write(reg, LCD_DMA_CTRL_REG);
  341. return 0;
  342. }
  343. static void lcd_cfg_ac_bias(int period, int transitions_per_int)
  344. {
  345. u32 reg;
  346. /* Set the AC Bias Period and Number of Transisitons per Interrupt */
  347. reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
  348. reg |= LCD_AC_BIAS_FREQUENCY(period) |
  349. LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
  350. lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
  351. }
  352. static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
  353. int front_porch)
  354. {
  355. u32 reg;
  356. reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
  357. reg |= ((back_porch & 0xff) << 24)
  358. | ((front_porch & 0xff) << 16)
  359. | ((pulse_width & 0x3f) << 10);
  360. lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
  361. }
  362. static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
  363. int front_porch)
  364. {
  365. u32 reg;
  366. reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
  367. reg |= ((back_porch & 0xff) << 24)
  368. | ((front_porch & 0xff) << 16)
  369. | ((pulse_width & 0x3f) << 10);
  370. lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
  371. }
  372. static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
  373. {
  374. u32 reg;
  375. u32 reg_int;
  376. reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
  377. LCD_MONO_8BIT_MODE |
  378. LCD_MONOCHROME_MODE);
  379. switch (cfg->p_disp_panel->panel_shade) {
  380. case MONOCHROME:
  381. reg |= LCD_MONOCHROME_MODE;
  382. if (cfg->mono_8bit_mode)
  383. reg |= LCD_MONO_8BIT_MODE;
  384. break;
  385. case COLOR_ACTIVE:
  386. reg |= LCD_TFT_MODE;
  387. if (cfg->tft_alt_mode)
  388. reg |= LCD_TFT_ALT_ENABLE;
  389. break;
  390. case COLOR_PASSIVE:
  391. if (cfg->stn_565_mode)
  392. reg |= LCD_STN_565_ENABLE;
  393. break;
  394. default:
  395. return -EINVAL;
  396. }
  397. /* enable additional interrupts here */
  398. if (lcd_revision == LCD_VERSION_1) {
  399. reg |= LCD_V1_UNDERFLOW_INT_ENA;
  400. } else {
  401. reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
  402. LCD_V2_UNDERFLOW_INT_ENA;
  403. lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
  404. }
  405. lcdc_write(reg, LCD_RASTER_CTRL_REG);
  406. reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
  407. if (cfg->sync_ctrl)
  408. reg |= LCD_SYNC_CTRL;
  409. else
  410. reg &= ~LCD_SYNC_CTRL;
  411. if (cfg->sync_edge)
  412. reg |= LCD_SYNC_EDGE;
  413. else
  414. reg &= ~LCD_SYNC_EDGE;
  415. if (cfg->invert_line_clock)
  416. reg |= LCD_INVERT_LINE_CLOCK;
  417. else
  418. reg &= ~LCD_INVERT_LINE_CLOCK;
  419. if (cfg->invert_frm_clock)
  420. reg |= LCD_INVERT_FRAME_CLOCK;
  421. else
  422. reg &= ~LCD_INVERT_FRAME_CLOCK;
  423. lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
  424. return 0;
  425. }
  426. static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
  427. u32 bpp, u32 raster_order)
  428. {
  429. u32 reg;
  430. /* Set the Panel Width */
  431. /* Pixels per line = (PPL + 1)*16 */
  432. if (lcd_revision == LCD_VERSION_1) {
  433. /*
  434. * 0x3F in bits 4..9 gives max horizontal resolution = 1024
  435. * pixels.
  436. */
  437. width &= 0x3f0;
  438. } else {
  439. /*
  440. * 0x7F in bits 4..10 gives max horizontal resolution = 2048
  441. * pixels.
  442. */
  443. width &= 0x7f0;
  444. }
  445. reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
  446. reg &= 0xfffffc00;
  447. if (lcd_revision == LCD_VERSION_1) {
  448. reg |= ((width >> 4) - 1) << 4;
  449. } else {
  450. width = (width >> 4) - 1;
  451. reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
  452. }
  453. lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
  454. /* Set the Panel Height */
  455. /* Set bits 9:0 of Lines Per Pixel */
  456. reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
  457. reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
  458. lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
  459. /* Set bit 10 of Lines Per Pixel */
  460. if (lcd_revision == LCD_VERSION_2) {
  461. reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
  462. reg |= ((height - 1) & 0x400) << 16;
  463. lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
  464. }
  465. /* Set the Raster Order of the Frame Buffer */
  466. reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
  467. if (raster_order)
  468. reg |= LCD_RASTER_ORDER;
  469. lcdc_write(reg, LCD_RASTER_CTRL_REG);
  470. switch (bpp) {
  471. case 1:
  472. case 2:
  473. case 4:
  474. case 16:
  475. par->palette_sz = 16 * 2;
  476. break;
  477. case 8:
  478. par->palette_sz = 256 * 2;
  479. break;
  480. default:
  481. return -EINVAL;
  482. }
  483. return 0;
  484. }
  485. static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  486. unsigned blue, unsigned transp,
  487. struct fb_info *info)
  488. {
  489. struct da8xx_fb_par *par = info->par;
  490. unsigned short *palette = (unsigned short *) par->v_palette_base;
  491. u_short pal;
  492. int update_hw = 0;
  493. if (regno > 255)
  494. return 1;
  495. if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
  496. return 1;
  497. if (info->var.bits_per_pixel == 4) {
  498. if (regno > 15)
  499. return 1;
  500. if (info->var.grayscale) {
  501. pal = regno;
  502. } else {
  503. red >>= 4;
  504. green >>= 8;
  505. blue >>= 12;
  506. pal = (red & 0x0f00);
  507. pal |= (green & 0x00f0);
  508. pal |= (blue & 0x000f);
  509. }
  510. if (regno == 0)
  511. pal |= 0x2000;
  512. palette[regno] = pal;
  513. } else if (info->var.bits_per_pixel == 8) {
  514. red >>= 4;
  515. green >>= 8;
  516. blue >>= 12;
  517. pal = (red & 0x0f00);
  518. pal |= (green & 0x00f0);
  519. pal |= (blue & 0x000f);
  520. if (palette[regno] != pal) {
  521. update_hw = 1;
  522. palette[regno] = pal;
  523. }
  524. } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
  525. red >>= (16 - info->var.red.length);
  526. red <<= info->var.red.offset;
  527. green >>= (16 - info->var.green.length);
  528. green <<= info->var.green.offset;
  529. blue >>= (16 - info->var.blue.length);
  530. blue <<= info->var.blue.offset;
  531. par->pseudo_palette[regno] = red | green | blue;
  532. if (palette[0] != 0x4000) {
  533. update_hw = 1;
  534. palette[0] = 0x4000;
  535. }
  536. }
  537. /* Update the palette in the h/w as needed. */
  538. if (update_hw)
  539. lcd_blit(LOAD_PALETTE, par);
  540. return 0;
  541. }
  542. static void lcd_reset(struct da8xx_fb_par *par)
  543. {
  544. /* Disable the Raster if previously Enabled */
  545. lcd_disable_raster();
  546. /* DMA has to be disabled */
  547. lcdc_write(0, LCD_DMA_CTRL_REG);
  548. lcdc_write(0, LCD_RASTER_CTRL_REG);
  549. if (lcd_revision == LCD_VERSION_2) {
  550. lcdc_write(0, LCD_INT_ENABLE_SET_REG);
  551. /* Write 1 to reset */
  552. lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
  553. lcdc_write(0, LCD_CLK_RESET_REG);
  554. }
  555. }
  556. static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
  557. {
  558. unsigned int lcd_clk, div;
  559. lcd_clk = clk_get_rate(par->lcdc_clk);
  560. div = lcd_clk / par->pxl_clk;
  561. /* Configure the LCD clock divisor. */
  562. lcdc_write(LCD_CLK_DIVISOR(div) |
  563. (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
  564. if (lcd_revision == LCD_VERSION_2)
  565. lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
  566. LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
  567. }
  568. static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
  569. struct da8xx_panel *panel)
  570. {
  571. u32 bpp;
  572. int ret = 0;
  573. lcd_reset(par);
  574. /* Calculate the divider */
  575. lcd_calc_clk_divider(par);
  576. if (panel->invert_pxl_clk)
  577. lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
  578. LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
  579. else
  580. lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
  581. ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
  582. /* Configure the DMA burst size. */
  583. ret = lcd_cfg_dma(cfg->dma_burst_sz);
  584. if (ret < 0)
  585. return ret;
  586. /* Configure the AC bias properties. */
  587. lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
  588. /* Configure the vertical and horizontal sync properties. */
  589. lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
  590. lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
  591. /* Configure for disply */
  592. ret = lcd_cfg_display(cfg);
  593. if (ret < 0)
  594. return ret;
  595. if (QVGA != cfg->p_disp_panel->panel_type)
  596. return -EINVAL;
  597. if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
  598. cfg->bpp >= cfg->p_disp_panel->min_bpp)
  599. bpp = cfg->bpp;
  600. else
  601. bpp = cfg->p_disp_panel->max_bpp;
  602. if (bpp == 12)
  603. bpp = 16;
  604. ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
  605. (unsigned int)panel->height, bpp,
  606. cfg->raster_order);
  607. if (ret < 0)
  608. return ret;
  609. /* Configure FDD */
  610. lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
  611. (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
  612. return 0;
  613. }
  614. /* IRQ handler for version 2 of LCDC */
  615. static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
  616. {
  617. struct da8xx_fb_par *par = arg;
  618. u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
  619. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  620. lcd_disable_raster();
  621. lcdc_write(stat, LCD_MASKED_STAT_REG);
  622. lcd_enable_raster();
  623. } else if (stat & LCD_PL_LOAD_DONE) {
  624. /*
  625. * Must disable raster before changing state of any control bit.
  626. * And also must be disabled before clearing the PL loading
  627. * interrupt via the following write to the status register. If
  628. * this is done after then one gets multiple PL done interrupts.
  629. */
  630. lcd_disable_raster();
  631. lcdc_write(stat, LCD_MASKED_STAT_REG);
  632. /* Disable PL completion interrupt */
  633. lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
  634. /* Setup and start data loading mode */
  635. lcd_blit(LOAD_DATA, par);
  636. } else {
  637. lcdc_write(stat, LCD_MASKED_STAT_REG);
  638. if (stat & LCD_END_OF_FRAME0) {
  639. par->which_dma_channel_done = 0;
  640. lcdc_write(par->dma_start,
  641. LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
  642. lcdc_write(par->dma_end,
  643. LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
  644. par->vsync_flag = 1;
  645. wake_up_interruptible(&par->vsync_wait);
  646. }
  647. if (stat & LCD_END_OF_FRAME1) {
  648. par->which_dma_channel_done = 1;
  649. lcdc_write(par->dma_start,
  650. LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
  651. lcdc_write(par->dma_end,
  652. LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
  653. par->vsync_flag = 1;
  654. wake_up_interruptible(&par->vsync_wait);
  655. }
  656. }
  657. lcdc_write(0, LCD_END_OF_INT_IND_REG);
  658. return IRQ_HANDLED;
  659. }
  660. /* IRQ handler for version 1 LCDC */
  661. static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
  662. {
  663. struct da8xx_fb_par *par = arg;
  664. u32 stat = lcdc_read(LCD_STAT_REG);
  665. u32 reg_ras;
  666. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  667. lcd_disable_raster();
  668. lcdc_write(stat, LCD_STAT_REG);
  669. lcd_enable_raster();
  670. } else if (stat & LCD_PL_LOAD_DONE) {
  671. /*
  672. * Must disable raster before changing state of any control bit.
  673. * And also must be disabled before clearing the PL loading
  674. * interrupt via the following write to the status register. If
  675. * this is done after then one gets multiple PL done interrupts.
  676. */
  677. lcd_disable_raster();
  678. lcdc_write(stat, LCD_STAT_REG);
  679. /* Disable PL completion inerrupt */
  680. reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
  681. reg_ras &= ~LCD_V1_PL_INT_ENA;
  682. lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
  683. /* Setup and start data loading mode */
  684. lcd_blit(LOAD_DATA, par);
  685. } else {
  686. lcdc_write(stat, LCD_STAT_REG);
  687. if (stat & LCD_END_OF_FRAME0) {
  688. par->which_dma_channel_done = 0;
  689. lcdc_write(par->dma_start,
  690. LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
  691. lcdc_write(par->dma_end,
  692. LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
  693. par->vsync_flag = 1;
  694. wake_up_interruptible(&par->vsync_wait);
  695. }
  696. if (stat & LCD_END_OF_FRAME1) {
  697. par->which_dma_channel_done = 1;
  698. lcdc_write(par->dma_start,
  699. LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
  700. lcdc_write(par->dma_end,
  701. LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
  702. par->vsync_flag = 1;
  703. wake_up_interruptible(&par->vsync_wait);
  704. }
  705. }
  706. return IRQ_HANDLED;
  707. }
  708. static int fb_check_var(struct fb_var_screeninfo *var,
  709. struct fb_info *info)
  710. {
  711. int err = 0;
  712. switch (var->bits_per_pixel) {
  713. case 1:
  714. case 8:
  715. var->red.offset = 0;
  716. var->red.length = 8;
  717. var->green.offset = 0;
  718. var->green.length = 8;
  719. var->blue.offset = 0;
  720. var->blue.length = 8;
  721. var->transp.offset = 0;
  722. var->transp.length = 0;
  723. var->nonstd = 0;
  724. break;
  725. case 4:
  726. var->red.offset = 0;
  727. var->red.length = 4;
  728. var->green.offset = 0;
  729. var->green.length = 4;
  730. var->blue.offset = 0;
  731. var->blue.length = 4;
  732. var->transp.offset = 0;
  733. var->transp.length = 0;
  734. var->nonstd = FB_NONSTD_REV_PIX_IN_B;
  735. break;
  736. case 16: /* RGB 565 */
  737. var->red.offset = 11;
  738. var->red.length = 5;
  739. var->green.offset = 5;
  740. var->green.length = 6;
  741. var->blue.offset = 0;
  742. var->blue.length = 5;
  743. var->transp.offset = 0;
  744. var->transp.length = 0;
  745. var->nonstd = 0;
  746. break;
  747. default:
  748. err = -EINVAL;
  749. }
  750. var->red.msb_right = 0;
  751. var->green.msb_right = 0;
  752. var->blue.msb_right = 0;
  753. var->transp.msb_right = 0;
  754. return err;
  755. }
  756. #ifdef CONFIG_CPU_FREQ
  757. static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
  758. unsigned long val, void *data)
  759. {
  760. struct da8xx_fb_par *par;
  761. par = container_of(nb, struct da8xx_fb_par, freq_transition);
  762. if (val == CPUFREQ_POSTCHANGE) {
  763. if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
  764. par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
  765. lcd_disable_raster();
  766. lcd_calc_clk_divider(par);
  767. lcd_enable_raster();
  768. }
  769. }
  770. return 0;
  771. }
  772. static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
  773. {
  774. par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
  775. return cpufreq_register_notifier(&par->freq_transition,
  776. CPUFREQ_TRANSITION_NOTIFIER);
  777. }
  778. static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
  779. {
  780. cpufreq_unregister_notifier(&par->freq_transition,
  781. CPUFREQ_TRANSITION_NOTIFIER);
  782. }
  783. #endif
  784. static int __devexit fb_remove(struct platform_device *dev)
  785. {
  786. struct fb_info *info = dev_get_drvdata(&dev->dev);
  787. if (info) {
  788. struct da8xx_fb_par *par = info->par;
  789. #ifdef CONFIG_CPU_FREQ
  790. lcd_da8xx_cpufreq_deregister(par);
  791. #endif
  792. if (par->panel_power_ctrl)
  793. par->panel_power_ctrl(0);
  794. lcd_disable_raster();
  795. lcdc_write(0, LCD_RASTER_CTRL_REG);
  796. /* disable DMA */
  797. lcdc_write(0, LCD_DMA_CTRL_REG);
  798. unregister_framebuffer(info);
  799. fb_dealloc_cmap(&info->cmap);
  800. dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
  801. par->p_palette_base);
  802. dma_free_coherent(NULL, par->vram_size, par->vram_virt,
  803. par->vram_phys);
  804. free_irq(par->irq, par);
  805. clk_disable(par->lcdc_clk);
  806. clk_put(par->lcdc_clk);
  807. framebuffer_release(info);
  808. iounmap((void __iomem *)da8xx_fb_reg_base);
  809. release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
  810. }
  811. return 0;
  812. }
  813. /*
  814. * Function to wait for vertical sync which for this LCD peripheral
  815. * translates into waiting for the current raster frame to complete.
  816. */
  817. static int fb_wait_for_vsync(struct fb_info *info)
  818. {
  819. struct da8xx_fb_par *par = info->par;
  820. int ret;
  821. /*
  822. * Set flag to 0 and wait for isr to set to 1. It would seem there is a
  823. * race condition here where the ISR could have occurred just before or
  824. * just after this set. But since we are just coarsely waiting for
  825. * a frame to complete then that's OK. i.e. if the frame completed
  826. * just before this code executed then we have to wait another full
  827. * frame time but there is no way to avoid such a situation. On the
  828. * other hand if the frame completed just after then we don't need
  829. * to wait long at all. Either way we are guaranteed to return to the
  830. * user immediately after a frame completion which is all that is
  831. * required.
  832. */
  833. par->vsync_flag = 0;
  834. ret = wait_event_interruptible_timeout(par->vsync_wait,
  835. par->vsync_flag != 0,
  836. par->vsync_timeout);
  837. if (ret < 0)
  838. return ret;
  839. if (ret == 0)
  840. return -ETIMEDOUT;
  841. return 0;
  842. }
  843. static int fb_ioctl(struct fb_info *info, unsigned int cmd,
  844. unsigned long arg)
  845. {
  846. struct lcd_sync_arg sync_arg;
  847. switch (cmd) {
  848. case FBIOGET_CONTRAST:
  849. case FBIOPUT_CONTRAST:
  850. case FBIGET_BRIGHTNESS:
  851. case FBIPUT_BRIGHTNESS:
  852. case FBIGET_COLOR:
  853. case FBIPUT_COLOR:
  854. return -ENOTTY;
  855. case FBIPUT_HSYNC:
  856. if (copy_from_user(&sync_arg, (char *)arg,
  857. sizeof(struct lcd_sync_arg)))
  858. return -EFAULT;
  859. lcd_cfg_horizontal_sync(sync_arg.back_porch,
  860. sync_arg.pulse_width,
  861. sync_arg.front_porch);
  862. break;
  863. case FBIPUT_VSYNC:
  864. if (copy_from_user(&sync_arg, (char *)arg,
  865. sizeof(struct lcd_sync_arg)))
  866. return -EFAULT;
  867. lcd_cfg_vertical_sync(sync_arg.back_porch,
  868. sync_arg.pulse_width,
  869. sync_arg.front_porch);
  870. break;
  871. case FBIO_WAITFORVSYNC:
  872. return fb_wait_for_vsync(info);
  873. default:
  874. return -EINVAL;
  875. }
  876. return 0;
  877. }
  878. static int cfb_blank(int blank, struct fb_info *info)
  879. {
  880. struct da8xx_fb_par *par = info->par;
  881. int ret = 0;
  882. if (par->blank == blank)
  883. return 0;
  884. par->blank = blank;
  885. switch (blank) {
  886. case FB_BLANK_UNBLANK:
  887. if (par->panel_power_ctrl)
  888. par->panel_power_ctrl(1);
  889. lcd_enable_raster();
  890. break;
  891. case FB_BLANK_NORMAL:
  892. case FB_BLANK_VSYNC_SUSPEND:
  893. case FB_BLANK_HSYNC_SUSPEND:
  894. case FB_BLANK_POWERDOWN:
  895. if (par->panel_power_ctrl)
  896. par->panel_power_ctrl(0);
  897. lcd_disable_raster();
  898. break;
  899. default:
  900. ret = -EINVAL;
  901. }
  902. return ret;
  903. }
  904. /*
  905. * Set new x,y offsets in the virtual display for the visible area and switch
  906. * to the new mode.
  907. */
  908. static int da8xx_pan_display(struct fb_var_screeninfo *var,
  909. struct fb_info *fbi)
  910. {
  911. int ret = 0;
  912. struct fb_var_screeninfo new_var;
  913. struct da8xx_fb_par *par = fbi->par;
  914. struct fb_fix_screeninfo *fix = &fbi->fix;
  915. unsigned int end;
  916. unsigned int start;
  917. unsigned long irq_flags;
  918. if (var->xoffset != fbi->var.xoffset ||
  919. var->yoffset != fbi->var.yoffset) {
  920. memcpy(&new_var, &fbi->var, sizeof(new_var));
  921. new_var.xoffset = var->xoffset;
  922. new_var.yoffset = var->yoffset;
  923. if (fb_check_var(&new_var, fbi))
  924. ret = -EINVAL;
  925. else {
  926. memcpy(&fbi->var, &new_var, sizeof(new_var));
  927. start = fix->smem_start +
  928. new_var.yoffset * fix->line_length +
  929. new_var.xoffset * fbi->var.bits_per_pixel / 8;
  930. end = start + fbi->var.yres * fix->line_length - 1;
  931. par->dma_start = start;
  932. par->dma_end = end;
  933. spin_lock_irqsave(&par->lock_for_chan_update,
  934. irq_flags);
  935. if (par->which_dma_channel_done == 0) {
  936. lcdc_write(par->dma_start,
  937. LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
  938. lcdc_write(par->dma_end,
  939. LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
  940. } else if (par->which_dma_channel_done == 1) {
  941. lcdc_write(par->dma_start,
  942. LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
  943. lcdc_write(par->dma_end,
  944. LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
  945. }
  946. spin_unlock_irqrestore(&par->lock_for_chan_update,
  947. irq_flags);
  948. }
  949. }
  950. return ret;
  951. }
  952. static struct fb_ops da8xx_fb_ops = {
  953. .owner = THIS_MODULE,
  954. .fb_check_var = fb_check_var,
  955. .fb_setcolreg = fb_setcolreg,
  956. .fb_pan_display = da8xx_pan_display,
  957. .fb_ioctl = fb_ioctl,
  958. .fb_fillrect = cfb_fillrect,
  959. .fb_copyarea = cfb_copyarea,
  960. .fb_imageblit = cfb_imageblit,
  961. .fb_blank = cfb_blank,
  962. };
  963. /* Calculate and return pixel clock period in pico seconds */
  964. static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
  965. {
  966. unsigned int lcd_clk, div;
  967. unsigned int configured_pix_clk;
  968. unsigned long long pix_clk_period_picosec = 1000000000000ULL;
  969. lcd_clk = clk_get_rate(par->lcdc_clk);
  970. div = lcd_clk / par->pxl_clk;
  971. configured_pix_clk = (lcd_clk / div);
  972. do_div(pix_clk_period_picosec, configured_pix_clk);
  973. return pix_clk_period_picosec;
  974. }
  975. static int __devinit fb_probe(struct platform_device *device)
  976. {
  977. struct da8xx_lcdc_platform_data *fb_pdata =
  978. device->dev.platform_data;
  979. struct lcd_ctrl_config *lcd_cfg;
  980. struct da8xx_panel *lcdc_info;
  981. struct fb_info *da8xx_fb_info;
  982. struct clk *fb_clk = NULL;
  983. struct da8xx_fb_par *par;
  984. resource_size_t len;
  985. int ret, i;
  986. unsigned long ulcm;
  987. if (fb_pdata == NULL) {
  988. dev_err(&device->dev, "Can not get platform data\n");
  989. return -ENOENT;
  990. }
  991. lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
  992. if (!lcdc_regs) {
  993. dev_err(&device->dev,
  994. "Can not get memory resource for LCD controller\n");
  995. return -ENOENT;
  996. }
  997. len = resource_size(lcdc_regs);
  998. lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
  999. if (!lcdc_regs)
  1000. return -EBUSY;
  1001. da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
  1002. if (!da8xx_fb_reg_base) {
  1003. ret = -EBUSY;
  1004. goto err_request_mem;
  1005. }
  1006. fb_clk = clk_get(&device->dev, NULL);
  1007. if (IS_ERR(fb_clk)) {
  1008. dev_err(&device->dev, "Can not get device clock\n");
  1009. ret = -ENODEV;
  1010. goto err_ioremap;
  1011. }
  1012. ret = clk_enable(fb_clk);
  1013. if (ret)
  1014. goto err_clk_put;
  1015. /* Determine LCD IP Version */
  1016. switch (lcdc_read(LCD_PID_REG)) {
  1017. case 0x4C100102:
  1018. lcd_revision = LCD_VERSION_1;
  1019. break;
  1020. case 0x4F200800:
  1021. lcd_revision = LCD_VERSION_2;
  1022. break;
  1023. default:
  1024. dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
  1025. "defaulting to LCD revision 1\n",
  1026. lcdc_read(LCD_PID_REG));
  1027. lcd_revision = LCD_VERSION_1;
  1028. break;
  1029. }
  1030. for (i = 0, lcdc_info = known_lcd_panels;
  1031. i < ARRAY_SIZE(known_lcd_panels);
  1032. i++, lcdc_info++) {
  1033. if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
  1034. break;
  1035. }
  1036. if (i == ARRAY_SIZE(known_lcd_panels)) {
  1037. dev_err(&device->dev, "GLCD: No valid panel found\n");
  1038. ret = -ENODEV;
  1039. goto err_clk_disable;
  1040. } else
  1041. dev_info(&device->dev, "GLCD: Found %s panel\n",
  1042. fb_pdata->type);
  1043. lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
  1044. da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
  1045. &device->dev);
  1046. if (!da8xx_fb_info) {
  1047. dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
  1048. ret = -ENOMEM;
  1049. goto err_clk_disable;
  1050. }
  1051. par = da8xx_fb_info->par;
  1052. par->lcdc_clk = fb_clk;
  1053. #ifdef CONFIG_CPU_FREQ
  1054. par->lcd_fck_rate = clk_get_rate(fb_clk);
  1055. #endif
  1056. par->pxl_clk = lcdc_info->pxl_clk;
  1057. if (fb_pdata->panel_power_ctrl) {
  1058. par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
  1059. par->panel_power_ctrl(1);
  1060. }
  1061. if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
  1062. dev_err(&device->dev, "lcd_init failed\n");
  1063. ret = -EFAULT;
  1064. goto err_release_fb;
  1065. }
  1066. /* allocate frame buffer */
  1067. par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
  1068. ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE);
  1069. par->vram_size = roundup(par->vram_size/8, ulcm);
  1070. par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
  1071. par->vram_virt = dma_alloc_coherent(NULL,
  1072. par->vram_size,
  1073. (resource_size_t *) &par->vram_phys,
  1074. GFP_KERNEL | GFP_DMA);
  1075. if (!par->vram_virt) {
  1076. dev_err(&device->dev,
  1077. "GLCD: kmalloc for frame buffer failed\n");
  1078. ret = -EINVAL;
  1079. goto err_release_fb;
  1080. }
  1081. da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
  1082. da8xx_fb_fix.smem_start = par->vram_phys;
  1083. da8xx_fb_fix.smem_len = par->vram_size;
  1084. da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
  1085. par->dma_start = par->vram_phys;
  1086. par->dma_end = par->dma_start + lcdc_info->height *
  1087. da8xx_fb_fix.line_length - 1;
  1088. /* allocate palette buffer */
  1089. par->v_palette_base = dma_alloc_coherent(NULL,
  1090. PALETTE_SIZE,
  1091. (resource_size_t *)
  1092. &par->p_palette_base,
  1093. GFP_KERNEL | GFP_DMA);
  1094. if (!par->v_palette_base) {
  1095. dev_err(&device->dev,
  1096. "GLCD: kmalloc for palette buffer failed\n");
  1097. ret = -EINVAL;
  1098. goto err_release_fb_mem;
  1099. }
  1100. memset(par->v_palette_base, 0, PALETTE_SIZE);
  1101. par->irq = platform_get_irq(device, 0);
  1102. if (par->irq < 0) {
  1103. ret = -ENOENT;
  1104. goto err_release_pl_mem;
  1105. }
  1106. /* Initialize par */
  1107. da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
  1108. da8xx_fb_var.xres = lcdc_info->width;
  1109. da8xx_fb_var.xres_virtual = lcdc_info->width;
  1110. da8xx_fb_var.yres = lcdc_info->height;
  1111. da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
  1112. da8xx_fb_var.grayscale =
  1113. lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
  1114. da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
  1115. da8xx_fb_var.hsync_len = lcdc_info->hsw;
  1116. da8xx_fb_var.vsync_len = lcdc_info->vsw;
  1117. da8xx_fb_var.right_margin = lcdc_info->hfp;
  1118. da8xx_fb_var.left_margin = lcdc_info->hbp;
  1119. da8xx_fb_var.lower_margin = lcdc_info->vfp;
  1120. da8xx_fb_var.upper_margin = lcdc_info->vbp;
  1121. da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
  1122. /* Initialize fbinfo */
  1123. da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
  1124. da8xx_fb_info->fix = da8xx_fb_fix;
  1125. da8xx_fb_info->var = da8xx_fb_var;
  1126. da8xx_fb_info->fbops = &da8xx_fb_ops;
  1127. da8xx_fb_info->pseudo_palette = par->pseudo_palette;
  1128. da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
  1129. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  1130. ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
  1131. if (ret)
  1132. goto err_release_pl_mem;
  1133. da8xx_fb_info->cmap.len = par->palette_sz;
  1134. /* initialize var_screeninfo */
  1135. da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
  1136. fb_set_var(da8xx_fb_info, &da8xx_fb_var);
  1137. dev_set_drvdata(&device->dev, da8xx_fb_info);
  1138. /* initialize the vsync wait queue */
  1139. init_waitqueue_head(&par->vsync_wait);
  1140. par->vsync_timeout = HZ / 5;
  1141. par->which_dma_channel_done = -1;
  1142. spin_lock_init(&par->lock_for_chan_update);
  1143. /* Register the Frame Buffer */
  1144. if (register_framebuffer(da8xx_fb_info) < 0) {
  1145. dev_err(&device->dev,
  1146. "GLCD: Frame Buffer Registration Failed!\n");
  1147. ret = -EINVAL;
  1148. goto err_dealloc_cmap;
  1149. }
  1150. #ifdef CONFIG_CPU_FREQ
  1151. ret = lcd_da8xx_cpufreq_register(par);
  1152. if (ret) {
  1153. dev_err(&device->dev, "failed to register cpufreq\n");
  1154. goto err_cpu_freq;
  1155. }
  1156. #endif
  1157. if (lcd_revision == LCD_VERSION_1)
  1158. lcdc_irq_handler = lcdc_irq_handler_rev01;
  1159. else
  1160. lcdc_irq_handler = lcdc_irq_handler_rev02;
  1161. ret = request_irq(par->irq, lcdc_irq_handler, 0,
  1162. DRIVER_NAME, par);
  1163. if (ret)
  1164. goto irq_freq;
  1165. return 0;
  1166. irq_freq:
  1167. #ifdef CONFIG_CPU_FREQ
  1168. lcd_da8xx_cpufreq_deregister(par);
  1169. err_cpu_freq:
  1170. #endif
  1171. unregister_framebuffer(da8xx_fb_info);
  1172. err_dealloc_cmap:
  1173. fb_dealloc_cmap(&da8xx_fb_info->cmap);
  1174. err_release_pl_mem:
  1175. dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
  1176. par->p_palette_base);
  1177. err_release_fb_mem:
  1178. dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
  1179. err_release_fb:
  1180. framebuffer_release(da8xx_fb_info);
  1181. err_clk_disable:
  1182. clk_disable(fb_clk);
  1183. err_clk_put:
  1184. clk_put(fb_clk);
  1185. err_ioremap:
  1186. iounmap((void __iomem *)da8xx_fb_reg_base);
  1187. err_request_mem:
  1188. release_mem_region(lcdc_regs->start, len);
  1189. return ret;
  1190. }
  1191. #ifdef CONFIG_PM
  1192. static int fb_suspend(struct platform_device *dev, pm_message_t state)
  1193. {
  1194. struct fb_info *info = platform_get_drvdata(dev);
  1195. struct da8xx_fb_par *par = info->par;
  1196. console_lock();
  1197. if (par->panel_power_ctrl)
  1198. par->panel_power_ctrl(0);
  1199. fb_set_suspend(info, 1);
  1200. lcd_disable_raster();
  1201. clk_disable(par->lcdc_clk);
  1202. console_unlock();
  1203. return 0;
  1204. }
  1205. static int fb_resume(struct platform_device *dev)
  1206. {
  1207. struct fb_info *info = platform_get_drvdata(dev);
  1208. struct da8xx_fb_par *par = info->par;
  1209. console_lock();
  1210. if (par->panel_power_ctrl)
  1211. par->panel_power_ctrl(1);
  1212. clk_enable(par->lcdc_clk);
  1213. lcd_enable_raster();
  1214. fb_set_suspend(info, 0);
  1215. console_unlock();
  1216. return 0;
  1217. }
  1218. #else
  1219. #define fb_suspend NULL
  1220. #define fb_resume NULL
  1221. #endif
  1222. static struct platform_driver da8xx_fb_driver = {
  1223. .probe = fb_probe,
  1224. .remove = __devexit_p(fb_remove),
  1225. .suspend = fb_suspend,
  1226. .resume = fb_resume,
  1227. .driver = {
  1228. .name = DRIVER_NAME,
  1229. .owner = THIS_MODULE,
  1230. },
  1231. };
  1232. static int __init da8xx_fb_init(void)
  1233. {
  1234. return platform_driver_register(&da8xx_fb_driver);
  1235. }
  1236. static void __exit da8xx_fb_cleanup(void)
  1237. {
  1238. platform_driver_unregister(&da8xx_fb_driver);
  1239. }
  1240. module_init(da8xx_fb_init);
  1241. module_exit(da8xx_fb_cleanup);
  1242. MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
  1243. MODULE_AUTHOR("Texas Instruments");
  1244. MODULE_LICENSE("GPL");