ipath_intr.c 36 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
  3. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/pci.h>
  34. #include "ipath_kernel.h"
  35. #include "ipath_verbs.h"
  36. #include "ipath_common.h"
  37. /*
  38. * clear (write) a pio buffer, to clear a parity error. This routine
  39. * should only be called when in freeze mode, and the buffer should be
  40. * canceled afterwards.
  41. */
  42. static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum)
  43. {
  44. u32 __iomem *pbuf;
  45. u32 dwcnt; /* dword count to write */
  46. if (pnum < dd->ipath_piobcnt2k) {
  47. pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum *
  48. dd->ipath_palign);
  49. dwcnt = dd->ipath_piosize2k >> 2;
  50. }
  51. else {
  52. pbuf = (u32 __iomem *) (dd->ipath_pio4kbase +
  53. (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
  54. dwcnt = dd->ipath_piosize4k >> 2;
  55. }
  56. dev_info(&dd->pcidev->dev,
  57. "Rewrite PIO buffer %u, to recover from parity error\n",
  58. pnum);
  59. *pbuf = dwcnt+1; /* no flush required, since already in freeze */
  60. while(--dwcnt)
  61. *pbuf++ = 0;
  62. }
  63. /*
  64. * Called when we might have an error that is specific to a particular
  65. * PIO buffer, and may need to cancel that buffer, so it can be re-used.
  66. * If rewrite is true, and bits are set in the sendbufferror registers,
  67. * we'll write to the buffer, for error recovery on parity errors.
  68. */
  69. static void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
  70. {
  71. u32 piobcnt;
  72. unsigned long sbuf[4];
  73. /*
  74. * it's possible that sendbuffererror could have bits set; might
  75. * have already done this as a result of hardware error handling
  76. */
  77. piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
  78. /* read these before writing errorclear */
  79. sbuf[0] = ipath_read_kreg64(
  80. dd, dd->ipath_kregs->kr_sendbuffererror);
  81. sbuf[1] = ipath_read_kreg64(
  82. dd, dd->ipath_kregs->kr_sendbuffererror + 1);
  83. if (piobcnt > 128) {
  84. sbuf[2] = ipath_read_kreg64(
  85. dd, dd->ipath_kregs->kr_sendbuffererror + 2);
  86. sbuf[3] = ipath_read_kreg64(
  87. dd, dd->ipath_kregs->kr_sendbuffererror + 3);
  88. }
  89. if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
  90. int i;
  91. if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
  92. dd->ipath_lastcancel > jiffies) {
  93. __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
  94. "SendbufErrs %lx %lx", sbuf[0],
  95. sbuf[1]);
  96. if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
  97. printk(" %lx %lx ", sbuf[2], sbuf[3]);
  98. printk("\n");
  99. }
  100. for (i = 0; i < piobcnt; i++)
  101. if (test_bit(i, sbuf)) {
  102. if (rewrite)
  103. ipath_clrpiobuf(dd, i);
  104. ipath_disarm_piobufs(dd, i, 1);
  105. }
  106. /* ignore armlaunch errs for a bit */
  107. dd->ipath_lastcancel = jiffies+3;
  108. }
  109. }
  110. /* These are all rcv-related errors which we want to count for stats */
  111. #define E_SUM_PKTERRS \
  112. (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
  113. INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
  114. INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
  115. INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  116. INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
  117. INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
  118. /* These are all send-related errors which we want to count for stats */
  119. #define E_SUM_ERRS \
  120. (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
  121. INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  122. INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
  123. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  124. INFINIPATH_E_INVALIDADDR)
  125. /*
  126. * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
  127. * errors not related to freeze and cancelling buffers. Can't ignore
  128. * armlaunch because could get more while still cleaning up, and need
  129. * to cancel those as they happen.
  130. */
  131. #define E_SPKT_ERRS_IGNORE \
  132. (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  133. INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \
  134. INFINIPATH_E_SPKTLEN)
  135. /*
  136. * these are errors that can occur when the link changes state while
  137. * a packet is being sent or received. This doesn't cover things
  138. * like EBP or VCRC that can be the result of a sending having the
  139. * link change state, so we receive a "known bad" packet.
  140. */
  141. #define E_SUM_LINK_PKTERRS \
  142. (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  143. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  144. INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  145. INFINIPATH_E_RUNEXPCHAR)
  146. static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
  147. {
  148. u64 ignore_this_time = 0;
  149. ipath_disarm_senderrbufs(dd, 0);
  150. if ((errs & E_SUM_LINK_PKTERRS) &&
  151. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  152. /*
  153. * This can happen when SMA is trying to bring the link
  154. * up, but the IB link changes state at the "wrong" time.
  155. * The IB logic then complains that the packet isn't
  156. * valid. We don't want to confuse people, so we just
  157. * don't print them, except at debug
  158. */
  159. ipath_dbg("Ignoring packet errors %llx, because link not "
  160. "ACTIVE\n", (unsigned long long) errs);
  161. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  162. }
  163. return ignore_this_time;
  164. }
  165. /* generic hw error messages... */
  166. #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
  167. { \
  168. .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
  169. INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
  170. .msg = "TXE " #a " Memory Parity" \
  171. }
  172. #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
  173. { \
  174. .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
  175. INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
  176. .msg = "RXE " #a " Memory Parity" \
  177. }
  178. static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
  179. INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
  180. INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
  181. INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
  182. INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
  183. INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
  184. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
  185. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
  186. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
  187. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
  188. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
  189. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
  190. INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
  191. };
  192. /**
  193. * ipath_format_hwmsg - format a single hwerror message
  194. * @msg message buffer
  195. * @msgl length of message buffer
  196. * @hwmsg message to add to message buffer
  197. */
  198. static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
  199. {
  200. strlcat(msg, "[", msgl);
  201. strlcat(msg, hwmsg, msgl);
  202. strlcat(msg, "]", msgl);
  203. }
  204. /**
  205. * ipath_format_hwerrors - format hardware error messages for display
  206. * @hwerrs hardware errors bit vector
  207. * @hwerrmsgs hardware error descriptions
  208. * @nhwerrmsgs number of hwerrmsgs
  209. * @msg message buffer
  210. * @msgl message buffer length
  211. */
  212. void ipath_format_hwerrors(u64 hwerrs,
  213. const struct ipath_hwerror_msgs *hwerrmsgs,
  214. size_t nhwerrmsgs,
  215. char *msg, size_t msgl)
  216. {
  217. int i;
  218. const int glen =
  219. sizeof(ipath_generic_hwerror_msgs) /
  220. sizeof(ipath_generic_hwerror_msgs[0]);
  221. for (i=0; i<glen; i++) {
  222. if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
  223. ipath_format_hwmsg(msg, msgl,
  224. ipath_generic_hwerror_msgs[i].msg);
  225. }
  226. }
  227. for (i=0; i<nhwerrmsgs; i++) {
  228. if (hwerrs & hwerrmsgs[i].mask) {
  229. ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
  230. }
  231. }
  232. }
  233. /* return the strings for the most common link states */
  234. static char *ib_linkstate(u32 linkstate)
  235. {
  236. char *ret;
  237. switch (linkstate) {
  238. case IPATH_IBSTATE_INIT:
  239. ret = "Init";
  240. break;
  241. case IPATH_IBSTATE_ARM:
  242. ret = "Arm";
  243. break;
  244. case IPATH_IBSTATE_ACTIVE:
  245. ret = "Active";
  246. break;
  247. default:
  248. ret = "Down";
  249. }
  250. return ret;
  251. }
  252. static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
  253. ipath_err_t errs, int noprint)
  254. {
  255. u64 val;
  256. u32 ltstate, lstate;
  257. /*
  258. * even if diags are enabled, we want to notice LINKINIT, etc.
  259. * We just don't want to change the LED state, or
  260. * dd->ipath_kregs->kr_ibcctrl
  261. */
  262. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
  263. lstate = val & IPATH_IBSTATE_MASK;
  264. /*
  265. * this is confusing enough when it happens that I want to always put it
  266. * on the console and in the logs. If it was a requested state change,
  267. * we'll have already cleared the flags, so we won't print this warning
  268. */
  269. if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE)
  270. && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
  271. dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n",
  272. (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE",
  273. ib_linkstate(lstate));
  274. /*
  275. * Flush all queued sends when link went to DOWN or INIT,
  276. * to be sure that they don't block SMA and other MAD packets
  277. */
  278. ipath_cancel_sends(dd, 1);
  279. }
  280. else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
  281. lstate == IPATH_IBSTATE_ACTIVE) {
  282. /*
  283. * only print at SMA if there is a change, debug if not
  284. * (sometimes we want to know that, usually not).
  285. */
  286. if (lstate == ((unsigned) dd->ipath_lastibcstat
  287. & IPATH_IBSTATE_MASK)) {
  288. ipath_dbg("Status change intr but no change (%s)\n",
  289. ib_linkstate(lstate));
  290. }
  291. else
  292. ipath_cdbg(VERBOSE, "Unit %u link state %s, last "
  293. "was %s\n", dd->ipath_unit,
  294. ib_linkstate(lstate),
  295. ib_linkstate((unsigned)
  296. dd->ipath_lastibcstat
  297. & IPATH_IBSTATE_MASK));
  298. }
  299. else {
  300. lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
  301. if (lstate == IPATH_IBSTATE_INIT ||
  302. lstate == IPATH_IBSTATE_ARM ||
  303. lstate == IPATH_IBSTATE_ACTIVE)
  304. ipath_cdbg(VERBOSE, "Unit %u link state down"
  305. " (state 0x%x), from %s\n",
  306. dd->ipath_unit,
  307. (u32)val & IPATH_IBSTATE_MASK,
  308. ib_linkstate(lstate));
  309. else
  310. ipath_cdbg(VERBOSE, "Unit %u link state changed "
  311. "to 0x%x from down (%x)\n",
  312. dd->ipath_unit, (u32) val, lstate);
  313. }
  314. ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
  315. INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  316. lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  317. INFINIPATH_IBCS_LINKSTATE_MASK;
  318. if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
  319. ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  320. u32 last_ltstate;
  321. /*
  322. * Ignore cycling back and forth from Polling.Active
  323. * to Polling.Quiet while waiting for the other end of
  324. * the link to come up. We will cycle back and forth
  325. * between them if no cable is plugged in,
  326. * the other device is powered off or disabled, etc.
  327. */
  328. last_ltstate = (dd->ipath_lastibcstat >>
  329. INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
  330. & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  331. if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
  332. || last_ltstate ==
  333. INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  334. if (dd->ipath_ibpollcnt > 40) {
  335. dd->ipath_flags |= IPATH_NOCABLE;
  336. *dd->ipath_statusp |=
  337. IPATH_STATUS_IB_NOCABLE;
  338. } else
  339. dd->ipath_ibpollcnt++;
  340. goto skip_ibchange;
  341. }
  342. }
  343. dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */
  344. ipath_stats.sps_iblink++;
  345. if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
  346. dd->ipath_flags |= IPATH_LINKDOWN;
  347. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  348. | IPATH_LINKACTIVE |
  349. IPATH_LINKARMED);
  350. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  351. dd->ipath_lli_counter = 0;
  352. if (!noprint) {
  353. if (((dd->ipath_lastibcstat >>
  354. INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  355. INFINIPATH_IBCS_LINKSTATE_MASK)
  356. == INFINIPATH_IBCS_L_STATE_ACTIVE)
  357. /* if from up to down be more vocal */
  358. ipath_cdbg(VERBOSE,
  359. "Unit %u link now down (%s)\n",
  360. dd->ipath_unit,
  361. ipath_ibcstatus_str[ltstate]);
  362. else
  363. ipath_cdbg(VERBOSE, "Unit %u link is "
  364. "down (%s)\n", dd->ipath_unit,
  365. ipath_ibcstatus_str[ltstate]);
  366. }
  367. dd->ipath_f_setextled(dd, lstate, ltstate);
  368. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
  369. dd->ipath_flags |= IPATH_LINKACTIVE;
  370. dd->ipath_flags &=
  371. ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
  372. IPATH_LINKARMED | IPATH_NOCABLE);
  373. *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
  374. *dd->ipath_statusp |=
  375. IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
  376. dd->ipath_f_setextled(dd, lstate, ltstate);
  377. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
  378. /*
  379. * set INIT and DOWN. Down is checked by most of the other
  380. * code, but INIT is useful to know in a few places.
  381. */
  382. dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
  383. dd->ipath_flags &=
  384. ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
  385. | IPATH_NOCABLE);
  386. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  387. | IPATH_STATUS_IB_READY);
  388. dd->ipath_f_setextled(dd, lstate, ltstate);
  389. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
  390. dd->ipath_flags |= IPATH_LINKARMED;
  391. dd->ipath_flags &=
  392. ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
  393. IPATH_LINKACTIVE | IPATH_NOCABLE);
  394. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  395. | IPATH_STATUS_IB_READY);
  396. dd->ipath_f_setextled(dd, lstate, ltstate);
  397. } else {
  398. if (!noprint)
  399. ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
  400. dd->ipath_unit,
  401. ipath_ibcstatus_str[ltstate], ltstate);
  402. }
  403. skip_ibchange:
  404. dd->ipath_lastibcstat = val;
  405. }
  406. static void handle_supp_msgs(struct ipath_devdata *dd,
  407. unsigned supp_msgs, char msg[512])
  408. {
  409. /*
  410. * Print the message unless it's ibc status change only, which
  411. * happens so often we never want to count it.
  412. */
  413. if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
  414. int iserr;
  415. iserr = ipath_decode_err(msg, sizeof msg,
  416. dd->ipath_lasterror &
  417. ~INFINIPATH_E_IBSTATUSCHANGED);
  418. if (dd->ipath_lasterror &
  419. ~(INFINIPATH_E_RRCVEGRFULL |
  420. INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
  421. ipath_dev_err(dd, "Suppressed %u messages for "
  422. "fast-repeating errors (%s) (%llx)\n",
  423. supp_msgs, msg,
  424. (unsigned long long)
  425. dd->ipath_lasterror);
  426. else {
  427. /*
  428. * rcvegrfull and rcvhdrqfull are "normal", for some
  429. * types of processes (mostly benchmarks) that send
  430. * huge numbers of messages, while not processing
  431. * them. So only complain about these at debug
  432. * level.
  433. */
  434. if (iserr)
  435. ipath_dbg("Suppressed %u messages for %s\n",
  436. supp_msgs, msg);
  437. else
  438. ipath_cdbg(ERRPKT,
  439. "Suppressed %u messages for %s\n",
  440. supp_msgs, msg);
  441. }
  442. }
  443. }
  444. static unsigned handle_frequent_errors(struct ipath_devdata *dd,
  445. ipath_err_t errs, char msg[512],
  446. int *noprint)
  447. {
  448. unsigned long nc;
  449. static unsigned long nextmsg_time;
  450. static unsigned nmsgs, supp_msgs;
  451. /*
  452. * Throttle back "fast" messages to no more than 10 per 5 seconds.
  453. * This isn't perfect, but it's a reasonable heuristic. If we get
  454. * more than 10, give a 6x longer delay.
  455. */
  456. nc = jiffies;
  457. if (nmsgs > 10) {
  458. if (time_before(nc, nextmsg_time)) {
  459. *noprint = 1;
  460. if (!supp_msgs++)
  461. nextmsg_time = nc + HZ * 3;
  462. }
  463. else if (supp_msgs) {
  464. handle_supp_msgs(dd, supp_msgs, msg);
  465. supp_msgs = 0;
  466. nmsgs = 0;
  467. }
  468. }
  469. else if (!nmsgs++ || time_after(nc, nextmsg_time))
  470. nextmsg_time = nc + HZ / 2;
  471. return supp_msgs;
  472. }
  473. static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
  474. {
  475. char msg[512];
  476. u64 ignore_this_time = 0;
  477. int i, iserr = 0;
  478. int chkerrpkts = 0, noprint = 0;
  479. unsigned supp_msgs;
  480. int log_idx;
  481. supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
  482. /* don't report errors that are masked */
  483. errs &= ~dd->ipath_maskederrs;
  484. /* do these first, they are most important */
  485. if (errs & INFINIPATH_E_HARDWARE) {
  486. /* reuse same msg buf */
  487. dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
  488. } else {
  489. u64 mask;
  490. for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) {
  491. mask = dd->ipath_eep_st_masks[log_idx].errs_to_log;
  492. if (errs & mask)
  493. ipath_inc_eeprom_err(dd, log_idx, 1);
  494. }
  495. }
  496. if (!noprint && (errs & ~dd->ipath_e_bitsextant))
  497. ipath_dev_err(dd, "error interrupt with unknown errors "
  498. "%llx set\n", (unsigned long long)
  499. (errs & ~dd->ipath_e_bitsextant));
  500. if (errs & E_SUM_ERRS)
  501. ignore_this_time = handle_e_sum_errs(dd, errs);
  502. else if ((errs & E_SUM_LINK_PKTERRS) &&
  503. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  504. /*
  505. * This can happen when SMA is trying to bring the link
  506. * up, but the IB link changes state at the "wrong" time.
  507. * The IB logic then complains that the packet isn't
  508. * valid. We don't want to confuse people, so we just
  509. * don't print them, except at debug
  510. */
  511. ipath_dbg("Ignoring packet errors %llx, because link not "
  512. "ACTIVE\n", (unsigned long long) errs);
  513. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  514. }
  515. if (supp_msgs == 250000) {
  516. int s_iserr;
  517. /*
  518. * It's not entirely reasonable assuming that the errors set
  519. * in the last clear period are all responsible for the
  520. * problem, but the alternative is to assume it's the only
  521. * ones on this particular interrupt, which also isn't great
  522. */
  523. dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
  524. dd->ipath_errormask &= ~dd->ipath_maskederrs;
  525. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
  526. dd->ipath_errormask);
  527. s_iserr = ipath_decode_err(msg, sizeof msg,
  528. dd->ipath_maskederrs);
  529. if (dd->ipath_maskederrs &
  530. ~(INFINIPATH_E_RRCVEGRFULL |
  531. INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
  532. ipath_dev_err(dd, "Temporarily disabling "
  533. "error(s) %llx reporting; too frequent (%s)\n",
  534. (unsigned long long)dd->ipath_maskederrs,
  535. msg);
  536. else {
  537. /*
  538. * rcvegrfull and rcvhdrqfull are "normal",
  539. * for some types of processes (mostly benchmarks)
  540. * that send huge numbers of messages, while not
  541. * processing them. So only complain about
  542. * these at debug level.
  543. */
  544. if (s_iserr)
  545. ipath_dbg("Temporarily disabling reporting "
  546. "too frequent queue full errors (%s)\n",
  547. msg);
  548. else
  549. ipath_cdbg(ERRPKT,
  550. "Temporarily disabling reporting too"
  551. " frequent packet errors (%s)\n",
  552. msg);
  553. }
  554. /*
  555. * Re-enable the masked errors after around 3 minutes. in
  556. * ipath_get_faststats(). If we have a series of fast
  557. * repeating but different errors, the interval will keep
  558. * stretching out, but that's OK, as that's pretty
  559. * catastrophic.
  560. */
  561. dd->ipath_unmasktime = jiffies + HZ * 180;
  562. }
  563. ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
  564. if (ignore_this_time)
  565. errs &= ~ignore_this_time;
  566. if (errs & ~dd->ipath_lasterror) {
  567. errs &= ~dd->ipath_lasterror;
  568. /* never suppress duplicate hwerrors or ibstatuschange */
  569. dd->ipath_lasterror |= errs &
  570. ~(INFINIPATH_E_HARDWARE |
  571. INFINIPATH_E_IBSTATUSCHANGED);
  572. }
  573. /* likely due to cancel, so suppress */
  574. if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) &&
  575. dd->ipath_lastcancel > jiffies) {
  576. ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n");
  577. errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN);
  578. }
  579. if (!errs)
  580. return 0;
  581. if (!noprint)
  582. /*
  583. * the ones we mask off are handled specially below or above
  584. */
  585. ipath_decode_err(msg, sizeof msg,
  586. errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
  587. INFINIPATH_E_RRCVEGRFULL |
  588. INFINIPATH_E_RRCVHDRFULL |
  589. INFINIPATH_E_HARDWARE));
  590. else
  591. /* so we don't need if (!noprint) at strlcat's below */
  592. *msg = 0;
  593. if (errs & E_SUM_PKTERRS) {
  594. ipath_stats.sps_pkterrs++;
  595. chkerrpkts = 1;
  596. }
  597. if (errs & E_SUM_ERRS)
  598. ipath_stats.sps_errs++;
  599. if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
  600. ipath_stats.sps_crcerrs++;
  601. chkerrpkts = 1;
  602. }
  603. iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS);
  604. /*
  605. * We don't want to print these two as they happen, or we can make
  606. * the situation even worse, because it takes so long to print
  607. * messages to serial consoles. Kernel ports get printed from
  608. * fast_stats, no more than every 5 seconds, user ports get printed
  609. * on close
  610. */
  611. if (errs & INFINIPATH_E_RRCVHDRFULL) {
  612. u32 hd, tl;
  613. ipath_stats.sps_hdrqfull++;
  614. for (i = 0; i < dd->ipath_cfgports; i++) {
  615. struct ipath_portdata *pd = dd->ipath_pd[i];
  616. if (i == 0) {
  617. hd = dd->ipath_port0head;
  618. tl = (u32) le64_to_cpu(
  619. *dd->ipath_hdrqtailptr);
  620. } else if (pd && pd->port_cnt &&
  621. pd->port_rcvhdrtail_kvaddr) {
  622. /*
  623. * don't report same point multiple times,
  624. * except kernel
  625. */
  626. tl = *(u64 *) pd->port_rcvhdrtail_kvaddr;
  627. if (tl == dd->ipath_lastrcvhdrqtails[i])
  628. continue;
  629. hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
  630. i);
  631. } else
  632. continue;
  633. if (hd == (tl + 1) ||
  634. (!hd && tl == dd->ipath_hdrqlast)) {
  635. if (i == 0)
  636. chkerrpkts = 1;
  637. dd->ipath_lastrcvhdrqtails[i] = tl;
  638. pd->port_hdrqfull++;
  639. if (test_bit(IPATH_PORT_WAITING_OVERFLOW,
  640. &pd->port_flag)) {
  641. clear_bit(
  642. IPATH_PORT_WAITING_OVERFLOW,
  643. &pd->port_flag);
  644. set_bit(
  645. IPATH_PORT_WAITING_OVERFLOW,
  646. &pd->int_flag);
  647. wake_up_interruptible(
  648. &pd->port_wait);
  649. }
  650. }
  651. }
  652. }
  653. if (errs & INFINIPATH_E_RRCVEGRFULL) {
  654. /*
  655. * since this is of less importance and not likely to
  656. * happen without also getting hdrfull, only count
  657. * occurrences; don't check each port (or even the kernel
  658. * vs user)
  659. */
  660. ipath_stats.sps_etidfull++;
  661. if (dd->ipath_port0head !=
  662. (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
  663. chkerrpkts = 1;
  664. }
  665. /*
  666. * do this before IBSTATUSCHANGED, in case both bits set in a single
  667. * interrupt; we want the STATUSCHANGE to "win", so we do our
  668. * internal copy of state machine correctly
  669. */
  670. if (errs & INFINIPATH_E_RIBLOSTLINK) {
  671. /*
  672. * force through block below
  673. */
  674. errs |= INFINIPATH_E_IBSTATUSCHANGED;
  675. ipath_stats.sps_iblink++;
  676. dd->ipath_flags |= IPATH_LINKDOWN;
  677. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  678. | IPATH_LINKARMED | IPATH_LINKACTIVE);
  679. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  680. if (!noprint) {
  681. u64 st = ipath_read_kreg64(
  682. dd, dd->ipath_kregs->kr_ibcstatus);
  683. ipath_dbg("Lost link, link now down (%s)\n",
  684. ipath_ibcstatus_str[st & 0xf]);
  685. }
  686. }
  687. if (errs & INFINIPATH_E_IBSTATUSCHANGED)
  688. handle_e_ibstatuschanged(dd, errs, noprint);
  689. if (errs & INFINIPATH_E_RESET) {
  690. if (!noprint)
  691. ipath_dev_err(dd, "Got reset, requires re-init "
  692. "(unload and reload driver)\n");
  693. dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
  694. /* mark as having had error */
  695. *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
  696. *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
  697. }
  698. if (!noprint && *msg) {
  699. if (iserr)
  700. ipath_dev_err(dd, "%s error\n", msg);
  701. else
  702. dev_info(&dd->pcidev->dev, "%s packet problems\n",
  703. msg);
  704. }
  705. if (dd->ipath_state_wanted & dd->ipath_flags) {
  706. ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
  707. "waking\n", dd->ipath_state_wanted,
  708. dd->ipath_flags);
  709. wake_up_interruptible(&ipath_state_wait);
  710. }
  711. return chkerrpkts;
  712. }
  713. /*
  714. * try to cleanup as much as possible for anything that might have gone
  715. * wrong while in freeze mode, such as pio buffers being written by user
  716. * processes (causing armlaunch), send errors due to going into freeze mode,
  717. * etc., and try to avoid causing extra interrupts while doing so.
  718. * Forcibly update the in-memory pioavail register copies after cleanup
  719. * because the chip won't do it for anything changing while in freeze mode
  720. * (we don't want to wait for the next pio buffer state change).
  721. * Make sure that we don't lose any important interrupts by using the chip
  722. * feature that says that writing 0 to a bit in *clear that is set in
  723. * *status will cause an interrupt to be generated again (if allowed by
  724. * the *mask value).
  725. */
  726. void ipath_clear_freeze(struct ipath_devdata *dd)
  727. {
  728. int i, im;
  729. __le64 val;
  730. /* disable error interrupts, to avoid confusion */
  731. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL);
  732. /* also disable interrupts; errormask is sometimes overwriten */
  733. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
  734. /*
  735. * clear all sends, because they have may been
  736. * completed by usercode while in freeze mode, and
  737. * therefore would not be sent, and eventually
  738. * might cause the process to run out of bufs
  739. */
  740. ipath_cancel_sends(dd, 0);
  741. ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
  742. dd->ipath_control);
  743. /* ensure pio avail updates continue */
  744. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  745. dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
  746. ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
  747. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  748. dd->ipath_sendctrl);
  749. /*
  750. * We just enabled pioavailupdate, so dma copy is almost certainly
  751. * not yet right, so read the registers directly. Similar to init
  752. */
  753. for (i = 0; i < dd->ipath_pioavregs; i++) {
  754. /* deal with 6110 chip bug */
  755. im = i > 3 ? ((i&1) ? i-1 : i+1) : i;
  756. val = ipath_read_kreg64(dd, (0x1000/sizeof(u64))+im);
  757. dd->ipath_pioavailregs_dma[i] = dd->ipath_pioavailshadow[i]
  758. = le64_to_cpu(val);
  759. }
  760. /*
  761. * force new interrupt if any hwerr, error or interrupt bits are
  762. * still set, and clear "safe" send packet errors related to freeze
  763. * and cancelling sends. Re-enable error interrupts before possible
  764. * force of re-interrupt on pending interrupts.
  765. */
  766. ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL);
  767. ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
  768. E_SPKT_ERRS_IGNORE);
  769. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
  770. dd->ipath_errormask);
  771. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL);
  772. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
  773. }
  774. /* this is separate to allow for better optimization of ipath_intr() */
  775. static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
  776. {
  777. /*
  778. * sometimes happen during driver init and unload, don't want
  779. * to process any interrupts at that point
  780. */
  781. /* this is just a bandaid, not a fix, if something goes badly
  782. * wrong */
  783. if (++*unexpectp > 100) {
  784. if (++*unexpectp > 105) {
  785. /*
  786. * ok, we must be taking somebody else's interrupts,
  787. * due to a messed up mptable and/or PIRQ table, so
  788. * unregister the interrupt. We've seen this during
  789. * linuxbios development work, and it may happen in
  790. * the future again.
  791. */
  792. if (dd->pcidev && dd->ipath_irq) {
  793. ipath_dev_err(dd, "Now %u unexpected "
  794. "interrupts, unregistering "
  795. "interrupt handler\n",
  796. *unexpectp);
  797. ipath_dbg("free_irq of irq %d\n",
  798. dd->ipath_irq);
  799. dd->ipath_f_free_irq(dd);
  800. }
  801. }
  802. if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
  803. ipath_dev_err(dd, "%u unexpected interrupts, "
  804. "disabling interrupts completely\n",
  805. *unexpectp);
  806. /*
  807. * disable all interrupts, something is very wrong
  808. */
  809. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
  810. 0ULL);
  811. }
  812. } else if (*unexpectp > 1)
  813. ipath_dbg("Interrupt when not ready, should not happen, "
  814. "ignoring\n");
  815. }
  816. static void ipath_bad_regread(struct ipath_devdata *dd)
  817. {
  818. static int allbits;
  819. /* separate routine, for better optimization of ipath_intr() */
  820. /*
  821. * We print the message and disable interrupts, in hope of
  822. * having a better chance of debugging the problem.
  823. */
  824. ipath_dev_err(dd,
  825. "Read of interrupt status failed (all bits set)\n");
  826. if (allbits++) {
  827. /* disable all interrupts, something is very wrong */
  828. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
  829. if (allbits == 2) {
  830. ipath_dev_err(dd, "Still bad interrupt status, "
  831. "unregistering interrupt\n");
  832. dd->ipath_f_free_irq(dd);
  833. } else if (allbits > 2) {
  834. if ((allbits % 10000) == 0)
  835. printk(".");
  836. } else
  837. ipath_dev_err(dd, "Disabling interrupts, "
  838. "multiple errors\n");
  839. }
  840. }
  841. static void handle_port_pioavail(struct ipath_devdata *dd)
  842. {
  843. u32 i;
  844. /*
  845. * start from port 1, since for now port 0 is never using
  846. * wait_event for PIO
  847. */
  848. for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
  849. struct ipath_portdata *pd = dd->ipath_pd[i];
  850. if (pd && pd->port_cnt &&
  851. dd->ipath_portpiowait & (1U << i)) {
  852. clear_bit(i, &dd->ipath_portpiowait);
  853. if (test_bit(IPATH_PORT_WAITING_PIO,
  854. &pd->port_flag)) {
  855. clear_bit(IPATH_PORT_WAITING_PIO,
  856. &pd->port_flag);
  857. wake_up_interruptible(&pd->port_wait);
  858. }
  859. }
  860. }
  861. }
  862. static void handle_layer_pioavail(struct ipath_devdata *dd)
  863. {
  864. int ret;
  865. ret = ipath_ib_piobufavail(dd->verbs_dev);
  866. if (ret > 0)
  867. goto set;
  868. return;
  869. set:
  870. set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  871. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  872. dd->ipath_sendctrl);
  873. }
  874. /*
  875. * Handle receive interrupts for user ports; this means a user
  876. * process was waiting for a packet to arrive, and didn't want
  877. * to poll
  878. */
  879. static void handle_urcv(struct ipath_devdata *dd, u32 istat)
  880. {
  881. u64 portr;
  882. int i;
  883. int rcvdint = 0;
  884. portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
  885. dd->ipath_i_rcvavail_mask)
  886. | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
  887. dd->ipath_i_rcvurg_mask);
  888. for (i = 1; i < dd->ipath_cfgports; i++) {
  889. struct ipath_portdata *pd = dd->ipath_pd[i];
  890. if (portr & (1 << i) && pd && pd->port_cnt) {
  891. if (test_bit(IPATH_PORT_WAITING_RCV,
  892. &pd->port_flag)) {
  893. clear_bit(IPATH_PORT_WAITING_RCV,
  894. &pd->port_flag);
  895. set_bit(IPATH_PORT_WAITING_RCV,
  896. &pd->int_flag);
  897. clear_bit(i + INFINIPATH_R_INTRAVAIL_SHIFT,
  898. &dd->ipath_rcvctrl);
  899. wake_up_interruptible(&pd->port_wait);
  900. rcvdint = 1;
  901. } else if (test_bit(IPATH_PORT_WAITING_URG,
  902. &pd->port_flag)) {
  903. clear_bit(IPATH_PORT_WAITING_URG,
  904. &pd->port_flag);
  905. set_bit(IPATH_PORT_WAITING_URG,
  906. &pd->int_flag);
  907. wake_up_interruptible(&pd->port_wait);
  908. }
  909. }
  910. }
  911. if (rcvdint) {
  912. /* only want to take one interrupt, so turn off the rcv
  913. * interrupt for all the ports that we did the wakeup on
  914. * (but never for kernel port)
  915. */
  916. ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
  917. dd->ipath_rcvctrl);
  918. }
  919. }
  920. irqreturn_t ipath_intr(int irq, void *data)
  921. {
  922. struct ipath_devdata *dd = data;
  923. u32 istat, chk0rcv = 0;
  924. ipath_err_t estat = 0;
  925. irqreturn_t ret;
  926. static unsigned unexpected = 0;
  927. static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
  928. (1U<<INFINIPATH_I_RCVURG_SHIFT);
  929. ipath_stats.sps_ints++;
  930. if (dd->ipath_int_counter != (u32) -1)
  931. dd->ipath_int_counter++;
  932. if (!(dd->ipath_flags & IPATH_PRESENT)) {
  933. /*
  934. * This return value is not great, but we do not want the
  935. * interrupt core code to remove our interrupt handler
  936. * because we don't appear to be handling an interrupt
  937. * during a chip reset.
  938. */
  939. return IRQ_HANDLED;
  940. }
  941. /*
  942. * this needs to be flags&initted, not statusp, so we keep
  943. * taking interrupts even after link goes down, etc.
  944. * Also, we *must* clear the interrupt at some point, or we won't
  945. * take it again, which can be real bad for errors, etc...
  946. */
  947. if (!(dd->ipath_flags & IPATH_INITTED)) {
  948. ipath_bad_intr(dd, &unexpected);
  949. ret = IRQ_NONE;
  950. goto bail;
  951. }
  952. istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
  953. if (unlikely(!istat)) {
  954. ipath_stats.sps_nullintr++;
  955. ret = IRQ_NONE; /* not our interrupt, or already handled */
  956. goto bail;
  957. }
  958. if (unlikely(istat == -1)) {
  959. ipath_bad_regread(dd);
  960. /* don't know if it was our interrupt or not */
  961. ret = IRQ_NONE;
  962. goto bail;
  963. }
  964. if (unexpected)
  965. unexpected = 0;
  966. if (unlikely(istat & ~dd->ipath_i_bitsextant))
  967. ipath_dev_err(dd,
  968. "interrupt with unknown interrupts %x set\n",
  969. istat & (u32) ~ dd->ipath_i_bitsextant);
  970. else
  971. ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
  972. if (unlikely(istat & INFINIPATH_I_ERROR)) {
  973. ipath_stats.sps_errints++;
  974. estat = ipath_read_kreg64(dd,
  975. dd->ipath_kregs->kr_errorstatus);
  976. if (!estat)
  977. dev_info(&dd->pcidev->dev, "error interrupt (%x), "
  978. "but no error bits set!\n", istat);
  979. else if (estat == -1LL)
  980. /*
  981. * should we try clearing all, or hope next read
  982. * works?
  983. */
  984. ipath_dev_err(dd, "Read of error status failed "
  985. "(all bits set); ignoring\n");
  986. else
  987. if (handle_errors(dd, estat))
  988. /* force calling ipath_kreceive() */
  989. chk0rcv = 1;
  990. }
  991. if (istat & INFINIPATH_I_GPIO) {
  992. /*
  993. * GPIO interrupts fall in two broad classes:
  994. * GPIO_2 indicates (on some HT4xx boards) that a packet
  995. * has arrived for Port 0. Checking for this
  996. * is controlled by flag IPATH_GPIO_INTR.
  997. * GPIO_3..5 on IBA6120 Rev2 chips indicate errors
  998. * that we need to count. Checking for this
  999. * is controlled by flag IPATH_GPIO_ERRINTRS.
  1000. */
  1001. u32 gpiostatus;
  1002. u32 to_clear = 0;
  1003. gpiostatus = ipath_read_kreg32(
  1004. dd, dd->ipath_kregs->kr_gpio_status);
  1005. /* First the error-counter case.
  1006. */
  1007. if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
  1008. (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
  1009. /* want to clear the bits we see asserted. */
  1010. to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
  1011. /*
  1012. * Count appropriately, clear bits out of our copy,
  1013. * as they have been "handled".
  1014. */
  1015. if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
  1016. ipath_dbg("FlowCtl on UnsupVL\n");
  1017. dd->ipath_rxfc_unsupvl_errs++;
  1018. }
  1019. if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
  1020. ipath_dbg("Overrun Threshold exceeded\n");
  1021. dd->ipath_overrun_thresh_errs++;
  1022. }
  1023. if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
  1024. ipath_dbg("Local Link Integrity error\n");
  1025. dd->ipath_lli_errs++;
  1026. }
  1027. gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
  1028. }
  1029. /* Now the Port0 Receive case */
  1030. if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
  1031. (dd->ipath_flags & IPATH_GPIO_INTR)) {
  1032. /*
  1033. * GPIO status bit 2 is set, and we expected it.
  1034. * clear it and indicate in p0bits.
  1035. * This probably only happens if a Port0 pkt
  1036. * arrives at _just_ the wrong time, and we
  1037. * handle that by seting chk0rcv;
  1038. */
  1039. to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
  1040. gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
  1041. chk0rcv = 1;
  1042. }
  1043. if (gpiostatus) {
  1044. /*
  1045. * Some unexpected bits remain. If they could have
  1046. * caused the interrupt, complain and clear.
  1047. * MEA: this is almost certainly non-ideal.
  1048. * we should look into auto-disable of unexpected
  1049. * GPIO interrupts, possibly on a "three strikes"
  1050. * basis.
  1051. */
  1052. const u32 mask = (u32) dd->ipath_gpio_mask;
  1053. if (mask & gpiostatus) {
  1054. ipath_dbg("Unexpected GPIO IRQ bits %x\n",
  1055. gpiostatus & mask);
  1056. to_clear |= (gpiostatus & mask);
  1057. }
  1058. }
  1059. if (to_clear) {
  1060. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  1061. (u64) to_clear);
  1062. }
  1063. }
  1064. chk0rcv |= istat & port0rbits;
  1065. /*
  1066. * Clear the interrupt bits we found set, unless they are receive
  1067. * related, in which case we already cleared them above, and don't
  1068. * want to clear them again, because we might lose an interrupt.
  1069. * Clear it early, so we "know" know the chip will have seen this by
  1070. * the time we process the queue, and will re-interrupt if necessary.
  1071. * The processor itself won't take the interrupt again until we return.
  1072. */
  1073. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  1074. /*
  1075. * handle port0 receive before checking for pio buffers available,
  1076. * since receives can overflow; piobuf waiters can afford a few
  1077. * extra cycles, since they were waiting anyway, and user's waiting
  1078. * for receive are at the bottom.
  1079. */
  1080. if (chk0rcv) {
  1081. ipath_kreceive(dd);
  1082. istat &= ~port0rbits;
  1083. }
  1084. if (istat & ((dd->ipath_i_rcvavail_mask <<
  1085. INFINIPATH_I_RCVAVAIL_SHIFT)
  1086. | (dd->ipath_i_rcvurg_mask <<
  1087. INFINIPATH_I_RCVURG_SHIFT)))
  1088. handle_urcv(dd, istat);
  1089. if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
  1090. clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  1091. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  1092. dd->ipath_sendctrl);
  1093. if (dd->ipath_portpiowait)
  1094. handle_port_pioavail(dd);
  1095. handle_layer_pioavail(dd);
  1096. }
  1097. ret = IRQ_HANDLED;
  1098. bail:
  1099. return ret;
  1100. }