sata_sil.c 19 KB

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  1. /*
  2. * sata_sil.c - Silicon Image SATA
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2003-2005 Red Hat, Inc.
  9. * Copyright 2003 Benjamin Herrenschmidt
  10. *
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2, or (at your option)
  15. * any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; see the file COPYING. If not, write to
  24. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  25. *
  26. *
  27. * libata documentation is available via 'make {ps|pdf}docs',
  28. * as Documentation/DocBook/libata.*
  29. *
  30. * Documentation for SiI 3112:
  31. * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  32. *
  33. * Other errata and documentation available under NDA.
  34. *
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/pci.h>
  39. #include <linux/init.h>
  40. #include <linux/blkdev.h>
  41. #include <linux/delay.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/device.h>
  44. #include <scsi/scsi_host.h>
  45. #include <linux/libata.h>
  46. #define DRV_NAME "sata_sil"
  47. #define DRV_VERSION "2.2"
  48. enum {
  49. SIL_MMIO_BAR = 5,
  50. /*
  51. * host flags
  52. */
  53. SIL_FLAG_NO_SATA_IRQ = (1 << 28),
  54. SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
  55. SIL_FLAG_MOD15WRITE = (1 << 30),
  56. SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  57. ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
  58. /*
  59. * Controller IDs
  60. */
  61. sil_3112 = 0,
  62. sil_3112_no_sata_irq = 1,
  63. sil_3512 = 2,
  64. sil_3114 = 3,
  65. /*
  66. * Register offsets
  67. */
  68. SIL_SYSCFG = 0x48,
  69. /*
  70. * Register bits
  71. */
  72. /* SYSCFG */
  73. SIL_MASK_IDE0_INT = (1 << 22),
  74. SIL_MASK_IDE1_INT = (1 << 23),
  75. SIL_MASK_IDE2_INT = (1 << 24),
  76. SIL_MASK_IDE3_INT = (1 << 25),
  77. SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
  78. SIL_MASK_4PORT = SIL_MASK_2PORT |
  79. SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
  80. /* BMDMA/BMDMA2 */
  81. SIL_INTR_STEERING = (1 << 1),
  82. SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
  83. SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
  84. SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
  85. SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
  86. SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
  87. SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
  88. SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
  89. SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
  90. SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
  91. SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
  92. /* SIEN */
  93. SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
  94. /*
  95. * Others
  96. */
  97. SIL_QUIRK_MOD15WRITE = (1 << 0),
  98. SIL_QUIRK_UDMA5MAX = (1 << 1),
  99. };
  100. static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  101. #ifdef CONFIG_PM
  102. static int sil_pci_device_resume(struct pci_dev *pdev);
  103. #endif
  104. static void sil_dev_config(struct ata_device *dev);
  105. static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
  106. static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
  107. static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed);
  108. static void sil_freeze(struct ata_port *ap);
  109. static void sil_thaw(struct ata_port *ap);
  110. static const struct pci_device_id sil_pci_tbl[] = {
  111. { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
  112. { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
  113. { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
  114. { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
  115. { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
  116. { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
  117. { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
  118. { } /* terminate list */
  119. };
  120. /* TODO firmware versions should be added - eric */
  121. static const struct sil_drivelist {
  122. const char * product;
  123. unsigned int quirk;
  124. } sil_blacklist [] = {
  125. { "ST320012AS", SIL_QUIRK_MOD15WRITE },
  126. { "ST330013AS", SIL_QUIRK_MOD15WRITE },
  127. { "ST340017AS", SIL_QUIRK_MOD15WRITE },
  128. { "ST360015AS", SIL_QUIRK_MOD15WRITE },
  129. { "ST380023AS", SIL_QUIRK_MOD15WRITE },
  130. { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
  131. { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
  132. { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
  133. { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
  134. { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
  135. { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
  136. { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
  137. { }
  138. };
  139. static struct pci_driver sil_pci_driver = {
  140. .name = DRV_NAME,
  141. .id_table = sil_pci_tbl,
  142. .probe = sil_init_one,
  143. .remove = ata_pci_remove_one,
  144. #ifdef CONFIG_PM
  145. .suspend = ata_pci_device_suspend,
  146. .resume = sil_pci_device_resume,
  147. #endif
  148. };
  149. static struct scsi_host_template sil_sht = {
  150. .module = THIS_MODULE,
  151. .name = DRV_NAME,
  152. .ioctl = ata_scsi_ioctl,
  153. .queuecommand = ata_scsi_queuecmd,
  154. .can_queue = ATA_DEF_QUEUE,
  155. .this_id = ATA_SHT_THIS_ID,
  156. .sg_tablesize = LIBATA_MAX_PRD,
  157. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  158. .emulated = ATA_SHT_EMULATED,
  159. .use_clustering = ATA_SHT_USE_CLUSTERING,
  160. .proc_name = DRV_NAME,
  161. .dma_boundary = ATA_DMA_BOUNDARY,
  162. .slave_configure = ata_scsi_slave_config,
  163. .slave_destroy = ata_scsi_slave_destroy,
  164. .bios_param = ata_std_bios_param,
  165. };
  166. static const struct ata_port_operations sil_ops = {
  167. .port_disable = ata_port_disable,
  168. .dev_config = sil_dev_config,
  169. .tf_load = ata_tf_load,
  170. .tf_read = ata_tf_read,
  171. .check_status = ata_check_status,
  172. .exec_command = ata_exec_command,
  173. .dev_select = ata_std_dev_select,
  174. .set_mode = sil_set_mode,
  175. .bmdma_setup = ata_bmdma_setup,
  176. .bmdma_start = ata_bmdma_start,
  177. .bmdma_stop = ata_bmdma_stop,
  178. .bmdma_status = ata_bmdma_status,
  179. .qc_prep = ata_qc_prep,
  180. .qc_issue = ata_qc_issue_prot,
  181. .data_xfer = ata_data_xfer,
  182. .freeze = sil_freeze,
  183. .thaw = sil_thaw,
  184. .error_handler = ata_bmdma_error_handler,
  185. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  186. .irq_clear = ata_bmdma_irq_clear,
  187. .irq_on = ata_irq_on,
  188. .irq_ack = ata_irq_ack,
  189. .scr_read = sil_scr_read,
  190. .scr_write = sil_scr_write,
  191. .port_start = ata_port_start,
  192. };
  193. static const struct ata_port_info sil_port_info[] = {
  194. /* sil_3112 */
  195. {
  196. .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
  197. .pio_mask = 0x1f, /* pio0-4 */
  198. .mwdma_mask = 0x07, /* mwdma0-2 */
  199. .udma_mask = ATA_UDMA5,
  200. .port_ops = &sil_ops,
  201. },
  202. /* sil_3112_no_sata_irq */
  203. {
  204. .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
  205. SIL_FLAG_NO_SATA_IRQ,
  206. .pio_mask = 0x1f, /* pio0-4 */
  207. .mwdma_mask = 0x07, /* mwdma0-2 */
  208. .udma_mask = ATA_UDMA5,
  209. .port_ops = &sil_ops,
  210. },
  211. /* sil_3512 */
  212. {
  213. .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
  214. .pio_mask = 0x1f, /* pio0-4 */
  215. .mwdma_mask = 0x07, /* mwdma0-2 */
  216. .udma_mask = ATA_UDMA5,
  217. .port_ops = &sil_ops,
  218. },
  219. /* sil_3114 */
  220. {
  221. .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
  222. .pio_mask = 0x1f, /* pio0-4 */
  223. .mwdma_mask = 0x07, /* mwdma0-2 */
  224. .udma_mask = ATA_UDMA5,
  225. .port_ops = &sil_ops,
  226. },
  227. };
  228. /* per-port register offsets */
  229. /* TODO: we can probably calculate rather than use a table */
  230. static const struct {
  231. unsigned long tf; /* ATA taskfile register block */
  232. unsigned long ctl; /* ATA control/altstatus register block */
  233. unsigned long bmdma; /* DMA register block */
  234. unsigned long bmdma2; /* DMA register block #2 */
  235. unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
  236. unsigned long scr; /* SATA control register block */
  237. unsigned long sien; /* SATA Interrupt Enable register */
  238. unsigned long xfer_mode;/* data transfer mode register */
  239. unsigned long sfis_cfg; /* SATA FIS reception config register */
  240. } sil_port[] = {
  241. /* port 0 ... */
  242. /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
  243. { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
  244. { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
  245. { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
  246. { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
  247. /* ... port 3 */
  248. };
  249. MODULE_AUTHOR("Jeff Garzik");
  250. MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
  251. MODULE_LICENSE("GPL");
  252. MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
  253. MODULE_VERSION(DRV_VERSION);
  254. static int slow_down = 0;
  255. module_param(slow_down, int, 0444);
  256. MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
  257. static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
  258. {
  259. u8 cache_line = 0;
  260. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
  261. return cache_line;
  262. }
  263. /**
  264. * sil_set_mode - wrap set_mode functions
  265. * @ap: port to set up
  266. * @r_failed: returned device when we fail
  267. *
  268. * Wrap the libata method for device setup as after the setup we need
  269. * to inspect the results and do some configuration work
  270. */
  271. static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed)
  272. {
  273. struct ata_host *host = ap->host;
  274. struct ata_device *dev;
  275. void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
  276. void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
  277. u32 tmp, dev_mode[2];
  278. unsigned int i;
  279. int rc;
  280. rc = ata_do_set_mode(ap, r_failed);
  281. if (rc)
  282. return rc;
  283. for (i = 0; i < 2; i++) {
  284. dev = &ap->device[i];
  285. if (!ata_dev_enabled(dev))
  286. dev_mode[i] = 0; /* PIO0/1/2 */
  287. else if (dev->flags & ATA_DFLAG_PIO)
  288. dev_mode[i] = 1; /* PIO3/4 */
  289. else
  290. dev_mode[i] = 3; /* UDMA */
  291. /* value 2 indicates MDMA */
  292. }
  293. tmp = readl(addr);
  294. tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
  295. tmp |= dev_mode[0];
  296. tmp |= (dev_mode[1] << 4);
  297. writel(tmp, addr);
  298. readl(addr); /* flush */
  299. return 0;
  300. }
  301. static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
  302. {
  303. void __iomem *offset = ap->ioaddr.scr_addr;
  304. switch (sc_reg) {
  305. case SCR_STATUS:
  306. return offset + 4;
  307. case SCR_ERROR:
  308. return offset + 8;
  309. case SCR_CONTROL:
  310. return offset;
  311. default:
  312. /* do nothing */
  313. break;
  314. }
  315. return NULL;
  316. }
  317. static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
  318. {
  319. void __iomem *mmio = sil_scr_addr(ap, sc_reg);
  320. if (mmio) {
  321. *val = readl(mmio);
  322. return 0;
  323. }
  324. return -EINVAL;
  325. }
  326. static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
  327. {
  328. void __iomem *mmio = sil_scr_addr(ap, sc_reg);
  329. if (mmio) {
  330. writel(val, mmio);
  331. return 0;
  332. }
  333. return -EINVAL;
  334. }
  335. static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
  336. {
  337. struct ata_eh_info *ehi = &ap->eh_info;
  338. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
  339. u8 status;
  340. if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
  341. u32 serror;
  342. /* SIEN doesn't mask SATA IRQs on some 3112s. Those
  343. * controllers continue to assert IRQ as long as
  344. * SError bits are pending. Clear SError immediately.
  345. */
  346. sil_scr_read(ap, SCR_ERROR, &serror);
  347. sil_scr_write(ap, SCR_ERROR, serror);
  348. /* Trigger hotplug and accumulate SError only if the
  349. * port isn't already frozen. Otherwise, PHY events
  350. * during hardreset makes controllers with broken SIEN
  351. * repeat probing needlessly.
  352. */
  353. if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
  354. ata_ehi_hotplugged(&ap->eh_info);
  355. ap->eh_info.serror |= serror;
  356. }
  357. goto freeze;
  358. }
  359. if (unlikely(!qc))
  360. goto freeze;
  361. if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) {
  362. /* this sometimes happens, just clear IRQ */
  363. ata_chk_status(ap);
  364. return;
  365. }
  366. /* Check whether we are expecting interrupt in this state */
  367. switch (ap->hsm_task_state) {
  368. case HSM_ST_FIRST:
  369. /* Some pre-ATAPI-4 devices assert INTRQ
  370. * at this state when ready to receive CDB.
  371. */
  372. /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
  373. * The flag was turned on only for atapi devices.
  374. * No need to check is_atapi_taskfile(&qc->tf) again.
  375. */
  376. if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  377. goto err_hsm;
  378. break;
  379. case HSM_ST_LAST:
  380. if (qc->tf.protocol == ATA_PROT_DMA ||
  381. qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
  382. /* clear DMA-Start bit */
  383. ap->ops->bmdma_stop(qc);
  384. if (bmdma2 & SIL_DMA_ERROR) {
  385. qc->err_mask |= AC_ERR_HOST_BUS;
  386. ap->hsm_task_state = HSM_ST_ERR;
  387. }
  388. }
  389. break;
  390. case HSM_ST:
  391. break;
  392. default:
  393. goto err_hsm;
  394. }
  395. /* check main status, clearing INTRQ */
  396. status = ata_chk_status(ap);
  397. if (unlikely(status & ATA_BUSY))
  398. goto err_hsm;
  399. /* ack bmdma irq events */
  400. ata_bmdma_irq_clear(ap);
  401. /* kick HSM in the ass */
  402. ata_hsm_move(ap, qc, status, 0);
  403. if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
  404. qc->tf.protocol == ATA_PROT_ATAPI_DMA))
  405. ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
  406. return;
  407. err_hsm:
  408. qc->err_mask |= AC_ERR_HSM;
  409. freeze:
  410. ata_port_freeze(ap);
  411. }
  412. static irqreturn_t sil_interrupt(int irq, void *dev_instance)
  413. {
  414. struct ata_host *host = dev_instance;
  415. void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
  416. int handled = 0;
  417. int i;
  418. spin_lock(&host->lock);
  419. for (i = 0; i < host->n_ports; i++) {
  420. struct ata_port *ap = host->ports[i];
  421. u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
  422. if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
  423. continue;
  424. /* turn off SATA_IRQ if not supported */
  425. if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
  426. bmdma2 &= ~SIL_DMA_SATA_IRQ;
  427. if (bmdma2 == 0xffffffff ||
  428. !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
  429. continue;
  430. sil_host_intr(ap, bmdma2);
  431. handled = 1;
  432. }
  433. spin_unlock(&host->lock);
  434. return IRQ_RETVAL(handled);
  435. }
  436. static void sil_freeze(struct ata_port *ap)
  437. {
  438. void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
  439. u32 tmp;
  440. /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
  441. writel(0, mmio_base + sil_port[ap->port_no].sien);
  442. /* plug IRQ */
  443. tmp = readl(mmio_base + SIL_SYSCFG);
  444. tmp |= SIL_MASK_IDE0_INT << ap->port_no;
  445. writel(tmp, mmio_base + SIL_SYSCFG);
  446. readl(mmio_base + SIL_SYSCFG); /* flush */
  447. }
  448. static void sil_thaw(struct ata_port *ap)
  449. {
  450. void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
  451. u32 tmp;
  452. /* clear IRQ */
  453. ata_chk_status(ap);
  454. ata_bmdma_irq_clear(ap);
  455. /* turn on SATA IRQ if supported */
  456. if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
  457. writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
  458. /* turn on IRQ */
  459. tmp = readl(mmio_base + SIL_SYSCFG);
  460. tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
  461. writel(tmp, mmio_base + SIL_SYSCFG);
  462. }
  463. /**
  464. * sil_dev_config - Apply device/host-specific errata fixups
  465. * @dev: Device to be examined
  466. *
  467. * After the IDENTIFY [PACKET] DEVICE step is complete, and a
  468. * device is known to be present, this function is called.
  469. * We apply two errata fixups which are specific to Silicon Image,
  470. * a Seagate and a Maxtor fixup.
  471. *
  472. * For certain Seagate devices, we must limit the maximum sectors
  473. * to under 8K.
  474. *
  475. * For certain Maxtor devices, we must not program the drive
  476. * beyond udma5.
  477. *
  478. * Both fixups are unfairly pessimistic. As soon as I get more
  479. * information on these errata, I will create a more exhaustive
  480. * list, and apply the fixups to only the specific
  481. * devices/hosts/firmwares that need it.
  482. *
  483. * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
  484. * The Maxtor quirk is in the blacklist, but I'm keeping the original
  485. * pessimistic fix for the following reasons...
  486. * - There seems to be less info on it, only one device gleaned off the
  487. * Windows driver, maybe only one is affected. More info would be greatly
  488. * appreciated.
  489. * - But then again UDMA5 is hardly anything to complain about
  490. */
  491. static void sil_dev_config(struct ata_device *dev)
  492. {
  493. struct ata_port *ap = dev->ap;
  494. int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
  495. unsigned int n, quirks = 0;
  496. unsigned char model_num[ATA_ID_PROD_LEN + 1];
  497. ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
  498. for (n = 0; sil_blacklist[n].product; n++)
  499. if (!strcmp(sil_blacklist[n].product, model_num)) {
  500. quirks = sil_blacklist[n].quirk;
  501. break;
  502. }
  503. /* limit requests to 15 sectors */
  504. if (slow_down ||
  505. ((ap->flags & SIL_FLAG_MOD15WRITE) &&
  506. (quirks & SIL_QUIRK_MOD15WRITE))) {
  507. if (print_info)
  508. ata_dev_printk(dev, KERN_INFO, "applying Seagate "
  509. "errata fix (mod15write workaround)\n");
  510. dev->max_sectors = 15;
  511. return;
  512. }
  513. /* limit to udma5 */
  514. if (quirks & SIL_QUIRK_UDMA5MAX) {
  515. if (print_info)
  516. ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
  517. "errata fix %s\n", model_num);
  518. dev->udma_mask &= ATA_UDMA5;
  519. return;
  520. }
  521. }
  522. static void sil_init_controller(struct ata_host *host)
  523. {
  524. struct pci_dev *pdev = to_pci_dev(host->dev);
  525. void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
  526. u8 cls;
  527. u32 tmp;
  528. int i;
  529. /* Initialize FIFO PCI bus arbitration */
  530. cls = sil_get_device_cache_line(pdev);
  531. if (cls) {
  532. cls >>= 3;
  533. cls++; /* cls = (line_size/8)+1 */
  534. for (i = 0; i < host->n_ports; i++)
  535. writew(cls << 8 | cls,
  536. mmio_base + sil_port[i].fifo_cfg);
  537. } else
  538. dev_printk(KERN_WARNING, &pdev->dev,
  539. "cache line size not set. Driver may not function\n");
  540. /* Apply R_ERR on DMA activate FIS errata workaround */
  541. if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
  542. int cnt;
  543. for (i = 0, cnt = 0; i < host->n_ports; i++) {
  544. tmp = readl(mmio_base + sil_port[i].sfis_cfg);
  545. if ((tmp & 0x3) != 0x01)
  546. continue;
  547. if (!cnt)
  548. dev_printk(KERN_INFO, &pdev->dev,
  549. "Applying R_ERR on DMA activate "
  550. "FIS errata fix\n");
  551. writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
  552. cnt++;
  553. }
  554. }
  555. if (host->n_ports == 4) {
  556. /* flip the magic "make 4 ports work" bit */
  557. tmp = readl(mmio_base + sil_port[2].bmdma);
  558. if ((tmp & SIL_INTR_STEERING) == 0)
  559. writel(tmp | SIL_INTR_STEERING,
  560. mmio_base + sil_port[2].bmdma);
  561. }
  562. }
  563. static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  564. {
  565. static int printed_version;
  566. int board_id = ent->driver_data;
  567. const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
  568. struct ata_host *host;
  569. void __iomem *mmio_base;
  570. int n_ports, rc;
  571. unsigned int i;
  572. if (!printed_version++)
  573. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  574. /* allocate host */
  575. n_ports = 2;
  576. if (board_id == sil_3114)
  577. n_ports = 4;
  578. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  579. if (!host)
  580. return -ENOMEM;
  581. /* acquire resources and fill host */
  582. rc = pcim_enable_device(pdev);
  583. if (rc)
  584. return rc;
  585. rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
  586. if (rc == -EBUSY)
  587. pcim_pin_device(pdev);
  588. if (rc)
  589. return rc;
  590. host->iomap = pcim_iomap_table(pdev);
  591. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  592. if (rc)
  593. return rc;
  594. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  595. if (rc)
  596. return rc;
  597. mmio_base = host->iomap[SIL_MMIO_BAR];
  598. for (i = 0; i < host->n_ports; i++) {
  599. struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
  600. ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
  601. ioaddr->altstatus_addr =
  602. ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
  603. ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
  604. ioaddr->scr_addr = mmio_base + sil_port[i].scr;
  605. ata_std_ports(ioaddr);
  606. }
  607. /* initialize and activate */
  608. sil_init_controller(host);
  609. pci_set_master(pdev);
  610. return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
  611. &sil_sht);
  612. }
  613. #ifdef CONFIG_PM
  614. static int sil_pci_device_resume(struct pci_dev *pdev)
  615. {
  616. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  617. int rc;
  618. rc = ata_pci_device_do_resume(pdev);
  619. if (rc)
  620. return rc;
  621. sil_init_controller(host);
  622. ata_host_resume(host);
  623. return 0;
  624. }
  625. #endif
  626. static int __init sil_init(void)
  627. {
  628. return pci_register_driver(&sil_pci_driver);
  629. }
  630. static void __exit sil_exit(void)
  631. {
  632. pci_unregister_driver(&sil_pci_driver);
  633. }
  634. module_init(sil_init);
  635. module_exit(sil_exit);