ata_piix.c 35 KB

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  1. /*
  2. * ata_piix.c - Intel PATA/SATA controllers
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. *
  9. * Copyright 2003-2005 Red Hat Inc
  10. * Copyright 2003-2005 Jeff Garzik
  11. *
  12. *
  13. * Copyright header from piix.c:
  14. *
  15. * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  16. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  17. * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
  18. *
  19. *
  20. * This program is free software; you can redistribute it and/or modify
  21. * it under the terms of the GNU General Public License as published by
  22. * the Free Software Foundation; either version 2, or (at your option)
  23. * any later version.
  24. *
  25. * This program is distributed in the hope that it will be useful,
  26. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28. * GNU General Public License for more details.
  29. *
  30. * You should have received a copy of the GNU General Public License
  31. * along with this program; see the file COPYING. If not, write to
  32. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  33. *
  34. *
  35. * libata documentation is available via 'make {ps|pdf}docs',
  36. * as Documentation/DocBook/libata.*
  37. *
  38. * Hardware documentation available at http://developer.intel.com/
  39. *
  40. * Documentation
  41. * Publically available from Intel web site. Errata documentation
  42. * is also publically available. As an aide to anyone hacking on this
  43. * driver the list of errata that are relevant is below, going back to
  44. * PIIX4. Older device documentation is now a bit tricky to find.
  45. *
  46. * The chipsets all follow very much the same design. The orginal Triton
  47. * series chipsets do _not_ support independant device timings, but this
  48. * is fixed in Triton II. With the odd mobile exception the chips then
  49. * change little except in gaining more modes until SATA arrives. This
  50. * driver supports only the chips with independant timing (that is those
  51. * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
  52. * for the early chip drivers.
  53. *
  54. * Errata of note:
  55. *
  56. * Unfixable
  57. * PIIX4 errata #9 - Only on ultra obscure hw
  58. * ICH3 errata #13 - Not observed to affect real hw
  59. * by Intel
  60. *
  61. * Things we must deal with
  62. * PIIX4 errata #10 - BM IDE hang with non UDMA
  63. * (must stop/start dma to recover)
  64. * 440MX errata #15 - As PIIX4 errata #10
  65. * PIIX4 errata #15 - Must not read control registers
  66. * during a PIO transfer
  67. * 440MX errata #13 - As PIIX4 errata #15
  68. * ICH2 errata #21 - DMA mode 0 doesn't work right
  69. * ICH0/1 errata #55 - As ICH2 errata #21
  70. * ICH2 spec c #9 - Extra operations needed to handle
  71. * drive hotswap [NOT YET SUPPORTED]
  72. * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
  73. * and must be dword aligned
  74. * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  75. *
  76. * Should have been BIOS fixed:
  77. * 450NX: errata #19 - DMA hangs on old 450NX
  78. * 450NX: errata #20 - DMA hangs on old 450NX
  79. * 450NX: errata #25 - Corruption with DMA on old 450NX
  80. * ICH3 errata #15 - IDE deadlock under high load
  81. * (BIOS must set dev 31 fn 0 bit 23)
  82. * ICH3 errata #18 - Don't use native mode
  83. */
  84. #include <linux/kernel.h>
  85. #include <linux/module.h>
  86. #include <linux/pci.h>
  87. #include <linux/init.h>
  88. #include <linux/blkdev.h>
  89. #include <linux/delay.h>
  90. #include <linux/device.h>
  91. #include <scsi/scsi_host.h>
  92. #include <linux/libata.h>
  93. #include <linux/dmi.h>
  94. #define DRV_NAME "ata_piix"
  95. #define DRV_VERSION "2.11"
  96. enum {
  97. PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
  98. ICH5_PMR = 0x90, /* port mapping register */
  99. ICH5_PCS = 0x92, /* port control and status */
  100. PIIX_SCC = 0x0A, /* sub-class code register */
  101. PIIX_FLAG_SCR = (1 << 26), /* SCR available */
  102. PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
  103. PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
  104. PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
  105. PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
  106. /* combined mode. if set, PATA is channel 0.
  107. * if clear, PATA is channel 1.
  108. */
  109. PIIX_PORT_ENABLED = (1 << 0),
  110. PIIX_PORT_PRESENT = (1 << 4),
  111. PIIX_80C_PRI = (1 << 5) | (1 << 4),
  112. PIIX_80C_SEC = (1 << 7) | (1 << 6),
  113. /* controller IDs */
  114. piix_pata_33 = 0, /* PIIX4 at 33Mhz */
  115. ich_pata_33 = 1, /* ICH up to UDMA 33 only */
  116. ich_pata_66 = 2, /* ICH up to 66 Mhz */
  117. ich_pata_100 = 3, /* ICH up to UDMA 100 */
  118. ich_pata_133 = 4, /* ICH up to UDMA 133 */
  119. ich5_sata = 5,
  120. ich6_sata = 6,
  121. ich6_sata_ahci = 7,
  122. ich6m_sata_ahci = 8,
  123. ich8_sata_ahci = 9,
  124. piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
  125. /* constants for mapping table */
  126. P0 = 0, /* port 0 */
  127. P1 = 1, /* port 1 */
  128. P2 = 2, /* port 2 */
  129. P3 = 3, /* port 3 */
  130. IDE = -1, /* IDE */
  131. NA = -2, /* not avaliable */
  132. RV = -3, /* reserved */
  133. PIIX_AHCI_DEVICE = 6,
  134. /* host->flags bits */
  135. PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
  136. };
  137. struct piix_map_db {
  138. const u32 mask;
  139. const u16 port_enable;
  140. const int map[][4];
  141. };
  142. struct piix_host_priv {
  143. const int *map;
  144. };
  145. static int piix_init_one (struct pci_dev *pdev,
  146. const struct pci_device_id *ent);
  147. static void piix_pata_error_handler(struct ata_port *ap);
  148. static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
  149. static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
  150. static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
  151. static int ich_pata_cable_detect(struct ata_port *ap);
  152. #ifdef CONFIG_PM
  153. static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  154. static int piix_pci_device_resume(struct pci_dev *pdev);
  155. #endif
  156. static unsigned int in_module_init = 1;
  157. static const struct pci_device_id piix_pci_tbl[] = {
  158. /* Intel PIIX3 for the 430HX etc */
  159. { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
  160. /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
  161. /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
  162. { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
  163. /* Intel PIIX4 */
  164. { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
  165. /* Intel PIIX4 */
  166. { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
  167. /* Intel PIIX */
  168. { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
  169. /* Intel ICH (i810, i815, i840) UDMA 66*/
  170. { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
  171. /* Intel ICH0 : UDMA 33*/
  172. { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
  173. /* Intel ICH2M */
  174. { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  175. /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
  176. { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  177. /* Intel ICH3M */
  178. { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  179. /* Intel ICH3 (E7500/1) UDMA 100 */
  180. { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  181. /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
  182. { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  183. { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  184. /* Intel ICH5 */
  185. { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
  186. /* C-ICH (i810E2) */
  187. { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  188. /* ESB (855GME/875P + 6300ESB) UDMA 100 */
  189. { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  190. /* ICH6 (and 6) (i915) UDMA 100 */
  191. { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  192. /* ICH7/7-R (i945, i975) UDMA 100*/
  193. { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
  194. { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  195. /* ICH8 Mobile PATA Controller */
  196. { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
  197. /* NOTE: The following PCI ids must be kept in sync with the
  198. * list in drivers/pci/quirks.c.
  199. */
  200. /* 82801EB (ICH5) */
  201. { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
  202. /* 82801EB (ICH5) */
  203. { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
  204. /* 6300ESB (ICH5 variant with broken PCS present bits) */
  205. { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
  206. /* 6300ESB pretending RAID */
  207. { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
  208. /* 82801FB/FW (ICH6/ICH6W) */
  209. { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
  210. /* 82801FR/FRW (ICH6R/ICH6RW) */
  211. { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
  212. /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
  213. { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
  214. /* 82801GB/GR/GH (ICH7, identical to ICH6) */
  215. { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
  216. /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
  217. { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
  218. /* Enterprise Southbridge 2 (631xESB/632xESB) */
  219. { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
  220. /* SATA Controller 1 IDE (ICH8) */
  221. { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  222. /* SATA Controller 2 IDE (ICH8) */
  223. { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  224. /* Mobile SATA Controller IDE (ICH8M) */
  225. { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  226. /* SATA Controller IDE (ICH9) */
  227. { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  228. /* SATA Controller IDE (ICH9) */
  229. { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  230. /* SATA Controller IDE (ICH9) */
  231. { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  232. /* SATA Controller IDE (ICH9M) */
  233. { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  234. /* SATA Controller IDE (ICH9M) */
  235. { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  236. /* SATA Controller IDE (ICH9M) */
  237. { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
  238. { } /* terminate list */
  239. };
  240. static struct pci_driver piix_pci_driver = {
  241. .name = DRV_NAME,
  242. .id_table = piix_pci_tbl,
  243. .probe = piix_init_one,
  244. .remove = ata_pci_remove_one,
  245. #ifdef CONFIG_PM
  246. .suspend = piix_pci_device_suspend,
  247. .resume = piix_pci_device_resume,
  248. #endif
  249. };
  250. static struct scsi_host_template piix_sht = {
  251. .module = THIS_MODULE,
  252. .name = DRV_NAME,
  253. .ioctl = ata_scsi_ioctl,
  254. .queuecommand = ata_scsi_queuecmd,
  255. .can_queue = ATA_DEF_QUEUE,
  256. .this_id = ATA_SHT_THIS_ID,
  257. .sg_tablesize = LIBATA_MAX_PRD,
  258. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  259. .emulated = ATA_SHT_EMULATED,
  260. .use_clustering = ATA_SHT_USE_CLUSTERING,
  261. .proc_name = DRV_NAME,
  262. .dma_boundary = ATA_DMA_BOUNDARY,
  263. .slave_configure = ata_scsi_slave_config,
  264. .slave_destroy = ata_scsi_slave_destroy,
  265. .bios_param = ata_std_bios_param,
  266. };
  267. static const struct ata_port_operations piix_pata_ops = {
  268. .port_disable = ata_port_disable,
  269. .set_piomode = piix_set_piomode,
  270. .set_dmamode = piix_set_dmamode,
  271. .mode_filter = ata_pci_default_filter,
  272. .tf_load = ata_tf_load,
  273. .tf_read = ata_tf_read,
  274. .check_status = ata_check_status,
  275. .exec_command = ata_exec_command,
  276. .dev_select = ata_std_dev_select,
  277. .bmdma_setup = ata_bmdma_setup,
  278. .bmdma_start = ata_bmdma_start,
  279. .bmdma_stop = ata_bmdma_stop,
  280. .bmdma_status = ata_bmdma_status,
  281. .qc_prep = ata_qc_prep,
  282. .qc_issue = ata_qc_issue_prot,
  283. .data_xfer = ata_data_xfer,
  284. .freeze = ata_bmdma_freeze,
  285. .thaw = ata_bmdma_thaw,
  286. .error_handler = piix_pata_error_handler,
  287. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  288. .cable_detect = ata_cable_40wire,
  289. .irq_handler = ata_interrupt,
  290. .irq_clear = ata_bmdma_irq_clear,
  291. .irq_on = ata_irq_on,
  292. .irq_ack = ata_irq_ack,
  293. .port_start = ata_port_start,
  294. };
  295. static const struct ata_port_operations ich_pata_ops = {
  296. .port_disable = ata_port_disable,
  297. .set_piomode = piix_set_piomode,
  298. .set_dmamode = ich_set_dmamode,
  299. .mode_filter = ata_pci_default_filter,
  300. .tf_load = ata_tf_load,
  301. .tf_read = ata_tf_read,
  302. .check_status = ata_check_status,
  303. .exec_command = ata_exec_command,
  304. .dev_select = ata_std_dev_select,
  305. .bmdma_setup = ata_bmdma_setup,
  306. .bmdma_start = ata_bmdma_start,
  307. .bmdma_stop = ata_bmdma_stop,
  308. .bmdma_status = ata_bmdma_status,
  309. .qc_prep = ata_qc_prep,
  310. .qc_issue = ata_qc_issue_prot,
  311. .data_xfer = ata_data_xfer,
  312. .freeze = ata_bmdma_freeze,
  313. .thaw = ata_bmdma_thaw,
  314. .error_handler = piix_pata_error_handler,
  315. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  316. .cable_detect = ich_pata_cable_detect,
  317. .irq_handler = ata_interrupt,
  318. .irq_clear = ata_bmdma_irq_clear,
  319. .irq_on = ata_irq_on,
  320. .irq_ack = ata_irq_ack,
  321. .port_start = ata_port_start,
  322. };
  323. static const struct ata_port_operations piix_sata_ops = {
  324. .port_disable = ata_port_disable,
  325. .tf_load = ata_tf_load,
  326. .tf_read = ata_tf_read,
  327. .check_status = ata_check_status,
  328. .exec_command = ata_exec_command,
  329. .dev_select = ata_std_dev_select,
  330. .bmdma_setup = ata_bmdma_setup,
  331. .bmdma_start = ata_bmdma_start,
  332. .bmdma_stop = ata_bmdma_stop,
  333. .bmdma_status = ata_bmdma_status,
  334. .qc_prep = ata_qc_prep,
  335. .qc_issue = ata_qc_issue_prot,
  336. .data_xfer = ata_data_xfer,
  337. .freeze = ata_bmdma_freeze,
  338. .thaw = ata_bmdma_thaw,
  339. .error_handler = ata_bmdma_error_handler,
  340. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  341. .irq_handler = ata_interrupt,
  342. .irq_clear = ata_bmdma_irq_clear,
  343. .irq_on = ata_irq_on,
  344. .irq_ack = ata_irq_ack,
  345. .port_start = ata_port_start,
  346. };
  347. static const struct piix_map_db ich5_map_db = {
  348. .mask = 0x7,
  349. .port_enable = 0x3,
  350. .map = {
  351. /* PM PS SM SS MAP */
  352. { P0, NA, P1, NA }, /* 000b */
  353. { P1, NA, P0, NA }, /* 001b */
  354. { RV, RV, RV, RV },
  355. { RV, RV, RV, RV },
  356. { P0, P1, IDE, IDE }, /* 100b */
  357. { P1, P0, IDE, IDE }, /* 101b */
  358. { IDE, IDE, P0, P1 }, /* 110b */
  359. { IDE, IDE, P1, P0 }, /* 111b */
  360. },
  361. };
  362. static const struct piix_map_db ich6_map_db = {
  363. .mask = 0x3,
  364. .port_enable = 0xf,
  365. .map = {
  366. /* PM PS SM SS MAP */
  367. { P0, P2, P1, P3 }, /* 00b */
  368. { IDE, IDE, P1, P3 }, /* 01b */
  369. { P0, P2, IDE, IDE }, /* 10b */
  370. { RV, RV, RV, RV },
  371. },
  372. };
  373. static const struct piix_map_db ich6m_map_db = {
  374. .mask = 0x3,
  375. .port_enable = 0x5,
  376. /* Map 01b isn't specified in the doc but some notebooks use
  377. * it anyway. MAP 01b have been spotted on both ICH6M and
  378. * ICH7M.
  379. */
  380. .map = {
  381. /* PM PS SM SS MAP */
  382. { P0, P2, NA, NA }, /* 00b */
  383. { IDE, IDE, P1, P3 }, /* 01b */
  384. { P0, P2, IDE, IDE }, /* 10b */
  385. { RV, RV, RV, RV },
  386. },
  387. };
  388. static const struct piix_map_db ich8_map_db = {
  389. .mask = 0x3,
  390. .port_enable = 0x3,
  391. .map = {
  392. /* PM PS SM SS MAP */
  393. { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
  394. { RV, RV, RV, RV },
  395. { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
  396. { RV, RV, RV, RV },
  397. },
  398. };
  399. static const struct piix_map_db *piix_map_db_table[] = {
  400. [ich5_sata] = &ich5_map_db,
  401. [ich6_sata] = &ich6_map_db,
  402. [ich6_sata_ahci] = &ich6_map_db,
  403. [ich6m_sata_ahci] = &ich6m_map_db,
  404. [ich8_sata_ahci] = &ich8_map_db,
  405. };
  406. static struct ata_port_info piix_port_info[] = {
  407. /* piix_pata_33: 0: PIIX4 at 33MHz */
  408. {
  409. .sht = &piix_sht,
  410. .flags = PIIX_PATA_FLAGS,
  411. .pio_mask = 0x1f, /* pio0-4 */
  412. .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
  413. .udma_mask = ATA_UDMA_MASK_40C,
  414. .port_ops = &piix_pata_ops,
  415. },
  416. /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
  417. {
  418. .sht = &piix_sht,
  419. .flags = PIIX_PATA_FLAGS,
  420. .pio_mask = 0x1f, /* pio 0-4 */
  421. .mwdma_mask = 0x06, /* Check: maybe 0x07 */
  422. .udma_mask = ATA_UDMA2, /* UDMA33 */
  423. .port_ops = &ich_pata_ops,
  424. },
  425. /* ich_pata_66: 2 ICH controllers up to 66MHz */
  426. {
  427. .sht = &piix_sht,
  428. .flags = PIIX_PATA_FLAGS,
  429. .pio_mask = 0x1f, /* pio 0-4 */
  430. .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
  431. .udma_mask = ATA_UDMA4,
  432. .port_ops = &ich_pata_ops,
  433. },
  434. /* ich_pata_100: 3 */
  435. {
  436. .sht = &piix_sht,
  437. .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
  438. .pio_mask = 0x1f, /* pio0-4 */
  439. .mwdma_mask = 0x06, /* mwdma1-2 */
  440. .udma_mask = ATA_UDMA5, /* udma0-5 */
  441. .port_ops = &ich_pata_ops,
  442. },
  443. /* ich_pata_133: 4 ICH with full UDMA6 */
  444. {
  445. .sht = &piix_sht,
  446. .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
  447. .pio_mask = 0x1f, /* pio 0-4 */
  448. .mwdma_mask = 0x06, /* Check: maybe 0x07 */
  449. .udma_mask = ATA_UDMA6, /* UDMA133 */
  450. .port_ops = &ich_pata_ops,
  451. },
  452. /* ich5_sata: 5 */
  453. {
  454. .sht = &piix_sht,
  455. .flags = PIIX_SATA_FLAGS,
  456. .pio_mask = 0x1f, /* pio0-4 */
  457. .mwdma_mask = 0x07, /* mwdma0-2 */
  458. .udma_mask = ATA_UDMA6,
  459. .port_ops = &piix_sata_ops,
  460. },
  461. /* ich6_sata: 6 */
  462. {
  463. .sht = &piix_sht,
  464. .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
  465. .pio_mask = 0x1f, /* pio0-4 */
  466. .mwdma_mask = 0x07, /* mwdma0-2 */
  467. .udma_mask = ATA_UDMA6,
  468. .port_ops = &piix_sata_ops,
  469. },
  470. /* ich6_sata_ahci: 7 */
  471. {
  472. .sht = &piix_sht,
  473. .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
  474. PIIX_FLAG_AHCI,
  475. .pio_mask = 0x1f, /* pio0-4 */
  476. .mwdma_mask = 0x07, /* mwdma0-2 */
  477. .udma_mask = ATA_UDMA6,
  478. .port_ops = &piix_sata_ops,
  479. },
  480. /* ich6m_sata_ahci: 8 */
  481. {
  482. .sht = &piix_sht,
  483. .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
  484. PIIX_FLAG_AHCI,
  485. .pio_mask = 0x1f, /* pio0-4 */
  486. .mwdma_mask = 0x07, /* mwdma0-2 */
  487. .udma_mask = ATA_UDMA6,
  488. .port_ops = &piix_sata_ops,
  489. },
  490. /* ich8_sata_ahci: 9 */
  491. {
  492. .sht = &piix_sht,
  493. .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
  494. PIIX_FLAG_AHCI,
  495. .pio_mask = 0x1f, /* pio0-4 */
  496. .mwdma_mask = 0x07, /* mwdma0-2 */
  497. .udma_mask = ATA_UDMA6,
  498. .port_ops = &piix_sata_ops,
  499. },
  500. /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
  501. {
  502. .sht = &piix_sht,
  503. .flags = PIIX_PATA_FLAGS,
  504. .pio_mask = 0x1f, /* pio0-4 */
  505. .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
  506. .port_ops = &piix_pata_ops,
  507. },
  508. };
  509. static struct pci_bits piix_enable_bits[] = {
  510. { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
  511. { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
  512. };
  513. MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
  514. MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
  515. MODULE_LICENSE("GPL");
  516. MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
  517. MODULE_VERSION(DRV_VERSION);
  518. struct ich_laptop {
  519. u16 device;
  520. u16 subvendor;
  521. u16 subdevice;
  522. };
  523. /*
  524. * List of laptops that use short cables rather than 80 wire
  525. */
  526. static const struct ich_laptop ich_laptop[] = {
  527. /* devid, subvendor, subdev */
  528. { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
  529. { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
  530. { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
  531. { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
  532. /* end marker */
  533. { 0, }
  534. };
  535. /**
  536. * ich_pata_cable_detect - Probe host controller cable detect info
  537. * @ap: Port for which cable detect info is desired
  538. *
  539. * Read 80c cable indicator from ATA PCI device's PCI config
  540. * register. This register is normally set by firmware (BIOS).
  541. *
  542. * LOCKING:
  543. * None (inherited from caller).
  544. */
  545. static int ich_pata_cable_detect(struct ata_port *ap)
  546. {
  547. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  548. const struct ich_laptop *lap = &ich_laptop[0];
  549. u8 tmp, mask;
  550. /* Check for specials - Acer Aspire 5602WLMi */
  551. while (lap->device) {
  552. if (lap->device == pdev->device &&
  553. lap->subvendor == pdev->subsystem_vendor &&
  554. lap->subdevice == pdev->subsystem_device) {
  555. return ATA_CBL_PATA40_SHORT;
  556. }
  557. lap++;
  558. }
  559. /* check BIOS cable detect results */
  560. mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
  561. pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
  562. if ((tmp & mask) == 0)
  563. return ATA_CBL_PATA40;
  564. return ATA_CBL_PATA80;
  565. }
  566. /**
  567. * piix_pata_prereset - prereset for PATA host controller
  568. * @ap: Target port
  569. * @deadline: deadline jiffies for the operation
  570. *
  571. * LOCKING:
  572. * None (inherited from caller).
  573. */
  574. static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline)
  575. {
  576. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  577. if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
  578. return -ENOENT;
  579. return ata_std_prereset(ap, deadline);
  580. }
  581. static void piix_pata_error_handler(struct ata_port *ap)
  582. {
  583. ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
  584. ata_std_postreset);
  585. }
  586. /**
  587. * piix_set_piomode - Initialize host controller PATA PIO timings
  588. * @ap: Port whose timings we are configuring
  589. * @adev: um
  590. *
  591. * Set PIO mode for device, in host controller PCI config space.
  592. *
  593. * LOCKING:
  594. * None (inherited from caller).
  595. */
  596. static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
  597. {
  598. unsigned int pio = adev->pio_mode - XFER_PIO_0;
  599. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  600. unsigned int is_slave = (adev->devno != 0);
  601. unsigned int master_port= ap->port_no ? 0x42 : 0x40;
  602. unsigned int slave_port = 0x44;
  603. u16 master_data;
  604. u8 slave_data;
  605. u8 udma_enable;
  606. int control = 0;
  607. /*
  608. * See Intel Document 298600-004 for the timing programing rules
  609. * for ICH controllers.
  610. */
  611. static const /* ISP RTC */
  612. u8 timings[][2] = { { 0, 0 },
  613. { 0, 0 },
  614. { 1, 0 },
  615. { 2, 1 },
  616. { 2, 3 }, };
  617. if (pio >= 2)
  618. control |= 1; /* TIME1 enable */
  619. if (ata_pio_need_iordy(adev))
  620. control |= 2; /* IE enable */
  621. /* Intel specifies that the PPE functionality is for disk only */
  622. if (adev->class == ATA_DEV_ATA)
  623. control |= 4; /* PPE enable */
  624. /* PIO configuration clears DTE unconditionally. It will be
  625. * programmed in set_dmamode which is guaranteed to be called
  626. * after set_piomode if any DMA mode is available.
  627. */
  628. pci_read_config_word(dev, master_port, &master_data);
  629. if (is_slave) {
  630. /* clear TIME1|IE1|PPE1|DTE1 */
  631. master_data &= 0xff0f;
  632. /* Enable SITRE (seperate slave timing register) */
  633. master_data |= 0x4000;
  634. /* enable PPE1, IE1 and TIME1 as needed */
  635. master_data |= (control << 4);
  636. pci_read_config_byte(dev, slave_port, &slave_data);
  637. slave_data &= (ap->port_no ? 0x0f : 0xf0);
  638. /* Load the timing nibble for this slave */
  639. slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
  640. << (ap->port_no ? 4 : 0);
  641. } else {
  642. /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
  643. master_data &= 0xccf0;
  644. /* Enable PPE, IE and TIME as appropriate */
  645. master_data |= control;
  646. /* load ISP and RCT */
  647. master_data |=
  648. (timings[pio][0] << 12) |
  649. (timings[pio][1] << 8);
  650. }
  651. pci_write_config_word(dev, master_port, master_data);
  652. if (is_slave)
  653. pci_write_config_byte(dev, slave_port, slave_data);
  654. /* Ensure the UDMA bit is off - it will be turned back on if
  655. UDMA is selected */
  656. if (ap->udma_mask) {
  657. pci_read_config_byte(dev, 0x48, &udma_enable);
  658. udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
  659. pci_write_config_byte(dev, 0x48, udma_enable);
  660. }
  661. }
  662. /**
  663. * do_pata_set_dmamode - Initialize host controller PATA PIO timings
  664. * @ap: Port whose timings we are configuring
  665. * @adev: Drive in question
  666. * @udma: udma mode, 0 - 6
  667. * @isich: set if the chip is an ICH device
  668. *
  669. * Set UDMA mode for device, in host controller PCI config space.
  670. *
  671. * LOCKING:
  672. * None (inherited from caller).
  673. */
  674. static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
  675. {
  676. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  677. u8 master_port = ap->port_no ? 0x42 : 0x40;
  678. u16 master_data;
  679. u8 speed = adev->dma_mode;
  680. int devid = adev->devno + 2 * ap->port_no;
  681. u8 udma_enable = 0;
  682. static const /* ISP RTC */
  683. u8 timings[][2] = { { 0, 0 },
  684. { 0, 0 },
  685. { 1, 0 },
  686. { 2, 1 },
  687. { 2, 3 }, };
  688. pci_read_config_word(dev, master_port, &master_data);
  689. if (ap->udma_mask)
  690. pci_read_config_byte(dev, 0x48, &udma_enable);
  691. if (speed >= XFER_UDMA_0) {
  692. unsigned int udma = adev->dma_mode - XFER_UDMA_0;
  693. u16 udma_timing;
  694. u16 ideconf;
  695. int u_clock, u_speed;
  696. /*
  697. * UDMA is handled by a combination of clock switching and
  698. * selection of dividers
  699. *
  700. * Handy rule: Odd modes are UDMATIMx 01, even are 02
  701. * except UDMA0 which is 00
  702. */
  703. u_speed = min(2 - (udma & 1), udma);
  704. if (udma == 5)
  705. u_clock = 0x1000; /* 100Mhz */
  706. else if (udma > 2)
  707. u_clock = 1; /* 66Mhz */
  708. else
  709. u_clock = 0; /* 33Mhz */
  710. udma_enable |= (1 << devid);
  711. /* Load the CT/RP selection */
  712. pci_read_config_word(dev, 0x4A, &udma_timing);
  713. udma_timing &= ~(3 << (4 * devid));
  714. udma_timing |= u_speed << (4 * devid);
  715. pci_write_config_word(dev, 0x4A, udma_timing);
  716. if (isich) {
  717. /* Select a 33/66/100Mhz clock */
  718. pci_read_config_word(dev, 0x54, &ideconf);
  719. ideconf &= ~(0x1001 << devid);
  720. ideconf |= u_clock << devid;
  721. /* For ICH or later we should set bit 10 for better
  722. performance (WR_PingPong_En) */
  723. pci_write_config_word(dev, 0x54, ideconf);
  724. }
  725. } else {
  726. /*
  727. * MWDMA is driven by the PIO timings. We must also enable
  728. * IORDY unconditionally along with TIME1. PPE has already
  729. * been set when the PIO timing was set.
  730. */
  731. unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
  732. unsigned int control;
  733. u8 slave_data;
  734. const unsigned int needed_pio[3] = {
  735. XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
  736. };
  737. int pio = needed_pio[mwdma] - XFER_PIO_0;
  738. control = 3; /* IORDY|TIME1 */
  739. /* If the drive MWDMA is faster than it can do PIO then
  740. we must force PIO into PIO0 */
  741. if (adev->pio_mode < needed_pio[mwdma])
  742. /* Enable DMA timing only */
  743. control |= 8; /* PIO cycles in PIO0 */
  744. if (adev->devno) { /* Slave */
  745. master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
  746. master_data |= control << 4;
  747. pci_read_config_byte(dev, 0x44, &slave_data);
  748. slave_data &= (ap->port_no ? 0x0f : 0xf0);
  749. /* Load the matching timing */
  750. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
  751. pci_write_config_byte(dev, 0x44, slave_data);
  752. } else { /* Master */
  753. master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
  754. and master timing bits */
  755. master_data |= control;
  756. master_data |=
  757. (timings[pio][0] << 12) |
  758. (timings[pio][1] << 8);
  759. }
  760. if (ap->udma_mask) {
  761. udma_enable &= ~(1 << devid);
  762. pci_write_config_word(dev, master_port, master_data);
  763. }
  764. }
  765. /* Don't scribble on 0x48 if the controller does not support UDMA */
  766. if (ap->udma_mask)
  767. pci_write_config_byte(dev, 0x48, udma_enable);
  768. }
  769. /**
  770. * piix_set_dmamode - Initialize host controller PATA DMA timings
  771. * @ap: Port whose timings we are configuring
  772. * @adev: um
  773. *
  774. * Set MW/UDMA mode for device, in host controller PCI config space.
  775. *
  776. * LOCKING:
  777. * None (inherited from caller).
  778. */
  779. static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  780. {
  781. do_pata_set_dmamode(ap, adev, 0);
  782. }
  783. /**
  784. * ich_set_dmamode - Initialize host controller PATA DMA timings
  785. * @ap: Port whose timings we are configuring
  786. * @adev: um
  787. *
  788. * Set MW/UDMA mode for device, in host controller PCI config space.
  789. *
  790. * LOCKING:
  791. * None (inherited from caller).
  792. */
  793. static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  794. {
  795. do_pata_set_dmamode(ap, adev, 1);
  796. }
  797. #ifdef CONFIG_PM
  798. static int piix_broken_suspend(void)
  799. {
  800. static struct dmi_system_id sysids[] = {
  801. {
  802. .ident = "TECRA M5",
  803. .matches = {
  804. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  805. DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
  806. },
  807. },
  808. {
  809. .ident = "TECRA M7",
  810. .matches = {
  811. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  812. DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
  813. },
  814. },
  815. {
  816. .ident = "Satellite U205",
  817. .matches = {
  818. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  819. DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
  820. },
  821. },
  822. {
  823. .ident = "Portege M500",
  824. .matches = {
  825. DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
  826. DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
  827. },
  828. },
  829. { }
  830. };
  831. static const char *oemstrs[] = {
  832. "Tecra M3,",
  833. };
  834. int i;
  835. if (dmi_check_system(sysids))
  836. return 1;
  837. for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
  838. if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
  839. return 1;
  840. return 0;
  841. }
  842. static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
  843. {
  844. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  845. unsigned long flags;
  846. int rc = 0;
  847. rc = ata_host_suspend(host, mesg);
  848. if (rc)
  849. return rc;
  850. /* Some braindamaged ACPI suspend implementations expect the
  851. * controller to be awake on entry; otherwise, it burns cpu
  852. * cycles and power trying to do something to the sleeping
  853. * beauty.
  854. */
  855. if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
  856. pci_save_state(pdev);
  857. /* mark its power state as "unknown", since we don't
  858. * know if e.g. the BIOS will change its device state
  859. * when we suspend.
  860. */
  861. if (pdev->current_state == PCI_D0)
  862. pdev->current_state = PCI_UNKNOWN;
  863. /* tell resume that it's waking up from broken suspend */
  864. spin_lock_irqsave(&host->lock, flags);
  865. host->flags |= PIIX_HOST_BROKEN_SUSPEND;
  866. spin_unlock_irqrestore(&host->lock, flags);
  867. } else
  868. ata_pci_device_do_suspend(pdev, mesg);
  869. return 0;
  870. }
  871. static int piix_pci_device_resume(struct pci_dev *pdev)
  872. {
  873. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  874. unsigned long flags;
  875. int rc;
  876. if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
  877. spin_lock_irqsave(&host->lock, flags);
  878. host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
  879. spin_unlock_irqrestore(&host->lock, flags);
  880. pci_set_power_state(pdev, PCI_D0);
  881. pci_restore_state(pdev);
  882. /* PCI device wasn't disabled during suspend. Use
  883. * pci_reenable_device() to avoid affecting the enable
  884. * count.
  885. */
  886. rc = pci_reenable_device(pdev);
  887. if (rc)
  888. dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
  889. "device after resume (%d)\n", rc);
  890. } else
  891. rc = ata_pci_device_do_resume(pdev);
  892. if (rc == 0)
  893. ata_host_resume(host);
  894. return rc;
  895. }
  896. #endif
  897. #define AHCI_PCI_BAR 5
  898. #define AHCI_GLOBAL_CTL 0x04
  899. #define AHCI_ENABLE (1 << 31)
  900. static int piix_disable_ahci(struct pci_dev *pdev)
  901. {
  902. void __iomem *mmio;
  903. u32 tmp;
  904. int rc = 0;
  905. /* BUG: pci_enable_device has not yet been called. This
  906. * works because this device is usually set up by BIOS.
  907. */
  908. if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
  909. !pci_resource_len(pdev, AHCI_PCI_BAR))
  910. return 0;
  911. mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
  912. if (!mmio)
  913. return -ENOMEM;
  914. tmp = readl(mmio + AHCI_GLOBAL_CTL);
  915. if (tmp & AHCI_ENABLE) {
  916. tmp &= ~AHCI_ENABLE;
  917. writel(tmp, mmio + AHCI_GLOBAL_CTL);
  918. tmp = readl(mmio + AHCI_GLOBAL_CTL);
  919. if (tmp & AHCI_ENABLE)
  920. rc = -EIO;
  921. }
  922. pci_iounmap(pdev, mmio);
  923. return rc;
  924. }
  925. /**
  926. * piix_check_450nx_errata - Check for problem 450NX setup
  927. * @ata_dev: the PCI device to check
  928. *
  929. * Check for the present of 450NX errata #19 and errata #25. If
  930. * they are found return an error code so we can turn off DMA
  931. */
  932. static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
  933. {
  934. struct pci_dev *pdev = NULL;
  935. u16 cfg;
  936. int no_piix_dma = 0;
  937. while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
  938. {
  939. /* Look for 450NX PXB. Check for problem configurations
  940. A PCI quirk checks bit 6 already */
  941. pci_read_config_word(pdev, 0x41, &cfg);
  942. /* Only on the original revision: IDE DMA can hang */
  943. if (pdev->revision == 0x00)
  944. no_piix_dma = 1;
  945. /* On all revisions below 5 PXB bus lock must be disabled for IDE */
  946. else if (cfg & (1<<14) && pdev->revision < 5)
  947. no_piix_dma = 2;
  948. }
  949. if (no_piix_dma)
  950. dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
  951. if (no_piix_dma == 2)
  952. dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
  953. return no_piix_dma;
  954. }
  955. static void __devinit piix_init_pcs(struct pci_dev *pdev,
  956. struct ata_port_info *pinfo,
  957. const struct piix_map_db *map_db)
  958. {
  959. u16 pcs, new_pcs;
  960. pci_read_config_word(pdev, ICH5_PCS, &pcs);
  961. new_pcs = pcs | map_db->port_enable;
  962. if (new_pcs != pcs) {
  963. DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
  964. pci_write_config_word(pdev, ICH5_PCS, new_pcs);
  965. msleep(150);
  966. }
  967. }
  968. static void __devinit piix_init_sata_map(struct pci_dev *pdev,
  969. struct ata_port_info *pinfo,
  970. const struct piix_map_db *map_db)
  971. {
  972. struct piix_host_priv *hpriv = pinfo[0].private_data;
  973. const unsigned int *map;
  974. int i, invalid_map = 0;
  975. u8 map_value;
  976. pci_read_config_byte(pdev, ICH5_PMR, &map_value);
  977. map = map_db->map[map_value & map_db->mask];
  978. dev_printk(KERN_INFO, &pdev->dev, "MAP [");
  979. for (i = 0; i < 4; i++) {
  980. switch (map[i]) {
  981. case RV:
  982. invalid_map = 1;
  983. printk(" XX");
  984. break;
  985. case NA:
  986. printk(" --");
  987. break;
  988. case IDE:
  989. WARN_ON((i & 1) || map[i + 1] != IDE);
  990. pinfo[i / 2] = piix_port_info[ich_pata_100];
  991. pinfo[i / 2].private_data = hpriv;
  992. i++;
  993. printk(" IDE IDE");
  994. break;
  995. default:
  996. printk(" P%d", map[i]);
  997. if (i & 1)
  998. pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
  999. break;
  1000. }
  1001. }
  1002. printk(" ]\n");
  1003. if (invalid_map)
  1004. dev_printk(KERN_ERR, &pdev->dev,
  1005. "invalid MAP value %u\n", map_value);
  1006. hpriv->map = map;
  1007. }
  1008. /**
  1009. * piix_init_one - Register PIIX ATA PCI device with kernel services
  1010. * @pdev: PCI device to register
  1011. * @ent: Entry in piix_pci_tbl matching with @pdev
  1012. *
  1013. * Called from kernel PCI layer. We probe for combined mode (sigh),
  1014. * and then hand over control to libata, for it to do the rest.
  1015. *
  1016. * LOCKING:
  1017. * Inherited from PCI layer (may sleep).
  1018. *
  1019. * RETURNS:
  1020. * Zero on success, or -ERRNO value.
  1021. */
  1022. static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  1023. {
  1024. static int printed_version;
  1025. struct device *dev = &pdev->dev;
  1026. struct ata_port_info port_info[2];
  1027. const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
  1028. struct piix_host_priv *hpriv;
  1029. unsigned long port_flags;
  1030. if (!printed_version++)
  1031. dev_printk(KERN_DEBUG, &pdev->dev,
  1032. "version " DRV_VERSION "\n");
  1033. /* no hotplugging support (FIXME) */
  1034. if (!in_module_init)
  1035. return -ENODEV;
  1036. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  1037. if (!hpriv)
  1038. return -ENOMEM;
  1039. port_info[0] = piix_port_info[ent->driver_data];
  1040. port_info[1] = piix_port_info[ent->driver_data];
  1041. port_info[0].private_data = hpriv;
  1042. port_info[1].private_data = hpriv;
  1043. port_flags = port_info[0].flags;
  1044. if (port_flags & PIIX_FLAG_AHCI) {
  1045. u8 tmp;
  1046. pci_read_config_byte(pdev, PIIX_SCC, &tmp);
  1047. if (tmp == PIIX_AHCI_DEVICE) {
  1048. int rc = piix_disable_ahci(pdev);
  1049. if (rc)
  1050. return rc;
  1051. }
  1052. }
  1053. /* Initialize SATA map */
  1054. if (port_flags & ATA_FLAG_SATA) {
  1055. piix_init_sata_map(pdev, port_info,
  1056. piix_map_db_table[ent->driver_data]);
  1057. piix_init_pcs(pdev, port_info,
  1058. piix_map_db_table[ent->driver_data]);
  1059. }
  1060. /* On ICH5, some BIOSen disable the interrupt using the
  1061. * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
  1062. * On ICH6, this bit has the same effect, but only when
  1063. * MSI is disabled (and it is disabled, as we don't use
  1064. * message-signalled interrupts currently).
  1065. */
  1066. if (port_flags & PIIX_FLAG_CHECKINTR)
  1067. pci_intx(pdev, 1);
  1068. if (piix_check_450nx_errata(pdev)) {
  1069. /* This writes into the master table but it does not
  1070. really matter for this errata as we will apply it to
  1071. all the PIIX devices on the board */
  1072. port_info[0].mwdma_mask = 0;
  1073. port_info[0].udma_mask = 0;
  1074. port_info[1].mwdma_mask = 0;
  1075. port_info[1].udma_mask = 0;
  1076. }
  1077. return ata_pci_init_one(pdev, ppi);
  1078. }
  1079. static int __init piix_init(void)
  1080. {
  1081. int rc;
  1082. DPRINTK("pci_register_driver\n");
  1083. rc = pci_register_driver(&piix_pci_driver);
  1084. if (rc)
  1085. return rc;
  1086. in_module_init = 0;
  1087. DPRINTK("done\n");
  1088. return 0;
  1089. }
  1090. static void __exit piix_exit(void)
  1091. {
  1092. pci_unregister_driver(&piix_pci_driver);
  1093. }
  1094. module_init(piix_init);
  1095. module_exit(piix_exit);