main.c 53 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125
  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_update_txpow(struct ath_softc *sc)
  20. {
  21. struct ath_hw *ah = sc->sc_ah;
  22. if (sc->curtxpow != sc->config.txpowlimit) {
  23. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
  24. /* read back in case value is clamped */
  25. sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  26. }
  27. }
  28. static u8 parse_mpdudensity(u8 mpdudensity)
  29. {
  30. /*
  31. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  32. * 0 for no restriction
  33. * 1 for 1/4 us
  34. * 2 for 1/2 us
  35. * 3 for 1 us
  36. * 4 for 2 us
  37. * 5 for 4 us
  38. * 6 for 8 us
  39. * 7 for 16 us
  40. */
  41. switch (mpdudensity) {
  42. case 0:
  43. return 0;
  44. case 1:
  45. case 2:
  46. case 3:
  47. /* Our lower layer calculations limit our precision to
  48. 1 microsecond */
  49. return 1;
  50. case 4:
  51. return 2;
  52. case 5:
  53. return 4;
  54. case 6:
  55. return 8;
  56. case 7:
  57. return 16;
  58. default:
  59. return 0;
  60. }
  61. }
  62. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  63. struct ieee80211_hw *hw)
  64. {
  65. struct ieee80211_channel *curchan = hw->conf.channel;
  66. struct ath9k_channel *channel;
  67. u8 chan_idx;
  68. chan_idx = curchan->hw_value;
  69. channel = &sc->sc_ah->channels[chan_idx];
  70. ath9k_cmn_update_ichannel(channel, curchan, hw->conf.channel_type);
  71. return channel;
  72. }
  73. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  74. {
  75. unsigned long flags;
  76. bool ret;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  79. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  80. return ret;
  81. }
  82. void ath9k_ps_wakeup(struct ath_softc *sc)
  83. {
  84. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  85. unsigned long flags;
  86. enum ath9k_power_mode power_mode;
  87. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  88. if (++sc->ps_usecount != 1)
  89. goto unlock;
  90. power_mode = sc->sc_ah->power_mode;
  91. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  92. /*
  93. * While the hardware is asleep, the cycle counters contain no
  94. * useful data. Better clear them now so that they don't mess up
  95. * survey data results.
  96. */
  97. if (power_mode != ATH9K_PM_AWAKE) {
  98. spin_lock(&common->cc_lock);
  99. ath_hw_cycle_counters_update(common);
  100. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  101. spin_unlock(&common->cc_lock);
  102. }
  103. unlock:
  104. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  105. }
  106. void ath9k_ps_restore(struct ath_softc *sc)
  107. {
  108. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  109. unsigned long flags;
  110. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  111. if (--sc->ps_usecount != 0)
  112. goto unlock;
  113. spin_lock(&common->cc_lock);
  114. ath_hw_cycle_counters_update(common);
  115. spin_unlock(&common->cc_lock);
  116. if (sc->ps_idle)
  117. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  118. else if (sc->ps_enabled &&
  119. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  120. PS_WAIT_FOR_CAB |
  121. PS_WAIT_FOR_PSPOLL_DATA |
  122. PS_WAIT_FOR_TX_ACK)))
  123. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  124. unlock:
  125. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  126. }
  127. static void ath_start_ani(struct ath_common *common)
  128. {
  129. struct ath_hw *ah = common->ah;
  130. unsigned long timestamp = jiffies_to_msecs(jiffies);
  131. struct ath_softc *sc = (struct ath_softc *) common->priv;
  132. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  133. return;
  134. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  135. return;
  136. common->ani.longcal_timer = timestamp;
  137. common->ani.shortcal_timer = timestamp;
  138. common->ani.checkani_timer = timestamp;
  139. mod_timer(&common->ani.timer,
  140. jiffies +
  141. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  142. }
  143. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  144. {
  145. struct ath_hw *ah = sc->sc_ah;
  146. struct ath9k_channel *chan = &ah->channels[channel];
  147. struct survey_info *survey = &sc->survey[channel];
  148. if (chan->noisefloor) {
  149. survey->filled |= SURVEY_INFO_NOISE_DBM;
  150. survey->noise = chan->noisefloor;
  151. }
  152. }
  153. static void ath_update_survey_stats(struct ath_softc *sc)
  154. {
  155. struct ath_hw *ah = sc->sc_ah;
  156. struct ath_common *common = ath9k_hw_common(ah);
  157. int pos = ah->curchan - &ah->channels[0];
  158. struct survey_info *survey = &sc->survey[pos];
  159. struct ath_cycle_counters *cc = &common->cc_survey;
  160. unsigned int div = common->clockrate * 1000;
  161. if (!ah->curchan)
  162. return;
  163. if (ah->power_mode == ATH9K_PM_AWAKE)
  164. ath_hw_cycle_counters_update(common);
  165. if (cc->cycles > 0) {
  166. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  167. SURVEY_INFO_CHANNEL_TIME_BUSY |
  168. SURVEY_INFO_CHANNEL_TIME_RX |
  169. SURVEY_INFO_CHANNEL_TIME_TX;
  170. survey->channel_time += cc->cycles / div;
  171. survey->channel_time_busy += cc->rx_busy / div;
  172. survey->channel_time_rx += cc->rx_frame / div;
  173. survey->channel_time_tx += cc->tx_frame / div;
  174. }
  175. memset(cc, 0, sizeof(*cc));
  176. ath_update_survey_nf(sc, pos);
  177. }
  178. /*
  179. * Set/change channels. If the channel is really being changed, it's done
  180. * by reseting the chip. To accomplish this we must first cleanup any pending
  181. * DMA, then restart stuff.
  182. */
  183. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  184. struct ath9k_channel *hchan)
  185. {
  186. struct ath_hw *ah = sc->sc_ah;
  187. struct ath_common *common = ath9k_hw_common(ah);
  188. struct ieee80211_conf *conf = &common->hw->conf;
  189. bool fastcc = true, stopped;
  190. struct ieee80211_channel *channel = hw->conf.channel;
  191. struct ath9k_hw_cal_data *caldata = NULL;
  192. int r;
  193. if (sc->sc_flags & SC_OP_INVALID)
  194. return -EIO;
  195. del_timer_sync(&common->ani.timer);
  196. cancel_work_sync(&sc->paprd_work);
  197. cancel_work_sync(&sc->hw_check_work);
  198. cancel_delayed_work_sync(&sc->tx_complete_work);
  199. cancel_delayed_work_sync(&sc->hw_pll_work);
  200. ath9k_ps_wakeup(sc);
  201. spin_lock_bh(&sc->sc_pcu_lock);
  202. /*
  203. * This is only performed if the channel settings have
  204. * actually changed.
  205. *
  206. * To switch channels clear any pending DMA operations;
  207. * wait long enough for the RX fifo to drain, reset the
  208. * hardware at the new frequency, and then re-enable
  209. * the relevant bits of the h/w.
  210. */
  211. ath9k_hw_disable_interrupts(ah);
  212. stopped = ath_drain_all_txq(sc, false);
  213. if (!ath_stoprecv(sc))
  214. stopped = false;
  215. if (!ath9k_hw_check_alive(ah))
  216. stopped = false;
  217. /* XXX: do not flush receive queue here. We don't want
  218. * to flush data frames already in queue because of
  219. * changing channel. */
  220. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  221. fastcc = false;
  222. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  223. caldata = &sc->caldata;
  224. ath_dbg(common, ATH_DBG_CONFIG,
  225. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  226. sc->sc_ah->curchan->channel,
  227. channel->center_freq, conf_is_ht40(conf),
  228. fastcc);
  229. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  230. if (r) {
  231. ath_err(common,
  232. "Unable to reset channel (%u MHz), reset status %d\n",
  233. channel->center_freq, r);
  234. goto ps_restore;
  235. }
  236. if (ath_startrecv(sc) != 0) {
  237. ath_err(common, "Unable to restart recv logic\n");
  238. r = -EIO;
  239. goto ps_restore;
  240. }
  241. ath_update_txpow(sc);
  242. ath9k_hw_set_interrupts(ah, ah->imask);
  243. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  244. if (sc->sc_flags & SC_OP_BEACONS)
  245. ath_beacon_config(sc, NULL);
  246. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  247. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  248. ath_start_ani(common);
  249. }
  250. ps_restore:
  251. ieee80211_wake_queues(hw);
  252. spin_unlock_bh(&sc->sc_pcu_lock);
  253. ath9k_ps_restore(sc);
  254. return r;
  255. }
  256. static void ath_paprd_activate(struct ath_softc *sc)
  257. {
  258. struct ath_hw *ah = sc->sc_ah;
  259. struct ath9k_hw_cal_data *caldata = ah->caldata;
  260. struct ath_common *common = ath9k_hw_common(ah);
  261. int chain;
  262. if (!caldata || !caldata->paprd_done)
  263. return;
  264. ath9k_ps_wakeup(sc);
  265. ar9003_paprd_enable(ah, false);
  266. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  267. if (!(common->tx_chainmask & BIT(chain)))
  268. continue;
  269. ar9003_paprd_populate_single_table(ah, caldata, chain);
  270. }
  271. ar9003_paprd_enable(ah, true);
  272. ath9k_ps_restore(sc);
  273. }
  274. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  275. {
  276. struct ieee80211_hw *hw = sc->hw;
  277. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  278. struct ath_tx_control txctl;
  279. int time_left;
  280. memset(&txctl, 0, sizeof(txctl));
  281. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  282. memset(tx_info, 0, sizeof(*tx_info));
  283. tx_info->band = hw->conf.channel->band;
  284. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  285. tx_info->control.rates[0].idx = 0;
  286. tx_info->control.rates[0].count = 1;
  287. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  288. tx_info->control.rates[1].idx = -1;
  289. init_completion(&sc->paprd_complete);
  290. sc->paprd_pending = true;
  291. txctl.paprd = BIT(chain);
  292. if (ath_tx_start(hw, skb, &txctl) != 0)
  293. return false;
  294. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  295. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  296. sc->paprd_pending = false;
  297. if (!time_left)
  298. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
  299. "Timeout waiting for paprd training on TX chain %d\n",
  300. chain);
  301. return !!time_left;
  302. }
  303. void ath_paprd_calibrate(struct work_struct *work)
  304. {
  305. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  306. struct ieee80211_hw *hw = sc->hw;
  307. struct ath_hw *ah = sc->sc_ah;
  308. struct ieee80211_hdr *hdr;
  309. struct sk_buff *skb = NULL;
  310. struct ath9k_hw_cal_data *caldata = ah->caldata;
  311. struct ath_common *common = ath9k_hw_common(ah);
  312. int ftype;
  313. int chain_ok = 0;
  314. int chain;
  315. int len = 1800;
  316. if (!caldata)
  317. return;
  318. if (ar9003_paprd_init_table(ah) < 0)
  319. return;
  320. skb = alloc_skb(len, GFP_KERNEL);
  321. if (!skb)
  322. return;
  323. skb_put(skb, len);
  324. memset(skb->data, 0, len);
  325. hdr = (struct ieee80211_hdr *)skb->data;
  326. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  327. hdr->frame_control = cpu_to_le16(ftype);
  328. hdr->duration_id = cpu_to_le16(10);
  329. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  330. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  331. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  332. ath9k_ps_wakeup(sc);
  333. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  334. if (!(common->tx_chainmask & BIT(chain)))
  335. continue;
  336. chain_ok = 0;
  337. ath_dbg(common, ATH_DBG_CALIBRATE,
  338. "Sending PAPRD frame for thermal measurement "
  339. "on chain %d\n", chain);
  340. if (!ath_paprd_send_frame(sc, skb, chain))
  341. goto fail_paprd;
  342. ar9003_paprd_setup_gain_table(ah, chain);
  343. ath_dbg(common, ATH_DBG_CALIBRATE,
  344. "Sending PAPRD training frame on chain %d\n", chain);
  345. if (!ath_paprd_send_frame(sc, skb, chain))
  346. goto fail_paprd;
  347. if (!ar9003_paprd_is_done(ah))
  348. break;
  349. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  350. break;
  351. chain_ok = 1;
  352. }
  353. kfree_skb(skb);
  354. if (chain_ok) {
  355. caldata->paprd_done = true;
  356. ath_paprd_activate(sc);
  357. }
  358. fail_paprd:
  359. ath9k_ps_restore(sc);
  360. }
  361. /*
  362. * This routine performs the periodic noise floor calibration function
  363. * that is used to adjust and optimize the chip performance. This
  364. * takes environmental changes (location, temperature) into account.
  365. * When the task is complete, it reschedules itself depending on the
  366. * appropriate interval that was calculated.
  367. */
  368. void ath_ani_calibrate(unsigned long data)
  369. {
  370. struct ath_softc *sc = (struct ath_softc *)data;
  371. struct ath_hw *ah = sc->sc_ah;
  372. struct ath_common *common = ath9k_hw_common(ah);
  373. bool longcal = false;
  374. bool shortcal = false;
  375. bool aniflag = false;
  376. unsigned int timestamp = jiffies_to_msecs(jiffies);
  377. u32 cal_interval, short_cal_interval, long_cal_interval;
  378. unsigned long flags;
  379. if (ah->caldata && ah->caldata->nfcal_interference)
  380. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  381. else
  382. long_cal_interval = ATH_LONG_CALINTERVAL;
  383. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  384. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  385. /* Only calibrate if awake */
  386. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  387. goto set_timer;
  388. ath9k_ps_wakeup(sc);
  389. /* Long calibration runs independently of short calibration. */
  390. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  391. longcal = true;
  392. ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  393. common->ani.longcal_timer = timestamp;
  394. }
  395. /* Short calibration applies only while caldone is false */
  396. if (!common->ani.caldone) {
  397. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  398. shortcal = true;
  399. ath_dbg(common, ATH_DBG_ANI,
  400. "shortcal @%lu\n", jiffies);
  401. common->ani.shortcal_timer = timestamp;
  402. common->ani.resetcal_timer = timestamp;
  403. }
  404. } else {
  405. if ((timestamp - common->ani.resetcal_timer) >=
  406. ATH_RESTART_CALINTERVAL) {
  407. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  408. if (common->ani.caldone)
  409. common->ani.resetcal_timer = timestamp;
  410. }
  411. }
  412. /* Verify whether we must check ANI */
  413. if ((timestamp - common->ani.checkani_timer) >=
  414. ah->config.ani_poll_interval) {
  415. aniflag = true;
  416. common->ani.checkani_timer = timestamp;
  417. }
  418. /* Skip all processing if there's nothing to do. */
  419. if (longcal || shortcal || aniflag) {
  420. /* Call ANI routine if necessary */
  421. if (aniflag) {
  422. spin_lock_irqsave(&common->cc_lock, flags);
  423. ath9k_hw_ani_monitor(ah, ah->curchan);
  424. ath_update_survey_stats(sc);
  425. spin_unlock_irqrestore(&common->cc_lock, flags);
  426. }
  427. /* Perform calibration if necessary */
  428. if (longcal || shortcal) {
  429. common->ani.caldone =
  430. ath9k_hw_calibrate(ah,
  431. ah->curchan,
  432. common->rx_chainmask,
  433. longcal);
  434. }
  435. }
  436. ath9k_ps_restore(sc);
  437. set_timer:
  438. /*
  439. * Set timer interval based on previous results.
  440. * The interval must be the shortest necessary to satisfy ANI,
  441. * short calibration and long calibration.
  442. */
  443. cal_interval = ATH_LONG_CALINTERVAL;
  444. if (sc->sc_ah->config.enable_ani)
  445. cal_interval = min(cal_interval,
  446. (u32)ah->config.ani_poll_interval);
  447. if (!common->ani.caldone)
  448. cal_interval = min(cal_interval, (u32)short_cal_interval);
  449. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  450. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  451. if (!ah->caldata->paprd_done)
  452. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  453. else if (!ah->paprd_table_write_done)
  454. ath_paprd_activate(sc);
  455. }
  456. }
  457. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  458. {
  459. struct ath_node *an;
  460. struct ath_hw *ah = sc->sc_ah;
  461. an = (struct ath_node *)sta->drv_priv;
  462. #ifdef CONFIG_ATH9K_DEBUGFS
  463. spin_lock(&sc->nodes_lock);
  464. list_add(&an->list, &sc->nodes);
  465. spin_unlock(&sc->nodes_lock);
  466. an->sta = sta;
  467. #endif
  468. if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
  469. sc->sc_flags |= SC_OP_ENABLE_APM;
  470. if (sc->sc_flags & SC_OP_TXAGGR) {
  471. ath_tx_node_init(sc, an);
  472. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  473. sta->ht_cap.ampdu_factor);
  474. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  475. }
  476. }
  477. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  478. {
  479. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  480. #ifdef CONFIG_ATH9K_DEBUGFS
  481. spin_lock(&sc->nodes_lock);
  482. list_del(&an->list);
  483. spin_unlock(&sc->nodes_lock);
  484. an->sta = NULL;
  485. #endif
  486. if (sc->sc_flags & SC_OP_TXAGGR)
  487. ath_tx_node_cleanup(sc, an);
  488. }
  489. void ath_hw_check(struct work_struct *work)
  490. {
  491. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  492. int i;
  493. ath9k_ps_wakeup(sc);
  494. for (i = 0; i < 3; i++) {
  495. if (ath9k_hw_check_alive(sc->sc_ah))
  496. goto out;
  497. msleep(1);
  498. }
  499. ath_reset(sc, true);
  500. out:
  501. ath9k_ps_restore(sc);
  502. }
  503. void ath9k_tasklet(unsigned long data)
  504. {
  505. struct ath_softc *sc = (struct ath_softc *)data;
  506. struct ath_hw *ah = sc->sc_ah;
  507. struct ath_common *common = ath9k_hw_common(ah);
  508. u32 status = sc->intrstatus;
  509. u32 rxmask;
  510. ath9k_ps_wakeup(sc);
  511. if (status & ATH9K_INT_FATAL) {
  512. ath_reset(sc, true);
  513. ath9k_ps_restore(sc);
  514. return;
  515. }
  516. spin_lock(&sc->sc_pcu_lock);
  517. /*
  518. * Only run the baseband hang check if beacons stop working in AP or
  519. * IBSS mode, because it has a high false positive rate. For station
  520. * mode it should not be necessary, since the upper layers will detect
  521. * this through a beacon miss automatically and the following channel
  522. * change will trigger a hardware reset anyway
  523. */
  524. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  525. !ath9k_hw_check_alive(ah))
  526. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  527. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  528. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  529. ATH9K_INT_RXORN);
  530. else
  531. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  532. if (status & rxmask) {
  533. /* Check for high priority Rx first */
  534. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  535. (status & ATH9K_INT_RXHP))
  536. ath_rx_tasklet(sc, 0, true);
  537. ath_rx_tasklet(sc, 0, false);
  538. }
  539. if (status & ATH9K_INT_TX) {
  540. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  541. ath_tx_edma_tasklet(sc);
  542. else
  543. ath_tx_tasklet(sc);
  544. }
  545. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  546. /*
  547. * TSF sync does not look correct; remain awake to sync with
  548. * the next Beacon.
  549. */
  550. ath_dbg(common, ATH_DBG_PS,
  551. "TSFOOR - Sync with next Beacon\n");
  552. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  553. }
  554. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  555. if (status & ATH9K_INT_GENTIMER)
  556. ath_gen_timer_isr(sc->sc_ah);
  557. /* re-enable hardware interrupt */
  558. ath9k_hw_enable_interrupts(ah);
  559. spin_unlock(&sc->sc_pcu_lock);
  560. ath9k_ps_restore(sc);
  561. }
  562. irqreturn_t ath_isr(int irq, void *dev)
  563. {
  564. #define SCHED_INTR ( \
  565. ATH9K_INT_FATAL | \
  566. ATH9K_INT_RXORN | \
  567. ATH9K_INT_RXEOL | \
  568. ATH9K_INT_RX | \
  569. ATH9K_INT_RXLP | \
  570. ATH9K_INT_RXHP | \
  571. ATH9K_INT_TX | \
  572. ATH9K_INT_BMISS | \
  573. ATH9K_INT_CST | \
  574. ATH9K_INT_TSFOOR | \
  575. ATH9K_INT_GENTIMER)
  576. struct ath_softc *sc = dev;
  577. struct ath_hw *ah = sc->sc_ah;
  578. struct ath_common *common = ath9k_hw_common(ah);
  579. enum ath9k_int status;
  580. bool sched = false;
  581. /*
  582. * The hardware is not ready/present, don't
  583. * touch anything. Note this can happen early
  584. * on if the IRQ is shared.
  585. */
  586. if (sc->sc_flags & SC_OP_INVALID)
  587. return IRQ_NONE;
  588. /* shared irq, not for us */
  589. if (!ath9k_hw_intrpend(ah))
  590. return IRQ_NONE;
  591. /*
  592. * Figure out the reason(s) for the interrupt. Note
  593. * that the hal returns a pseudo-ISR that may include
  594. * bits we haven't explicitly enabled so we mask the
  595. * value to insure we only process bits we requested.
  596. */
  597. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  598. status &= ah->imask; /* discard unasked-for bits */
  599. /*
  600. * If there are no status bits set, then this interrupt was not
  601. * for me (should have been caught above).
  602. */
  603. if (!status)
  604. return IRQ_NONE;
  605. /* Cache the status */
  606. sc->intrstatus = status;
  607. if (status & SCHED_INTR)
  608. sched = true;
  609. /*
  610. * If a FATAL or RXORN interrupt is received, we have to reset the
  611. * chip immediately.
  612. */
  613. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  614. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  615. goto chip_reset;
  616. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  617. (status & ATH9K_INT_BB_WATCHDOG)) {
  618. spin_lock(&common->cc_lock);
  619. ath_hw_cycle_counters_update(common);
  620. ar9003_hw_bb_watchdog_dbg_info(ah);
  621. spin_unlock(&common->cc_lock);
  622. goto chip_reset;
  623. }
  624. if (status & ATH9K_INT_SWBA)
  625. tasklet_schedule(&sc->bcon_tasklet);
  626. if (status & ATH9K_INT_TXURN)
  627. ath9k_hw_updatetxtriglevel(ah, true);
  628. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  629. if (status & ATH9K_INT_RXEOL) {
  630. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  631. ath9k_hw_set_interrupts(ah, ah->imask);
  632. }
  633. }
  634. if (status & ATH9K_INT_MIB) {
  635. /*
  636. * Disable interrupts until we service the MIB
  637. * interrupt; otherwise it will continue to
  638. * fire.
  639. */
  640. ath9k_hw_disable_interrupts(ah);
  641. /*
  642. * Let the hal handle the event. We assume
  643. * it will clear whatever condition caused
  644. * the interrupt.
  645. */
  646. spin_lock(&common->cc_lock);
  647. ath9k_hw_proc_mib_event(ah);
  648. spin_unlock(&common->cc_lock);
  649. ath9k_hw_enable_interrupts(ah);
  650. }
  651. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  652. if (status & ATH9K_INT_TIM_TIMER) {
  653. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  654. goto chip_reset;
  655. /* Clear RxAbort bit so that we can
  656. * receive frames */
  657. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  658. ath9k_hw_setrxabort(sc->sc_ah, 0);
  659. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  660. }
  661. chip_reset:
  662. ath_debug_stat_interrupt(sc, status);
  663. if (sched) {
  664. /* turn off every interrupt */
  665. ath9k_hw_disable_interrupts(ah);
  666. tasklet_schedule(&sc->intr_tq);
  667. }
  668. return IRQ_HANDLED;
  669. #undef SCHED_INTR
  670. }
  671. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  672. struct ieee80211_hw *hw,
  673. struct ieee80211_vif *vif,
  674. struct ieee80211_bss_conf *bss_conf)
  675. {
  676. struct ath_hw *ah = sc->sc_ah;
  677. struct ath_common *common = ath9k_hw_common(ah);
  678. if (bss_conf->assoc) {
  679. ath_dbg(common, ATH_DBG_CONFIG,
  680. "Bss Info ASSOC %d, bssid: %pM\n",
  681. bss_conf->aid, common->curbssid);
  682. /* New association, store aid */
  683. common->curaid = bss_conf->aid;
  684. ath9k_hw_write_associd(ah);
  685. /*
  686. * Request a re-configuration of Beacon related timers
  687. * on the receipt of the first Beacon frame (i.e.,
  688. * after time sync with the AP).
  689. */
  690. sc->ps_flags |= PS_BEACON_SYNC;
  691. /* Configure the beacon */
  692. ath_beacon_config(sc, vif);
  693. /* Reset rssi stats */
  694. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  695. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  696. sc->sc_flags |= SC_OP_ANI_RUN;
  697. ath_start_ani(common);
  698. } else {
  699. ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  700. common->curaid = 0;
  701. /* Stop ANI */
  702. sc->sc_flags &= ~SC_OP_ANI_RUN;
  703. del_timer_sync(&common->ani.timer);
  704. }
  705. }
  706. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  707. {
  708. struct ath_hw *ah = sc->sc_ah;
  709. struct ath_common *common = ath9k_hw_common(ah);
  710. struct ieee80211_channel *channel = hw->conf.channel;
  711. int r;
  712. ath9k_ps_wakeup(sc);
  713. spin_lock_bh(&sc->sc_pcu_lock);
  714. ath9k_hw_configpcipowersave(ah, 0, 0);
  715. if (!ah->curchan)
  716. ah->curchan = ath_get_curchannel(sc, sc->hw);
  717. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  718. if (r) {
  719. ath_err(common,
  720. "Unable to reset channel (%u MHz), reset status %d\n",
  721. channel->center_freq, r);
  722. }
  723. ath_update_txpow(sc);
  724. if (ath_startrecv(sc) != 0) {
  725. ath_err(common, "Unable to restart recv logic\n");
  726. goto out;
  727. }
  728. if (sc->sc_flags & SC_OP_BEACONS)
  729. ath_beacon_config(sc, NULL); /* restart beacons */
  730. /* Re-Enable interrupts */
  731. ath9k_hw_set_interrupts(ah, ah->imask);
  732. /* Enable LED */
  733. ath9k_hw_cfg_output(ah, ah->led_pin,
  734. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  735. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  736. ieee80211_wake_queues(hw);
  737. out:
  738. spin_unlock_bh(&sc->sc_pcu_lock);
  739. ath9k_ps_restore(sc);
  740. }
  741. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  742. {
  743. struct ath_hw *ah = sc->sc_ah;
  744. struct ieee80211_channel *channel = hw->conf.channel;
  745. int r;
  746. ath9k_ps_wakeup(sc);
  747. spin_lock_bh(&sc->sc_pcu_lock);
  748. ieee80211_stop_queues(hw);
  749. /*
  750. * Keep the LED on when the radio is disabled
  751. * during idle unassociated state.
  752. */
  753. if (!sc->ps_idle) {
  754. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  755. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  756. }
  757. /* Disable interrupts */
  758. ath9k_hw_disable_interrupts(ah);
  759. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  760. ath_stoprecv(sc); /* turn off frame recv */
  761. ath_flushrecv(sc); /* flush recv queue */
  762. if (!ah->curchan)
  763. ah->curchan = ath_get_curchannel(sc, hw);
  764. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  765. if (r) {
  766. ath_err(ath9k_hw_common(sc->sc_ah),
  767. "Unable to reset channel (%u MHz), reset status %d\n",
  768. channel->center_freq, r);
  769. }
  770. ath9k_hw_phy_disable(ah);
  771. ath9k_hw_configpcipowersave(ah, 1, 1);
  772. spin_unlock_bh(&sc->sc_pcu_lock);
  773. ath9k_ps_restore(sc);
  774. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  775. }
  776. int ath_reset(struct ath_softc *sc, bool retry_tx)
  777. {
  778. struct ath_hw *ah = sc->sc_ah;
  779. struct ath_common *common = ath9k_hw_common(ah);
  780. struct ieee80211_hw *hw = sc->hw;
  781. int r;
  782. /* Stop ANI */
  783. del_timer_sync(&common->ani.timer);
  784. spin_lock_bh(&sc->sc_pcu_lock);
  785. ieee80211_stop_queues(hw);
  786. ath9k_hw_disable_interrupts(ah);
  787. ath_drain_all_txq(sc, retry_tx);
  788. ath_stoprecv(sc);
  789. ath_flushrecv(sc);
  790. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  791. if (r)
  792. ath_err(common,
  793. "Unable to reset hardware; reset status %d\n", r);
  794. if (ath_startrecv(sc) != 0)
  795. ath_err(common, "Unable to start recv logic\n");
  796. /*
  797. * We may be doing a reset in response to a request
  798. * that changes the channel so update any state that
  799. * might change as a result.
  800. */
  801. ath_update_txpow(sc);
  802. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  803. ath_beacon_config(sc, NULL); /* restart beacons */
  804. ath9k_hw_set_interrupts(ah, ah->imask);
  805. if (retry_tx) {
  806. int i;
  807. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  808. if (ATH_TXQ_SETUP(sc, i)) {
  809. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  810. ath_txq_schedule(sc, &sc->tx.txq[i]);
  811. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  812. }
  813. }
  814. }
  815. ieee80211_wake_queues(hw);
  816. spin_unlock_bh(&sc->sc_pcu_lock);
  817. /* Start ANI */
  818. ath_start_ani(common);
  819. return r;
  820. }
  821. /**********************/
  822. /* mac80211 callbacks */
  823. /**********************/
  824. static int ath9k_start(struct ieee80211_hw *hw)
  825. {
  826. struct ath_softc *sc = hw->priv;
  827. struct ath_hw *ah = sc->sc_ah;
  828. struct ath_common *common = ath9k_hw_common(ah);
  829. struct ieee80211_channel *curchan = hw->conf.channel;
  830. struct ath9k_channel *init_channel;
  831. int r;
  832. ath_dbg(common, ATH_DBG_CONFIG,
  833. "Starting driver with initial channel: %d MHz\n",
  834. curchan->center_freq);
  835. mutex_lock(&sc->mutex);
  836. /* setup initial channel */
  837. sc->chan_idx = curchan->hw_value;
  838. init_channel = ath_get_curchannel(sc, hw);
  839. /* Reset SERDES registers */
  840. ath9k_hw_configpcipowersave(ah, 0, 0);
  841. /*
  842. * The basic interface to setting the hardware in a good
  843. * state is ``reset''. On return the hardware is known to
  844. * be powered up and with interrupts disabled. This must
  845. * be followed by initialization of the appropriate bits
  846. * and then setup of the interrupt mask.
  847. */
  848. spin_lock_bh(&sc->sc_pcu_lock);
  849. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  850. if (r) {
  851. ath_err(common,
  852. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  853. r, curchan->center_freq);
  854. spin_unlock_bh(&sc->sc_pcu_lock);
  855. goto mutex_unlock;
  856. }
  857. /*
  858. * This is needed only to setup initial state
  859. * but it's best done after a reset.
  860. */
  861. ath_update_txpow(sc);
  862. /*
  863. * Setup the hardware after reset:
  864. * The receive engine is set going.
  865. * Frame transmit is handled entirely
  866. * in the frame output path; there's nothing to do
  867. * here except setup the interrupt mask.
  868. */
  869. if (ath_startrecv(sc) != 0) {
  870. ath_err(common, "Unable to start recv logic\n");
  871. r = -EIO;
  872. spin_unlock_bh(&sc->sc_pcu_lock);
  873. goto mutex_unlock;
  874. }
  875. spin_unlock_bh(&sc->sc_pcu_lock);
  876. /* Setup our intr mask. */
  877. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  878. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  879. ATH9K_INT_GLOBAL;
  880. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  881. ah->imask |= ATH9K_INT_RXHP |
  882. ATH9K_INT_RXLP |
  883. ATH9K_INT_BB_WATCHDOG;
  884. else
  885. ah->imask |= ATH9K_INT_RX;
  886. ah->imask |= ATH9K_INT_GTT;
  887. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  888. ah->imask |= ATH9K_INT_CST;
  889. sc->sc_flags &= ~SC_OP_INVALID;
  890. sc->sc_ah->is_monitoring = false;
  891. /* Disable BMISS interrupt when we're not associated */
  892. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  893. ath9k_hw_set_interrupts(ah, ah->imask);
  894. ieee80211_wake_queues(hw);
  895. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  896. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  897. !ah->btcoex_hw.enabled) {
  898. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  899. AR_STOMP_LOW_WLAN_WGHT);
  900. ath9k_hw_btcoex_enable(ah);
  901. if (common->bus_ops->bt_coex_prep)
  902. common->bus_ops->bt_coex_prep(common);
  903. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  904. ath9k_btcoex_timer_resume(sc);
  905. }
  906. /* User has the option to provide pm-qos value as a module
  907. * parameter rather than using the default value of
  908. * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
  909. */
  910. pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
  911. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  912. common->bus_ops->extn_synch_en(common);
  913. mutex_unlock:
  914. mutex_unlock(&sc->mutex);
  915. return r;
  916. }
  917. static int ath9k_tx(struct ieee80211_hw *hw,
  918. struct sk_buff *skb)
  919. {
  920. struct ath_softc *sc = hw->priv;
  921. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  922. struct ath_tx_control txctl;
  923. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  924. if (sc->ps_enabled) {
  925. /*
  926. * mac80211 does not set PM field for normal data frames, so we
  927. * need to update that based on the current PS mode.
  928. */
  929. if (ieee80211_is_data(hdr->frame_control) &&
  930. !ieee80211_is_nullfunc(hdr->frame_control) &&
  931. !ieee80211_has_pm(hdr->frame_control)) {
  932. ath_dbg(common, ATH_DBG_PS,
  933. "Add PM=1 for a TX frame while in PS mode\n");
  934. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  935. }
  936. }
  937. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  938. /*
  939. * We are using PS-Poll and mac80211 can request TX while in
  940. * power save mode. Need to wake up hardware for the TX to be
  941. * completed and if needed, also for RX of buffered frames.
  942. */
  943. ath9k_ps_wakeup(sc);
  944. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  945. ath9k_hw_setrxabort(sc->sc_ah, 0);
  946. if (ieee80211_is_pspoll(hdr->frame_control)) {
  947. ath_dbg(common, ATH_DBG_PS,
  948. "Sending PS-Poll to pick a buffered frame\n");
  949. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  950. } else {
  951. ath_dbg(common, ATH_DBG_PS,
  952. "Wake up to complete TX\n");
  953. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  954. }
  955. /*
  956. * The actual restore operation will happen only after
  957. * the sc_flags bit is cleared. We are just dropping
  958. * the ps_usecount here.
  959. */
  960. ath9k_ps_restore(sc);
  961. }
  962. memset(&txctl, 0, sizeof(struct ath_tx_control));
  963. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  964. ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  965. if (ath_tx_start(hw, skb, &txctl) != 0) {
  966. ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
  967. goto exit;
  968. }
  969. return 0;
  970. exit:
  971. dev_kfree_skb_any(skb);
  972. return 0;
  973. }
  974. static void ath9k_stop(struct ieee80211_hw *hw)
  975. {
  976. struct ath_softc *sc = hw->priv;
  977. struct ath_hw *ah = sc->sc_ah;
  978. struct ath_common *common = ath9k_hw_common(ah);
  979. mutex_lock(&sc->mutex);
  980. if (led_blink)
  981. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  982. cancel_delayed_work_sync(&sc->tx_complete_work);
  983. cancel_delayed_work_sync(&sc->hw_pll_work);
  984. cancel_work_sync(&sc->paprd_work);
  985. cancel_work_sync(&sc->hw_check_work);
  986. if (sc->sc_flags & SC_OP_INVALID) {
  987. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  988. mutex_unlock(&sc->mutex);
  989. return;
  990. }
  991. /* Ensure HW is awake when we try to shut it down. */
  992. ath9k_ps_wakeup(sc);
  993. if (ah->btcoex_hw.enabled) {
  994. ath9k_hw_btcoex_disable(ah);
  995. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  996. ath9k_btcoex_timer_pause(sc);
  997. }
  998. spin_lock_bh(&sc->sc_pcu_lock);
  999. /* make sure h/w will not generate any interrupt
  1000. * before setting the invalid flag. */
  1001. ath9k_hw_disable_interrupts(ah);
  1002. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1003. ath_drain_all_txq(sc, false);
  1004. ath_stoprecv(sc);
  1005. ath9k_hw_phy_disable(ah);
  1006. } else
  1007. sc->rx.rxlink = NULL;
  1008. if (sc->rx.frag) {
  1009. dev_kfree_skb_any(sc->rx.frag);
  1010. sc->rx.frag = NULL;
  1011. }
  1012. /* disable HAL and put h/w to sleep */
  1013. ath9k_hw_disable(ah);
  1014. ath9k_hw_configpcipowersave(ah, 1, 1);
  1015. spin_unlock_bh(&sc->sc_pcu_lock);
  1016. ath9k_ps_restore(sc);
  1017. sc->ps_idle = true;
  1018. ath_radio_disable(sc, hw);
  1019. sc->sc_flags |= SC_OP_INVALID;
  1020. pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
  1021. mutex_unlock(&sc->mutex);
  1022. ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
  1023. }
  1024. bool ath9k_uses_beacons(int type)
  1025. {
  1026. switch (type) {
  1027. case NL80211_IFTYPE_AP:
  1028. case NL80211_IFTYPE_ADHOC:
  1029. case NL80211_IFTYPE_MESH_POINT:
  1030. return true;
  1031. default:
  1032. return false;
  1033. }
  1034. }
  1035. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1036. struct ieee80211_vif *vif)
  1037. {
  1038. struct ath_vif *avp = (void *)vif->drv_priv;
  1039. /* Disable SWBA interrupt */
  1040. sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
  1041. ath9k_ps_wakeup(sc);
  1042. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
  1043. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1044. tasklet_kill(&sc->bcon_tasklet);
  1045. ath9k_ps_restore(sc);
  1046. ath_beacon_return(sc, avp);
  1047. sc->sc_flags &= ~SC_OP_BEACONS;
  1048. if (sc->nbcnvifs > 0) {
  1049. /* Re-enable beaconing */
  1050. sc->sc_ah->imask |= ATH9K_INT_SWBA;
  1051. ath9k_ps_wakeup(sc);
  1052. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
  1053. ath9k_ps_restore(sc);
  1054. }
  1055. }
  1056. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1057. {
  1058. struct ath9k_vif_iter_data *iter_data = data;
  1059. int i;
  1060. if (iter_data->hw_macaddr)
  1061. for (i = 0; i < ETH_ALEN; i++)
  1062. iter_data->mask[i] &=
  1063. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1064. switch (vif->type) {
  1065. case NL80211_IFTYPE_AP:
  1066. iter_data->naps++;
  1067. break;
  1068. case NL80211_IFTYPE_STATION:
  1069. iter_data->nstations++;
  1070. break;
  1071. case NL80211_IFTYPE_ADHOC:
  1072. iter_data->nadhocs++;
  1073. break;
  1074. case NL80211_IFTYPE_MESH_POINT:
  1075. iter_data->nmeshes++;
  1076. break;
  1077. case NL80211_IFTYPE_WDS:
  1078. iter_data->nwds++;
  1079. break;
  1080. default:
  1081. iter_data->nothers++;
  1082. break;
  1083. }
  1084. }
  1085. /* Called with sc->mutex held. */
  1086. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1087. struct ieee80211_vif *vif,
  1088. struct ath9k_vif_iter_data *iter_data)
  1089. {
  1090. struct ath_softc *sc = hw->priv;
  1091. struct ath_hw *ah = sc->sc_ah;
  1092. struct ath_common *common = ath9k_hw_common(ah);
  1093. /*
  1094. * Use the hardware MAC address as reference, the hardware uses it
  1095. * together with the BSSID mask when matching addresses.
  1096. */
  1097. memset(iter_data, 0, sizeof(*iter_data));
  1098. iter_data->hw_macaddr = common->macaddr;
  1099. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1100. if (vif)
  1101. ath9k_vif_iter(iter_data, vif->addr, vif);
  1102. /* Get list of all active MAC addresses */
  1103. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1104. iter_data);
  1105. }
  1106. /* Called with sc->mutex held. */
  1107. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1108. struct ieee80211_vif *vif)
  1109. {
  1110. struct ath_softc *sc = hw->priv;
  1111. struct ath_hw *ah = sc->sc_ah;
  1112. struct ath_common *common = ath9k_hw_common(ah);
  1113. struct ath9k_vif_iter_data iter_data;
  1114. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1115. /* Set BSSID mask. */
  1116. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1117. ath_hw_setbssidmask(common);
  1118. /* Set op-mode & TSF */
  1119. if (iter_data.naps > 0) {
  1120. ath9k_hw_set_tsfadjust(ah, 1);
  1121. sc->sc_flags |= SC_OP_TSF_RESET;
  1122. ah->opmode = NL80211_IFTYPE_AP;
  1123. } else {
  1124. ath9k_hw_set_tsfadjust(ah, 0);
  1125. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1126. if (iter_data.nwds + iter_data.nmeshes)
  1127. ah->opmode = NL80211_IFTYPE_AP;
  1128. else if (iter_data.nadhocs)
  1129. ah->opmode = NL80211_IFTYPE_ADHOC;
  1130. else
  1131. ah->opmode = NL80211_IFTYPE_STATION;
  1132. }
  1133. /*
  1134. * Enable MIB interrupts when there are hardware phy counters.
  1135. */
  1136. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1137. if (ah->config.enable_ani)
  1138. ah->imask |= ATH9K_INT_MIB;
  1139. ah->imask |= ATH9K_INT_TSFOOR;
  1140. } else {
  1141. ah->imask &= ~ATH9K_INT_MIB;
  1142. ah->imask &= ~ATH9K_INT_TSFOOR;
  1143. }
  1144. ath9k_hw_set_interrupts(ah, ah->imask);
  1145. /* Set up ANI */
  1146. if ((iter_data.naps + iter_data.nadhocs) > 0) {
  1147. sc->sc_flags |= SC_OP_ANI_RUN;
  1148. ath_start_ani(common);
  1149. } else {
  1150. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1151. del_timer_sync(&common->ani.timer);
  1152. }
  1153. }
  1154. /* Called with sc->mutex held, vif counts set up properly. */
  1155. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1156. struct ieee80211_vif *vif)
  1157. {
  1158. struct ath_softc *sc = hw->priv;
  1159. ath9k_calculate_summary_state(hw, vif);
  1160. if (ath9k_uses_beacons(vif->type)) {
  1161. int error;
  1162. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1163. /* This may fail because upper levels do not have beacons
  1164. * properly configured yet. That's OK, we assume it
  1165. * will be properly configured and then we will be notified
  1166. * in the info_changed method and set up beacons properly
  1167. * there.
  1168. */
  1169. error = ath_beacon_alloc(sc, vif);
  1170. if (error)
  1171. ath9k_reclaim_beacon(sc, vif);
  1172. else
  1173. ath_beacon_config(sc, vif);
  1174. }
  1175. }
  1176. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1177. struct ieee80211_vif *vif)
  1178. {
  1179. struct ath_softc *sc = hw->priv;
  1180. struct ath_hw *ah = sc->sc_ah;
  1181. struct ath_common *common = ath9k_hw_common(ah);
  1182. struct ath_vif *avp = (void *)vif->drv_priv;
  1183. int ret = 0;
  1184. mutex_lock(&sc->mutex);
  1185. switch (vif->type) {
  1186. case NL80211_IFTYPE_STATION:
  1187. case NL80211_IFTYPE_WDS:
  1188. case NL80211_IFTYPE_ADHOC:
  1189. case NL80211_IFTYPE_AP:
  1190. case NL80211_IFTYPE_MESH_POINT:
  1191. break;
  1192. default:
  1193. ath_err(common, "Interface type %d not yet supported\n",
  1194. vif->type);
  1195. ret = -EOPNOTSUPP;
  1196. goto out;
  1197. }
  1198. if (ath9k_uses_beacons(vif->type)) {
  1199. if (sc->nbcnvifs >= ATH_BCBUF) {
  1200. ath_err(common, "Not enough beacon buffers when adding"
  1201. " new interface of type: %i\n",
  1202. vif->type);
  1203. ret = -ENOBUFS;
  1204. goto out;
  1205. }
  1206. }
  1207. if ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1208. sc->nvifs > 0) {
  1209. ath_err(common, "Cannot create ADHOC interface when other"
  1210. " interfaces already exist.\n");
  1211. ret = -EINVAL;
  1212. goto out;
  1213. }
  1214. ath_dbg(common, ATH_DBG_CONFIG,
  1215. "Attach a VIF of type: %d\n", vif->type);
  1216. /* Set the VIF opmode */
  1217. avp->av_opmode = vif->type;
  1218. avp->av_bslot = -1;
  1219. sc->nvifs++;
  1220. ath9k_do_vif_add_setup(hw, vif);
  1221. out:
  1222. mutex_unlock(&sc->mutex);
  1223. return ret;
  1224. }
  1225. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1226. struct ieee80211_vif *vif,
  1227. enum nl80211_iftype new_type,
  1228. bool p2p)
  1229. {
  1230. struct ath_softc *sc = hw->priv;
  1231. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1232. int ret = 0;
  1233. ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
  1234. mutex_lock(&sc->mutex);
  1235. /* See if new interface type is valid. */
  1236. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1237. (sc->nvifs > 1)) {
  1238. ath_err(common, "When using ADHOC, it must be the only"
  1239. " interface.\n");
  1240. ret = -EINVAL;
  1241. goto out;
  1242. }
  1243. if (ath9k_uses_beacons(new_type) &&
  1244. !ath9k_uses_beacons(vif->type)) {
  1245. if (sc->nbcnvifs >= ATH_BCBUF) {
  1246. ath_err(common, "No beacon slot available\n");
  1247. ret = -ENOBUFS;
  1248. goto out;
  1249. }
  1250. }
  1251. /* Clean up old vif stuff */
  1252. if (ath9k_uses_beacons(vif->type))
  1253. ath9k_reclaim_beacon(sc, vif);
  1254. /* Add new settings */
  1255. vif->type = new_type;
  1256. vif->p2p = p2p;
  1257. ath9k_do_vif_add_setup(hw, vif);
  1258. out:
  1259. mutex_unlock(&sc->mutex);
  1260. return ret;
  1261. }
  1262. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1263. struct ieee80211_vif *vif)
  1264. {
  1265. struct ath_softc *sc = hw->priv;
  1266. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1267. ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1268. mutex_lock(&sc->mutex);
  1269. sc->nvifs--;
  1270. /* Reclaim beacon resources */
  1271. if (ath9k_uses_beacons(vif->type))
  1272. ath9k_reclaim_beacon(sc, vif);
  1273. ath9k_calculate_summary_state(hw, NULL);
  1274. mutex_unlock(&sc->mutex);
  1275. }
  1276. static void ath9k_enable_ps(struct ath_softc *sc)
  1277. {
  1278. struct ath_hw *ah = sc->sc_ah;
  1279. sc->ps_enabled = true;
  1280. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1281. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1282. ah->imask |= ATH9K_INT_TIM_TIMER;
  1283. ath9k_hw_set_interrupts(ah, ah->imask);
  1284. }
  1285. ath9k_hw_setrxabort(ah, 1);
  1286. }
  1287. }
  1288. static void ath9k_disable_ps(struct ath_softc *sc)
  1289. {
  1290. struct ath_hw *ah = sc->sc_ah;
  1291. sc->ps_enabled = false;
  1292. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1293. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1294. ath9k_hw_setrxabort(ah, 0);
  1295. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1296. PS_WAIT_FOR_CAB |
  1297. PS_WAIT_FOR_PSPOLL_DATA |
  1298. PS_WAIT_FOR_TX_ACK);
  1299. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1300. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1301. ath9k_hw_set_interrupts(ah, ah->imask);
  1302. }
  1303. }
  1304. }
  1305. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1306. {
  1307. struct ath_softc *sc = hw->priv;
  1308. struct ath_hw *ah = sc->sc_ah;
  1309. struct ath_common *common = ath9k_hw_common(ah);
  1310. struct ieee80211_conf *conf = &hw->conf;
  1311. bool disable_radio = false;
  1312. mutex_lock(&sc->mutex);
  1313. /*
  1314. * Leave this as the first check because we need to turn on the
  1315. * radio if it was disabled before prior to processing the rest
  1316. * of the changes. Likewise we must only disable the radio towards
  1317. * the end.
  1318. */
  1319. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1320. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1321. if (!sc->ps_idle) {
  1322. ath_radio_enable(sc, hw);
  1323. ath_dbg(common, ATH_DBG_CONFIG,
  1324. "not-idle: enabling radio\n");
  1325. } else {
  1326. disable_radio = true;
  1327. }
  1328. }
  1329. /*
  1330. * We just prepare to enable PS. We have to wait until our AP has
  1331. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1332. * those ACKs and end up retransmitting the same null data frames.
  1333. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1334. */
  1335. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1336. unsigned long flags;
  1337. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1338. if (conf->flags & IEEE80211_CONF_PS)
  1339. ath9k_enable_ps(sc);
  1340. else
  1341. ath9k_disable_ps(sc);
  1342. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1343. }
  1344. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1345. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1346. ath_dbg(common, ATH_DBG_CONFIG,
  1347. "Monitor mode is enabled\n");
  1348. sc->sc_ah->is_monitoring = true;
  1349. } else {
  1350. ath_dbg(common, ATH_DBG_CONFIG,
  1351. "Monitor mode is disabled\n");
  1352. sc->sc_ah->is_monitoring = false;
  1353. }
  1354. }
  1355. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1356. struct ieee80211_channel *curchan = hw->conf.channel;
  1357. int pos = curchan->hw_value;
  1358. int old_pos = -1;
  1359. unsigned long flags;
  1360. if (ah->curchan)
  1361. old_pos = ah->curchan - &ah->channels[0];
  1362. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1363. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1364. else
  1365. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1366. ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1367. curchan->center_freq);
  1368. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1369. curchan, conf->channel_type);
  1370. /* update survey stats for the old channel before switching */
  1371. spin_lock_irqsave(&common->cc_lock, flags);
  1372. ath_update_survey_stats(sc);
  1373. spin_unlock_irqrestore(&common->cc_lock, flags);
  1374. /*
  1375. * If the operating channel changes, change the survey in-use flags
  1376. * along with it.
  1377. * Reset the survey data for the new channel, unless we're switching
  1378. * back to the operating channel from an off-channel operation.
  1379. */
  1380. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1381. sc->cur_survey != &sc->survey[pos]) {
  1382. if (sc->cur_survey)
  1383. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1384. sc->cur_survey = &sc->survey[pos];
  1385. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1386. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1387. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1388. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1389. }
  1390. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1391. ath_err(common, "Unable to set channel\n");
  1392. mutex_unlock(&sc->mutex);
  1393. return -EINVAL;
  1394. }
  1395. /*
  1396. * The most recent snapshot of channel->noisefloor for the old
  1397. * channel is only available after the hardware reset. Copy it to
  1398. * the survey stats now.
  1399. */
  1400. if (old_pos >= 0)
  1401. ath_update_survey_nf(sc, old_pos);
  1402. }
  1403. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1404. sc->config.txpowlimit = 2 * conf->power_level;
  1405. ath_update_txpow(sc);
  1406. }
  1407. if (disable_radio) {
  1408. ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1409. ath_radio_disable(sc, hw);
  1410. }
  1411. mutex_unlock(&sc->mutex);
  1412. return 0;
  1413. }
  1414. #define SUPPORTED_FILTERS \
  1415. (FIF_PROMISC_IN_BSS | \
  1416. FIF_ALLMULTI | \
  1417. FIF_CONTROL | \
  1418. FIF_PSPOLL | \
  1419. FIF_OTHER_BSS | \
  1420. FIF_BCN_PRBRESP_PROMISC | \
  1421. FIF_PROBE_REQ | \
  1422. FIF_FCSFAIL)
  1423. /* FIXME: sc->sc_full_reset ? */
  1424. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1425. unsigned int changed_flags,
  1426. unsigned int *total_flags,
  1427. u64 multicast)
  1428. {
  1429. struct ath_softc *sc = hw->priv;
  1430. u32 rfilt;
  1431. changed_flags &= SUPPORTED_FILTERS;
  1432. *total_flags &= SUPPORTED_FILTERS;
  1433. sc->rx.rxfilter = *total_flags;
  1434. ath9k_ps_wakeup(sc);
  1435. rfilt = ath_calcrxfilter(sc);
  1436. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1437. ath9k_ps_restore(sc);
  1438. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1439. "Set HW RX filter: 0x%x\n", rfilt);
  1440. }
  1441. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1442. struct ieee80211_vif *vif,
  1443. struct ieee80211_sta *sta)
  1444. {
  1445. struct ath_softc *sc = hw->priv;
  1446. ath_node_attach(sc, sta);
  1447. return 0;
  1448. }
  1449. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1450. struct ieee80211_vif *vif,
  1451. struct ieee80211_sta *sta)
  1452. {
  1453. struct ath_softc *sc = hw->priv;
  1454. ath_node_detach(sc, sta);
  1455. return 0;
  1456. }
  1457. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1458. const struct ieee80211_tx_queue_params *params)
  1459. {
  1460. struct ath_softc *sc = hw->priv;
  1461. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1462. struct ath_txq *txq;
  1463. struct ath9k_tx_queue_info qi;
  1464. int ret = 0;
  1465. if (queue >= WME_NUM_AC)
  1466. return 0;
  1467. txq = sc->tx.txq_map[queue];
  1468. mutex_lock(&sc->mutex);
  1469. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1470. qi.tqi_aifs = params->aifs;
  1471. qi.tqi_cwmin = params->cw_min;
  1472. qi.tqi_cwmax = params->cw_max;
  1473. qi.tqi_burstTime = params->txop;
  1474. ath_dbg(common, ATH_DBG_CONFIG,
  1475. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1476. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1477. params->cw_max, params->txop);
  1478. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1479. if (ret)
  1480. ath_err(common, "TXQ Update failed\n");
  1481. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1482. if (queue == WME_AC_BE && !ret)
  1483. ath_beaconq_config(sc);
  1484. mutex_unlock(&sc->mutex);
  1485. return ret;
  1486. }
  1487. static int ath9k_set_key(struct ieee80211_hw *hw,
  1488. enum set_key_cmd cmd,
  1489. struct ieee80211_vif *vif,
  1490. struct ieee80211_sta *sta,
  1491. struct ieee80211_key_conf *key)
  1492. {
  1493. struct ath_softc *sc = hw->priv;
  1494. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1495. int ret = 0;
  1496. if (ath9k_modparam_nohwcrypt)
  1497. return -ENOSPC;
  1498. mutex_lock(&sc->mutex);
  1499. ath9k_ps_wakeup(sc);
  1500. ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1501. switch (cmd) {
  1502. case SET_KEY:
  1503. ret = ath_key_config(common, vif, sta, key);
  1504. if (ret >= 0) {
  1505. key->hw_key_idx = ret;
  1506. /* push IV and Michael MIC generation to stack */
  1507. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1508. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1509. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1510. if (sc->sc_ah->sw_mgmt_crypto &&
  1511. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1512. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1513. ret = 0;
  1514. }
  1515. break;
  1516. case DISABLE_KEY:
  1517. ath_key_delete(common, key);
  1518. break;
  1519. default:
  1520. ret = -EINVAL;
  1521. }
  1522. ath9k_ps_restore(sc);
  1523. mutex_unlock(&sc->mutex);
  1524. return ret;
  1525. }
  1526. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1527. struct ieee80211_vif *vif,
  1528. struct ieee80211_bss_conf *bss_conf,
  1529. u32 changed)
  1530. {
  1531. struct ath_softc *sc = hw->priv;
  1532. struct ath_hw *ah = sc->sc_ah;
  1533. struct ath_common *common = ath9k_hw_common(ah);
  1534. struct ath_vif *avp = (void *)vif->drv_priv;
  1535. int slottime;
  1536. int error;
  1537. mutex_lock(&sc->mutex);
  1538. if (changed & BSS_CHANGED_BSSID) {
  1539. /* Set BSSID */
  1540. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1541. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1542. common->curaid = 0;
  1543. ath9k_hw_write_associd(ah);
  1544. /* Set aggregation protection mode parameters */
  1545. sc->config.ath_aggr_prot = 0;
  1546. ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
  1547. common->curbssid, common->curaid);
  1548. /* need to reconfigure the beacon */
  1549. sc->sc_flags &= ~SC_OP_BEACONS ;
  1550. }
  1551. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1552. if ((changed & BSS_CHANGED_BEACON) ||
  1553. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1554. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1555. error = ath_beacon_alloc(sc, vif);
  1556. if (!error)
  1557. ath_beacon_config(sc, vif);
  1558. }
  1559. if (changed & BSS_CHANGED_ERP_SLOT) {
  1560. if (bss_conf->use_short_slot)
  1561. slottime = 9;
  1562. else
  1563. slottime = 20;
  1564. if (vif->type == NL80211_IFTYPE_AP) {
  1565. /*
  1566. * Defer update, so that connected stations can adjust
  1567. * their settings at the same time.
  1568. * See beacon.c for more details
  1569. */
  1570. sc->beacon.slottime = slottime;
  1571. sc->beacon.updateslot = UPDATE;
  1572. } else {
  1573. ah->slottime = slottime;
  1574. ath9k_hw_init_global_settings(ah);
  1575. }
  1576. }
  1577. /* Disable transmission of beacons */
  1578. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1579. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1580. if (changed & BSS_CHANGED_BEACON_INT) {
  1581. sc->beacon_interval = bss_conf->beacon_int;
  1582. /*
  1583. * In case of AP mode, the HW TSF has to be reset
  1584. * when the beacon interval changes.
  1585. */
  1586. if (vif->type == NL80211_IFTYPE_AP) {
  1587. sc->sc_flags |= SC_OP_TSF_RESET;
  1588. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1589. error = ath_beacon_alloc(sc, vif);
  1590. if (!error)
  1591. ath_beacon_config(sc, vif);
  1592. } else {
  1593. ath_beacon_config(sc, vif);
  1594. }
  1595. }
  1596. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1597. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1598. bss_conf->use_short_preamble);
  1599. if (bss_conf->use_short_preamble)
  1600. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1601. else
  1602. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1603. }
  1604. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1605. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1606. bss_conf->use_cts_prot);
  1607. if (bss_conf->use_cts_prot &&
  1608. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1609. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1610. else
  1611. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1612. }
  1613. if (changed & BSS_CHANGED_ASSOC) {
  1614. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1615. bss_conf->assoc);
  1616. ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
  1617. }
  1618. mutex_unlock(&sc->mutex);
  1619. }
  1620. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1621. {
  1622. struct ath_softc *sc = hw->priv;
  1623. u64 tsf;
  1624. mutex_lock(&sc->mutex);
  1625. ath9k_ps_wakeup(sc);
  1626. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1627. ath9k_ps_restore(sc);
  1628. mutex_unlock(&sc->mutex);
  1629. return tsf;
  1630. }
  1631. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1632. {
  1633. struct ath_softc *sc = hw->priv;
  1634. mutex_lock(&sc->mutex);
  1635. ath9k_ps_wakeup(sc);
  1636. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1637. ath9k_ps_restore(sc);
  1638. mutex_unlock(&sc->mutex);
  1639. }
  1640. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1641. {
  1642. struct ath_softc *sc = hw->priv;
  1643. mutex_lock(&sc->mutex);
  1644. ath9k_ps_wakeup(sc);
  1645. ath9k_hw_reset_tsf(sc->sc_ah);
  1646. ath9k_ps_restore(sc);
  1647. mutex_unlock(&sc->mutex);
  1648. }
  1649. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1650. struct ieee80211_vif *vif,
  1651. enum ieee80211_ampdu_mlme_action action,
  1652. struct ieee80211_sta *sta,
  1653. u16 tid, u16 *ssn, u8 buf_size)
  1654. {
  1655. struct ath_softc *sc = hw->priv;
  1656. int ret = 0;
  1657. local_bh_disable();
  1658. switch (action) {
  1659. case IEEE80211_AMPDU_RX_START:
  1660. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1661. ret = -ENOTSUPP;
  1662. break;
  1663. case IEEE80211_AMPDU_RX_STOP:
  1664. break;
  1665. case IEEE80211_AMPDU_TX_START:
  1666. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1667. return -EOPNOTSUPP;
  1668. ath9k_ps_wakeup(sc);
  1669. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1670. if (!ret)
  1671. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1672. ath9k_ps_restore(sc);
  1673. break;
  1674. case IEEE80211_AMPDU_TX_STOP:
  1675. ath9k_ps_wakeup(sc);
  1676. ath_tx_aggr_stop(sc, sta, tid);
  1677. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1678. ath9k_ps_restore(sc);
  1679. break;
  1680. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1681. ath9k_ps_wakeup(sc);
  1682. ath_tx_aggr_resume(sc, sta, tid);
  1683. ath9k_ps_restore(sc);
  1684. break;
  1685. default:
  1686. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1687. }
  1688. local_bh_enable();
  1689. return ret;
  1690. }
  1691. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1692. struct survey_info *survey)
  1693. {
  1694. struct ath_softc *sc = hw->priv;
  1695. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1696. struct ieee80211_supported_band *sband;
  1697. struct ieee80211_channel *chan;
  1698. unsigned long flags;
  1699. int pos;
  1700. spin_lock_irqsave(&common->cc_lock, flags);
  1701. if (idx == 0)
  1702. ath_update_survey_stats(sc);
  1703. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1704. if (sband && idx >= sband->n_channels) {
  1705. idx -= sband->n_channels;
  1706. sband = NULL;
  1707. }
  1708. if (!sband)
  1709. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1710. if (!sband || idx >= sband->n_channels) {
  1711. spin_unlock_irqrestore(&common->cc_lock, flags);
  1712. return -ENOENT;
  1713. }
  1714. chan = &sband->channels[idx];
  1715. pos = chan->hw_value;
  1716. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1717. survey->channel = chan;
  1718. spin_unlock_irqrestore(&common->cc_lock, flags);
  1719. return 0;
  1720. }
  1721. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1722. {
  1723. struct ath_softc *sc = hw->priv;
  1724. struct ath_hw *ah = sc->sc_ah;
  1725. mutex_lock(&sc->mutex);
  1726. ah->coverage_class = coverage_class;
  1727. ath9k_hw_init_global_settings(ah);
  1728. mutex_unlock(&sc->mutex);
  1729. }
  1730. struct ieee80211_ops ath9k_ops = {
  1731. .tx = ath9k_tx,
  1732. .start = ath9k_start,
  1733. .stop = ath9k_stop,
  1734. .add_interface = ath9k_add_interface,
  1735. .change_interface = ath9k_change_interface,
  1736. .remove_interface = ath9k_remove_interface,
  1737. .config = ath9k_config,
  1738. .configure_filter = ath9k_configure_filter,
  1739. .sta_add = ath9k_sta_add,
  1740. .sta_remove = ath9k_sta_remove,
  1741. .conf_tx = ath9k_conf_tx,
  1742. .bss_info_changed = ath9k_bss_info_changed,
  1743. .set_key = ath9k_set_key,
  1744. .get_tsf = ath9k_get_tsf,
  1745. .set_tsf = ath9k_set_tsf,
  1746. .reset_tsf = ath9k_reset_tsf,
  1747. .ampdu_action = ath9k_ampdu_action,
  1748. .get_survey = ath9k_get_survey,
  1749. .rfkill_poll = ath9k_rfkill_poll_state,
  1750. .set_coverage_class = ath9k_set_coverage_class,
  1751. };