i915_debugfs.c 41 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. #include "intel_ringbuffer.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. #define DRM_I915_RING_DEBUG 1
  38. #if defined(CONFIG_DEBUG_FS)
  39. enum {
  40. ACTIVE_LIST,
  41. FLUSHING_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. DEFERRED_FREE_LIST,
  45. };
  46. static const char *yesno(int v)
  47. {
  48. return v ? "yes" : "no";
  49. }
  50. static int i915_capabilities(struct seq_file *m, void *data)
  51. {
  52. struct drm_info_node *node = (struct drm_info_node *) m->private;
  53. struct drm_device *dev = node->minor->dev;
  54. const struct intel_device_info *info = INTEL_INFO(dev);
  55. seq_printf(m, "gen: %d\n", info->gen);
  56. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. B(is_mobile);
  58. B(is_i85x);
  59. B(is_i915g);
  60. B(is_i945gm);
  61. B(is_g33);
  62. B(need_gfx_hws);
  63. B(is_g4x);
  64. B(is_pineview);
  65. B(is_broadwater);
  66. B(is_crestline);
  67. B(has_fbc);
  68. B(has_pipe_cxsr);
  69. B(has_hotplug);
  70. B(cursor_needs_physical);
  71. B(has_overlay);
  72. B(overlay_needs_physical);
  73. B(supports_tv);
  74. B(has_bsd_ring);
  75. B(has_blt_ring);
  76. #undef B
  77. return 0;
  78. }
  79. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  80. {
  81. if (obj->user_pin_count > 0)
  82. return "P";
  83. else if (obj->pin_count > 0)
  84. return "p";
  85. else
  86. return " ";
  87. }
  88. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  89. {
  90. switch (obj->tiling_mode) {
  91. default:
  92. case I915_TILING_NONE: return " ";
  93. case I915_TILING_X: return "X";
  94. case I915_TILING_Y: return "Y";
  95. }
  96. }
  97. static const char *cache_level_str(int type)
  98. {
  99. switch (type) {
  100. case I915_CACHE_NONE: return " uncached";
  101. case I915_CACHE_LLC: return " snooped (LLC)";
  102. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  103. default: return "";
  104. }
  105. }
  106. static void
  107. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  108. {
  109. seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
  110. &obj->base,
  111. get_pin_flag(obj),
  112. get_tiling_flag(obj),
  113. obj->base.size,
  114. obj->base.read_domains,
  115. obj->base.write_domain,
  116. obj->last_rendering_seqno,
  117. obj->last_fenced_seqno,
  118. cache_level_str(obj->cache_level),
  119. obj->dirty ? " dirty" : "",
  120. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  121. if (obj->base.name)
  122. seq_printf(m, " (name: %d)", obj->base.name);
  123. if (obj->fence_reg != I915_FENCE_REG_NONE)
  124. seq_printf(m, " (fence: %d)", obj->fence_reg);
  125. if (obj->gtt_space != NULL)
  126. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  127. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  128. if (obj->pin_mappable || obj->fault_mappable) {
  129. char s[3], *t = s;
  130. if (obj->pin_mappable)
  131. *t++ = 'p';
  132. if (obj->fault_mappable)
  133. *t++ = 'f';
  134. *t = '\0';
  135. seq_printf(m, " (%s mappable)", s);
  136. }
  137. if (obj->ring != NULL)
  138. seq_printf(m, " (%s)", obj->ring->name);
  139. }
  140. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  141. {
  142. struct drm_info_node *node = (struct drm_info_node *) m->private;
  143. uintptr_t list = (uintptr_t) node->info_ent->data;
  144. struct list_head *head;
  145. struct drm_device *dev = node->minor->dev;
  146. drm_i915_private_t *dev_priv = dev->dev_private;
  147. struct drm_i915_gem_object *obj;
  148. size_t total_obj_size, total_gtt_size;
  149. int count, ret;
  150. ret = mutex_lock_interruptible(&dev->struct_mutex);
  151. if (ret)
  152. return ret;
  153. switch (list) {
  154. case ACTIVE_LIST:
  155. seq_printf(m, "Active:\n");
  156. head = &dev_priv->mm.active_list;
  157. break;
  158. case INACTIVE_LIST:
  159. seq_printf(m, "Inactive:\n");
  160. head = &dev_priv->mm.inactive_list;
  161. break;
  162. case PINNED_LIST:
  163. seq_printf(m, "Pinned:\n");
  164. head = &dev_priv->mm.pinned_list;
  165. break;
  166. case FLUSHING_LIST:
  167. seq_printf(m, "Flushing:\n");
  168. head = &dev_priv->mm.flushing_list;
  169. break;
  170. case DEFERRED_FREE_LIST:
  171. seq_printf(m, "Deferred free:\n");
  172. head = &dev_priv->mm.deferred_free_list;
  173. break;
  174. default:
  175. mutex_unlock(&dev->struct_mutex);
  176. return -EINVAL;
  177. }
  178. total_obj_size = total_gtt_size = count = 0;
  179. list_for_each_entry(obj, head, mm_list) {
  180. seq_printf(m, " ");
  181. describe_obj(m, obj);
  182. seq_printf(m, "\n");
  183. total_obj_size += obj->base.size;
  184. total_gtt_size += obj->gtt_space->size;
  185. count++;
  186. }
  187. mutex_unlock(&dev->struct_mutex);
  188. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  189. count, total_obj_size, total_gtt_size);
  190. return 0;
  191. }
  192. #define count_objects(list, member) do { \
  193. list_for_each_entry(obj, list, member) { \
  194. size += obj->gtt_space->size; \
  195. ++count; \
  196. if (obj->map_and_fenceable) { \
  197. mappable_size += obj->gtt_space->size; \
  198. ++mappable_count; \
  199. } \
  200. } \
  201. } while(0)
  202. static int i915_gem_object_info(struct seq_file *m, void* data)
  203. {
  204. struct drm_info_node *node = (struct drm_info_node *) m->private;
  205. struct drm_device *dev = node->minor->dev;
  206. struct drm_i915_private *dev_priv = dev->dev_private;
  207. u32 count, mappable_count;
  208. size_t size, mappable_size;
  209. struct drm_i915_gem_object *obj;
  210. int ret;
  211. ret = mutex_lock_interruptible(&dev->struct_mutex);
  212. if (ret)
  213. return ret;
  214. seq_printf(m, "%u objects, %zu bytes\n",
  215. dev_priv->mm.object_count,
  216. dev_priv->mm.object_memory);
  217. size = count = mappable_size = mappable_count = 0;
  218. count_objects(&dev_priv->mm.gtt_list, gtt_list);
  219. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  220. count, mappable_count, size, mappable_size);
  221. size = count = mappable_size = mappable_count = 0;
  222. count_objects(&dev_priv->mm.active_list, mm_list);
  223. count_objects(&dev_priv->mm.flushing_list, mm_list);
  224. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  225. count, mappable_count, size, mappable_size);
  226. size = count = mappable_size = mappable_count = 0;
  227. count_objects(&dev_priv->mm.pinned_list, mm_list);
  228. seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
  229. count, mappable_count, size, mappable_size);
  230. size = count = mappable_size = mappable_count = 0;
  231. count_objects(&dev_priv->mm.inactive_list, mm_list);
  232. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  233. count, mappable_count, size, mappable_size);
  234. size = count = mappable_size = mappable_count = 0;
  235. count_objects(&dev_priv->mm.deferred_free_list, mm_list);
  236. seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
  237. count, mappable_count, size, mappable_size);
  238. size = count = mappable_size = mappable_count = 0;
  239. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  240. if (obj->fault_mappable) {
  241. size += obj->gtt_space->size;
  242. ++count;
  243. }
  244. if (obj->pin_mappable) {
  245. mappable_size += obj->gtt_space->size;
  246. ++mappable_count;
  247. }
  248. }
  249. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  250. mappable_count, mappable_size);
  251. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  252. count, size);
  253. seq_printf(m, "%zu [%zu] gtt total\n",
  254. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  255. mutex_unlock(&dev->struct_mutex);
  256. return 0;
  257. }
  258. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  259. {
  260. struct drm_info_node *node = (struct drm_info_node *) m->private;
  261. struct drm_device *dev = node->minor->dev;
  262. struct drm_i915_private *dev_priv = dev->dev_private;
  263. struct drm_i915_gem_object *obj;
  264. size_t total_obj_size, total_gtt_size;
  265. int count, ret;
  266. ret = mutex_lock_interruptible(&dev->struct_mutex);
  267. if (ret)
  268. return ret;
  269. total_obj_size = total_gtt_size = count = 0;
  270. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  271. seq_printf(m, " ");
  272. describe_obj(m, obj);
  273. seq_printf(m, "\n");
  274. total_obj_size += obj->base.size;
  275. total_gtt_size += obj->gtt_space->size;
  276. count++;
  277. }
  278. mutex_unlock(&dev->struct_mutex);
  279. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  280. count, total_obj_size, total_gtt_size);
  281. return 0;
  282. }
  283. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  284. {
  285. struct drm_info_node *node = (struct drm_info_node *) m->private;
  286. struct drm_device *dev = node->minor->dev;
  287. unsigned long flags;
  288. struct intel_crtc *crtc;
  289. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  290. const char pipe = pipe_name(crtc->pipe);
  291. const char plane = plane_name(crtc->plane);
  292. struct intel_unpin_work *work;
  293. spin_lock_irqsave(&dev->event_lock, flags);
  294. work = crtc->unpin_work;
  295. if (work == NULL) {
  296. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  297. pipe, plane);
  298. } else {
  299. if (!work->pending) {
  300. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  301. pipe, plane);
  302. } else {
  303. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  304. pipe, plane);
  305. }
  306. if (work->enable_stall_check)
  307. seq_printf(m, "Stall check enabled, ");
  308. else
  309. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  310. seq_printf(m, "%d prepares\n", work->pending);
  311. if (work->old_fb_obj) {
  312. struct drm_i915_gem_object *obj = work->old_fb_obj;
  313. if (obj)
  314. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  315. }
  316. if (work->pending_flip_obj) {
  317. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  318. if (obj)
  319. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  320. }
  321. }
  322. spin_unlock_irqrestore(&dev->event_lock, flags);
  323. }
  324. return 0;
  325. }
  326. static int i915_gem_request_info(struct seq_file *m, void *data)
  327. {
  328. struct drm_info_node *node = (struct drm_info_node *) m->private;
  329. struct drm_device *dev = node->minor->dev;
  330. drm_i915_private_t *dev_priv = dev->dev_private;
  331. struct drm_i915_gem_request *gem_request;
  332. int ret, count;
  333. ret = mutex_lock_interruptible(&dev->struct_mutex);
  334. if (ret)
  335. return ret;
  336. count = 0;
  337. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  338. seq_printf(m, "Render requests:\n");
  339. list_for_each_entry(gem_request,
  340. &dev_priv->ring[RCS].request_list,
  341. list) {
  342. seq_printf(m, " %d @ %d\n",
  343. gem_request->seqno,
  344. (int) (jiffies - gem_request->emitted_jiffies));
  345. }
  346. count++;
  347. }
  348. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  349. seq_printf(m, "BSD requests:\n");
  350. list_for_each_entry(gem_request,
  351. &dev_priv->ring[VCS].request_list,
  352. list) {
  353. seq_printf(m, " %d @ %d\n",
  354. gem_request->seqno,
  355. (int) (jiffies - gem_request->emitted_jiffies));
  356. }
  357. count++;
  358. }
  359. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  360. seq_printf(m, "BLT requests:\n");
  361. list_for_each_entry(gem_request,
  362. &dev_priv->ring[BCS].request_list,
  363. list) {
  364. seq_printf(m, " %d @ %d\n",
  365. gem_request->seqno,
  366. (int) (jiffies - gem_request->emitted_jiffies));
  367. }
  368. count++;
  369. }
  370. mutex_unlock(&dev->struct_mutex);
  371. if (count == 0)
  372. seq_printf(m, "No requests\n");
  373. return 0;
  374. }
  375. static void i915_ring_seqno_info(struct seq_file *m,
  376. struct intel_ring_buffer *ring)
  377. {
  378. if (ring->get_seqno) {
  379. seq_printf(m, "Current sequence (%s): %d\n",
  380. ring->name, ring->get_seqno(ring));
  381. seq_printf(m, "Waiter sequence (%s): %d\n",
  382. ring->name, ring->waiting_seqno);
  383. seq_printf(m, "IRQ sequence (%s): %d\n",
  384. ring->name, ring->irq_seqno);
  385. }
  386. }
  387. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  388. {
  389. struct drm_info_node *node = (struct drm_info_node *) m->private;
  390. struct drm_device *dev = node->minor->dev;
  391. drm_i915_private_t *dev_priv = dev->dev_private;
  392. int ret, i;
  393. ret = mutex_lock_interruptible(&dev->struct_mutex);
  394. if (ret)
  395. return ret;
  396. for (i = 0; i < I915_NUM_RINGS; i++)
  397. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  398. mutex_unlock(&dev->struct_mutex);
  399. return 0;
  400. }
  401. static int i915_interrupt_info(struct seq_file *m, void *data)
  402. {
  403. struct drm_info_node *node = (struct drm_info_node *) m->private;
  404. struct drm_device *dev = node->minor->dev;
  405. drm_i915_private_t *dev_priv = dev->dev_private;
  406. int ret, i, pipe;
  407. ret = mutex_lock_interruptible(&dev->struct_mutex);
  408. if (ret)
  409. return ret;
  410. if (!HAS_PCH_SPLIT(dev)) {
  411. seq_printf(m, "Interrupt enable: %08x\n",
  412. I915_READ(IER));
  413. seq_printf(m, "Interrupt identity: %08x\n",
  414. I915_READ(IIR));
  415. seq_printf(m, "Interrupt mask: %08x\n",
  416. I915_READ(IMR));
  417. for_each_pipe(pipe)
  418. seq_printf(m, "Pipe %c stat: %08x\n",
  419. pipe_name(pipe),
  420. I915_READ(PIPESTAT(pipe)));
  421. } else {
  422. seq_printf(m, "North Display Interrupt enable: %08x\n",
  423. I915_READ(DEIER));
  424. seq_printf(m, "North Display Interrupt identity: %08x\n",
  425. I915_READ(DEIIR));
  426. seq_printf(m, "North Display Interrupt mask: %08x\n",
  427. I915_READ(DEIMR));
  428. seq_printf(m, "South Display Interrupt enable: %08x\n",
  429. I915_READ(SDEIER));
  430. seq_printf(m, "South Display Interrupt identity: %08x\n",
  431. I915_READ(SDEIIR));
  432. seq_printf(m, "South Display Interrupt mask: %08x\n",
  433. I915_READ(SDEIMR));
  434. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  435. I915_READ(GTIER));
  436. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  437. I915_READ(GTIIR));
  438. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  439. I915_READ(GTIMR));
  440. }
  441. seq_printf(m, "Interrupts received: %d\n",
  442. atomic_read(&dev_priv->irq_received));
  443. for (i = 0; i < I915_NUM_RINGS; i++) {
  444. if (IS_GEN6(dev)) {
  445. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  446. dev_priv->ring[i].name,
  447. I915_READ_IMR(&dev_priv->ring[i]));
  448. }
  449. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  450. }
  451. mutex_unlock(&dev->struct_mutex);
  452. return 0;
  453. }
  454. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  455. {
  456. struct drm_info_node *node = (struct drm_info_node *) m->private;
  457. struct drm_device *dev = node->minor->dev;
  458. drm_i915_private_t *dev_priv = dev->dev_private;
  459. int i, ret;
  460. ret = mutex_lock_interruptible(&dev->struct_mutex);
  461. if (ret)
  462. return ret;
  463. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  464. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  465. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  466. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  467. seq_printf(m, "Fenced object[%2d] = ", i);
  468. if (obj == NULL)
  469. seq_printf(m, "unused");
  470. else
  471. describe_obj(m, obj);
  472. seq_printf(m, "\n");
  473. }
  474. mutex_unlock(&dev->struct_mutex);
  475. return 0;
  476. }
  477. static int i915_hws_info(struct seq_file *m, void *data)
  478. {
  479. struct drm_info_node *node = (struct drm_info_node *) m->private;
  480. struct drm_device *dev = node->minor->dev;
  481. drm_i915_private_t *dev_priv = dev->dev_private;
  482. struct intel_ring_buffer *ring;
  483. const volatile u32 __iomem *hws;
  484. int i;
  485. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  486. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  487. if (hws == NULL)
  488. return 0;
  489. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  490. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  491. i * 4,
  492. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  493. }
  494. return 0;
  495. }
  496. static void i915_dump_object(struct seq_file *m,
  497. struct io_mapping *mapping,
  498. struct drm_i915_gem_object *obj)
  499. {
  500. int page, page_count, i;
  501. page_count = obj->base.size / PAGE_SIZE;
  502. for (page = 0; page < page_count; page++) {
  503. u32 *mem = io_mapping_map_wc(mapping,
  504. obj->gtt_offset + page * PAGE_SIZE);
  505. for (i = 0; i < PAGE_SIZE; i += 4)
  506. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  507. io_mapping_unmap(mem);
  508. }
  509. }
  510. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  511. {
  512. struct drm_info_node *node = (struct drm_info_node *) m->private;
  513. struct drm_device *dev = node->minor->dev;
  514. drm_i915_private_t *dev_priv = dev->dev_private;
  515. struct drm_i915_gem_object *obj;
  516. int ret;
  517. ret = mutex_lock_interruptible(&dev->struct_mutex);
  518. if (ret)
  519. return ret;
  520. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  521. if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
  522. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  523. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
  524. }
  525. }
  526. mutex_unlock(&dev->struct_mutex);
  527. return 0;
  528. }
  529. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  530. {
  531. struct drm_info_node *node = (struct drm_info_node *) m->private;
  532. struct drm_device *dev = node->minor->dev;
  533. drm_i915_private_t *dev_priv = dev->dev_private;
  534. struct intel_ring_buffer *ring;
  535. int ret;
  536. ret = mutex_lock_interruptible(&dev->struct_mutex);
  537. if (ret)
  538. return ret;
  539. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  540. if (!ring->obj) {
  541. seq_printf(m, "No ringbuffer setup\n");
  542. } else {
  543. const u8 __iomem *virt = ring->virtual_start;
  544. uint32_t off;
  545. for (off = 0; off < ring->size; off += 4) {
  546. uint32_t *ptr = (uint32_t *)(virt + off);
  547. seq_printf(m, "%08x : %08x\n", off, *ptr);
  548. }
  549. }
  550. mutex_unlock(&dev->struct_mutex);
  551. return 0;
  552. }
  553. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  554. {
  555. struct drm_info_node *node = (struct drm_info_node *) m->private;
  556. struct drm_device *dev = node->minor->dev;
  557. drm_i915_private_t *dev_priv = dev->dev_private;
  558. struct intel_ring_buffer *ring;
  559. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  560. if (ring->size == 0)
  561. return 0;
  562. seq_printf(m, "Ring %s:\n", ring->name);
  563. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  564. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  565. seq_printf(m, " Size : %08x\n", ring->size);
  566. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  567. seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
  568. if (IS_GEN6(dev)) {
  569. seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
  570. seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
  571. }
  572. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  573. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  574. return 0;
  575. }
  576. static const char *ring_str(int ring)
  577. {
  578. switch (ring) {
  579. case RING_RENDER: return " render";
  580. case RING_BSD: return " bsd";
  581. case RING_BLT: return " blt";
  582. default: return "";
  583. }
  584. }
  585. static const char *pin_flag(int pinned)
  586. {
  587. if (pinned > 0)
  588. return " P";
  589. else if (pinned < 0)
  590. return " p";
  591. else
  592. return "";
  593. }
  594. static const char *tiling_flag(int tiling)
  595. {
  596. switch (tiling) {
  597. default:
  598. case I915_TILING_NONE: return "";
  599. case I915_TILING_X: return " X";
  600. case I915_TILING_Y: return " Y";
  601. }
  602. }
  603. static const char *dirty_flag(int dirty)
  604. {
  605. return dirty ? " dirty" : "";
  606. }
  607. static const char *purgeable_flag(int purgeable)
  608. {
  609. return purgeable ? " purgeable" : "";
  610. }
  611. static void print_error_buffers(struct seq_file *m,
  612. const char *name,
  613. struct drm_i915_error_buffer *err,
  614. int count)
  615. {
  616. seq_printf(m, "%s [%d]:\n", name, count);
  617. while (count--) {
  618. seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
  619. err->gtt_offset,
  620. err->size,
  621. err->read_domains,
  622. err->write_domain,
  623. err->seqno,
  624. pin_flag(err->pinned),
  625. tiling_flag(err->tiling),
  626. dirty_flag(err->dirty),
  627. purgeable_flag(err->purgeable),
  628. ring_str(err->ring),
  629. cache_level_str(err->cache_level));
  630. if (err->name)
  631. seq_printf(m, " (name: %d)", err->name);
  632. if (err->fence_reg != I915_FENCE_REG_NONE)
  633. seq_printf(m, " (fence: %d)", err->fence_reg);
  634. seq_printf(m, "\n");
  635. err++;
  636. }
  637. }
  638. static int i915_error_state(struct seq_file *m, void *unused)
  639. {
  640. struct drm_info_node *node = (struct drm_info_node *) m->private;
  641. struct drm_device *dev = node->minor->dev;
  642. drm_i915_private_t *dev_priv = dev->dev_private;
  643. struct drm_i915_error_state *error;
  644. unsigned long flags;
  645. int i, page, offset, elt;
  646. spin_lock_irqsave(&dev_priv->error_lock, flags);
  647. if (!dev_priv->first_error) {
  648. seq_printf(m, "no error state collected\n");
  649. goto out;
  650. }
  651. error = dev_priv->first_error;
  652. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  653. error->time.tv_usec);
  654. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  655. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  656. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  657. if (INTEL_INFO(dev)->gen >= 6) {
  658. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  659. seq_printf(m, "Blitter command stream:\n");
  660. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  661. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  662. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  663. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  664. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  665. seq_printf(m, "Video (BSD) command stream:\n");
  666. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  667. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  668. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  669. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  670. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  671. }
  672. seq_printf(m, "Render command stream:\n");
  673. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  674. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  675. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  676. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  677. if (INTEL_INFO(dev)->gen >= 4) {
  678. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  679. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  680. }
  681. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  682. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  683. for (i = 0; i < dev_priv->num_fence_regs; i++)
  684. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  685. if (error->active_bo)
  686. print_error_buffers(m, "Active",
  687. error->active_bo,
  688. error->active_bo_count);
  689. if (error->pinned_bo)
  690. print_error_buffers(m, "Pinned",
  691. error->pinned_bo,
  692. error->pinned_bo_count);
  693. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  694. if (error->batchbuffer[i]) {
  695. struct drm_i915_error_object *obj = error->batchbuffer[i];
  696. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  697. dev_priv->ring[i].name,
  698. obj->gtt_offset);
  699. offset = 0;
  700. for (page = 0; page < obj->page_count; page++) {
  701. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  702. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  703. offset += 4;
  704. }
  705. }
  706. }
  707. }
  708. for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
  709. if (error->ringbuffer[i]) {
  710. struct drm_i915_error_object *obj = error->ringbuffer[i];
  711. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  712. dev_priv->ring[i].name,
  713. obj->gtt_offset);
  714. offset = 0;
  715. for (page = 0; page < obj->page_count; page++) {
  716. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  717. seq_printf(m, "%08x : %08x\n",
  718. offset,
  719. obj->pages[page][elt]);
  720. offset += 4;
  721. }
  722. }
  723. }
  724. }
  725. if (error->overlay)
  726. intel_overlay_print_error_state(m, error->overlay);
  727. if (error->display)
  728. intel_display_print_error_state(m, dev, error->display);
  729. out:
  730. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  731. return 0;
  732. }
  733. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  734. {
  735. struct drm_info_node *node = (struct drm_info_node *) m->private;
  736. struct drm_device *dev = node->minor->dev;
  737. drm_i915_private_t *dev_priv = dev->dev_private;
  738. u16 crstanddelay = I915_READ16(CRSTANDVID);
  739. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  740. return 0;
  741. }
  742. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  743. {
  744. struct drm_info_node *node = (struct drm_info_node *) m->private;
  745. struct drm_device *dev = node->minor->dev;
  746. drm_i915_private_t *dev_priv = dev->dev_private;
  747. int ret;
  748. if (IS_GEN5(dev)) {
  749. u16 rgvswctl = I915_READ16(MEMSWCTL);
  750. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  751. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  752. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  753. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  754. MEMSTAT_VID_SHIFT);
  755. seq_printf(m, "Current P-state: %d\n",
  756. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  757. } else if (IS_GEN6(dev)) {
  758. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  759. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  760. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  761. u32 rpstat;
  762. u32 rpupei, rpcurup, rpprevup;
  763. u32 rpdownei, rpcurdown, rpprevdown;
  764. int max_freq;
  765. /* RPSTAT1 is in the GT power well */
  766. ret = mutex_lock_interruptible(&dev->struct_mutex);
  767. if (ret)
  768. return ret;
  769. gen6_gt_force_wake_get(dev_priv);
  770. rpstat = I915_READ(GEN6_RPSTAT1);
  771. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  772. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  773. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  774. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  775. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  776. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  777. gen6_gt_force_wake_put(dev_priv);
  778. mutex_unlock(&dev->struct_mutex);
  779. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  780. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  781. seq_printf(m, "Render p-state ratio: %d\n",
  782. (gt_perf_status & 0xff00) >> 8);
  783. seq_printf(m, "Render p-state VID: %d\n",
  784. gt_perf_status & 0xff);
  785. seq_printf(m, "Render p-state limit: %d\n",
  786. rp_state_limits & 0xff);
  787. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  788. GEN6_CAGF_SHIFT) * 50);
  789. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  790. GEN6_CURICONT_MASK);
  791. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  792. GEN6_CURBSYTAVG_MASK);
  793. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  794. GEN6_CURBSYTAVG_MASK);
  795. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  796. GEN6_CURIAVG_MASK);
  797. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  798. GEN6_CURBSYTAVG_MASK);
  799. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  800. GEN6_CURBSYTAVG_MASK);
  801. max_freq = (rp_state_cap & 0xff0000) >> 16;
  802. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  803. max_freq * 50);
  804. max_freq = (rp_state_cap & 0xff00) >> 8;
  805. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  806. max_freq * 50);
  807. max_freq = rp_state_cap & 0xff;
  808. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  809. max_freq * 50);
  810. } else {
  811. seq_printf(m, "no P-state info available\n");
  812. }
  813. return 0;
  814. }
  815. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  816. {
  817. struct drm_info_node *node = (struct drm_info_node *) m->private;
  818. struct drm_device *dev = node->minor->dev;
  819. drm_i915_private_t *dev_priv = dev->dev_private;
  820. u32 delayfreq;
  821. int i;
  822. for (i = 0; i < 16; i++) {
  823. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  824. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  825. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  826. }
  827. return 0;
  828. }
  829. static inline int MAP_TO_MV(int map)
  830. {
  831. return 1250 - (map * 25);
  832. }
  833. static int i915_inttoext_table(struct seq_file *m, void *unused)
  834. {
  835. struct drm_info_node *node = (struct drm_info_node *) m->private;
  836. struct drm_device *dev = node->minor->dev;
  837. drm_i915_private_t *dev_priv = dev->dev_private;
  838. u32 inttoext;
  839. int i;
  840. for (i = 1; i <= 32; i++) {
  841. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  842. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  843. }
  844. return 0;
  845. }
  846. static int i915_drpc_info(struct seq_file *m, void *unused)
  847. {
  848. struct drm_info_node *node = (struct drm_info_node *) m->private;
  849. struct drm_device *dev = node->minor->dev;
  850. drm_i915_private_t *dev_priv = dev->dev_private;
  851. u32 rgvmodectl = I915_READ(MEMMODECTL);
  852. u32 rstdbyctl = I915_READ(RSTDBYCTL);
  853. u16 crstandvid = I915_READ16(CRSTANDVID);
  854. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  855. "yes" : "no");
  856. seq_printf(m, "Boost freq: %d\n",
  857. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  858. MEMMODE_BOOST_FREQ_SHIFT);
  859. seq_printf(m, "HW control enabled: %s\n",
  860. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  861. seq_printf(m, "SW control enabled: %s\n",
  862. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  863. seq_printf(m, "Gated voltage change: %s\n",
  864. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  865. seq_printf(m, "Starting frequency: P%d\n",
  866. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  867. seq_printf(m, "Max P-state: P%d\n",
  868. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  869. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  870. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  871. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  872. seq_printf(m, "Render standby enabled: %s\n",
  873. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  874. seq_printf(m, "Current RS state: ");
  875. switch (rstdbyctl & RSX_STATUS_MASK) {
  876. case RSX_STATUS_ON:
  877. seq_printf(m, "on\n");
  878. break;
  879. case RSX_STATUS_RC1:
  880. seq_printf(m, "RC1\n");
  881. break;
  882. case RSX_STATUS_RC1E:
  883. seq_printf(m, "RC1E\n");
  884. break;
  885. case RSX_STATUS_RS1:
  886. seq_printf(m, "RS1\n");
  887. break;
  888. case RSX_STATUS_RS2:
  889. seq_printf(m, "RS2 (RC6)\n");
  890. break;
  891. case RSX_STATUS_RS3:
  892. seq_printf(m, "RC3 (RC6+)\n");
  893. break;
  894. default:
  895. seq_printf(m, "unknown\n");
  896. break;
  897. }
  898. return 0;
  899. }
  900. static int i915_fbc_status(struct seq_file *m, void *unused)
  901. {
  902. struct drm_info_node *node = (struct drm_info_node *) m->private;
  903. struct drm_device *dev = node->minor->dev;
  904. drm_i915_private_t *dev_priv = dev->dev_private;
  905. if (!I915_HAS_FBC(dev)) {
  906. seq_printf(m, "FBC unsupported on this chipset\n");
  907. return 0;
  908. }
  909. if (intel_fbc_enabled(dev)) {
  910. seq_printf(m, "FBC enabled\n");
  911. } else {
  912. seq_printf(m, "FBC disabled: ");
  913. switch (dev_priv->no_fbc_reason) {
  914. case FBC_NO_OUTPUT:
  915. seq_printf(m, "no outputs");
  916. break;
  917. case FBC_STOLEN_TOO_SMALL:
  918. seq_printf(m, "not enough stolen memory");
  919. break;
  920. case FBC_UNSUPPORTED_MODE:
  921. seq_printf(m, "mode not supported");
  922. break;
  923. case FBC_MODE_TOO_LARGE:
  924. seq_printf(m, "mode too large");
  925. break;
  926. case FBC_BAD_PLANE:
  927. seq_printf(m, "FBC unsupported on plane");
  928. break;
  929. case FBC_NOT_TILED:
  930. seq_printf(m, "scanout buffer not tiled");
  931. break;
  932. case FBC_MULTIPLE_PIPES:
  933. seq_printf(m, "multiple pipes are enabled");
  934. break;
  935. case FBC_MODULE_PARAM:
  936. seq_printf(m, "disabled per module param (default off)");
  937. break;
  938. default:
  939. seq_printf(m, "unknown reason");
  940. }
  941. seq_printf(m, "\n");
  942. }
  943. return 0;
  944. }
  945. static int i915_sr_status(struct seq_file *m, void *unused)
  946. {
  947. struct drm_info_node *node = (struct drm_info_node *) m->private;
  948. struct drm_device *dev = node->minor->dev;
  949. drm_i915_private_t *dev_priv = dev->dev_private;
  950. bool sr_enabled = false;
  951. if (HAS_PCH_SPLIT(dev))
  952. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  953. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  954. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  955. else if (IS_I915GM(dev))
  956. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  957. else if (IS_PINEVIEW(dev))
  958. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  959. seq_printf(m, "self-refresh: %s\n",
  960. sr_enabled ? "enabled" : "disabled");
  961. return 0;
  962. }
  963. static int i915_emon_status(struct seq_file *m, void *unused)
  964. {
  965. struct drm_info_node *node = (struct drm_info_node *) m->private;
  966. struct drm_device *dev = node->minor->dev;
  967. drm_i915_private_t *dev_priv = dev->dev_private;
  968. unsigned long temp, chipset, gfx;
  969. int ret;
  970. ret = mutex_lock_interruptible(&dev->struct_mutex);
  971. if (ret)
  972. return ret;
  973. temp = i915_mch_val(dev_priv);
  974. chipset = i915_chipset_val(dev_priv);
  975. gfx = i915_gfx_val(dev_priv);
  976. mutex_unlock(&dev->struct_mutex);
  977. seq_printf(m, "GMCH temp: %ld\n", temp);
  978. seq_printf(m, "Chipset power: %ld\n", chipset);
  979. seq_printf(m, "GFX power: %ld\n", gfx);
  980. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  981. return 0;
  982. }
  983. static int i915_gfxec(struct seq_file *m, void *unused)
  984. {
  985. struct drm_info_node *node = (struct drm_info_node *) m->private;
  986. struct drm_device *dev = node->minor->dev;
  987. drm_i915_private_t *dev_priv = dev->dev_private;
  988. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  989. return 0;
  990. }
  991. static int i915_opregion(struct seq_file *m, void *unused)
  992. {
  993. struct drm_info_node *node = (struct drm_info_node *) m->private;
  994. struct drm_device *dev = node->minor->dev;
  995. drm_i915_private_t *dev_priv = dev->dev_private;
  996. struct intel_opregion *opregion = &dev_priv->opregion;
  997. int ret;
  998. ret = mutex_lock_interruptible(&dev->struct_mutex);
  999. if (ret)
  1000. return ret;
  1001. if (opregion->header)
  1002. seq_write(m, opregion->header, OPREGION_SIZE);
  1003. mutex_unlock(&dev->struct_mutex);
  1004. return 0;
  1005. }
  1006. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1007. {
  1008. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1009. struct drm_device *dev = node->minor->dev;
  1010. drm_i915_private_t *dev_priv = dev->dev_private;
  1011. struct intel_fbdev *ifbdev;
  1012. struct intel_framebuffer *fb;
  1013. int ret;
  1014. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1015. if (ret)
  1016. return ret;
  1017. ifbdev = dev_priv->fbdev;
  1018. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1019. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1020. fb->base.width,
  1021. fb->base.height,
  1022. fb->base.depth,
  1023. fb->base.bits_per_pixel);
  1024. describe_obj(m, fb->obj);
  1025. seq_printf(m, "\n");
  1026. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1027. if (&fb->base == ifbdev->helper.fb)
  1028. continue;
  1029. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1030. fb->base.width,
  1031. fb->base.height,
  1032. fb->base.depth,
  1033. fb->base.bits_per_pixel);
  1034. describe_obj(m, fb->obj);
  1035. seq_printf(m, "\n");
  1036. }
  1037. mutex_unlock(&dev->mode_config.mutex);
  1038. return 0;
  1039. }
  1040. static int i915_context_status(struct seq_file *m, void *unused)
  1041. {
  1042. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1043. struct drm_device *dev = node->minor->dev;
  1044. drm_i915_private_t *dev_priv = dev->dev_private;
  1045. int ret;
  1046. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1047. if (ret)
  1048. return ret;
  1049. seq_printf(m, "power context ");
  1050. describe_obj(m, dev_priv->pwrctx);
  1051. seq_printf(m, "\n");
  1052. seq_printf(m, "render context ");
  1053. describe_obj(m, dev_priv->renderctx);
  1054. seq_printf(m, "\n");
  1055. mutex_unlock(&dev->mode_config.mutex);
  1056. return 0;
  1057. }
  1058. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1059. {
  1060. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1061. struct drm_device *dev = node->minor->dev;
  1062. struct drm_i915_private *dev_priv = dev->dev_private;
  1063. seq_printf(m, "forcewake count = %d\n",
  1064. atomic_read(&dev_priv->forcewake_count));
  1065. return 0;
  1066. }
  1067. static int
  1068. i915_wedged_open(struct inode *inode,
  1069. struct file *filp)
  1070. {
  1071. filp->private_data = inode->i_private;
  1072. return 0;
  1073. }
  1074. static ssize_t
  1075. i915_wedged_read(struct file *filp,
  1076. char __user *ubuf,
  1077. size_t max,
  1078. loff_t *ppos)
  1079. {
  1080. struct drm_device *dev = filp->private_data;
  1081. drm_i915_private_t *dev_priv = dev->dev_private;
  1082. char buf[80];
  1083. int len;
  1084. len = snprintf(buf, sizeof (buf),
  1085. "wedged : %d\n",
  1086. atomic_read(&dev_priv->mm.wedged));
  1087. if (len > sizeof (buf))
  1088. len = sizeof (buf);
  1089. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1090. }
  1091. static ssize_t
  1092. i915_wedged_write(struct file *filp,
  1093. const char __user *ubuf,
  1094. size_t cnt,
  1095. loff_t *ppos)
  1096. {
  1097. struct drm_device *dev = filp->private_data;
  1098. char buf[20];
  1099. int val = 1;
  1100. if (cnt > 0) {
  1101. if (cnt > sizeof (buf) - 1)
  1102. return -EINVAL;
  1103. if (copy_from_user(buf, ubuf, cnt))
  1104. return -EFAULT;
  1105. buf[cnt] = 0;
  1106. val = simple_strtoul(buf, NULL, 0);
  1107. }
  1108. DRM_INFO("Manually setting wedged to %d\n", val);
  1109. i915_handle_error(dev, val);
  1110. return cnt;
  1111. }
  1112. static const struct file_operations i915_wedged_fops = {
  1113. .owner = THIS_MODULE,
  1114. .open = i915_wedged_open,
  1115. .read = i915_wedged_read,
  1116. .write = i915_wedged_write,
  1117. .llseek = default_llseek,
  1118. };
  1119. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1120. * allocated we need to hook into the minor for release. */
  1121. static int
  1122. drm_add_fake_info_node(struct drm_minor *minor,
  1123. struct dentry *ent,
  1124. const void *key)
  1125. {
  1126. struct drm_info_node *node;
  1127. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1128. if (node == NULL) {
  1129. debugfs_remove(ent);
  1130. return -ENOMEM;
  1131. }
  1132. node->minor = minor;
  1133. node->dent = ent;
  1134. node->info_ent = (void *) key;
  1135. list_add(&node->list, &minor->debugfs_nodes.list);
  1136. return 0;
  1137. }
  1138. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  1139. {
  1140. struct drm_device *dev = minor->dev;
  1141. struct dentry *ent;
  1142. ent = debugfs_create_file("i915_wedged",
  1143. S_IRUGO | S_IWUSR,
  1144. root, dev,
  1145. &i915_wedged_fops);
  1146. if (IS_ERR(ent))
  1147. return PTR_ERR(ent);
  1148. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  1149. }
  1150. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1151. {
  1152. struct drm_device *dev = inode->i_private;
  1153. struct drm_i915_private *dev_priv = dev->dev_private;
  1154. int ret;
  1155. if (!IS_GEN6(dev))
  1156. return 0;
  1157. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1158. if (ret)
  1159. return ret;
  1160. gen6_gt_force_wake_get(dev_priv);
  1161. mutex_unlock(&dev->struct_mutex);
  1162. return 0;
  1163. }
  1164. int i915_forcewake_release(struct inode *inode, struct file *file)
  1165. {
  1166. struct drm_device *dev = inode->i_private;
  1167. struct drm_i915_private *dev_priv = dev->dev_private;
  1168. if (!IS_GEN6(dev))
  1169. return 0;
  1170. /*
  1171. * It's bad that we can potentially hang userspace if struct_mutex gets
  1172. * forever stuck. However, if we cannot acquire this lock it means that
  1173. * almost certainly the driver has hung, is not unload-able. Therefore
  1174. * hanging here is probably a minor inconvenience not to be seen my
  1175. * almost every user.
  1176. */
  1177. mutex_lock(&dev->struct_mutex);
  1178. gen6_gt_force_wake_put(dev_priv);
  1179. mutex_unlock(&dev->struct_mutex);
  1180. return 0;
  1181. }
  1182. static const struct file_operations i915_forcewake_fops = {
  1183. .owner = THIS_MODULE,
  1184. .open = i915_forcewake_open,
  1185. .release = i915_forcewake_release,
  1186. };
  1187. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1188. {
  1189. struct drm_device *dev = minor->dev;
  1190. struct dentry *ent;
  1191. ent = debugfs_create_file("i915_forcewake_user",
  1192. S_IRUSR,
  1193. root, dev,
  1194. &i915_forcewake_fops);
  1195. if (IS_ERR(ent))
  1196. return PTR_ERR(ent);
  1197. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1198. }
  1199. static struct drm_info_list i915_debugfs_list[] = {
  1200. {"i915_capabilities", i915_capabilities, 0},
  1201. {"i915_gem_objects", i915_gem_object_info, 0},
  1202. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1203. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1204. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  1205. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1206. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  1207. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  1208. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1209. {"i915_gem_request", i915_gem_request_info, 0},
  1210. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1211. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1212. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1213. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1214. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1215. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1216. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
  1217. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
  1218. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
  1219. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
  1220. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
  1221. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
  1222. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  1223. {"i915_error_state", i915_error_state, 0},
  1224. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1225. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1226. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1227. {"i915_inttoext_table", i915_inttoext_table, 0},
  1228. {"i915_drpc_info", i915_drpc_info, 0},
  1229. {"i915_emon_status", i915_emon_status, 0},
  1230. {"i915_gfxec", i915_gfxec, 0},
  1231. {"i915_fbc_status", i915_fbc_status, 0},
  1232. {"i915_sr_status", i915_sr_status, 0},
  1233. {"i915_opregion", i915_opregion, 0},
  1234. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1235. {"i915_context_status", i915_context_status, 0},
  1236. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1237. };
  1238. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1239. int i915_debugfs_init(struct drm_minor *minor)
  1240. {
  1241. int ret;
  1242. ret = i915_wedged_create(minor->debugfs_root, minor);
  1243. if (ret)
  1244. return ret;
  1245. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1246. if (ret)
  1247. return ret;
  1248. return drm_debugfs_create_files(i915_debugfs_list,
  1249. I915_DEBUGFS_ENTRIES,
  1250. minor->debugfs_root, minor);
  1251. }
  1252. void i915_debugfs_cleanup(struct drm_minor *minor)
  1253. {
  1254. drm_debugfs_remove_files(i915_debugfs_list,
  1255. I915_DEBUGFS_ENTRIES, minor);
  1256. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1257. 1, minor);
  1258. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1259. 1, minor);
  1260. }
  1261. #endif /* CONFIG_DEBUG_FS */