phy.c 31 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /**
  17. * DOC: Programming Atheros 802.11n analog front end radios
  18. *
  19. * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
  20. * devices have either an external AR2133 analog front end radio for single
  21. * band 2.4 GHz communication or an AR5133 analog front end radio for dual
  22. * band 2.4 GHz / 5 GHz communication.
  23. *
  24. * All devices after the AR5416 and AR5418 family starting with the AR9280
  25. * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
  26. * into a single-chip and require less programming.
  27. *
  28. * The following single-chips exist with a respective embedded radio:
  29. *
  30. * AR9280 - 11n dual-band 2x2 MIMO for PCIe
  31. * AR9281 - 11n single-band 1x2 MIMO for PCIe
  32. * AR9285 - 11n single-band 1x1 for PCIe
  33. * AR9287 - 11n single-band 2x2 MIMO for PCIe
  34. *
  35. * AR9220 - 11n dual-band 2x2 MIMO for PCI
  36. * AR9223 - 11n single-band 2x2 MIMO for PCI
  37. *
  38. * AR9287 - 11n single-band 1x1 MIMO for USB
  39. */
  40. #include "hw.h"
  41. /**
  42. * ath9k_hw_write_regs - ??
  43. *
  44. * @ah: atheros hardware structure
  45. * @freqIndex:
  46. * @regWrites:
  47. *
  48. * Used for both the chipsets with an external AR2133/AR5133 radios and
  49. * single-chip devices.
  50. */
  51. void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
  52. {
  53. REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
  54. }
  55. /**
  56. * ath9k_hw_ar9280_set_channel - set channel on single-chip device
  57. * @ah: atheros hardware structure
  58. * @chan:
  59. *
  60. * This is the function to change channel on single-chip devices, that is
  61. * all devices after ar9280.
  62. *
  63. * This function takes the channel value in MHz and sets
  64. * hardware channel value. Assumes writes have been enabled to analog bus.
  65. *
  66. * Actual Expression,
  67. *
  68. * For 2GHz channel,
  69. * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  70. * (freq_ref = 40MHz)
  71. *
  72. * For 5GHz channel,
  73. * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  74. * (freq_ref = 40MHz/(24>>amodeRefSel))
  75. */
  76. int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  77. {
  78. u16 bMode, fracMode, aModeRefSel = 0;
  79. u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
  80. struct chan_centers centers;
  81. u32 refDivA = 24;
  82. ath9k_hw_get_channel_centers(ah, chan, &centers);
  83. freq = centers.synth_center;
  84. reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
  85. reg32 &= 0xc0000000;
  86. if (freq < 4800) { /* 2 GHz, fractional mode */
  87. u32 txctl;
  88. int regWrites = 0;
  89. bMode = 1;
  90. fracMode = 1;
  91. aModeRefSel = 0;
  92. channelSel = (freq * 0x10000) / 15;
  93. if (AR_SREV_9287_11_OR_LATER(ah)) {
  94. if (freq == 2484) {
  95. /* Enable channel spreading for channel 14 */
  96. REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
  97. 1, regWrites);
  98. } else {
  99. REG_WRITE_ARRAY(&ah->iniCckfirNormal,
  100. 1, regWrites);
  101. }
  102. } else {
  103. txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  104. if (freq == 2484) {
  105. /* Enable channel spreading for channel 14 */
  106. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  107. txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  108. } else {
  109. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  110. txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
  111. }
  112. }
  113. } else {
  114. bMode = 0;
  115. fracMode = 0;
  116. switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
  117. case 0:
  118. if ((freq % 20) == 0) {
  119. aModeRefSel = 3;
  120. } else if ((freq % 10) == 0) {
  121. aModeRefSel = 2;
  122. }
  123. if (aModeRefSel)
  124. break;
  125. case 1:
  126. default:
  127. aModeRefSel = 0;
  128. /*
  129. * Enable 2G (fractional) mode for channels
  130. * which are 5MHz spaced.
  131. */
  132. fracMode = 1;
  133. refDivA = 1;
  134. channelSel = (freq * 0x8000) / 15;
  135. /* RefDivA setting */
  136. REG_RMW_FIELD(ah, AR_AN_SYNTH9,
  137. AR_AN_SYNTH9_REFDIVA, refDivA);
  138. }
  139. if (!fracMode) {
  140. ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
  141. channelSel = ndiv & 0x1ff;
  142. channelFrac = (ndiv & 0xfffffe00) * 2;
  143. channelSel = (channelSel << 17) | channelFrac;
  144. }
  145. }
  146. reg32 = reg32 |
  147. (bMode << 29) |
  148. (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
  149. REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
  150. ah->curchan = chan;
  151. ah->curchan_rad_index = -1;
  152. return 0;
  153. }
  154. /**
  155. * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
  156. * @ah: atheros hardware structure
  157. * @chan:
  158. *
  159. * For single-chip solutions. Converts to baseband spur frequency given the
  160. * input channel frequency and compute register settings below.
  161. */
  162. void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
  163. {
  164. int bb_spur = AR_NO_SPUR;
  165. int freq;
  166. int bin, cur_bin;
  167. int bb_spur_off, spur_subchannel_sd;
  168. int spur_freq_sd;
  169. int spur_delta_phase;
  170. int denominator;
  171. int upper, lower, cur_vit_mask;
  172. int tmp, newVal;
  173. int i;
  174. int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
  175. AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
  176. };
  177. int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
  178. AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
  179. };
  180. int inc[4] = { 0, 100, 0, 0 };
  181. struct chan_centers centers;
  182. int8_t mask_m[123];
  183. int8_t mask_p[123];
  184. int8_t mask_amt;
  185. int tmp_mask;
  186. int cur_bb_spur;
  187. bool is2GHz = IS_CHAN_2GHZ(chan);
  188. memset(&mask_m, 0, sizeof(int8_t) * 123);
  189. memset(&mask_p, 0, sizeof(int8_t) * 123);
  190. ath9k_hw_get_channel_centers(ah, chan, &centers);
  191. freq = centers.synth_center;
  192. ah->config.spurmode = SPUR_ENABLE_EEPROM;
  193. for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
  194. cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
  195. if (is2GHz)
  196. cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
  197. else
  198. cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
  199. if (AR_NO_SPUR == cur_bb_spur)
  200. break;
  201. cur_bb_spur = cur_bb_spur - freq;
  202. if (IS_CHAN_HT40(chan)) {
  203. if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
  204. (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
  205. bb_spur = cur_bb_spur;
  206. break;
  207. }
  208. } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
  209. (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
  210. bb_spur = cur_bb_spur;
  211. break;
  212. }
  213. }
  214. if (AR_NO_SPUR == bb_spur) {
  215. REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
  216. AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
  217. return;
  218. } else {
  219. REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
  220. AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
  221. }
  222. bin = bb_spur * 320;
  223. tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
  224. newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
  225. AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
  226. AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
  227. AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
  228. REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
  229. newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
  230. AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
  231. AR_PHY_SPUR_REG_MASK_RATE_SELECT |
  232. AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
  233. SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
  234. REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
  235. if (IS_CHAN_HT40(chan)) {
  236. if (bb_spur < 0) {
  237. spur_subchannel_sd = 1;
  238. bb_spur_off = bb_spur + 10;
  239. } else {
  240. spur_subchannel_sd = 0;
  241. bb_spur_off = bb_spur - 10;
  242. }
  243. } else {
  244. spur_subchannel_sd = 0;
  245. bb_spur_off = bb_spur;
  246. }
  247. if (IS_CHAN_HT40(chan))
  248. spur_delta_phase =
  249. ((bb_spur * 262144) /
  250. 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
  251. else
  252. spur_delta_phase =
  253. ((bb_spur * 524288) /
  254. 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
  255. denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
  256. spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
  257. newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
  258. SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
  259. SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
  260. REG_WRITE(ah, AR_PHY_TIMING11, newVal);
  261. newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
  262. REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
  263. cur_bin = -6000;
  264. upper = bin + 100;
  265. lower = bin - 100;
  266. for (i = 0; i < 4; i++) {
  267. int pilot_mask = 0;
  268. int chan_mask = 0;
  269. int bp = 0;
  270. for (bp = 0; bp < 30; bp++) {
  271. if ((cur_bin > lower) && (cur_bin < upper)) {
  272. pilot_mask = pilot_mask | 0x1 << bp;
  273. chan_mask = chan_mask | 0x1 << bp;
  274. }
  275. cur_bin += 100;
  276. }
  277. cur_bin += inc[i];
  278. REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
  279. REG_WRITE(ah, chan_mask_reg[i], chan_mask);
  280. }
  281. cur_vit_mask = 6100;
  282. upper = bin + 120;
  283. lower = bin - 120;
  284. for (i = 0; i < 123; i++) {
  285. if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
  286. /* workaround for gcc bug #37014 */
  287. volatile int tmp_v = abs(cur_vit_mask - bin);
  288. if (tmp_v < 75)
  289. mask_amt = 1;
  290. else
  291. mask_amt = 0;
  292. if (cur_vit_mask < 0)
  293. mask_m[abs(cur_vit_mask / 100)] = mask_amt;
  294. else
  295. mask_p[cur_vit_mask / 100] = mask_amt;
  296. }
  297. cur_vit_mask -= 100;
  298. }
  299. tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
  300. | (mask_m[48] << 26) | (mask_m[49] << 24)
  301. | (mask_m[50] << 22) | (mask_m[51] << 20)
  302. | (mask_m[52] << 18) | (mask_m[53] << 16)
  303. | (mask_m[54] << 14) | (mask_m[55] << 12)
  304. | (mask_m[56] << 10) | (mask_m[57] << 8)
  305. | (mask_m[58] << 6) | (mask_m[59] << 4)
  306. | (mask_m[60] << 2) | (mask_m[61] << 0);
  307. REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
  308. REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
  309. tmp_mask = (mask_m[31] << 28)
  310. | (mask_m[32] << 26) | (mask_m[33] << 24)
  311. | (mask_m[34] << 22) | (mask_m[35] << 20)
  312. | (mask_m[36] << 18) | (mask_m[37] << 16)
  313. | (mask_m[48] << 14) | (mask_m[39] << 12)
  314. | (mask_m[40] << 10) | (mask_m[41] << 8)
  315. | (mask_m[42] << 6) | (mask_m[43] << 4)
  316. | (mask_m[44] << 2) | (mask_m[45] << 0);
  317. REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
  318. REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
  319. tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
  320. | (mask_m[18] << 26) | (mask_m[18] << 24)
  321. | (mask_m[20] << 22) | (mask_m[20] << 20)
  322. | (mask_m[22] << 18) | (mask_m[22] << 16)
  323. | (mask_m[24] << 14) | (mask_m[24] << 12)
  324. | (mask_m[25] << 10) | (mask_m[26] << 8)
  325. | (mask_m[27] << 6) | (mask_m[28] << 4)
  326. | (mask_m[29] << 2) | (mask_m[30] << 0);
  327. REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
  328. REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
  329. tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
  330. | (mask_m[2] << 26) | (mask_m[3] << 24)
  331. | (mask_m[4] << 22) | (mask_m[5] << 20)
  332. | (mask_m[6] << 18) | (mask_m[7] << 16)
  333. | (mask_m[8] << 14) | (mask_m[9] << 12)
  334. | (mask_m[10] << 10) | (mask_m[11] << 8)
  335. | (mask_m[12] << 6) | (mask_m[13] << 4)
  336. | (mask_m[14] << 2) | (mask_m[15] << 0);
  337. REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
  338. REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
  339. tmp_mask = (mask_p[15] << 28)
  340. | (mask_p[14] << 26) | (mask_p[13] << 24)
  341. | (mask_p[12] << 22) | (mask_p[11] << 20)
  342. | (mask_p[10] << 18) | (mask_p[9] << 16)
  343. | (mask_p[8] << 14) | (mask_p[7] << 12)
  344. | (mask_p[6] << 10) | (mask_p[5] << 8)
  345. | (mask_p[4] << 6) | (mask_p[3] << 4)
  346. | (mask_p[2] << 2) | (mask_p[1] << 0);
  347. REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
  348. REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
  349. tmp_mask = (mask_p[30] << 28)
  350. | (mask_p[29] << 26) | (mask_p[28] << 24)
  351. | (mask_p[27] << 22) | (mask_p[26] << 20)
  352. | (mask_p[25] << 18) | (mask_p[24] << 16)
  353. | (mask_p[23] << 14) | (mask_p[22] << 12)
  354. | (mask_p[21] << 10) | (mask_p[20] << 8)
  355. | (mask_p[19] << 6) | (mask_p[18] << 4)
  356. | (mask_p[17] << 2) | (mask_p[16] << 0);
  357. REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
  358. REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
  359. tmp_mask = (mask_p[45] << 28)
  360. | (mask_p[44] << 26) | (mask_p[43] << 24)
  361. | (mask_p[42] << 22) | (mask_p[41] << 20)
  362. | (mask_p[40] << 18) | (mask_p[39] << 16)
  363. | (mask_p[38] << 14) | (mask_p[37] << 12)
  364. | (mask_p[36] << 10) | (mask_p[35] << 8)
  365. | (mask_p[34] << 6) | (mask_p[33] << 4)
  366. | (mask_p[32] << 2) | (mask_p[31] << 0);
  367. REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
  368. REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
  369. tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
  370. | (mask_p[59] << 26) | (mask_p[58] << 24)
  371. | (mask_p[57] << 22) | (mask_p[56] << 20)
  372. | (mask_p[55] << 18) | (mask_p[54] << 16)
  373. | (mask_p[53] << 14) | (mask_p[52] << 12)
  374. | (mask_p[51] << 10) | (mask_p[50] << 8)
  375. | (mask_p[49] << 6) | (mask_p[48] << 4)
  376. | (mask_p[47] << 2) | (mask_p[46] << 0);
  377. REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
  378. REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
  379. }
  380. /* All code below is for non single-chip solutions */
  381. /**
  382. * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
  383. * @rfbuf:
  384. * @reg32:
  385. * @numBits:
  386. * @firstBit:
  387. * @column:
  388. *
  389. * Performs analog "swizzling" of parameters into their location.
  390. * Used on external AR2133/AR5133 radios.
  391. */
  392. static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
  393. u32 numBits, u32 firstBit,
  394. u32 column)
  395. {
  396. u32 tmp32, mask, arrayEntry, lastBit;
  397. int32_t bitPosition, bitsLeft;
  398. tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
  399. arrayEntry = (firstBit - 1) / 8;
  400. bitPosition = (firstBit - 1) % 8;
  401. bitsLeft = numBits;
  402. while (bitsLeft > 0) {
  403. lastBit = (bitPosition + bitsLeft > 8) ?
  404. 8 : bitPosition + bitsLeft;
  405. mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
  406. (column * 8);
  407. rfBuf[arrayEntry] &= ~mask;
  408. rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
  409. (column * 8)) & mask;
  410. bitsLeft -= 8 - bitPosition;
  411. tmp32 = tmp32 >> (8 - bitPosition);
  412. bitPosition = 0;
  413. arrayEntry++;
  414. }
  415. }
  416. /*
  417. * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
  418. * rf_pwd_icsyndiv.
  419. *
  420. * Theoretical Rules:
  421. * if 2 GHz band
  422. * if forceBiasAuto
  423. * if synth_freq < 2412
  424. * bias = 0
  425. * else if 2412 <= synth_freq <= 2422
  426. * bias = 1
  427. * else // synth_freq > 2422
  428. * bias = 2
  429. * else if forceBias > 0
  430. * bias = forceBias & 7
  431. * else
  432. * no change, use value from ini file
  433. * else
  434. * no change, invalid band
  435. *
  436. * 1st Mod:
  437. * 2422 also uses value of 2
  438. * <approved>
  439. *
  440. * 2nd Mod:
  441. * Less than 2412 uses value of 0, 2412 and above uses value of 2
  442. */
  443. static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
  444. {
  445. struct ath_common *common = ath9k_hw_common(ah);
  446. u32 tmp_reg;
  447. int reg_writes = 0;
  448. u32 new_bias = 0;
  449. if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
  450. return;
  451. }
  452. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  453. if (synth_freq < 2412)
  454. new_bias = 0;
  455. else if (synth_freq < 2422)
  456. new_bias = 1;
  457. else
  458. new_bias = 2;
  459. /* pre-reverse this field */
  460. tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
  461. ath_print(common, ATH_DBG_CONFIG,
  462. "Force rf_pwd_icsyndiv to %1d on %4d\n",
  463. new_bias, synth_freq);
  464. /* swizzle rf_pwd_icsyndiv */
  465. ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
  466. /* write Bank 6 with new params */
  467. REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
  468. }
  469. /**
  470. * ath9k_hw_decrease_chain_power()
  471. *
  472. * @ah: atheros hardware structure
  473. * @chan:
  474. *
  475. * Only used on the AR5416 and AR5418 with the external AR2133/AR5133 radios.
  476. *
  477. * Sets a chain internal RF path to the lowest output power. Any
  478. * further writes to bank6 after this setting will override these
  479. * changes. Thus this function must be the last function in the
  480. * sequence to modify bank 6.
  481. *
  482. * This function must be called after ar5416SetRfRegs() which is
  483. * called from ath9k_hw_process_ini() due to swizzling of bank 6.
  484. * Depends on ah->analogBank6Data being initialized by
  485. * ath9k_hw_set_rf_regs()
  486. *
  487. * Additional additive reduction in power -
  488. * change chain's switch table so chain's tx state is actually the rx
  489. * state value. May produce different results in 2GHz/5GHz as well as
  490. * board to board but in general should be a reduction.
  491. *
  492. * Activated by #ifdef ALTER_SWITCH. Not tried yet. If so, must be
  493. * called after ah->eep_ops->set_board_values() due to RMW of
  494. * PHY_SWITCH_CHAIN_0.
  495. */
  496. void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
  497. struct ath9k_channel *chan)
  498. {
  499. int i, regWrites = 0;
  500. u32 bank6SelMask;
  501. u32 *bank6Temp = ah->bank6Temp;
  502. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  503. switch (ah->config.diversity_control) {
  504. case ATH9K_ANT_FIXED_A:
  505. bank6SelMask =
  506. (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
  507. REDUCE_CHAIN_0 : /* swapped, reduce chain 0 */
  508. REDUCE_CHAIN_1; /* normal, select chain 1/2 to reduce */
  509. break;
  510. case ATH9K_ANT_FIXED_B:
  511. bank6SelMask =
  512. (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
  513. REDUCE_CHAIN_1 : /* swapped, reduce chain 1/2 */
  514. REDUCE_CHAIN_0; /* normal, select chain 0 to reduce */
  515. break;
  516. case ATH9K_ANT_VARIABLE:
  517. return; /* do not change anything */
  518. break;
  519. default:
  520. return; /* do not change anything */
  521. break;
  522. }
  523. for (i = 0; i < ah->iniBank6.ia_rows; i++)
  524. bank6Temp[i] = ah->analogBank6Data[i];
  525. /* Write Bank 5 to switch Bank 6 write to selected chain only */
  526. REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
  527. /*
  528. * Modify Bank6 selected chain to use lowest amplification.
  529. * Modifies the parameters to a value of 1.
  530. * Depends on existing bank 6 values to be cached in
  531. * ah->analogBank6Data
  532. */
  533. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
  534. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
  535. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
  536. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
  537. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
  538. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
  539. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
  540. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
  541. ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
  542. REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
  543. REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
  544. #ifdef ALTER_SWITCH
  545. REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
  546. (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
  547. | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
  548. #endif
  549. }
  550. /**
  551. * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
  552. * @ah: atheros hardware stucture
  553. * @chan:
  554. *
  555. * For the external AR2133/AR5133 radios, takes the MHz channel value and set
  556. * the channel value. Assumes writes enabled to analog bus and bank6 register
  557. * cache in ah->analogBank6Data.
  558. */
  559. int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  560. {
  561. struct ath_common *common = ath9k_hw_common(ah);
  562. u32 channelSel = 0;
  563. u32 bModeSynth = 0;
  564. u32 aModeRefSel = 0;
  565. u32 reg32 = 0;
  566. u16 freq;
  567. struct chan_centers centers;
  568. ath9k_hw_get_channel_centers(ah, chan, &centers);
  569. freq = centers.synth_center;
  570. if (freq < 4800) {
  571. u32 txctl;
  572. if (((freq - 2192) % 5) == 0) {
  573. channelSel = ((freq - 672) * 2 - 3040) / 10;
  574. bModeSynth = 0;
  575. } else if (((freq - 2224) % 5) == 0) {
  576. channelSel = ((freq - 704) * 2 - 3040) / 10;
  577. bModeSynth = 1;
  578. } else {
  579. ath_print(common, ATH_DBG_FATAL,
  580. "Invalid channel %u MHz\n", freq);
  581. return -EINVAL;
  582. }
  583. channelSel = (channelSel << 2) & 0xff;
  584. channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  585. txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  586. if (freq == 2484) {
  587. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  588. txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  589. } else {
  590. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  591. txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  592. }
  593. } else if ((freq % 20) == 0 && freq >= 5120) {
  594. channelSel =
  595. ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  596. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  597. } else if ((freq % 10) == 0) {
  598. channelSel =
  599. ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  600. if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  601. aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  602. else
  603. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  604. } else if ((freq % 5) == 0) {
  605. channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  606. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  607. } else {
  608. ath_print(common, ATH_DBG_FATAL,
  609. "Invalid channel %u MHz\n", freq);
  610. return -EINVAL;
  611. }
  612. ath9k_hw_force_bias(ah, freq);
  613. ath9k_hw_decrease_chain_power(ah, chan);
  614. reg32 =
  615. (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  616. (1 << 5) | 0x1;
  617. REG_WRITE(ah, AR_PHY(0x37), reg32);
  618. ah->curchan = chan;
  619. ah->curchan_rad_index = -1;
  620. return 0;
  621. }
  622. /**
  623. * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
  624. * @ah: atheros hardware structure
  625. * @chan:
  626. *
  627. * For non single-chip solutions. Converts to baseband spur frequency given the
  628. * input channel frequency and compute register settings below.
  629. */
  630. void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
  631. {
  632. int bb_spur = AR_NO_SPUR;
  633. int bin, cur_bin;
  634. int spur_freq_sd;
  635. int spur_delta_phase;
  636. int denominator;
  637. int upper, lower, cur_vit_mask;
  638. int tmp, new;
  639. int i;
  640. int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
  641. AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
  642. };
  643. int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
  644. AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
  645. };
  646. int inc[4] = { 0, 100, 0, 0 };
  647. int8_t mask_m[123];
  648. int8_t mask_p[123];
  649. int8_t mask_amt;
  650. int tmp_mask;
  651. int cur_bb_spur;
  652. bool is2GHz = IS_CHAN_2GHZ(chan);
  653. memset(&mask_m, 0, sizeof(int8_t) * 123);
  654. memset(&mask_p, 0, sizeof(int8_t) * 123);
  655. for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
  656. cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
  657. if (AR_NO_SPUR == cur_bb_spur)
  658. break;
  659. cur_bb_spur = cur_bb_spur - (chan->channel * 10);
  660. if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
  661. bb_spur = cur_bb_spur;
  662. break;
  663. }
  664. }
  665. if (AR_NO_SPUR == bb_spur)
  666. return;
  667. bin = bb_spur * 32;
  668. tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
  669. new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
  670. AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
  671. AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
  672. AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
  673. REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
  674. new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
  675. AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
  676. AR_PHY_SPUR_REG_MASK_RATE_SELECT |
  677. AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
  678. SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
  679. REG_WRITE(ah, AR_PHY_SPUR_REG, new);
  680. spur_delta_phase = ((bb_spur * 524288) / 100) &
  681. AR_PHY_TIMING11_SPUR_DELTA_PHASE;
  682. denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
  683. spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
  684. new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
  685. SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
  686. SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
  687. REG_WRITE(ah, AR_PHY_TIMING11, new);
  688. cur_bin = -6000;
  689. upper = bin + 100;
  690. lower = bin - 100;
  691. for (i = 0; i < 4; i++) {
  692. int pilot_mask = 0;
  693. int chan_mask = 0;
  694. int bp = 0;
  695. for (bp = 0; bp < 30; bp++) {
  696. if ((cur_bin > lower) && (cur_bin < upper)) {
  697. pilot_mask = pilot_mask | 0x1 << bp;
  698. chan_mask = chan_mask | 0x1 << bp;
  699. }
  700. cur_bin += 100;
  701. }
  702. cur_bin += inc[i];
  703. REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
  704. REG_WRITE(ah, chan_mask_reg[i], chan_mask);
  705. }
  706. cur_vit_mask = 6100;
  707. upper = bin + 120;
  708. lower = bin - 120;
  709. for (i = 0; i < 123; i++) {
  710. if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
  711. /* workaround for gcc bug #37014 */
  712. volatile int tmp_v = abs(cur_vit_mask - bin);
  713. if (tmp_v < 75)
  714. mask_amt = 1;
  715. else
  716. mask_amt = 0;
  717. if (cur_vit_mask < 0)
  718. mask_m[abs(cur_vit_mask / 100)] = mask_amt;
  719. else
  720. mask_p[cur_vit_mask / 100] = mask_amt;
  721. }
  722. cur_vit_mask -= 100;
  723. }
  724. tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
  725. | (mask_m[48] << 26) | (mask_m[49] << 24)
  726. | (mask_m[50] << 22) | (mask_m[51] << 20)
  727. | (mask_m[52] << 18) | (mask_m[53] << 16)
  728. | (mask_m[54] << 14) | (mask_m[55] << 12)
  729. | (mask_m[56] << 10) | (mask_m[57] << 8)
  730. | (mask_m[58] << 6) | (mask_m[59] << 4)
  731. | (mask_m[60] << 2) | (mask_m[61] << 0);
  732. REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
  733. REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
  734. tmp_mask = (mask_m[31] << 28)
  735. | (mask_m[32] << 26) | (mask_m[33] << 24)
  736. | (mask_m[34] << 22) | (mask_m[35] << 20)
  737. | (mask_m[36] << 18) | (mask_m[37] << 16)
  738. | (mask_m[48] << 14) | (mask_m[39] << 12)
  739. | (mask_m[40] << 10) | (mask_m[41] << 8)
  740. | (mask_m[42] << 6) | (mask_m[43] << 4)
  741. | (mask_m[44] << 2) | (mask_m[45] << 0);
  742. REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
  743. REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
  744. tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
  745. | (mask_m[18] << 26) | (mask_m[18] << 24)
  746. | (mask_m[20] << 22) | (mask_m[20] << 20)
  747. | (mask_m[22] << 18) | (mask_m[22] << 16)
  748. | (mask_m[24] << 14) | (mask_m[24] << 12)
  749. | (mask_m[25] << 10) | (mask_m[26] << 8)
  750. | (mask_m[27] << 6) | (mask_m[28] << 4)
  751. | (mask_m[29] << 2) | (mask_m[30] << 0);
  752. REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
  753. REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
  754. tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
  755. | (mask_m[2] << 26) | (mask_m[3] << 24)
  756. | (mask_m[4] << 22) | (mask_m[5] << 20)
  757. | (mask_m[6] << 18) | (mask_m[7] << 16)
  758. | (mask_m[8] << 14) | (mask_m[9] << 12)
  759. | (mask_m[10] << 10) | (mask_m[11] << 8)
  760. | (mask_m[12] << 6) | (mask_m[13] << 4)
  761. | (mask_m[14] << 2) | (mask_m[15] << 0);
  762. REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
  763. REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
  764. tmp_mask = (mask_p[15] << 28)
  765. | (mask_p[14] << 26) | (mask_p[13] << 24)
  766. | (mask_p[12] << 22) | (mask_p[11] << 20)
  767. | (mask_p[10] << 18) | (mask_p[9] << 16)
  768. | (mask_p[8] << 14) | (mask_p[7] << 12)
  769. | (mask_p[6] << 10) | (mask_p[5] << 8)
  770. | (mask_p[4] << 6) | (mask_p[3] << 4)
  771. | (mask_p[2] << 2) | (mask_p[1] << 0);
  772. REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
  773. REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
  774. tmp_mask = (mask_p[30] << 28)
  775. | (mask_p[29] << 26) | (mask_p[28] << 24)
  776. | (mask_p[27] << 22) | (mask_p[26] << 20)
  777. | (mask_p[25] << 18) | (mask_p[24] << 16)
  778. | (mask_p[23] << 14) | (mask_p[22] << 12)
  779. | (mask_p[21] << 10) | (mask_p[20] << 8)
  780. | (mask_p[19] << 6) | (mask_p[18] << 4)
  781. | (mask_p[17] << 2) | (mask_p[16] << 0);
  782. REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
  783. REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
  784. tmp_mask = (mask_p[45] << 28)
  785. | (mask_p[44] << 26) | (mask_p[43] << 24)
  786. | (mask_p[42] << 22) | (mask_p[41] << 20)
  787. | (mask_p[40] << 18) | (mask_p[39] << 16)
  788. | (mask_p[38] << 14) | (mask_p[37] << 12)
  789. | (mask_p[36] << 10) | (mask_p[35] << 8)
  790. | (mask_p[34] << 6) | (mask_p[33] << 4)
  791. | (mask_p[32] << 2) | (mask_p[31] << 0);
  792. REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
  793. REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
  794. tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
  795. | (mask_p[59] << 26) | (mask_p[58] << 24)
  796. | (mask_p[57] << 22) | (mask_p[56] << 20)
  797. | (mask_p[55] << 18) | (mask_p[54] << 16)
  798. | (mask_p[53] << 14) | (mask_p[52] << 12)
  799. | (mask_p[51] << 10) | (mask_p[50] << 8)
  800. | (mask_p[49] << 6) | (mask_p[48] << 4)
  801. | (mask_p[47] << 2) | (mask_p[46] << 0);
  802. REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
  803. REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
  804. }
  805. /**
  806. * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
  807. * @ah: atheros hardware structure
  808. *
  809. * Only required for older devices with external AR2133/AR5133 radios.
  810. */
  811. int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
  812. {
  813. #define ATH_ALLOC_BANK(bank, size) do { \
  814. bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
  815. if (!bank) { \
  816. ath_print(common, ATH_DBG_FATAL, \
  817. "Cannot allocate RF banks\n"); \
  818. return -ENOMEM; \
  819. } \
  820. } while (0);
  821. struct ath_common *common = ath9k_hw_common(ah);
  822. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  823. ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
  824. ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
  825. ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
  826. ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
  827. ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
  828. ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
  829. ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
  830. ATH_ALLOC_BANK(ah->addac5416_21,
  831. ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
  832. ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
  833. return 0;
  834. #undef ATH_ALLOC_BANK
  835. }
  836. /**
  837. * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
  838. * @ah: atheros hardware struture
  839. * For the external AR2133/AR5133 radios banks.
  840. */
  841. void
  842. ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
  843. {
  844. #define ATH_FREE_BANK(bank) do { \
  845. kfree(bank); \
  846. bank = NULL; \
  847. } while (0);
  848. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  849. ATH_FREE_BANK(ah->analogBank0Data);
  850. ATH_FREE_BANK(ah->analogBank1Data);
  851. ATH_FREE_BANK(ah->analogBank2Data);
  852. ATH_FREE_BANK(ah->analogBank3Data);
  853. ATH_FREE_BANK(ah->analogBank6Data);
  854. ATH_FREE_BANK(ah->analogBank6TPCData);
  855. ATH_FREE_BANK(ah->analogBank7Data);
  856. ATH_FREE_BANK(ah->addac5416_21);
  857. ATH_FREE_BANK(ah->bank6Temp);
  858. #undef ATH_FREE_BANK
  859. }
  860. /* *
  861. * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
  862. * @ah: atheros hardware structure
  863. * @chan:
  864. * @modesIndex:
  865. *
  866. * Used for the external AR2133/AR5133 radios.
  867. *
  868. * Reads the EEPROM header info from the device structure and programs
  869. * all rf registers. This routine requires access to the analog
  870. * rf device. This is not required for single-chip devices.
  871. */
  872. bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  873. u16 modesIndex)
  874. {
  875. u32 eepMinorRev;
  876. u32 ob5GHz = 0, db5GHz = 0;
  877. u32 ob2GHz = 0, db2GHz = 0;
  878. int regWrites = 0;
  879. /*
  880. * Software does not need to program bank data
  881. * for single chip devices, that is AR9280 or anything
  882. * after that.
  883. */
  884. if (AR_SREV_9280_10_OR_LATER(ah))
  885. return true;
  886. /* Setup rf parameters */
  887. eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
  888. /* Setup Bank 0 Write */
  889. RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
  890. /* Setup Bank 1 Write */
  891. RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
  892. /* Setup Bank 2 Write */
  893. RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
  894. /* Setup Bank 6 Write */
  895. RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
  896. modesIndex);
  897. {
  898. int i;
  899. for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
  900. ah->analogBank6Data[i] =
  901. INI_RA(&ah->iniBank6TPC, i, modesIndex);
  902. }
  903. }
  904. /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
  905. if (eepMinorRev >= 2) {
  906. if (IS_CHAN_2GHZ(chan)) {
  907. ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
  908. db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
  909. ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
  910. ob2GHz, 3, 197, 0);
  911. ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
  912. db2GHz, 3, 194, 0);
  913. } else {
  914. ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
  915. db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
  916. ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
  917. ob5GHz, 3, 203, 0);
  918. ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
  919. db5GHz, 3, 200, 0);
  920. }
  921. }
  922. /* Setup Bank 7 Setup */
  923. RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
  924. /* Write Analog registers */
  925. REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
  926. regWrites);
  927. REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
  928. regWrites);
  929. REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
  930. regWrites);
  931. REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
  932. regWrites);
  933. REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
  934. regWrites);
  935. REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
  936. regWrites);
  937. return true;
  938. }