m5mols_controls.c 16 KB

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  1. /*
  2. * Controls for M-5MOLS 8M Pixel camera sensor with ISP
  3. *
  4. * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  5. * Author: HeungJun Kim <riverful.kim@samsung.com>
  6. *
  7. * Copyright (C) 2009 Samsung Electronics Co., Ltd.
  8. * Author: Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. #include <linux/i2c.h>
  16. #include <linux/delay.h>
  17. #include <linux/videodev2.h>
  18. #include <media/v4l2-ctrls.h>
  19. #include "m5mols.h"
  20. #include "m5mols_reg.h"
  21. static struct m5mols_scenemode m5mols_default_scenemode[] = {
  22. [REG_SCENE_NORMAL] = {
  23. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  24. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  25. REG_AF_NORMAL, REG_FD_OFF,
  26. REG_MCC_NORMAL, REG_LIGHT_OFF, REG_FLASH_OFF,
  27. 5, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  28. },
  29. [REG_SCENE_PORTRAIT] = {
  30. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  31. REG_CHROMA_ON, 3, REG_EDGE_ON, 4,
  32. REG_AF_NORMAL, BIT_FD_EN | BIT_FD_DRAW_FACE_FRAME,
  33. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  34. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  35. },
  36. [REG_SCENE_LANDSCAPE] = {
  37. REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  38. REG_CHROMA_ON, 4, REG_EDGE_ON, 6,
  39. REG_AF_NORMAL, REG_FD_OFF,
  40. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  41. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  42. },
  43. [REG_SCENE_SPORTS] = {
  44. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  45. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  46. REG_AF_NORMAL, REG_FD_OFF,
  47. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  48. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  49. },
  50. [REG_SCENE_PARTY_INDOOR] = {
  51. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  52. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  53. REG_AF_NORMAL, REG_FD_OFF,
  54. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  55. 6, REG_ISO_200, REG_CAP_NONE, REG_WDR_OFF,
  56. },
  57. [REG_SCENE_BEACH_SNOW] = {
  58. REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
  59. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  60. REG_AF_NORMAL, REG_FD_OFF,
  61. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  62. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  63. },
  64. [REG_SCENE_SUNSET] = {
  65. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  66. REG_AWB_DAYLIGHT,
  67. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  68. REG_AF_NORMAL, REG_FD_OFF,
  69. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  70. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  71. },
  72. [REG_SCENE_DAWN_DUSK] = {
  73. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  74. REG_AWB_FLUORESCENT_1,
  75. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  76. REG_AF_NORMAL, REG_FD_OFF,
  77. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  78. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  79. },
  80. [REG_SCENE_FALL] = {
  81. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  82. REG_CHROMA_ON, 5, REG_EDGE_ON, 5,
  83. REG_AF_NORMAL, REG_FD_OFF,
  84. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  85. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  86. },
  87. [REG_SCENE_NIGHT] = {
  88. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  89. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  90. REG_AF_NORMAL, REG_FD_OFF,
  91. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  92. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  93. },
  94. [REG_SCENE_AGAINST_LIGHT] = {
  95. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  96. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  97. REG_AF_NORMAL, REG_FD_OFF,
  98. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  99. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  100. },
  101. [REG_SCENE_FIRE] = {
  102. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  103. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  104. REG_AF_NORMAL, REG_FD_OFF,
  105. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  106. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  107. },
  108. [REG_SCENE_TEXT] = {
  109. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  110. REG_CHROMA_ON, 3, REG_EDGE_ON, 7,
  111. REG_AF_MACRO, REG_FD_OFF,
  112. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  113. 6, REG_ISO_AUTO, REG_CAP_ANTI_SHAKE, REG_WDR_ON,
  114. },
  115. [REG_SCENE_CANDLE] = {
  116. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  117. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  118. REG_AF_NORMAL, REG_FD_OFF,
  119. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  120. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  121. },
  122. };
  123. /**
  124. * m5mols_do_scenemode() - Change current scenemode
  125. * @mode: Desired mode of the scenemode
  126. *
  127. * WARNING: The execution order is important. Do not change the order.
  128. */
  129. int m5mols_do_scenemode(struct m5mols_info *info, u8 mode)
  130. {
  131. struct v4l2_subdev *sd = &info->sd;
  132. struct m5mols_scenemode scenemode = m5mols_default_scenemode[mode];
  133. int ret;
  134. if (mode > REG_SCENE_CANDLE)
  135. return -EINVAL;
  136. ret = m5mols_lock_3a(info, false);
  137. if (!ret)
  138. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, mode);
  139. if (!ret)
  140. ret = m5mols_write(sd, AE_EV_PRESET_CAPTURE, mode);
  141. if (!ret)
  142. ret = m5mols_write(sd, AE_MODE, scenemode.metering);
  143. if (!ret)
  144. ret = m5mols_write(sd, AE_INDEX, scenemode.ev_bias);
  145. if (!ret)
  146. ret = m5mols_write(sd, AWB_MODE, scenemode.wb_mode);
  147. if (!ret)
  148. ret = m5mols_write(sd, AWB_MANUAL, scenemode.wb_preset);
  149. if (!ret)
  150. ret = m5mols_write(sd, MON_CHROMA_EN, scenemode.chroma_en);
  151. if (!ret)
  152. ret = m5mols_write(sd, MON_CHROMA_LVL, scenemode.chroma_lvl);
  153. if (!ret)
  154. ret = m5mols_write(sd, MON_EDGE_EN, scenemode.edge_en);
  155. if (!ret)
  156. ret = m5mols_write(sd, MON_EDGE_LVL, scenemode.edge_lvl);
  157. if (!ret && is_available_af(info))
  158. ret = m5mols_write(sd, AF_MODE, scenemode.af_range);
  159. if (!ret && is_available_af(info))
  160. ret = m5mols_write(sd, FD_CTL, scenemode.fd_mode);
  161. if (!ret)
  162. ret = m5mols_write(sd, MON_TONE_CTL, scenemode.tone);
  163. if (!ret)
  164. ret = m5mols_write(sd, AE_ISO, scenemode.iso);
  165. if (!ret)
  166. ret = m5mols_set_mode(info, REG_CAPTURE);
  167. if (!ret)
  168. ret = m5mols_write(sd, CAPP_WDR_EN, scenemode.wdr);
  169. if (!ret)
  170. ret = m5mols_write(sd, CAPP_MCC_MODE, scenemode.mcc);
  171. if (!ret)
  172. ret = m5mols_write(sd, CAPP_LIGHT_CTRL, scenemode.light);
  173. if (!ret)
  174. ret = m5mols_write(sd, CAPP_FLASH_CTRL, scenemode.flash);
  175. if (!ret)
  176. ret = m5mols_write(sd, CAPC_MODE, scenemode.capt_mode);
  177. if (!ret)
  178. ret = m5mols_set_mode(info, REG_MONITOR);
  179. return ret;
  180. }
  181. static int m5mols_lock_ae(struct m5mols_info *info, bool lock)
  182. {
  183. int ret = 0;
  184. if (info->lock_ae != lock)
  185. ret = m5mols_write(&info->sd, AE_LOCK,
  186. lock ? REG_AE_LOCK : REG_AE_UNLOCK);
  187. if (!ret)
  188. info->lock_ae = lock;
  189. return ret;
  190. }
  191. static int m5mols_lock_awb(struct m5mols_info *info, bool lock)
  192. {
  193. int ret = 0;
  194. if (info->lock_awb != lock)
  195. ret = m5mols_write(&info->sd, AWB_LOCK,
  196. lock ? REG_AWB_LOCK : REG_AWB_UNLOCK);
  197. if (!ret)
  198. info->lock_awb = lock;
  199. return ret;
  200. }
  201. /* m5mols_lock_3a() - Lock 3A(Auto Exposure, Auto Whitebalance, Auto Focus) */
  202. int m5mols_lock_3a(struct m5mols_info *info, bool lock)
  203. {
  204. int ret;
  205. ret = m5mols_lock_ae(info, lock);
  206. if (!ret)
  207. ret = m5mols_lock_awb(info, lock);
  208. /* Don't need to handle unlocking AF */
  209. if (!ret && is_available_af(info) && lock)
  210. ret = m5mols_write(&info->sd, AF_EXECUTE, REG_AF_STOP);
  211. return ret;
  212. }
  213. static int m5mols_set_metering_mode(struct m5mols_info *info, int mode)
  214. {
  215. unsigned int metering;
  216. switch (mode) {
  217. case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
  218. metering = REG_AE_CENTER;
  219. break;
  220. case V4L2_EXPOSURE_METERING_SPOT:
  221. metering = REG_AE_SPOT;
  222. break;
  223. default:
  224. metering = REG_AE_ALL;
  225. break;
  226. }
  227. return m5mols_write(&info->sd, AE_MODE, metering);
  228. }
  229. static int m5mols_set_exposure(struct m5mols_info *info, int exposure)
  230. {
  231. struct v4l2_subdev *sd = &info->sd;
  232. int ret;
  233. ret = m5mols_lock_ae(info, exposure != V4L2_EXPOSURE_AUTO);
  234. if (ret < 0)
  235. return ret;
  236. if (exposure == V4L2_EXPOSURE_AUTO) {
  237. ret = m5mols_set_metering_mode(info, info->metering->val);
  238. if (ret < 0)
  239. return ret;
  240. v4l2_dbg(1, m5mols_debug, sd,
  241. "%s: exposure bias: %#x, metering: %#x\n",
  242. __func__, info->exposure_bias->val,
  243. info->metering->val);
  244. return m5mols_write(sd, AE_INDEX, info->exposure_bias->val);
  245. }
  246. if (exposure == V4L2_EXPOSURE_MANUAL) {
  247. ret = m5mols_write(sd, AE_MODE, REG_AE_OFF);
  248. if (ret == 0)
  249. ret = m5mols_write(sd, AE_MAN_GAIN_MON,
  250. info->exposure->val);
  251. if (ret == 0)
  252. ret = m5mols_write(sd, AE_MAN_GAIN_CAP,
  253. info->exposure->val);
  254. v4l2_dbg(1, m5mols_debug, sd, "%s: exposure: %#x\n",
  255. __func__, info->exposure->val);
  256. }
  257. return ret;
  258. }
  259. static int m5mols_set_white_balance(struct m5mols_info *info, int val)
  260. {
  261. static const unsigned short wb[][2] = {
  262. { V4L2_WHITE_BALANCE_INCANDESCENT, REG_AWB_INCANDESCENT },
  263. { V4L2_WHITE_BALANCE_FLUORESCENT, REG_AWB_FLUORESCENT_1 },
  264. { V4L2_WHITE_BALANCE_FLUORESCENT_H, REG_AWB_FLUORESCENT_2 },
  265. { V4L2_WHITE_BALANCE_HORIZON, REG_AWB_HORIZON },
  266. { V4L2_WHITE_BALANCE_DAYLIGHT, REG_AWB_DAYLIGHT },
  267. { V4L2_WHITE_BALANCE_FLASH, REG_AWB_LEDLIGHT },
  268. { V4L2_WHITE_BALANCE_CLOUDY, REG_AWB_CLOUDY },
  269. { V4L2_WHITE_BALANCE_SHADE, REG_AWB_SHADE },
  270. { V4L2_WHITE_BALANCE_AUTO, REG_AWB_AUTO },
  271. };
  272. int i;
  273. struct v4l2_subdev *sd = &info->sd;
  274. int ret = -EINVAL;
  275. for (i = 0; i < ARRAY_SIZE(wb); i++) {
  276. int awb;
  277. if (wb[i][0] != val)
  278. continue;
  279. v4l2_dbg(1, m5mols_debug, sd,
  280. "Setting white balance to: %#x\n", wb[i][0]);
  281. awb = wb[i][0] == V4L2_WHITE_BALANCE_AUTO;
  282. ret = m5mols_write(sd, AWB_MODE, awb ? REG_AWB_AUTO :
  283. REG_AWB_PRESET);
  284. if (ret < 0)
  285. return ret;
  286. if (!awb)
  287. ret = m5mols_write(sd, AWB_MANUAL, wb[i][1]);
  288. }
  289. return ret;
  290. }
  291. static int m5mols_set_saturation(struct m5mols_info *info, int val)
  292. {
  293. int ret = m5mols_write(&info->sd, MON_CHROMA_LVL, val);
  294. if (ret < 0)
  295. return ret;
  296. return m5mols_write(&info->sd, MON_CHROMA_EN, REG_CHROMA_ON);
  297. }
  298. static int m5mols_set_color_effect(struct m5mols_info *info, int val)
  299. {
  300. unsigned int m_effect = REG_COLOR_EFFECT_OFF;
  301. unsigned int p_effect = REG_EFFECT_OFF;
  302. unsigned int cfix_r = 0, cfix_b = 0;
  303. struct v4l2_subdev *sd = &info->sd;
  304. int ret = 0;
  305. switch (val) {
  306. case V4L2_COLORFX_BW:
  307. m_effect = REG_COLOR_EFFECT_ON;
  308. break;
  309. case V4L2_COLORFX_NEGATIVE:
  310. p_effect = REG_EFFECT_NEGA;
  311. break;
  312. case V4L2_COLORFX_EMBOSS:
  313. p_effect = REG_EFFECT_EMBOSS;
  314. break;
  315. case V4L2_COLORFX_SEPIA:
  316. m_effect = REG_COLOR_EFFECT_ON;
  317. cfix_r = REG_CFIXR_SEPIA;
  318. cfix_b = REG_CFIXB_SEPIA;
  319. break;
  320. }
  321. ret = m5mols_write(sd, PARM_EFFECT, p_effect);
  322. if (!ret)
  323. ret = m5mols_write(sd, MON_EFFECT, m_effect);
  324. if (ret == 0 && m_effect == REG_COLOR_EFFECT_ON) {
  325. ret = m5mols_write(sd, MON_CFIXR, cfix_r);
  326. if (!ret)
  327. ret = m5mols_write(sd, MON_CFIXB, cfix_b);
  328. }
  329. v4l2_dbg(1, m5mols_debug, sd,
  330. "p_effect: %#x, m_effect: %#x, r: %#x, b: %#x (%d)\n",
  331. p_effect, m_effect, cfix_r, cfix_b, ret);
  332. return ret;
  333. }
  334. static int m5mols_set_iso(struct m5mols_info *info, int auto_iso)
  335. {
  336. u32 iso = auto_iso ? 0 : info->iso->val + 1;
  337. return m5mols_write(&info->sd, AE_ISO, iso);
  338. }
  339. static int m5mols_set_wdr(struct m5mols_info *info, int wdr)
  340. {
  341. int ret;
  342. ret = m5mols_write(&info->sd, MON_TONE_CTL, wdr ? 9 : 5);
  343. if (ret < 0)
  344. return ret;
  345. ret = m5mols_set_mode(info, REG_CAPTURE);
  346. if (ret < 0)
  347. return ret;
  348. return m5mols_write(&info->sd, CAPP_WDR_EN, wdr);
  349. }
  350. static int m5mols_set_stabilization(struct m5mols_info *info, int val)
  351. {
  352. struct v4l2_subdev *sd = &info->sd;
  353. unsigned int evp = val ? 0xe : 0x0;
  354. int ret;
  355. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, evp);
  356. if (ret < 0)
  357. return ret;
  358. return m5mols_write(sd, AE_EV_PRESET_CAPTURE, evp);
  359. }
  360. static int m5mols_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
  361. {
  362. struct v4l2_subdev *sd = to_sd(ctrl);
  363. struct m5mols_info *info = to_m5mols(sd);
  364. int ret = 0;
  365. u8 status;
  366. v4l2_dbg(1, m5mols_debug, sd, "%s: ctrl: %s (%d)\n",
  367. __func__, ctrl->name, info->isp_ready);
  368. if (!info->isp_ready)
  369. return -EBUSY;
  370. switch (ctrl->id) {
  371. case V4L2_CID_ISO_SENSITIVITY_AUTO:
  372. ret = m5mols_read_u8(sd, AE_ISO, &status);
  373. if (ret == 0)
  374. ctrl->val = !status;
  375. if (status != REG_ISO_AUTO)
  376. info->iso->val = status - 1;
  377. break;
  378. }
  379. return ret;
  380. }
  381. static int m5mols_s_ctrl(struct v4l2_ctrl *ctrl)
  382. {
  383. unsigned int ctrl_mode = m5mols_get_ctrl_mode(ctrl);
  384. struct v4l2_subdev *sd = to_sd(ctrl);
  385. struct m5mols_info *info = to_m5mols(sd);
  386. int last_mode = info->mode;
  387. int ret = 0;
  388. /*
  389. * If needed, defer restoring the controls until
  390. * the device is fully initialized.
  391. */
  392. if (!info->isp_ready) {
  393. info->ctrl_sync = 0;
  394. return 0;
  395. }
  396. v4l2_dbg(1, m5mols_debug, sd, "%s: %s, val: %d, priv: %#x\n",
  397. __func__, ctrl->name, ctrl->val, (int)ctrl->priv);
  398. if (ctrl_mode && ctrl_mode != info->mode) {
  399. ret = m5mols_set_mode(info, ctrl_mode);
  400. if (ret < 0)
  401. return ret;
  402. }
  403. switch (ctrl->id) {
  404. case V4L2_CID_ZOOM_ABSOLUTE:
  405. ret = m5mols_write(sd, MON_ZOOM, ctrl->val);
  406. break;
  407. case V4L2_CID_EXPOSURE_AUTO:
  408. ret = m5mols_set_exposure(info, ctrl->val);
  409. break;
  410. case V4L2_CID_ISO_SENSITIVITY:
  411. ret = m5mols_set_iso(info, ctrl->val);
  412. break;
  413. case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
  414. ret = m5mols_set_white_balance(info, ctrl->val);
  415. break;
  416. case V4L2_CID_SATURATION:
  417. ret = m5mols_set_saturation(info, ctrl->val);
  418. break;
  419. case V4L2_CID_COLORFX:
  420. ret = m5mols_set_color_effect(info, ctrl->val);
  421. break;
  422. case V4L2_CID_WIDE_DYNAMIC_RANGE:
  423. ret = m5mols_set_wdr(info, ctrl->val);
  424. break;
  425. case V4L2_CID_IMAGE_STABILIZATION:
  426. ret = m5mols_set_stabilization(info, ctrl->val);
  427. break;
  428. case V4L2_CID_JPEG_COMPRESSION_QUALITY:
  429. ret = m5mols_write(sd, CAPP_JPEG_RATIO, ctrl->val);
  430. break;
  431. }
  432. if (ret == 0 && info->mode != last_mode)
  433. ret = m5mols_set_mode(info, last_mode);
  434. return ret;
  435. }
  436. static const struct v4l2_ctrl_ops m5mols_ctrl_ops = {
  437. .g_volatile_ctrl = m5mols_g_volatile_ctrl,
  438. .s_ctrl = m5mols_s_ctrl,
  439. };
  440. /* Supported manual ISO values */
  441. static const s64 iso_qmenu[] = {
  442. /* AE_ISO: 0x01...0x07 */
  443. 50, 100, 200, 400, 800, 1600, 3200
  444. };
  445. /* Supported Exposure Bias values, -2.0EV...+2.0EV */
  446. static const s64 ev_bias_qmenu[] = {
  447. /* AE_INDEX: 0x00...0x08 */
  448. -2000, -1500, -1000, -500, 0, 500, 1000, 1500, 2000
  449. };
  450. int m5mols_init_controls(struct v4l2_subdev *sd)
  451. {
  452. struct m5mols_info *info = to_m5mols(sd);
  453. u16 exposure_max;
  454. u16 zoom_step;
  455. int ret;
  456. /* Determine the firmware dependant control range and step values */
  457. ret = m5mols_read_u16(sd, AE_MAX_GAIN_MON, &exposure_max);
  458. if (ret < 0)
  459. return ret;
  460. zoom_step = is_manufacturer(info, REG_SAMSUNG_OPTICS) ? 31 : 1;
  461. v4l2_ctrl_handler_init(&info->handle, 20);
  462. info->auto_wb = v4l2_ctrl_new_std_menu(&info->handle,
  463. &m5mols_ctrl_ops, V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
  464. 9, ~0x3fe, V4L2_WHITE_BALANCE_AUTO);
  465. /* Exposure control cluster */
  466. info->auto_exposure = v4l2_ctrl_new_std_menu(&info->handle,
  467. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
  468. 1, ~0x03, V4L2_EXPOSURE_AUTO);
  469. info->exposure = v4l2_ctrl_new_std(&info->handle,
  470. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE,
  471. 0, exposure_max, 1, exposure_max / 2);
  472. info->exposure_bias = v4l2_ctrl_new_int_menu(&info->handle,
  473. &m5mols_ctrl_ops, V4L2_CID_AUTO_EXPOSURE_BIAS,
  474. ARRAY_SIZE(ev_bias_qmenu) - 1,
  475. ARRAY_SIZE(ev_bias_qmenu)/2 - 1,
  476. ev_bias_qmenu);
  477. info->metering = v4l2_ctrl_new_std_menu(&info->handle,
  478. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE_METERING,
  479. 2, ~0x7, V4L2_EXPOSURE_METERING_AVERAGE);
  480. /* ISO control cluster */
  481. info->auto_iso = v4l2_ctrl_new_std_menu(&info->handle, &m5mols_ctrl_ops,
  482. V4L2_CID_ISO_SENSITIVITY_AUTO, 1, ~0x03, 1);
  483. info->iso = v4l2_ctrl_new_int_menu(&info->handle, &m5mols_ctrl_ops,
  484. V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
  485. ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
  486. info->saturation = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  487. V4L2_CID_SATURATION, 1, 5, 1, 3);
  488. info->zoom = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  489. V4L2_CID_ZOOM_ABSOLUTE, 1, 70, zoom_step, 1);
  490. info->colorfx = v4l2_ctrl_new_std_menu(&info->handle, &m5mols_ctrl_ops,
  491. V4L2_CID_COLORFX, 4, 0, V4L2_COLORFX_NONE);
  492. info->wdr = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  493. V4L2_CID_WIDE_DYNAMIC_RANGE, 0, 1, 1, 0);
  494. info->stabilization = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  495. V4L2_CID_IMAGE_STABILIZATION, 0, 1, 1, 0);
  496. info->jpeg_quality = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  497. V4L2_CID_JPEG_COMPRESSION_QUALITY, 1, 100, 1, 80);
  498. if (info->handle.error) {
  499. int ret = info->handle.error;
  500. v4l2_err(sd, "Failed to initialize controls: %d\n", ret);
  501. v4l2_ctrl_handler_free(&info->handle);
  502. return ret;
  503. }
  504. v4l2_ctrl_auto_cluster(4, &info->auto_exposure, 1, false);
  505. info->auto_iso->flags |= V4L2_CTRL_FLAG_VOLATILE |
  506. V4L2_CTRL_FLAG_UPDATE;
  507. v4l2_ctrl_auto_cluster(2, &info->auto_iso, 0, false);
  508. m5mols_set_ctrl_mode(info->auto_exposure, REG_PARAMETER);
  509. m5mols_set_ctrl_mode(info->auto_wb, REG_PARAMETER);
  510. m5mols_set_ctrl_mode(info->colorfx, REG_MONITOR);
  511. sd->ctrl_handler = &info->handle;
  512. return 0;
  513. }