main.c 51 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. } else {
  117. goto unlock;
  118. }
  119. spin_lock(&common->cc_lock);
  120. ath_hw_cycle_counters_update(common);
  121. spin_unlock(&common->cc_lock);
  122. ath9k_hw_setpower(sc->sc_ah, mode);
  123. unlock:
  124. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  125. }
  126. static void __ath_cancel_work(struct ath_softc *sc)
  127. {
  128. cancel_work_sync(&sc->paprd_work);
  129. cancel_work_sync(&sc->hw_check_work);
  130. cancel_delayed_work_sync(&sc->tx_complete_work);
  131. cancel_delayed_work_sync(&sc->hw_pll_work);
  132. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  133. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  134. cancel_work_sync(&sc->mci_work);
  135. #endif
  136. }
  137. static void ath_cancel_work(struct ath_softc *sc)
  138. {
  139. __ath_cancel_work(sc);
  140. cancel_work_sync(&sc->hw_reset_work);
  141. }
  142. static void ath_restart_work(struct ath_softc *sc)
  143. {
  144. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  145. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  146. if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
  147. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  148. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  149. ath_start_rx_poll(sc, 3);
  150. if (!common->disable_ani)
  151. ath_start_ani(common);
  152. }
  153. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  154. {
  155. struct ath_hw *ah = sc->sc_ah;
  156. struct ath_common *common = ath9k_hw_common(ah);
  157. bool ret = true;
  158. ieee80211_stop_queues(sc->hw);
  159. sc->hw_busy_count = 0;
  160. del_timer_sync(&common->ani.timer);
  161. del_timer_sync(&sc->rx_poll_timer);
  162. ath9k_debug_samp_bb_mac(sc);
  163. ath9k_hw_disable_interrupts(ah);
  164. if (!ath_stoprecv(sc))
  165. ret = false;
  166. if (!ath_drain_all_txq(sc, retry_tx))
  167. ret = false;
  168. if (!flush) {
  169. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  170. ath_rx_tasklet(sc, 1, true);
  171. ath_rx_tasklet(sc, 1, false);
  172. } else {
  173. ath_flushrecv(sc);
  174. }
  175. return ret;
  176. }
  177. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  178. {
  179. struct ath_hw *ah = sc->sc_ah;
  180. struct ath_common *common = ath9k_hw_common(ah);
  181. unsigned long flags;
  182. if (ath_startrecv(sc) != 0) {
  183. ath_err(common, "Unable to restart recv logic\n");
  184. return false;
  185. }
  186. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  187. sc->config.txpowlimit, &sc->curtxpow);
  188. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  189. ath9k_hw_set_interrupts(ah);
  190. ath9k_hw_enable_interrupts(ah);
  191. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  192. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  193. goto work;
  194. ath_set_beacon(sc);
  195. if (ah->opmode == NL80211_IFTYPE_STATION &&
  196. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  197. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  198. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  199. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  200. }
  201. work:
  202. ath_restart_work(sc);
  203. }
  204. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  205. ath_ant_comb_update(sc);
  206. ieee80211_wake_queues(sc->hw);
  207. return true;
  208. }
  209. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  210. bool retry_tx)
  211. {
  212. struct ath_hw *ah = sc->sc_ah;
  213. struct ath_common *common = ath9k_hw_common(ah);
  214. struct ath9k_hw_cal_data *caldata = NULL;
  215. bool fastcc = true;
  216. bool flush = false;
  217. int r;
  218. __ath_cancel_work(sc);
  219. spin_lock_bh(&sc->sc_pcu_lock);
  220. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  221. fastcc = false;
  222. caldata = &sc->caldata;
  223. }
  224. if (!hchan) {
  225. fastcc = false;
  226. flush = true;
  227. hchan = ah->curchan;
  228. }
  229. if (!ath_prepare_reset(sc, retry_tx, flush))
  230. fastcc = false;
  231. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  232. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  233. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  234. if (r) {
  235. ath_err(common,
  236. "Unable to reset channel, reset status %d\n", r);
  237. goto out;
  238. }
  239. if (!ath_complete_reset(sc, true))
  240. r = -EIO;
  241. out:
  242. spin_unlock_bh(&sc->sc_pcu_lock);
  243. return r;
  244. }
  245. /*
  246. * Set/change channels. If the channel is really being changed, it's done
  247. * by reseting the chip. To accomplish this we must first cleanup any pending
  248. * DMA, then restart stuff.
  249. */
  250. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  251. struct ath9k_channel *hchan)
  252. {
  253. int r;
  254. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  255. return -EIO;
  256. r = ath_reset_internal(sc, hchan, false);
  257. return r;
  258. }
  259. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  260. struct ieee80211_vif *vif)
  261. {
  262. struct ath_node *an;
  263. u8 density;
  264. an = (struct ath_node *)sta->drv_priv;
  265. #ifdef CONFIG_ATH9K_DEBUGFS
  266. spin_lock(&sc->nodes_lock);
  267. list_add(&an->list, &sc->nodes);
  268. spin_unlock(&sc->nodes_lock);
  269. #endif
  270. an->sta = sta;
  271. an->vif = vif;
  272. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  273. ath_tx_node_init(sc, an);
  274. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  275. sta->ht_cap.ampdu_factor);
  276. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  277. an->mpdudensity = density;
  278. }
  279. }
  280. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  281. {
  282. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  283. #ifdef CONFIG_ATH9K_DEBUGFS
  284. spin_lock(&sc->nodes_lock);
  285. list_del(&an->list);
  286. spin_unlock(&sc->nodes_lock);
  287. an->sta = NULL;
  288. #endif
  289. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  290. ath_tx_node_cleanup(sc, an);
  291. }
  292. void ath9k_tasklet(unsigned long data)
  293. {
  294. struct ath_softc *sc = (struct ath_softc *)data;
  295. struct ath_hw *ah = sc->sc_ah;
  296. struct ath_common *common = ath9k_hw_common(ah);
  297. unsigned long flags;
  298. u32 status = sc->intrstatus;
  299. u32 rxmask;
  300. ath9k_ps_wakeup(sc);
  301. spin_lock(&sc->sc_pcu_lock);
  302. if ((status & ATH9K_INT_FATAL) ||
  303. (status & ATH9K_INT_BB_WATCHDOG)) {
  304. #ifdef CONFIG_ATH9K_DEBUGFS
  305. enum ath_reset_type type;
  306. if (status & ATH9K_INT_FATAL)
  307. type = RESET_TYPE_FATAL_INT;
  308. else
  309. type = RESET_TYPE_BB_WATCHDOG;
  310. RESET_STAT_INC(sc, type);
  311. #endif
  312. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  313. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  314. goto out;
  315. }
  316. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  317. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  318. /*
  319. * TSF sync does not look correct; remain awake to sync with
  320. * the next Beacon.
  321. */
  322. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  323. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  324. }
  325. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  326. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  327. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  328. ATH9K_INT_RXORN);
  329. else
  330. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  331. if (status & rxmask) {
  332. /* Check for high priority Rx first */
  333. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  334. (status & ATH9K_INT_RXHP))
  335. ath_rx_tasklet(sc, 0, true);
  336. ath_rx_tasklet(sc, 0, false);
  337. }
  338. if (status & ATH9K_INT_TX) {
  339. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  340. ath_tx_edma_tasklet(sc);
  341. else
  342. ath_tx_tasklet(sc);
  343. }
  344. ath9k_btcoex_handle_interrupt(sc, status);
  345. out:
  346. /* re-enable hardware interrupt */
  347. ath9k_hw_enable_interrupts(ah);
  348. spin_unlock(&sc->sc_pcu_lock);
  349. ath9k_ps_restore(sc);
  350. }
  351. irqreturn_t ath_isr(int irq, void *dev)
  352. {
  353. #define SCHED_INTR ( \
  354. ATH9K_INT_FATAL | \
  355. ATH9K_INT_BB_WATCHDOG | \
  356. ATH9K_INT_RXORN | \
  357. ATH9K_INT_RXEOL | \
  358. ATH9K_INT_RX | \
  359. ATH9K_INT_RXLP | \
  360. ATH9K_INT_RXHP | \
  361. ATH9K_INT_TX | \
  362. ATH9K_INT_BMISS | \
  363. ATH9K_INT_CST | \
  364. ATH9K_INT_TSFOOR | \
  365. ATH9K_INT_GENTIMER | \
  366. ATH9K_INT_MCI)
  367. struct ath_softc *sc = dev;
  368. struct ath_hw *ah = sc->sc_ah;
  369. struct ath_common *common = ath9k_hw_common(ah);
  370. enum ath9k_int status;
  371. bool sched = false;
  372. /*
  373. * The hardware is not ready/present, don't
  374. * touch anything. Note this can happen early
  375. * on if the IRQ is shared.
  376. */
  377. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  378. return IRQ_NONE;
  379. /* shared irq, not for us */
  380. if (!ath9k_hw_intrpend(ah))
  381. return IRQ_NONE;
  382. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  383. return IRQ_HANDLED;
  384. /*
  385. * Figure out the reason(s) for the interrupt. Note
  386. * that the hal returns a pseudo-ISR that may include
  387. * bits we haven't explicitly enabled so we mask the
  388. * value to insure we only process bits we requested.
  389. */
  390. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  391. status &= ah->imask; /* discard unasked-for bits */
  392. /*
  393. * If there are no status bits set, then this interrupt was not
  394. * for me (should have been caught above).
  395. */
  396. if (!status)
  397. return IRQ_NONE;
  398. /* Cache the status */
  399. sc->intrstatus = status;
  400. if (status & SCHED_INTR)
  401. sched = true;
  402. /*
  403. * If a FATAL or RXORN interrupt is received, we have to reset the
  404. * chip immediately.
  405. */
  406. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  407. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  408. goto chip_reset;
  409. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  410. (status & ATH9K_INT_BB_WATCHDOG)) {
  411. spin_lock(&common->cc_lock);
  412. ath_hw_cycle_counters_update(common);
  413. ar9003_hw_bb_watchdog_dbg_info(ah);
  414. spin_unlock(&common->cc_lock);
  415. goto chip_reset;
  416. }
  417. if (status & ATH9K_INT_SWBA)
  418. tasklet_schedule(&sc->bcon_tasklet);
  419. if (status & ATH9K_INT_TXURN)
  420. ath9k_hw_updatetxtriglevel(ah, true);
  421. if (status & ATH9K_INT_RXEOL) {
  422. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  423. ath9k_hw_set_interrupts(ah);
  424. }
  425. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  426. if (status & ATH9K_INT_TIM_TIMER) {
  427. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  428. goto chip_reset;
  429. /* Clear RxAbort bit so that we can
  430. * receive frames */
  431. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  432. spin_lock(&sc->sc_pm_lock);
  433. ath9k_hw_setrxabort(sc->sc_ah, 0);
  434. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  435. spin_unlock(&sc->sc_pm_lock);
  436. }
  437. chip_reset:
  438. ath_debug_stat_interrupt(sc, status);
  439. if (sched) {
  440. /* turn off every interrupt */
  441. ath9k_hw_disable_interrupts(ah);
  442. tasklet_schedule(&sc->intr_tq);
  443. }
  444. return IRQ_HANDLED;
  445. #undef SCHED_INTR
  446. }
  447. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  448. {
  449. int r;
  450. ath9k_ps_wakeup(sc);
  451. r = ath_reset_internal(sc, NULL, retry_tx);
  452. if (retry_tx) {
  453. int i;
  454. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  455. if (ATH_TXQ_SETUP(sc, i)) {
  456. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  457. ath_txq_schedule(sc, &sc->tx.txq[i]);
  458. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  459. }
  460. }
  461. }
  462. ath9k_ps_restore(sc);
  463. return r;
  464. }
  465. void ath_reset_work(struct work_struct *work)
  466. {
  467. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  468. ath_reset(sc, true);
  469. }
  470. /**********************/
  471. /* mac80211 callbacks */
  472. /**********************/
  473. static int ath9k_start(struct ieee80211_hw *hw)
  474. {
  475. struct ath_softc *sc = hw->priv;
  476. struct ath_hw *ah = sc->sc_ah;
  477. struct ath_common *common = ath9k_hw_common(ah);
  478. struct ieee80211_channel *curchan = hw->conf.channel;
  479. struct ath9k_channel *init_channel;
  480. int r;
  481. ath_dbg(common, CONFIG,
  482. "Starting driver with initial channel: %d MHz\n",
  483. curchan->center_freq);
  484. ath9k_ps_wakeup(sc);
  485. mutex_lock(&sc->mutex);
  486. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  487. /* Reset SERDES registers */
  488. ath9k_hw_configpcipowersave(ah, false);
  489. /*
  490. * The basic interface to setting the hardware in a good
  491. * state is ``reset''. On return the hardware is known to
  492. * be powered up and with interrupts disabled. This must
  493. * be followed by initialization of the appropriate bits
  494. * and then setup of the interrupt mask.
  495. */
  496. spin_lock_bh(&sc->sc_pcu_lock);
  497. atomic_set(&ah->intr_ref_cnt, -1);
  498. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  499. if (r) {
  500. ath_err(common,
  501. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  502. r, curchan->center_freq);
  503. spin_unlock_bh(&sc->sc_pcu_lock);
  504. goto mutex_unlock;
  505. }
  506. /* Setup our intr mask. */
  507. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  508. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  509. ATH9K_INT_GLOBAL;
  510. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  511. ah->imask |= ATH9K_INT_RXHP |
  512. ATH9K_INT_RXLP |
  513. ATH9K_INT_BB_WATCHDOG;
  514. else
  515. ah->imask |= ATH9K_INT_RX;
  516. ah->imask |= ATH9K_INT_GTT;
  517. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  518. ah->imask |= ATH9K_INT_CST;
  519. ath_mci_enable(sc);
  520. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  521. sc->sc_ah->is_monitoring = false;
  522. if (!ath_complete_reset(sc, false)) {
  523. r = -EIO;
  524. spin_unlock_bh(&sc->sc_pcu_lock);
  525. goto mutex_unlock;
  526. }
  527. if (ah->led_pin >= 0) {
  528. ath9k_hw_cfg_output(ah, ah->led_pin,
  529. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  530. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  531. }
  532. /*
  533. * Reset key cache to sane defaults (all entries cleared) instead of
  534. * semi-random values after suspend/resume.
  535. */
  536. ath9k_cmn_init_crypto(sc->sc_ah);
  537. spin_unlock_bh(&sc->sc_pcu_lock);
  538. ath9k_start_btcoex(sc);
  539. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  540. common->bus_ops->extn_synch_en(common);
  541. mutex_unlock:
  542. mutex_unlock(&sc->mutex);
  543. ath9k_ps_restore(sc);
  544. return r;
  545. }
  546. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  547. {
  548. struct ath_softc *sc = hw->priv;
  549. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  550. struct ath_tx_control txctl;
  551. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  552. unsigned long flags;
  553. if (sc->ps_enabled) {
  554. /*
  555. * mac80211 does not set PM field for normal data frames, so we
  556. * need to update that based on the current PS mode.
  557. */
  558. if (ieee80211_is_data(hdr->frame_control) &&
  559. !ieee80211_is_nullfunc(hdr->frame_control) &&
  560. !ieee80211_has_pm(hdr->frame_control)) {
  561. ath_dbg(common, PS,
  562. "Add PM=1 for a TX frame while in PS mode\n");
  563. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  564. }
  565. }
  566. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  567. /*
  568. * We are using PS-Poll and mac80211 can request TX while in
  569. * power save mode. Need to wake up hardware for the TX to be
  570. * completed and if needed, also for RX of buffered frames.
  571. */
  572. ath9k_ps_wakeup(sc);
  573. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  574. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  575. ath9k_hw_setrxabort(sc->sc_ah, 0);
  576. if (ieee80211_is_pspoll(hdr->frame_control)) {
  577. ath_dbg(common, PS,
  578. "Sending PS-Poll to pick a buffered frame\n");
  579. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  580. } else {
  581. ath_dbg(common, PS, "Wake up to complete TX\n");
  582. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  583. }
  584. /*
  585. * The actual restore operation will happen only after
  586. * the ps_flags bit is cleared. We are just dropping
  587. * the ps_usecount here.
  588. */
  589. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  590. ath9k_ps_restore(sc);
  591. }
  592. /*
  593. * Cannot tx while the hardware is in full sleep, it first needs a full
  594. * chip reset to recover from that
  595. */
  596. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  597. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  598. goto exit;
  599. }
  600. memset(&txctl, 0, sizeof(struct ath_tx_control));
  601. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  602. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  603. if (ath_tx_start(hw, skb, &txctl) != 0) {
  604. ath_dbg(common, XMIT, "TX failed\n");
  605. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  606. goto exit;
  607. }
  608. return;
  609. exit:
  610. dev_kfree_skb_any(skb);
  611. }
  612. static void ath9k_stop(struct ieee80211_hw *hw)
  613. {
  614. struct ath_softc *sc = hw->priv;
  615. struct ath_hw *ah = sc->sc_ah;
  616. struct ath_common *common = ath9k_hw_common(ah);
  617. bool prev_idle;
  618. mutex_lock(&sc->mutex);
  619. ath_cancel_work(sc);
  620. del_timer_sync(&sc->rx_poll_timer);
  621. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  622. ath_dbg(common, ANY, "Device not present\n");
  623. mutex_unlock(&sc->mutex);
  624. return;
  625. }
  626. /* Ensure HW is awake when we try to shut it down. */
  627. ath9k_ps_wakeup(sc);
  628. ath9k_stop_btcoex(sc);
  629. spin_lock_bh(&sc->sc_pcu_lock);
  630. /* prevent tasklets to enable interrupts once we disable them */
  631. ah->imask &= ~ATH9K_INT_GLOBAL;
  632. /* make sure h/w will not generate any interrupt
  633. * before setting the invalid flag. */
  634. ath9k_hw_disable_interrupts(ah);
  635. spin_unlock_bh(&sc->sc_pcu_lock);
  636. /* we can now sync irq and kill any running tasklets, since we already
  637. * disabled interrupts and not holding a spin lock */
  638. synchronize_irq(sc->irq);
  639. tasklet_kill(&sc->intr_tq);
  640. tasklet_kill(&sc->bcon_tasklet);
  641. prev_idle = sc->ps_idle;
  642. sc->ps_idle = true;
  643. spin_lock_bh(&sc->sc_pcu_lock);
  644. if (ah->led_pin >= 0) {
  645. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  646. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  647. }
  648. ath_prepare_reset(sc, false, true);
  649. if (sc->rx.frag) {
  650. dev_kfree_skb_any(sc->rx.frag);
  651. sc->rx.frag = NULL;
  652. }
  653. if (!ah->curchan)
  654. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  655. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  656. ath9k_hw_phy_disable(ah);
  657. ath9k_hw_configpcipowersave(ah, true);
  658. spin_unlock_bh(&sc->sc_pcu_lock);
  659. ath9k_ps_restore(sc);
  660. set_bit(SC_OP_INVALID, &sc->sc_flags);
  661. sc->ps_idle = prev_idle;
  662. mutex_unlock(&sc->mutex);
  663. ath_dbg(common, CONFIG, "Driver halt\n");
  664. }
  665. bool ath9k_uses_beacons(int type)
  666. {
  667. switch (type) {
  668. case NL80211_IFTYPE_AP:
  669. case NL80211_IFTYPE_ADHOC:
  670. case NL80211_IFTYPE_MESH_POINT:
  671. return true;
  672. default:
  673. return false;
  674. }
  675. }
  676. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  677. struct ieee80211_vif *vif)
  678. {
  679. struct ath_vif *avp = (void *)vif->drv_priv;
  680. ath9k_set_beaconing_status(sc, false);
  681. ath_beacon_return(sc, avp);
  682. ath9k_set_beaconing_status(sc, true);
  683. }
  684. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  685. {
  686. struct ath9k_vif_iter_data *iter_data = data;
  687. int i;
  688. if (iter_data->hw_macaddr)
  689. for (i = 0; i < ETH_ALEN; i++)
  690. iter_data->mask[i] &=
  691. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  692. switch (vif->type) {
  693. case NL80211_IFTYPE_AP:
  694. iter_data->naps++;
  695. break;
  696. case NL80211_IFTYPE_STATION:
  697. iter_data->nstations++;
  698. break;
  699. case NL80211_IFTYPE_ADHOC:
  700. iter_data->nadhocs++;
  701. break;
  702. case NL80211_IFTYPE_MESH_POINT:
  703. iter_data->nmeshes++;
  704. break;
  705. case NL80211_IFTYPE_WDS:
  706. iter_data->nwds++;
  707. break;
  708. default:
  709. break;
  710. }
  711. }
  712. /* Called with sc->mutex held. */
  713. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  714. struct ieee80211_vif *vif,
  715. struct ath9k_vif_iter_data *iter_data)
  716. {
  717. struct ath_softc *sc = hw->priv;
  718. struct ath_hw *ah = sc->sc_ah;
  719. struct ath_common *common = ath9k_hw_common(ah);
  720. /*
  721. * Use the hardware MAC address as reference, the hardware uses it
  722. * together with the BSSID mask when matching addresses.
  723. */
  724. memset(iter_data, 0, sizeof(*iter_data));
  725. iter_data->hw_macaddr = common->macaddr;
  726. memset(&iter_data->mask, 0xff, ETH_ALEN);
  727. if (vif)
  728. ath9k_vif_iter(iter_data, vif->addr, vif);
  729. /* Get list of all active MAC addresses */
  730. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  731. iter_data);
  732. }
  733. /* Called with sc->mutex held. */
  734. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  735. struct ieee80211_vif *vif)
  736. {
  737. struct ath_softc *sc = hw->priv;
  738. struct ath_hw *ah = sc->sc_ah;
  739. struct ath_common *common = ath9k_hw_common(ah);
  740. struct ath9k_vif_iter_data iter_data;
  741. ath9k_calculate_iter_data(hw, vif, &iter_data);
  742. /* Set BSSID mask. */
  743. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  744. ath_hw_setbssidmask(common);
  745. /* Set op-mode & TSF */
  746. if (iter_data.naps > 0) {
  747. ath9k_hw_set_tsfadjust(ah, 1);
  748. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  749. ah->opmode = NL80211_IFTYPE_AP;
  750. } else {
  751. ath9k_hw_set_tsfadjust(ah, 0);
  752. clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  753. if (iter_data.nmeshes)
  754. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  755. else if (iter_data.nwds)
  756. ah->opmode = NL80211_IFTYPE_AP;
  757. else if (iter_data.nadhocs)
  758. ah->opmode = NL80211_IFTYPE_ADHOC;
  759. else
  760. ah->opmode = NL80211_IFTYPE_STATION;
  761. }
  762. /*
  763. * Enable MIB interrupts when there are hardware phy counters.
  764. */
  765. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  766. ah->imask |= ATH9K_INT_TSFOOR;
  767. else
  768. ah->imask &= ~ATH9K_INT_TSFOOR;
  769. ath9k_hw_set_interrupts(ah);
  770. /* Set up ANI */
  771. if (iter_data.naps > 0) {
  772. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  773. if (!common->disable_ani) {
  774. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  775. ath_start_ani(common);
  776. }
  777. } else {
  778. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  779. del_timer_sync(&common->ani.timer);
  780. }
  781. }
  782. /* Called with sc->mutex held, vif counts set up properly. */
  783. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  784. struct ieee80211_vif *vif)
  785. {
  786. struct ath_softc *sc = hw->priv;
  787. ath9k_calculate_summary_state(hw, vif);
  788. if (ath9k_uses_beacons(vif->type)) {
  789. /* Reserve a beacon slot for the vif */
  790. ath9k_set_beaconing_status(sc, false);
  791. ath_beacon_alloc(sc, vif);
  792. ath9k_set_beaconing_status(sc, true);
  793. }
  794. }
  795. static int ath9k_add_interface(struct ieee80211_hw *hw,
  796. struct ieee80211_vif *vif)
  797. {
  798. struct ath_softc *sc = hw->priv;
  799. struct ath_hw *ah = sc->sc_ah;
  800. struct ath_common *common = ath9k_hw_common(ah);
  801. int ret = 0;
  802. ath9k_ps_wakeup(sc);
  803. mutex_lock(&sc->mutex);
  804. switch (vif->type) {
  805. case NL80211_IFTYPE_STATION:
  806. case NL80211_IFTYPE_WDS:
  807. case NL80211_IFTYPE_ADHOC:
  808. case NL80211_IFTYPE_AP:
  809. case NL80211_IFTYPE_MESH_POINT:
  810. break;
  811. default:
  812. ath_err(common, "Interface type %d not yet supported\n",
  813. vif->type);
  814. ret = -EOPNOTSUPP;
  815. goto out;
  816. }
  817. if (ath9k_uses_beacons(vif->type)) {
  818. if (sc->nbcnvifs >= ATH_BCBUF) {
  819. ath_err(common, "Not enough beacon buffers when adding"
  820. " new interface of type: %i\n",
  821. vif->type);
  822. ret = -ENOBUFS;
  823. goto out;
  824. }
  825. }
  826. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  827. sc->nvifs++;
  828. ath9k_do_vif_add_setup(hw, vif);
  829. out:
  830. mutex_unlock(&sc->mutex);
  831. ath9k_ps_restore(sc);
  832. return ret;
  833. }
  834. static int ath9k_change_interface(struct ieee80211_hw *hw,
  835. struct ieee80211_vif *vif,
  836. enum nl80211_iftype new_type,
  837. bool p2p)
  838. {
  839. struct ath_softc *sc = hw->priv;
  840. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  841. int ret = 0;
  842. ath_dbg(common, CONFIG, "Change Interface\n");
  843. mutex_lock(&sc->mutex);
  844. ath9k_ps_wakeup(sc);
  845. if (ath9k_uses_beacons(new_type) &&
  846. !ath9k_uses_beacons(vif->type)) {
  847. if (sc->nbcnvifs >= ATH_BCBUF) {
  848. ath_err(common, "No beacon slot available\n");
  849. ret = -ENOBUFS;
  850. goto out;
  851. }
  852. }
  853. /* Clean up old vif stuff */
  854. if (ath9k_uses_beacons(vif->type))
  855. ath9k_reclaim_beacon(sc, vif);
  856. /* Add new settings */
  857. vif->type = new_type;
  858. vif->p2p = p2p;
  859. ath9k_do_vif_add_setup(hw, vif);
  860. out:
  861. ath9k_ps_restore(sc);
  862. mutex_unlock(&sc->mutex);
  863. return ret;
  864. }
  865. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  866. struct ieee80211_vif *vif)
  867. {
  868. struct ath_softc *sc = hw->priv;
  869. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  870. ath_dbg(common, CONFIG, "Detach Interface\n");
  871. ath9k_ps_wakeup(sc);
  872. mutex_lock(&sc->mutex);
  873. sc->nvifs--;
  874. /* Reclaim beacon resources */
  875. if (ath9k_uses_beacons(vif->type))
  876. ath9k_reclaim_beacon(sc, vif);
  877. ath9k_calculate_summary_state(hw, NULL);
  878. mutex_unlock(&sc->mutex);
  879. ath9k_ps_restore(sc);
  880. }
  881. static void ath9k_enable_ps(struct ath_softc *sc)
  882. {
  883. struct ath_hw *ah = sc->sc_ah;
  884. struct ath_common *common = ath9k_hw_common(ah);
  885. sc->ps_enabled = true;
  886. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  887. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  888. ah->imask |= ATH9K_INT_TIM_TIMER;
  889. ath9k_hw_set_interrupts(ah);
  890. }
  891. ath9k_hw_setrxabort(ah, 1);
  892. }
  893. ath_dbg(common, PS, "PowerSave enabled\n");
  894. }
  895. static void ath9k_disable_ps(struct ath_softc *sc)
  896. {
  897. struct ath_hw *ah = sc->sc_ah;
  898. struct ath_common *common = ath9k_hw_common(ah);
  899. sc->ps_enabled = false;
  900. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  901. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  902. ath9k_hw_setrxabort(ah, 0);
  903. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  904. PS_WAIT_FOR_CAB |
  905. PS_WAIT_FOR_PSPOLL_DATA |
  906. PS_WAIT_FOR_TX_ACK);
  907. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  908. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  909. ath9k_hw_set_interrupts(ah);
  910. }
  911. }
  912. ath_dbg(common, PS, "PowerSave disabled\n");
  913. }
  914. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  915. {
  916. struct ath_softc *sc = hw->priv;
  917. struct ath_hw *ah = sc->sc_ah;
  918. struct ath_common *common = ath9k_hw_common(ah);
  919. struct ieee80211_conf *conf = &hw->conf;
  920. bool reset_channel = false;
  921. ath9k_ps_wakeup(sc);
  922. mutex_lock(&sc->mutex);
  923. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  924. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  925. if (sc->ps_idle)
  926. ath_cancel_work(sc);
  927. else
  928. /*
  929. * The chip needs a reset to properly wake up from
  930. * full sleep
  931. */
  932. reset_channel = ah->chip_fullsleep;
  933. }
  934. /*
  935. * We just prepare to enable PS. We have to wait until our AP has
  936. * ACK'd our null data frame to disable RX otherwise we'll ignore
  937. * those ACKs and end up retransmitting the same null data frames.
  938. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  939. */
  940. if (changed & IEEE80211_CONF_CHANGE_PS) {
  941. unsigned long flags;
  942. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  943. if (conf->flags & IEEE80211_CONF_PS)
  944. ath9k_enable_ps(sc);
  945. else
  946. ath9k_disable_ps(sc);
  947. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  948. }
  949. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  950. if (conf->flags & IEEE80211_CONF_MONITOR) {
  951. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  952. sc->sc_ah->is_monitoring = true;
  953. } else {
  954. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  955. sc->sc_ah->is_monitoring = false;
  956. }
  957. }
  958. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  959. struct ieee80211_channel *curchan = hw->conf.channel;
  960. int pos = curchan->hw_value;
  961. int old_pos = -1;
  962. unsigned long flags;
  963. if (ah->curchan)
  964. old_pos = ah->curchan - &ah->channels[0];
  965. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  966. curchan->center_freq, conf->channel_type);
  967. /* update survey stats for the old channel before switching */
  968. spin_lock_irqsave(&common->cc_lock, flags);
  969. ath_update_survey_stats(sc);
  970. spin_unlock_irqrestore(&common->cc_lock, flags);
  971. /*
  972. * Preserve the current channel values, before updating
  973. * the same channel
  974. */
  975. if (ah->curchan && (old_pos == pos))
  976. ath9k_hw_getnf(ah, ah->curchan);
  977. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  978. curchan, conf->channel_type);
  979. /*
  980. * If the operating channel changes, change the survey in-use flags
  981. * along with it.
  982. * Reset the survey data for the new channel, unless we're switching
  983. * back to the operating channel from an off-channel operation.
  984. */
  985. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  986. sc->cur_survey != &sc->survey[pos]) {
  987. if (sc->cur_survey)
  988. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  989. sc->cur_survey = &sc->survey[pos];
  990. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  991. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  992. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  993. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  994. }
  995. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  996. ath_err(common, "Unable to set channel\n");
  997. mutex_unlock(&sc->mutex);
  998. ath9k_ps_restore(sc);
  999. return -EINVAL;
  1000. }
  1001. /*
  1002. * The most recent snapshot of channel->noisefloor for the old
  1003. * channel is only available after the hardware reset. Copy it to
  1004. * the survey stats now.
  1005. */
  1006. if (old_pos >= 0)
  1007. ath_update_survey_nf(sc, old_pos);
  1008. }
  1009. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1010. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1011. sc->config.txpowlimit = 2 * conf->power_level;
  1012. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1013. sc->config.txpowlimit, &sc->curtxpow);
  1014. }
  1015. mutex_unlock(&sc->mutex);
  1016. ath9k_ps_restore(sc);
  1017. return 0;
  1018. }
  1019. #define SUPPORTED_FILTERS \
  1020. (FIF_PROMISC_IN_BSS | \
  1021. FIF_ALLMULTI | \
  1022. FIF_CONTROL | \
  1023. FIF_PSPOLL | \
  1024. FIF_OTHER_BSS | \
  1025. FIF_BCN_PRBRESP_PROMISC | \
  1026. FIF_PROBE_REQ | \
  1027. FIF_FCSFAIL)
  1028. /* FIXME: sc->sc_full_reset ? */
  1029. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1030. unsigned int changed_flags,
  1031. unsigned int *total_flags,
  1032. u64 multicast)
  1033. {
  1034. struct ath_softc *sc = hw->priv;
  1035. u32 rfilt;
  1036. changed_flags &= SUPPORTED_FILTERS;
  1037. *total_flags &= SUPPORTED_FILTERS;
  1038. sc->rx.rxfilter = *total_flags;
  1039. ath9k_ps_wakeup(sc);
  1040. rfilt = ath_calcrxfilter(sc);
  1041. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1042. ath9k_ps_restore(sc);
  1043. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1044. rfilt);
  1045. }
  1046. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1047. struct ieee80211_vif *vif,
  1048. struct ieee80211_sta *sta)
  1049. {
  1050. struct ath_softc *sc = hw->priv;
  1051. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1052. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1053. struct ieee80211_key_conf ps_key = { };
  1054. ath_node_attach(sc, sta, vif);
  1055. if (vif->type != NL80211_IFTYPE_AP &&
  1056. vif->type != NL80211_IFTYPE_AP_VLAN)
  1057. return 0;
  1058. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1059. return 0;
  1060. }
  1061. static void ath9k_del_ps_key(struct ath_softc *sc,
  1062. struct ieee80211_vif *vif,
  1063. struct ieee80211_sta *sta)
  1064. {
  1065. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1066. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1067. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1068. if (!an->ps_key)
  1069. return;
  1070. ath_key_delete(common, &ps_key);
  1071. }
  1072. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1073. struct ieee80211_vif *vif,
  1074. struct ieee80211_sta *sta)
  1075. {
  1076. struct ath_softc *sc = hw->priv;
  1077. ath9k_del_ps_key(sc, vif, sta);
  1078. ath_node_detach(sc, sta);
  1079. return 0;
  1080. }
  1081. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1082. struct ieee80211_vif *vif,
  1083. enum sta_notify_cmd cmd,
  1084. struct ieee80211_sta *sta)
  1085. {
  1086. struct ath_softc *sc = hw->priv;
  1087. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1088. if (!sta->ht_cap.ht_supported)
  1089. return;
  1090. switch (cmd) {
  1091. case STA_NOTIFY_SLEEP:
  1092. an->sleeping = true;
  1093. ath_tx_aggr_sleep(sta, sc, an);
  1094. break;
  1095. case STA_NOTIFY_AWAKE:
  1096. an->sleeping = false;
  1097. ath_tx_aggr_wakeup(sc, an);
  1098. break;
  1099. }
  1100. }
  1101. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1102. struct ieee80211_vif *vif, u16 queue,
  1103. const struct ieee80211_tx_queue_params *params)
  1104. {
  1105. struct ath_softc *sc = hw->priv;
  1106. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1107. struct ath_txq *txq;
  1108. struct ath9k_tx_queue_info qi;
  1109. int ret = 0;
  1110. if (queue >= WME_NUM_AC)
  1111. return 0;
  1112. txq = sc->tx.txq_map[queue];
  1113. ath9k_ps_wakeup(sc);
  1114. mutex_lock(&sc->mutex);
  1115. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1116. qi.tqi_aifs = params->aifs;
  1117. qi.tqi_cwmin = params->cw_min;
  1118. qi.tqi_cwmax = params->cw_max;
  1119. qi.tqi_burstTime = params->txop;
  1120. ath_dbg(common, CONFIG,
  1121. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1122. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1123. params->cw_max, params->txop);
  1124. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1125. if (ret)
  1126. ath_err(common, "TXQ Update failed\n");
  1127. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1128. if (queue == WME_AC_BE && !ret)
  1129. ath_beaconq_config(sc);
  1130. mutex_unlock(&sc->mutex);
  1131. ath9k_ps_restore(sc);
  1132. return ret;
  1133. }
  1134. static int ath9k_set_key(struct ieee80211_hw *hw,
  1135. enum set_key_cmd cmd,
  1136. struct ieee80211_vif *vif,
  1137. struct ieee80211_sta *sta,
  1138. struct ieee80211_key_conf *key)
  1139. {
  1140. struct ath_softc *sc = hw->priv;
  1141. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1142. int ret = 0;
  1143. if (ath9k_modparam_nohwcrypt)
  1144. return -ENOSPC;
  1145. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1146. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1147. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1148. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1149. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1150. /*
  1151. * For now, disable hw crypto for the RSN IBSS group keys. This
  1152. * could be optimized in the future to use a modified key cache
  1153. * design to support per-STA RX GTK, but until that gets
  1154. * implemented, use of software crypto for group addressed
  1155. * frames is a acceptable to allow RSN IBSS to be used.
  1156. */
  1157. return -EOPNOTSUPP;
  1158. }
  1159. mutex_lock(&sc->mutex);
  1160. ath9k_ps_wakeup(sc);
  1161. ath_dbg(common, CONFIG, "Set HW Key\n");
  1162. switch (cmd) {
  1163. case SET_KEY:
  1164. if (sta)
  1165. ath9k_del_ps_key(sc, vif, sta);
  1166. ret = ath_key_config(common, vif, sta, key);
  1167. if (ret >= 0) {
  1168. key->hw_key_idx = ret;
  1169. /* push IV and Michael MIC generation to stack */
  1170. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1171. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1172. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1173. if (sc->sc_ah->sw_mgmt_crypto &&
  1174. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1175. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1176. ret = 0;
  1177. }
  1178. break;
  1179. case DISABLE_KEY:
  1180. ath_key_delete(common, key);
  1181. break;
  1182. default:
  1183. ret = -EINVAL;
  1184. }
  1185. ath9k_ps_restore(sc);
  1186. mutex_unlock(&sc->mutex);
  1187. return ret;
  1188. }
  1189. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1190. {
  1191. struct ath_softc *sc = data;
  1192. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1193. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1194. struct ath_vif *avp = (void *)vif->drv_priv;
  1195. unsigned long flags;
  1196. /*
  1197. * Skip iteration if primary station vif's bss info
  1198. * was not changed
  1199. */
  1200. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1201. return;
  1202. if (bss_conf->assoc) {
  1203. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1204. avp->primary_sta_vif = true;
  1205. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1206. common->curaid = bss_conf->aid;
  1207. ath9k_hw_write_associd(sc->sc_ah);
  1208. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1209. bss_conf->aid, common->curbssid);
  1210. ath_beacon_config(sc, vif);
  1211. /*
  1212. * Request a re-configuration of Beacon related timers
  1213. * on the receipt of the first Beacon frame (i.e.,
  1214. * after time sync with the AP).
  1215. */
  1216. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1217. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1218. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1219. /* Reset rssi stats */
  1220. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1221. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1222. ath_start_rx_poll(sc, 3);
  1223. if (!common->disable_ani) {
  1224. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1225. ath_start_ani(common);
  1226. }
  1227. }
  1228. }
  1229. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1230. {
  1231. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1232. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1233. struct ath_vif *avp = (void *)vif->drv_priv;
  1234. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1235. return;
  1236. /* Reconfigure bss info */
  1237. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1238. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1239. common->curaid, common->curbssid);
  1240. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1241. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1242. avp->primary_sta_vif = false;
  1243. memset(common->curbssid, 0, ETH_ALEN);
  1244. common->curaid = 0;
  1245. }
  1246. ieee80211_iterate_active_interfaces_atomic(
  1247. sc->hw, ath9k_bss_iter, sc);
  1248. /*
  1249. * None of station vifs are associated.
  1250. * Clear bssid & aid
  1251. */
  1252. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1253. ath9k_hw_write_associd(sc->sc_ah);
  1254. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1255. del_timer_sync(&common->ani.timer);
  1256. del_timer_sync(&sc->rx_poll_timer);
  1257. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1258. }
  1259. }
  1260. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1261. struct ieee80211_vif *vif,
  1262. struct ieee80211_bss_conf *bss_conf,
  1263. u32 changed)
  1264. {
  1265. struct ath_softc *sc = hw->priv;
  1266. struct ath_hw *ah = sc->sc_ah;
  1267. struct ath_common *common = ath9k_hw_common(ah);
  1268. struct ath_vif *avp = (void *)vif->drv_priv;
  1269. int slottime;
  1270. ath9k_ps_wakeup(sc);
  1271. mutex_lock(&sc->mutex);
  1272. if (changed & BSS_CHANGED_ASSOC) {
  1273. ath9k_config_bss(sc, vif);
  1274. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1275. common->curbssid, common->curaid);
  1276. }
  1277. if (changed & BSS_CHANGED_IBSS) {
  1278. /* There can be only one vif available */
  1279. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1280. common->curaid = bss_conf->aid;
  1281. ath9k_hw_write_associd(sc->sc_ah);
  1282. if (bss_conf->ibss_joined) {
  1283. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1284. if (!common->disable_ani) {
  1285. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1286. ath_start_ani(common);
  1287. }
  1288. } else {
  1289. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1290. del_timer_sync(&common->ani.timer);
  1291. del_timer_sync(&sc->rx_poll_timer);
  1292. }
  1293. }
  1294. /*
  1295. * In case of AP mode, the HW TSF has to be reset
  1296. * when the beacon interval changes.
  1297. */
  1298. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1299. (vif->type == NL80211_IFTYPE_AP))
  1300. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  1301. /* Configure beaconing (AP, IBSS, MESH) */
  1302. if (ath9k_uses_beacons(vif->type) &&
  1303. ((changed & BSS_CHANGED_BEACON) ||
  1304. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1305. (changed & BSS_CHANGED_BEACON_INT))) {
  1306. ath9k_set_beaconing_status(sc, false);
  1307. if (bss_conf->enable_beacon)
  1308. ath_beacon_alloc(sc, vif);
  1309. else
  1310. avp->is_bslot_active = false;
  1311. ath_beacon_config(sc, vif);
  1312. ath9k_set_beaconing_status(sc, true);
  1313. }
  1314. if (changed & BSS_CHANGED_ERP_SLOT) {
  1315. if (bss_conf->use_short_slot)
  1316. slottime = 9;
  1317. else
  1318. slottime = 20;
  1319. if (vif->type == NL80211_IFTYPE_AP) {
  1320. /*
  1321. * Defer update, so that connected stations can adjust
  1322. * their settings at the same time.
  1323. * See beacon.c for more details
  1324. */
  1325. sc->beacon.slottime = slottime;
  1326. sc->beacon.updateslot = UPDATE;
  1327. } else {
  1328. ah->slottime = slottime;
  1329. ath9k_hw_init_global_settings(ah);
  1330. }
  1331. }
  1332. mutex_unlock(&sc->mutex);
  1333. ath9k_ps_restore(sc);
  1334. }
  1335. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1336. {
  1337. struct ath_softc *sc = hw->priv;
  1338. u64 tsf;
  1339. mutex_lock(&sc->mutex);
  1340. ath9k_ps_wakeup(sc);
  1341. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1342. ath9k_ps_restore(sc);
  1343. mutex_unlock(&sc->mutex);
  1344. return tsf;
  1345. }
  1346. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1347. struct ieee80211_vif *vif,
  1348. u64 tsf)
  1349. {
  1350. struct ath_softc *sc = hw->priv;
  1351. mutex_lock(&sc->mutex);
  1352. ath9k_ps_wakeup(sc);
  1353. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1354. ath9k_ps_restore(sc);
  1355. mutex_unlock(&sc->mutex);
  1356. }
  1357. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1358. {
  1359. struct ath_softc *sc = hw->priv;
  1360. mutex_lock(&sc->mutex);
  1361. ath9k_ps_wakeup(sc);
  1362. ath9k_hw_reset_tsf(sc->sc_ah);
  1363. ath9k_ps_restore(sc);
  1364. mutex_unlock(&sc->mutex);
  1365. }
  1366. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1367. struct ieee80211_vif *vif,
  1368. enum ieee80211_ampdu_mlme_action action,
  1369. struct ieee80211_sta *sta,
  1370. u16 tid, u16 *ssn, u8 buf_size)
  1371. {
  1372. struct ath_softc *sc = hw->priv;
  1373. int ret = 0;
  1374. local_bh_disable();
  1375. switch (action) {
  1376. case IEEE80211_AMPDU_RX_START:
  1377. break;
  1378. case IEEE80211_AMPDU_RX_STOP:
  1379. break;
  1380. case IEEE80211_AMPDU_TX_START:
  1381. ath9k_ps_wakeup(sc);
  1382. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1383. if (!ret)
  1384. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1385. ath9k_ps_restore(sc);
  1386. break;
  1387. case IEEE80211_AMPDU_TX_STOP:
  1388. ath9k_ps_wakeup(sc);
  1389. ath_tx_aggr_stop(sc, sta, tid);
  1390. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1391. ath9k_ps_restore(sc);
  1392. break;
  1393. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1394. ath9k_ps_wakeup(sc);
  1395. ath_tx_aggr_resume(sc, sta, tid);
  1396. ath9k_ps_restore(sc);
  1397. break;
  1398. default:
  1399. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1400. }
  1401. local_bh_enable();
  1402. return ret;
  1403. }
  1404. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1405. struct survey_info *survey)
  1406. {
  1407. struct ath_softc *sc = hw->priv;
  1408. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1409. struct ieee80211_supported_band *sband;
  1410. struct ieee80211_channel *chan;
  1411. unsigned long flags;
  1412. int pos;
  1413. spin_lock_irqsave(&common->cc_lock, flags);
  1414. if (idx == 0)
  1415. ath_update_survey_stats(sc);
  1416. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1417. if (sband && idx >= sband->n_channels) {
  1418. idx -= sband->n_channels;
  1419. sband = NULL;
  1420. }
  1421. if (!sband)
  1422. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1423. if (!sband || idx >= sband->n_channels) {
  1424. spin_unlock_irqrestore(&common->cc_lock, flags);
  1425. return -ENOENT;
  1426. }
  1427. chan = &sband->channels[idx];
  1428. pos = chan->hw_value;
  1429. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1430. survey->channel = chan;
  1431. spin_unlock_irqrestore(&common->cc_lock, flags);
  1432. return 0;
  1433. }
  1434. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1435. {
  1436. struct ath_softc *sc = hw->priv;
  1437. struct ath_hw *ah = sc->sc_ah;
  1438. mutex_lock(&sc->mutex);
  1439. ah->coverage_class = coverage_class;
  1440. ath9k_ps_wakeup(sc);
  1441. ath9k_hw_init_global_settings(ah);
  1442. ath9k_ps_restore(sc);
  1443. mutex_unlock(&sc->mutex);
  1444. }
  1445. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1446. {
  1447. struct ath_softc *sc = hw->priv;
  1448. struct ath_hw *ah = sc->sc_ah;
  1449. struct ath_common *common = ath9k_hw_common(ah);
  1450. int timeout = 200; /* ms */
  1451. int i, j;
  1452. bool drain_txq;
  1453. mutex_lock(&sc->mutex);
  1454. cancel_delayed_work_sync(&sc->tx_complete_work);
  1455. if (ah->ah_flags & AH_UNPLUGGED) {
  1456. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1457. mutex_unlock(&sc->mutex);
  1458. return;
  1459. }
  1460. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1461. ath_dbg(common, ANY, "Device not present\n");
  1462. mutex_unlock(&sc->mutex);
  1463. return;
  1464. }
  1465. for (j = 0; j < timeout; j++) {
  1466. bool npend = false;
  1467. if (j)
  1468. usleep_range(1000, 2000);
  1469. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1470. if (!ATH_TXQ_SETUP(sc, i))
  1471. continue;
  1472. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1473. if (npend)
  1474. break;
  1475. }
  1476. if (!npend)
  1477. break;
  1478. }
  1479. if (drop) {
  1480. ath9k_ps_wakeup(sc);
  1481. spin_lock_bh(&sc->sc_pcu_lock);
  1482. drain_txq = ath_drain_all_txq(sc, false);
  1483. spin_unlock_bh(&sc->sc_pcu_lock);
  1484. if (!drain_txq)
  1485. ath_reset(sc, false);
  1486. ath9k_ps_restore(sc);
  1487. ieee80211_wake_queues(hw);
  1488. }
  1489. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1490. mutex_unlock(&sc->mutex);
  1491. }
  1492. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1493. {
  1494. struct ath_softc *sc = hw->priv;
  1495. int i;
  1496. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1497. if (!ATH_TXQ_SETUP(sc, i))
  1498. continue;
  1499. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1500. return true;
  1501. }
  1502. return false;
  1503. }
  1504. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1505. {
  1506. struct ath_softc *sc = hw->priv;
  1507. struct ath_hw *ah = sc->sc_ah;
  1508. struct ieee80211_vif *vif;
  1509. struct ath_vif *avp;
  1510. struct ath_buf *bf;
  1511. struct ath_tx_status ts;
  1512. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1513. int status;
  1514. vif = sc->beacon.bslot[0];
  1515. if (!vif)
  1516. return 0;
  1517. avp = (void *)vif->drv_priv;
  1518. if (!avp->is_bslot_active)
  1519. return 0;
  1520. if (!sc->beacon.tx_processed && !edma) {
  1521. tasklet_disable(&sc->bcon_tasklet);
  1522. bf = avp->av_bcbuf;
  1523. if (!bf || !bf->bf_mpdu)
  1524. goto skip;
  1525. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1526. if (status == -EINPROGRESS)
  1527. goto skip;
  1528. sc->beacon.tx_processed = true;
  1529. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1530. skip:
  1531. tasklet_enable(&sc->bcon_tasklet);
  1532. }
  1533. return sc->beacon.tx_last;
  1534. }
  1535. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1536. struct ieee80211_low_level_stats *stats)
  1537. {
  1538. struct ath_softc *sc = hw->priv;
  1539. struct ath_hw *ah = sc->sc_ah;
  1540. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1541. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1542. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1543. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1544. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1545. return 0;
  1546. }
  1547. static u32 fill_chainmask(u32 cap, u32 new)
  1548. {
  1549. u32 filled = 0;
  1550. int i;
  1551. for (i = 0; cap && new; i++, cap >>= 1) {
  1552. if (!(cap & BIT(0)))
  1553. continue;
  1554. if (new & BIT(0))
  1555. filled |= BIT(i);
  1556. new >>= 1;
  1557. }
  1558. return filled;
  1559. }
  1560. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1561. {
  1562. struct ath_softc *sc = hw->priv;
  1563. struct ath_hw *ah = sc->sc_ah;
  1564. if (!rx_ant || !tx_ant)
  1565. return -EINVAL;
  1566. sc->ant_rx = rx_ant;
  1567. sc->ant_tx = tx_ant;
  1568. if (ah->caps.rx_chainmask == 1)
  1569. return 0;
  1570. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1571. if (AR_SREV_9100(ah))
  1572. ah->rxchainmask = 0x7;
  1573. else
  1574. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1575. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1576. ath9k_reload_chainmask_settings(sc);
  1577. return 0;
  1578. }
  1579. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1580. {
  1581. struct ath_softc *sc = hw->priv;
  1582. *tx_ant = sc->ant_tx;
  1583. *rx_ant = sc->ant_rx;
  1584. return 0;
  1585. }
  1586. #ifdef CONFIG_ATH9K_DEBUGFS
  1587. /* Ethtool support for get-stats */
  1588. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1589. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1590. "tx_pkts_nic",
  1591. "tx_bytes_nic",
  1592. "rx_pkts_nic",
  1593. "rx_bytes_nic",
  1594. AMKSTR(d_tx_pkts),
  1595. AMKSTR(d_tx_bytes),
  1596. AMKSTR(d_tx_mpdus_queued),
  1597. AMKSTR(d_tx_mpdus_completed),
  1598. AMKSTR(d_tx_mpdu_xretries),
  1599. AMKSTR(d_tx_aggregates),
  1600. AMKSTR(d_tx_ampdus_queued_hw),
  1601. AMKSTR(d_tx_ampdus_queued_sw),
  1602. AMKSTR(d_tx_ampdus_completed),
  1603. AMKSTR(d_tx_ampdu_retries),
  1604. AMKSTR(d_tx_ampdu_xretries),
  1605. AMKSTR(d_tx_fifo_underrun),
  1606. AMKSTR(d_tx_op_exceeded),
  1607. AMKSTR(d_tx_timer_expiry),
  1608. AMKSTR(d_tx_desc_cfg_err),
  1609. AMKSTR(d_tx_data_underrun),
  1610. AMKSTR(d_tx_delim_underrun),
  1611. "d_rx_decrypt_crc_err",
  1612. "d_rx_phy_err",
  1613. "d_rx_mic_err",
  1614. "d_rx_pre_delim_crc_err",
  1615. "d_rx_post_delim_crc_err",
  1616. "d_rx_decrypt_busy_err",
  1617. "d_rx_phyerr_radar",
  1618. "d_rx_phyerr_ofdm_timing",
  1619. "d_rx_phyerr_cck_timing",
  1620. };
  1621. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1622. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1623. struct ieee80211_vif *vif,
  1624. u32 sset, u8 *data)
  1625. {
  1626. if (sset == ETH_SS_STATS)
  1627. memcpy(data, *ath9k_gstrings_stats,
  1628. sizeof(ath9k_gstrings_stats));
  1629. }
  1630. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1631. struct ieee80211_vif *vif, int sset)
  1632. {
  1633. if (sset == ETH_SS_STATS)
  1634. return ATH9K_SSTATS_LEN;
  1635. return 0;
  1636. }
  1637. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1638. #define AWDATA(elem) \
  1639. do { \
  1640. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1641. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1642. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1643. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1644. } while (0)
  1645. #define AWDATA_RX(elem) \
  1646. do { \
  1647. data[i++] = sc->debug.stats.rxstats.elem; \
  1648. } while (0)
  1649. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1650. struct ieee80211_vif *vif,
  1651. struct ethtool_stats *stats, u64 *data)
  1652. {
  1653. struct ath_softc *sc = hw->priv;
  1654. int i = 0;
  1655. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1656. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1657. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1658. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1659. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1660. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1661. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1662. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1663. AWDATA_RX(rx_pkts_all);
  1664. AWDATA_RX(rx_bytes_all);
  1665. AWDATA(tx_pkts_all);
  1666. AWDATA(tx_bytes_all);
  1667. AWDATA(queued);
  1668. AWDATA(completed);
  1669. AWDATA(xretries);
  1670. AWDATA(a_aggr);
  1671. AWDATA(a_queued_hw);
  1672. AWDATA(a_queued_sw);
  1673. AWDATA(a_completed);
  1674. AWDATA(a_retries);
  1675. AWDATA(a_xretries);
  1676. AWDATA(fifo_underrun);
  1677. AWDATA(xtxop);
  1678. AWDATA(timer_exp);
  1679. AWDATA(desc_cfg_err);
  1680. AWDATA(data_underrun);
  1681. AWDATA(delim_underrun);
  1682. AWDATA_RX(decrypt_crc_err);
  1683. AWDATA_RX(phy_err);
  1684. AWDATA_RX(mic_err);
  1685. AWDATA_RX(pre_delim_crc_err);
  1686. AWDATA_RX(post_delim_crc_err);
  1687. AWDATA_RX(decrypt_busy_err);
  1688. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1689. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1690. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1691. WARN_ON(i != ATH9K_SSTATS_LEN);
  1692. }
  1693. /* End of ethtool get-stats functions */
  1694. #endif
  1695. struct ieee80211_ops ath9k_ops = {
  1696. .tx = ath9k_tx,
  1697. .start = ath9k_start,
  1698. .stop = ath9k_stop,
  1699. .add_interface = ath9k_add_interface,
  1700. .change_interface = ath9k_change_interface,
  1701. .remove_interface = ath9k_remove_interface,
  1702. .config = ath9k_config,
  1703. .configure_filter = ath9k_configure_filter,
  1704. .sta_add = ath9k_sta_add,
  1705. .sta_remove = ath9k_sta_remove,
  1706. .sta_notify = ath9k_sta_notify,
  1707. .conf_tx = ath9k_conf_tx,
  1708. .bss_info_changed = ath9k_bss_info_changed,
  1709. .set_key = ath9k_set_key,
  1710. .get_tsf = ath9k_get_tsf,
  1711. .set_tsf = ath9k_set_tsf,
  1712. .reset_tsf = ath9k_reset_tsf,
  1713. .ampdu_action = ath9k_ampdu_action,
  1714. .get_survey = ath9k_get_survey,
  1715. .rfkill_poll = ath9k_rfkill_poll_state,
  1716. .set_coverage_class = ath9k_set_coverage_class,
  1717. .flush = ath9k_flush,
  1718. .tx_frames_pending = ath9k_tx_frames_pending,
  1719. .tx_last_beacon = ath9k_tx_last_beacon,
  1720. .get_stats = ath9k_get_stats,
  1721. .set_antenna = ath9k_set_antenna,
  1722. .get_antenna = ath9k_get_antenna,
  1723. #ifdef CONFIG_ATH9K_DEBUGFS
  1724. .get_et_sset_count = ath9k_get_et_sset_count,
  1725. .get_et_stats = ath9k_get_et_stats,
  1726. .get_et_strings = ath9k_get_et_strings,
  1727. #endif
  1728. };