mptbase.c 214 KB

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  1. /*
  2. * linux/drivers/message/fusion/mptbase.c
  3. * This is the Fusion MPT base driver which supports multiple
  4. * (SCSI + LAN) specialized protocol drivers.
  5. * For use with LSI PCI chip/adapter(s)
  6. * running LSI Fusion MPT (Message Passing Technology) firmware.
  7. *
  8. * Copyright (c) 1999-2008 LSI Corporation
  9. * (mailto:DL-MPTFusionLinux@lsi.com)
  10. *
  11. */
  12. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  13. /*
  14. This program is free software; you can redistribute it and/or modify
  15. it under the terms of the GNU General Public License as published by
  16. the Free Software Foundation; version 2 of the License.
  17. This program is distributed in the hope that it will be useful,
  18. but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. GNU General Public License for more details.
  21. NO WARRANTY
  22. THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  23. CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  24. LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  25. MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  26. solely responsible for determining the appropriateness of using and
  27. distributing the Program and assumes all risks associated with its
  28. exercise of rights under this Agreement, including but not limited to
  29. the risks and costs of program errors, damage to or loss of data,
  30. programs or equipment, and unavailability or interruption of operations.
  31. DISCLAIMER OF LIABILITY
  32. NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33. DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34. DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35. ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36. TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37. USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38. HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39. You should have received a copy of the GNU General Public License
  40. along with this program; if not, write to the Free Software
  41. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  42. */
  43. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  44. #include <linux/kernel.h>
  45. #include <linux/module.h>
  46. #include <linux/errno.h>
  47. #include <linux/init.h>
  48. #include <linux/slab.h>
  49. #include <linux/types.h>
  50. #include <linux/pci.h>
  51. #include <linux/kdev_t.h>
  52. #include <linux/blkdev.h>
  53. #include <linux/delay.h>
  54. #include <linux/interrupt.h> /* needed for in_interrupt() proto */
  55. #include <linux/dma-mapping.h>
  56. #include <asm/io.h>
  57. #ifdef CONFIG_MTRR
  58. #include <asm/mtrr.h>
  59. #endif
  60. #include "mptbase.h"
  61. #include "lsi/mpi_log_fc.h"
  62. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  63. #define my_NAME "Fusion MPT base driver"
  64. #define my_VERSION MPT_LINUX_VERSION_COMMON
  65. #define MYNAM "mptbase"
  66. MODULE_AUTHOR(MODULEAUTHOR);
  67. MODULE_DESCRIPTION(my_NAME);
  68. MODULE_LICENSE("GPL");
  69. MODULE_VERSION(my_VERSION);
  70. /*
  71. * cmd line parameters
  72. */
  73. static int mpt_msi_enable = -1;
  74. module_param(mpt_msi_enable, int, 0);
  75. MODULE_PARM_DESC(mpt_msi_enable, " MSI Support Enable (default=0)");
  76. static int mpt_channel_mapping;
  77. module_param(mpt_channel_mapping, int, 0);
  78. MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
  79. static int mpt_debug_level;
  80. static int mpt_set_debug_level(const char *val, struct kernel_param *kp);
  81. module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
  82. &mpt_debug_level, 0600);
  83. MODULE_PARM_DESC(mpt_debug_level, " debug level - refer to mptdebug.h - (default=0)");
  84. #ifdef MFCNT
  85. static int mfcounter = 0;
  86. #define PRINT_MF_COUNT 20000
  87. #endif
  88. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  89. /*
  90. * Public data...
  91. */
  92. static struct proc_dir_entry *mpt_proc_root_dir;
  93. #define WHOINIT_UNKNOWN 0xAA
  94. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  95. /*
  96. * Private data...
  97. */
  98. /* Adapter link list */
  99. LIST_HEAD(ioc_list);
  100. /* Callback lookup table */
  101. static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
  102. /* Protocol driver class lookup table */
  103. static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
  104. /* Event handler lookup table */
  105. static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
  106. /* Reset handler lookup table */
  107. static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
  108. static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
  109. static DECLARE_WAIT_QUEUE_HEAD(mpt_waitq);
  110. /*
  111. * Driver Callback Index's
  112. */
  113. static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
  114. static u8 last_drv_idx;
  115. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  116. /*
  117. * Forward protos...
  118. */
  119. static irqreturn_t mpt_interrupt(int irq, void *bus_id);
  120. static int mpt_base_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply);
  121. static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
  122. u32 *req, int replyBytes, u16 *u16reply, int maxwait,
  123. int sleepFlag);
  124. static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
  125. static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
  126. static void mpt_adapter_disable(MPT_ADAPTER *ioc);
  127. static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
  128. static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
  129. static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
  130. static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
  131. static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
  132. static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
  133. static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
  134. static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
  135. static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
  136. static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
  137. static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
  138. static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
  139. static int PrimeIocFifos(MPT_ADAPTER *ioc);
  140. static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
  141. static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
  142. static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
  143. static int GetLanConfigPages(MPT_ADAPTER *ioc);
  144. static int GetIoUnitPage2(MPT_ADAPTER *ioc);
  145. int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
  146. static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
  147. static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
  148. static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
  149. static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
  150. static void mpt_timer_expired(unsigned long data);
  151. static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
  152. static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch);
  153. static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
  154. static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
  155. static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
  156. #ifdef CONFIG_PROC_FS
  157. static int procmpt_summary_read(char *buf, char **start, off_t offset,
  158. int request, int *eof, void *data);
  159. static int procmpt_version_read(char *buf, char **start, off_t offset,
  160. int request, int *eof, void *data);
  161. static int procmpt_iocinfo_read(char *buf, char **start, off_t offset,
  162. int request, int *eof, void *data);
  163. #endif
  164. static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
  165. //int mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag);
  166. static int ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *evReply, int *evHandlers);
  167. static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
  168. static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
  169. static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
  170. static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info);
  171. static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
  172. static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
  173. /* module entry point */
  174. static int __init fusion_init (void);
  175. static void __exit fusion_exit (void);
  176. #define CHIPREG_READ32(addr) readl_relaxed(addr)
  177. #define CHIPREG_READ32_dmasync(addr) readl(addr)
  178. #define CHIPREG_WRITE32(addr,val) writel(val, addr)
  179. #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
  180. #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
  181. static void
  182. pci_disable_io_access(struct pci_dev *pdev)
  183. {
  184. u16 command_reg;
  185. pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
  186. command_reg &= ~1;
  187. pci_write_config_word(pdev, PCI_COMMAND, command_reg);
  188. }
  189. static void
  190. pci_enable_io_access(struct pci_dev *pdev)
  191. {
  192. u16 command_reg;
  193. pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
  194. command_reg |= 1;
  195. pci_write_config_word(pdev, PCI_COMMAND, command_reg);
  196. }
  197. static int mpt_set_debug_level(const char *val, struct kernel_param *kp)
  198. {
  199. int ret = param_set_int(val, kp);
  200. MPT_ADAPTER *ioc;
  201. if (ret)
  202. return ret;
  203. list_for_each_entry(ioc, &ioc_list, list)
  204. ioc->debug_level = mpt_debug_level;
  205. return 0;
  206. }
  207. /**
  208. * mpt_get_cb_idx - obtain cb_idx for registered driver
  209. * @dclass: class driver enum
  210. *
  211. * Returns cb_idx, or zero means it wasn't found
  212. **/
  213. static u8
  214. mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
  215. {
  216. u8 cb_idx;
  217. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
  218. if (MptDriverClass[cb_idx] == dclass)
  219. return cb_idx;
  220. return 0;
  221. }
  222. /**
  223. * mpt_fault_reset_work - work performed on workq after ioc fault
  224. * @work: input argument, used to derive ioc
  225. *
  226. **/
  227. static void
  228. mpt_fault_reset_work(struct work_struct *work)
  229. {
  230. MPT_ADAPTER *ioc =
  231. container_of(work, MPT_ADAPTER, fault_reset_work.work);
  232. u32 ioc_raw_state;
  233. int rc;
  234. unsigned long flags;
  235. if (ioc->diagPending || !ioc->active)
  236. goto out;
  237. ioc_raw_state = mpt_GetIocState(ioc, 0);
  238. if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
  239. printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
  240. ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
  241. printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
  242. ioc->name, __func__);
  243. rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
  244. printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
  245. __func__, (rc == 0) ? "success" : "failed");
  246. ioc_raw_state = mpt_GetIocState(ioc, 0);
  247. if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
  248. printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
  249. "reset (%04xh)\n", ioc->name, ioc_raw_state &
  250. MPI_DOORBELL_DATA_MASK);
  251. }
  252. out:
  253. /*
  254. * Take turns polling alternate controller
  255. */
  256. if (ioc->alt_ioc)
  257. ioc = ioc->alt_ioc;
  258. /* rearm the timer */
  259. spin_lock_irqsave(&ioc->fault_reset_work_lock, flags);
  260. if (ioc->reset_work_q)
  261. queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
  262. msecs_to_jiffies(MPT_POLLING_INTERVAL));
  263. spin_unlock_irqrestore(&ioc->fault_reset_work_lock, flags);
  264. }
  265. /*
  266. * Process turbo (context) reply...
  267. */
  268. static void
  269. mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
  270. {
  271. MPT_FRAME_HDR *mf = NULL;
  272. MPT_FRAME_HDR *mr = NULL;
  273. u16 req_idx = 0;
  274. u8 cb_idx;
  275. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
  276. ioc->name, pa));
  277. switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
  278. case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
  279. req_idx = pa & 0x0000FFFF;
  280. cb_idx = (pa & 0x00FF0000) >> 16;
  281. mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
  282. break;
  283. case MPI_CONTEXT_REPLY_TYPE_LAN:
  284. cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
  285. /*
  286. * Blind set of mf to NULL here was fatal
  287. * after lan_reply says "freeme"
  288. * Fix sort of combined with an optimization here;
  289. * added explicit check for case where lan_reply
  290. * was just returning 1 and doing nothing else.
  291. * For this case skip the callback, but set up
  292. * proper mf value first here:-)
  293. */
  294. if ((pa & 0x58000000) == 0x58000000) {
  295. req_idx = pa & 0x0000FFFF;
  296. mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
  297. mpt_free_msg_frame(ioc, mf);
  298. mb();
  299. return;
  300. break;
  301. }
  302. mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
  303. break;
  304. case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
  305. cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
  306. mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
  307. break;
  308. default:
  309. cb_idx = 0;
  310. BUG();
  311. }
  312. /* Check for (valid) IO callback! */
  313. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
  314. MptCallbacks[cb_idx] == NULL) {
  315. printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
  316. __func__, ioc->name, cb_idx);
  317. goto out;
  318. }
  319. if (MptCallbacks[cb_idx](ioc, mf, mr))
  320. mpt_free_msg_frame(ioc, mf);
  321. out:
  322. mb();
  323. }
  324. static void
  325. mpt_reply(MPT_ADAPTER *ioc, u32 pa)
  326. {
  327. MPT_FRAME_HDR *mf;
  328. MPT_FRAME_HDR *mr;
  329. u16 req_idx;
  330. u8 cb_idx;
  331. int freeme;
  332. u32 reply_dma_low;
  333. u16 ioc_stat;
  334. /* non-TURBO reply! Hmmm, something may be up...
  335. * Newest turbo reply mechanism; get address
  336. * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
  337. */
  338. /* Map DMA address of reply header to cpu address.
  339. * pa is 32 bits - but the dma address may be 32 or 64 bits
  340. * get offset based only only the low addresses
  341. */
  342. reply_dma_low = (pa <<= 1);
  343. mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
  344. (reply_dma_low - ioc->reply_frames_low_dma));
  345. req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
  346. cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
  347. mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
  348. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
  349. ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
  350. DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
  351. /* Check/log IOC log info
  352. */
  353. ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
  354. if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
  355. u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
  356. if (ioc->bus_type == FC)
  357. mpt_fc_log_info(ioc, log_info);
  358. else if (ioc->bus_type == SPI)
  359. mpt_spi_log_info(ioc, log_info);
  360. else if (ioc->bus_type == SAS)
  361. mpt_sas_log_info(ioc, log_info);
  362. }
  363. if (ioc_stat & MPI_IOCSTATUS_MASK)
  364. mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
  365. /* Check for (valid) IO callback! */
  366. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
  367. MptCallbacks[cb_idx] == NULL) {
  368. printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
  369. __func__, ioc->name, cb_idx);
  370. freeme = 0;
  371. goto out;
  372. }
  373. freeme = MptCallbacks[cb_idx](ioc, mf, mr);
  374. out:
  375. /* Flush (non-TURBO) reply with a WRITE! */
  376. CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
  377. if (freeme)
  378. mpt_free_msg_frame(ioc, mf);
  379. mb();
  380. }
  381. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  382. /**
  383. * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
  384. * @irq: irq number (not used)
  385. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  386. *
  387. * This routine is registered via the request_irq() kernel API call,
  388. * and handles all interrupts generated from a specific MPT adapter
  389. * (also referred to as a IO Controller or IOC).
  390. * This routine must clear the interrupt from the adapter and does
  391. * so by reading the reply FIFO. Multiple replies may be processed
  392. * per single call to this routine.
  393. *
  394. * This routine handles register-level access of the adapter but
  395. * dispatches (calls) a protocol-specific callback routine to handle
  396. * the protocol-specific details of the MPT request completion.
  397. */
  398. static irqreturn_t
  399. mpt_interrupt(int irq, void *bus_id)
  400. {
  401. MPT_ADAPTER *ioc = bus_id;
  402. u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
  403. if (pa == 0xFFFFFFFF)
  404. return IRQ_NONE;
  405. /*
  406. * Drain the reply FIFO!
  407. */
  408. do {
  409. if (pa & MPI_ADDRESS_REPLY_A_BIT)
  410. mpt_reply(ioc, pa);
  411. else
  412. mpt_turbo_reply(ioc, pa);
  413. pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
  414. } while (pa != 0xFFFFFFFF);
  415. return IRQ_HANDLED;
  416. }
  417. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  418. /**
  419. * mpt_base_reply - MPT base driver's callback routine
  420. * @ioc: Pointer to MPT_ADAPTER structure
  421. * @mf: Pointer to original MPT request frame
  422. * @reply: Pointer to MPT reply frame (NULL if TurboReply)
  423. *
  424. * MPT base driver's callback routine; all base driver
  425. * "internal" request/reply processing is routed here.
  426. * Currently used for EventNotification and EventAck handling.
  427. *
  428. * Returns 1 indicating original alloc'd request frame ptr
  429. * should be freed, or 0 if it shouldn't.
  430. */
  431. static int
  432. mpt_base_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, MPT_FRAME_HDR *reply)
  433. {
  434. int freereq = 1;
  435. u8 func;
  436. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_base_reply() called\n", ioc->name));
  437. #ifdef CONFIG_FUSION_LOGGING
  438. if ((ioc->debug_level & MPT_DEBUG_MSG_FRAME) &&
  439. !(reply->u.hdr.MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)) {
  440. dmfprintk(ioc, printk(MYIOC_s_INFO_FMT ": Original request frame (@%p) header\n",
  441. ioc->name, mf));
  442. DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)mf);
  443. }
  444. #endif
  445. func = reply->u.hdr.Function;
  446. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_base_reply, Function=%02Xh\n",
  447. ioc->name, func));
  448. if (func == MPI_FUNCTION_EVENT_NOTIFICATION) {
  449. EventNotificationReply_t *pEvReply = (EventNotificationReply_t *) reply;
  450. int evHandlers = 0;
  451. int results;
  452. results = ProcessEventNotification(ioc, pEvReply, &evHandlers);
  453. if (results != evHandlers) {
  454. /* CHECKME! Any special handling needed here? */
  455. devtverboseprintk(ioc, printk(MYIOC_s_WARN_FMT "Called %d event handlers, sum results = %d\n",
  456. ioc->name, evHandlers, results));
  457. }
  458. /*
  459. * Hmmm... It seems that EventNotificationReply is an exception
  460. * to the rule of one reply per request.
  461. */
  462. if (pEvReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) {
  463. freereq = 0;
  464. } else {
  465. devtverboseprintk(ioc, printk(MYIOC_s_WARN_FMT "EVENT_NOTIFICATION reply %p returns Request frame\n",
  466. ioc->name, pEvReply));
  467. }
  468. #ifdef CONFIG_PROC_FS
  469. // LogEvent(ioc, pEvReply);
  470. #endif
  471. } else if (func == MPI_FUNCTION_EVENT_ACK) {
  472. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_base_reply, EventAck reply received\n",
  473. ioc->name));
  474. } else if (func == MPI_FUNCTION_CONFIG) {
  475. CONFIGPARMS *pCfg;
  476. unsigned long flags;
  477. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "config_complete (mf=%p,mr=%p)\n",
  478. ioc->name, mf, reply));
  479. pCfg = * ((CONFIGPARMS **)((u8 *) mf + ioc->req_sz - sizeof(void *)));
  480. if (pCfg) {
  481. /* disable timer and remove from linked list */
  482. del_timer(&pCfg->timer);
  483. spin_lock_irqsave(&ioc->FreeQlock, flags);
  484. list_del(&pCfg->linkage);
  485. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  486. /*
  487. * If IOC Status is SUCCESS, save the header
  488. * and set the status code to GOOD.
  489. */
  490. pCfg->status = MPT_CONFIG_ERROR;
  491. if (reply) {
  492. ConfigReply_t *pReply = (ConfigReply_t *)reply;
  493. u16 status;
  494. status = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
  495. dcprintk(ioc, printk(MYIOC_s_NOTE_FMT " IOCStatus=%04xh, IOCLogInfo=%08xh\n",
  496. ioc->name, status, le32_to_cpu(pReply->IOCLogInfo)));
  497. pCfg->status = status;
  498. if (status == MPI_IOCSTATUS_SUCCESS) {
  499. if ((pReply->Header.PageType &
  500. MPI_CONFIG_PAGETYPE_MASK) ==
  501. MPI_CONFIG_PAGETYPE_EXTENDED) {
  502. pCfg->cfghdr.ehdr->ExtPageLength =
  503. le16_to_cpu(pReply->ExtPageLength);
  504. pCfg->cfghdr.ehdr->ExtPageType =
  505. pReply->ExtPageType;
  506. }
  507. pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
  508. /* If this is a regular header, save PageLength. */
  509. /* LMP Do this better so not using a reserved field! */
  510. pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
  511. pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
  512. pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
  513. }
  514. }
  515. /*
  516. * Wake up the original calling thread
  517. */
  518. pCfg->wait_done = 1;
  519. wake_up(&mpt_waitq);
  520. }
  521. } else if (func == MPI_FUNCTION_SAS_IO_UNIT_CONTROL) {
  522. /* we should be always getting a reply frame */
  523. memcpy(ioc->persist_reply_frame, reply,
  524. min(MPT_DEFAULT_FRAME_SIZE,
  525. 4*reply->u.reply.MsgLength));
  526. del_timer(&ioc->persist_timer);
  527. ioc->persist_wait_done = 1;
  528. wake_up(&mpt_waitq);
  529. } else {
  530. printk(MYIOC_s_ERR_FMT "Unexpected msg function (=%02Xh) reply received!\n",
  531. ioc->name, func);
  532. }
  533. /*
  534. * Conditionally tell caller to free the original
  535. * EventNotification/EventAck/unexpected request frame!
  536. */
  537. return freereq;
  538. }
  539. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  540. /**
  541. * mpt_register - Register protocol-specific main callback handler.
  542. * @cbfunc: callback function pointer
  543. * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
  544. *
  545. * This routine is called by a protocol-specific driver (SCSI host,
  546. * LAN, SCSI target) to register its reply callback routine. Each
  547. * protocol-specific driver must do this before it will be able to
  548. * use any IOC resources, such as obtaining request frames.
  549. *
  550. * NOTES: The SCSI protocol driver currently calls this routine thrice
  551. * in order to register separate callbacks; one for "normal" SCSI IO;
  552. * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
  553. *
  554. * Returns u8 valued "handle" in the range (and S.O.D. order)
  555. * {N,...,7,6,5,...,1} if successful.
  556. * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
  557. * considered an error by the caller.
  558. */
  559. u8
  560. mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass)
  561. {
  562. u8 cb_idx;
  563. last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
  564. /*
  565. * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
  566. * (slot/handle 0 is reserved!)
  567. */
  568. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  569. if (MptCallbacks[cb_idx] == NULL) {
  570. MptCallbacks[cb_idx] = cbfunc;
  571. MptDriverClass[cb_idx] = dclass;
  572. MptEvHandlers[cb_idx] = NULL;
  573. last_drv_idx = cb_idx;
  574. break;
  575. }
  576. }
  577. return last_drv_idx;
  578. }
  579. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  580. /**
  581. * mpt_deregister - Deregister a protocol drivers resources.
  582. * @cb_idx: previously registered callback handle
  583. *
  584. * Each protocol-specific driver should call this routine when its
  585. * module is unloaded.
  586. */
  587. void
  588. mpt_deregister(u8 cb_idx)
  589. {
  590. if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
  591. MptCallbacks[cb_idx] = NULL;
  592. MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
  593. MptEvHandlers[cb_idx] = NULL;
  594. last_drv_idx++;
  595. }
  596. }
  597. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  598. /**
  599. * mpt_event_register - Register protocol-specific event callback handler.
  600. * @cb_idx: previously registered (via mpt_register) callback handle
  601. * @ev_cbfunc: callback function
  602. *
  603. * This routine can be called by one or more protocol-specific drivers
  604. * if/when they choose to be notified of MPT events.
  605. *
  606. * Returns 0 for success.
  607. */
  608. int
  609. mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
  610. {
  611. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  612. return -1;
  613. MptEvHandlers[cb_idx] = ev_cbfunc;
  614. return 0;
  615. }
  616. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  617. /**
  618. * mpt_event_deregister - Deregister protocol-specific event callback handler
  619. * @cb_idx: previously registered callback handle
  620. *
  621. * Each protocol-specific driver should call this routine
  622. * when it does not (or can no longer) handle events,
  623. * or when its module is unloaded.
  624. */
  625. void
  626. mpt_event_deregister(u8 cb_idx)
  627. {
  628. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  629. return;
  630. MptEvHandlers[cb_idx] = NULL;
  631. }
  632. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  633. /**
  634. * mpt_reset_register - Register protocol-specific IOC reset handler.
  635. * @cb_idx: previously registered (via mpt_register) callback handle
  636. * @reset_func: reset function
  637. *
  638. * This routine can be called by one or more protocol-specific drivers
  639. * if/when they choose to be notified of IOC resets.
  640. *
  641. * Returns 0 for success.
  642. */
  643. int
  644. mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
  645. {
  646. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  647. return -1;
  648. MptResetHandlers[cb_idx] = reset_func;
  649. return 0;
  650. }
  651. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  652. /**
  653. * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
  654. * @cb_idx: previously registered callback handle
  655. *
  656. * Each protocol-specific driver should call this routine
  657. * when it does not (or can no longer) handle IOC reset handling,
  658. * or when its module is unloaded.
  659. */
  660. void
  661. mpt_reset_deregister(u8 cb_idx)
  662. {
  663. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  664. return;
  665. MptResetHandlers[cb_idx] = NULL;
  666. }
  667. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  668. /**
  669. * mpt_device_driver_register - Register device driver hooks
  670. * @dd_cbfunc: driver callbacks struct
  671. * @cb_idx: MPT protocol driver index
  672. */
  673. int
  674. mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
  675. {
  676. MPT_ADAPTER *ioc;
  677. const struct pci_device_id *id;
  678. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  679. return -EINVAL;
  680. MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
  681. /* call per pci device probe entry point */
  682. list_for_each_entry(ioc, &ioc_list, list) {
  683. id = ioc->pcidev->driver ?
  684. ioc->pcidev->driver->id_table : NULL;
  685. if (dd_cbfunc->probe)
  686. dd_cbfunc->probe(ioc->pcidev, id);
  687. }
  688. return 0;
  689. }
  690. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  691. /**
  692. * mpt_device_driver_deregister - DeRegister device driver hooks
  693. * @cb_idx: MPT protocol driver index
  694. */
  695. void
  696. mpt_device_driver_deregister(u8 cb_idx)
  697. {
  698. struct mpt_pci_driver *dd_cbfunc;
  699. MPT_ADAPTER *ioc;
  700. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  701. return;
  702. dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
  703. list_for_each_entry(ioc, &ioc_list, list) {
  704. if (dd_cbfunc->remove)
  705. dd_cbfunc->remove(ioc->pcidev);
  706. }
  707. MptDeviceDriverHandlers[cb_idx] = NULL;
  708. }
  709. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  710. /**
  711. * mpt_get_msg_frame - Obtain an MPT request frame from the pool
  712. * @cb_idx: Handle of registered MPT protocol driver
  713. * @ioc: Pointer to MPT adapter structure
  714. *
  715. * Obtain an MPT request frame from the pool (of 1024) that are
  716. * allocated per MPT adapter.
  717. *
  718. * Returns pointer to a MPT request frame or %NULL if none are available
  719. * or IOC is not active.
  720. */
  721. MPT_FRAME_HDR*
  722. mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
  723. {
  724. MPT_FRAME_HDR *mf;
  725. unsigned long flags;
  726. u16 req_idx; /* Request index */
  727. /* validate handle and ioc identifier */
  728. #ifdef MFCNT
  729. if (!ioc->active)
  730. printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
  731. "returning NULL!\n", ioc->name);
  732. #endif
  733. /* If interrupts are not attached, do not return a request frame */
  734. if (!ioc->active)
  735. return NULL;
  736. spin_lock_irqsave(&ioc->FreeQlock, flags);
  737. if (!list_empty(&ioc->FreeQ)) {
  738. int req_offset;
  739. mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
  740. u.frame.linkage.list);
  741. list_del(&mf->u.frame.linkage.list);
  742. mf->u.frame.linkage.arg1 = 0;
  743. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
  744. req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
  745. /* u16! */
  746. req_idx = req_offset / ioc->req_sz;
  747. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
  748. mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
  749. /* Default, will be changed if necessary in SG generation */
  750. ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
  751. #ifdef MFCNT
  752. ioc->mfcnt++;
  753. #endif
  754. }
  755. else
  756. mf = NULL;
  757. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  758. #ifdef MFCNT
  759. if (mf == NULL)
  760. printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
  761. "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
  762. ioc->req_depth);
  763. mfcounter++;
  764. if (mfcounter == PRINT_MF_COUNT)
  765. printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
  766. ioc->mfcnt, ioc->req_depth);
  767. #endif
  768. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
  769. ioc->name, cb_idx, ioc->id, mf));
  770. return mf;
  771. }
  772. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  773. /**
  774. * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
  775. * @cb_idx: Handle of registered MPT protocol driver
  776. * @ioc: Pointer to MPT adapter structure
  777. * @mf: Pointer to MPT request frame
  778. *
  779. * This routine posts an MPT request frame to the request post FIFO of a
  780. * specific MPT adapter.
  781. */
  782. void
  783. mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
  784. {
  785. u32 mf_dma_addr;
  786. int req_offset;
  787. u16 req_idx; /* Request index */
  788. /* ensure values are reset properly! */
  789. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
  790. req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
  791. /* u16! */
  792. req_idx = req_offset / ioc->req_sz;
  793. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
  794. mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
  795. DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
  796. mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
  797. dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
  798. "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
  799. ioc->RequestNB[req_idx]));
  800. CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
  801. }
  802. /**
  803. * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
  804. * @cb_idx: Handle of registered MPT protocol driver
  805. * @ioc: Pointer to MPT adapter structure
  806. * @mf: Pointer to MPT request frame
  807. *
  808. * Send a protocol-specific MPT request frame to an IOC using
  809. * hi-priority request queue.
  810. *
  811. * This routine posts an MPT request frame to the request post FIFO of a
  812. * specific MPT adapter.
  813. **/
  814. void
  815. mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
  816. {
  817. u32 mf_dma_addr;
  818. int req_offset;
  819. u16 req_idx; /* Request index */
  820. /* ensure values are reset properly! */
  821. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
  822. req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
  823. req_idx = req_offset / ioc->req_sz;
  824. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
  825. mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
  826. DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
  827. mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
  828. dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
  829. ioc->name, mf_dma_addr, req_idx));
  830. CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
  831. }
  832. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  833. /**
  834. * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
  835. * @ioc: Pointer to MPT adapter structure
  836. * @mf: Pointer to MPT request frame
  837. *
  838. * This routine places a MPT request frame back on the MPT adapter's
  839. * FreeQ.
  840. */
  841. void
  842. mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
  843. {
  844. unsigned long flags;
  845. /* Put Request back on FreeQ! */
  846. spin_lock_irqsave(&ioc->FreeQlock, flags);
  847. mf->u.frame.linkage.arg1 = 0xdeadbeaf; /* signature to know if this mf is freed */
  848. list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
  849. #ifdef MFCNT
  850. ioc->mfcnt--;
  851. #endif
  852. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  853. }
  854. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  855. /**
  856. * mpt_add_sge - Place a simple SGE at address pAddr.
  857. * @pAddr: virtual address for SGE
  858. * @flagslength: SGE flags and data transfer length
  859. * @dma_addr: Physical address
  860. *
  861. * This routine places a MPT request frame back on the MPT adapter's
  862. * FreeQ.
  863. */
  864. void
  865. mpt_add_sge(char *pAddr, u32 flagslength, dma_addr_t dma_addr)
  866. {
  867. if (sizeof(dma_addr_t) == sizeof(u64)) {
  868. SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
  869. u32 tmp = dma_addr & 0xFFFFFFFF;
  870. pSge->FlagsLength = cpu_to_le32(flagslength);
  871. pSge->Address.Low = cpu_to_le32(tmp);
  872. tmp = (u32) ((u64)dma_addr >> 32);
  873. pSge->Address.High = cpu_to_le32(tmp);
  874. } else {
  875. SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
  876. pSge->FlagsLength = cpu_to_le32(flagslength);
  877. pSge->Address = cpu_to_le32(dma_addr);
  878. }
  879. }
  880. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  881. /**
  882. * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
  883. * @cb_idx: Handle of registered MPT protocol driver
  884. * @ioc: Pointer to MPT adapter structure
  885. * @reqBytes: Size of the request in bytes
  886. * @req: Pointer to MPT request frame
  887. * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
  888. *
  889. * This routine is used exclusively to send MptScsiTaskMgmt
  890. * requests since they are required to be sent via doorbell handshake.
  891. *
  892. * NOTE: It is the callers responsibility to byte-swap fields in the
  893. * request which are greater than 1 byte in size.
  894. *
  895. * Returns 0 for success, non-zero for failure.
  896. */
  897. int
  898. mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
  899. {
  900. int r = 0;
  901. u8 *req_as_bytes;
  902. int ii;
  903. /* State is known to be good upon entering
  904. * this function so issue the bus reset
  905. * request.
  906. */
  907. /*
  908. * Emulate what mpt_put_msg_frame() does /wrt to sanity
  909. * setting cb_idx/req_idx. But ONLY if this request
  910. * is in proper (pre-alloc'd) request buffer range...
  911. */
  912. ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
  913. if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
  914. MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
  915. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
  916. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
  917. }
  918. /* Make sure there are no doorbells */
  919. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  920. CHIPREG_WRITE32(&ioc->chip->Doorbell,
  921. ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
  922. ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
  923. /* Wait for IOC doorbell int */
  924. if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
  925. return ii;
  926. }
  927. /* Read doorbell and check for active bit */
  928. if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
  929. return -5;
  930. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
  931. ioc->name, ii));
  932. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  933. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
  934. return -2;
  935. }
  936. /* Send request via doorbell handshake */
  937. req_as_bytes = (u8 *) req;
  938. for (ii = 0; ii < reqBytes/4; ii++) {
  939. u32 word;
  940. word = ((req_as_bytes[(ii*4) + 0] << 0) |
  941. (req_as_bytes[(ii*4) + 1] << 8) |
  942. (req_as_bytes[(ii*4) + 2] << 16) |
  943. (req_as_bytes[(ii*4) + 3] << 24));
  944. CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
  945. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
  946. r = -3;
  947. break;
  948. }
  949. }
  950. if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
  951. r = 0;
  952. else
  953. r = -4;
  954. /* Make sure there are no doorbells */
  955. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  956. return r;
  957. }
  958. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  959. /**
  960. * mpt_host_page_access_control - control the IOC's Host Page Buffer access
  961. * @ioc: Pointer to MPT adapter structure
  962. * @access_control_value: define bits below
  963. * @sleepFlag: Specifies whether the process can sleep
  964. *
  965. * Provides mechanism for the host driver to control the IOC's
  966. * Host Page Buffer access.
  967. *
  968. * Access Control Value - bits[15:12]
  969. * 0h Reserved
  970. * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
  971. * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
  972. * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
  973. *
  974. * Returns 0 for success, non-zero for failure.
  975. */
  976. static int
  977. mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
  978. {
  979. int r = 0;
  980. /* return if in use */
  981. if (CHIPREG_READ32(&ioc->chip->Doorbell)
  982. & MPI_DOORBELL_ACTIVE)
  983. return -1;
  984. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  985. CHIPREG_WRITE32(&ioc->chip->Doorbell,
  986. ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
  987. <<MPI_DOORBELL_FUNCTION_SHIFT) |
  988. (access_control_value<<12)));
  989. /* Wait for IOC to clear Doorbell Status bit */
  990. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
  991. return -2;
  992. }else
  993. return 0;
  994. }
  995. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  996. /**
  997. * mpt_host_page_alloc - allocate system memory for the fw
  998. * @ioc: Pointer to pointer to IOC adapter
  999. * @ioc_init: Pointer to ioc init config page
  1000. *
  1001. * If we already allocated memory in past, then resend the same pointer.
  1002. * Returns 0 for success, non-zero for failure.
  1003. */
  1004. static int
  1005. mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
  1006. {
  1007. char *psge;
  1008. int flags_length;
  1009. u32 host_page_buffer_sz=0;
  1010. if(!ioc->HostPageBuffer) {
  1011. host_page_buffer_sz =
  1012. le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
  1013. if(!host_page_buffer_sz)
  1014. return 0; /* fw doesn't need any host buffers */
  1015. /* spin till we get enough memory */
  1016. while(host_page_buffer_sz > 0) {
  1017. if((ioc->HostPageBuffer = pci_alloc_consistent(
  1018. ioc->pcidev,
  1019. host_page_buffer_sz,
  1020. &ioc->HostPageBuffer_dma)) != NULL) {
  1021. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1022. "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
  1023. ioc->name, ioc->HostPageBuffer,
  1024. (u32)ioc->HostPageBuffer_dma,
  1025. host_page_buffer_sz));
  1026. ioc->alloc_total += host_page_buffer_sz;
  1027. ioc->HostPageBuffer_sz = host_page_buffer_sz;
  1028. break;
  1029. }
  1030. host_page_buffer_sz -= (4*1024);
  1031. }
  1032. }
  1033. if(!ioc->HostPageBuffer) {
  1034. printk(MYIOC_s_ERR_FMT
  1035. "Failed to alloc memory for host_page_buffer!\n",
  1036. ioc->name);
  1037. return -999;
  1038. }
  1039. psge = (char *)&ioc_init->HostPageBufferSGE;
  1040. flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
  1041. MPI_SGE_FLAGS_SYSTEM_ADDRESS |
  1042. MPI_SGE_FLAGS_32_BIT_ADDRESSING |
  1043. MPI_SGE_FLAGS_HOST_TO_IOC |
  1044. MPI_SGE_FLAGS_END_OF_BUFFER;
  1045. if (sizeof(dma_addr_t) == sizeof(u64)) {
  1046. flags_length |= MPI_SGE_FLAGS_64_BIT_ADDRESSING;
  1047. }
  1048. flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
  1049. flags_length |= ioc->HostPageBuffer_sz;
  1050. mpt_add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
  1051. ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
  1052. return 0;
  1053. }
  1054. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1055. /**
  1056. * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
  1057. * @iocid: IOC unique identifier (integer)
  1058. * @iocpp: Pointer to pointer to IOC adapter
  1059. *
  1060. * Given a unique IOC identifier, set pointer to the associated MPT
  1061. * adapter structure.
  1062. *
  1063. * Returns iocid and sets iocpp if iocid is found.
  1064. * Returns -1 if iocid is not found.
  1065. */
  1066. int
  1067. mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
  1068. {
  1069. MPT_ADAPTER *ioc;
  1070. list_for_each_entry(ioc,&ioc_list,list) {
  1071. if (ioc->id == iocid) {
  1072. *iocpp =ioc;
  1073. return iocid;
  1074. }
  1075. }
  1076. *iocpp = NULL;
  1077. return -1;
  1078. }
  1079. /**
  1080. * mpt_get_product_name - returns product string
  1081. * @vendor: pci vendor id
  1082. * @device: pci device id
  1083. * @revision: pci revision id
  1084. * @prod_name: string returned
  1085. *
  1086. * Returns product string displayed when driver loads,
  1087. * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
  1088. *
  1089. **/
  1090. static void
  1091. mpt_get_product_name(u16 vendor, u16 device, u8 revision, char *prod_name)
  1092. {
  1093. char *product_str = NULL;
  1094. if (vendor == PCI_VENDOR_ID_BROCADE) {
  1095. switch (device)
  1096. {
  1097. case MPI_MANUFACTPAGE_DEVICEID_FC949E:
  1098. switch (revision)
  1099. {
  1100. case 0x00:
  1101. product_str = "BRE040 A0";
  1102. break;
  1103. case 0x01:
  1104. product_str = "BRE040 A1";
  1105. break;
  1106. default:
  1107. product_str = "BRE040";
  1108. break;
  1109. }
  1110. break;
  1111. }
  1112. goto out;
  1113. }
  1114. switch (device)
  1115. {
  1116. case MPI_MANUFACTPAGE_DEVICEID_FC909:
  1117. product_str = "LSIFC909 B1";
  1118. break;
  1119. case MPI_MANUFACTPAGE_DEVICEID_FC919:
  1120. product_str = "LSIFC919 B0";
  1121. break;
  1122. case MPI_MANUFACTPAGE_DEVICEID_FC929:
  1123. product_str = "LSIFC929 B0";
  1124. break;
  1125. case MPI_MANUFACTPAGE_DEVICEID_FC919X:
  1126. if (revision < 0x80)
  1127. product_str = "LSIFC919X A0";
  1128. else
  1129. product_str = "LSIFC919XL A1";
  1130. break;
  1131. case MPI_MANUFACTPAGE_DEVICEID_FC929X:
  1132. if (revision < 0x80)
  1133. product_str = "LSIFC929X A0";
  1134. else
  1135. product_str = "LSIFC929XL A1";
  1136. break;
  1137. case MPI_MANUFACTPAGE_DEVICEID_FC939X:
  1138. product_str = "LSIFC939X A1";
  1139. break;
  1140. case MPI_MANUFACTPAGE_DEVICEID_FC949X:
  1141. product_str = "LSIFC949X A1";
  1142. break;
  1143. case MPI_MANUFACTPAGE_DEVICEID_FC949E:
  1144. switch (revision)
  1145. {
  1146. case 0x00:
  1147. product_str = "LSIFC949E A0";
  1148. break;
  1149. case 0x01:
  1150. product_str = "LSIFC949E A1";
  1151. break;
  1152. default:
  1153. product_str = "LSIFC949E";
  1154. break;
  1155. }
  1156. break;
  1157. case MPI_MANUFACTPAGE_DEVID_53C1030:
  1158. switch (revision)
  1159. {
  1160. case 0x00:
  1161. product_str = "LSI53C1030 A0";
  1162. break;
  1163. case 0x01:
  1164. product_str = "LSI53C1030 B0";
  1165. break;
  1166. case 0x03:
  1167. product_str = "LSI53C1030 B1";
  1168. break;
  1169. case 0x07:
  1170. product_str = "LSI53C1030 B2";
  1171. break;
  1172. case 0x08:
  1173. product_str = "LSI53C1030 C0";
  1174. break;
  1175. case 0x80:
  1176. product_str = "LSI53C1030T A0";
  1177. break;
  1178. case 0x83:
  1179. product_str = "LSI53C1030T A2";
  1180. break;
  1181. case 0x87:
  1182. product_str = "LSI53C1030T A3";
  1183. break;
  1184. case 0xc1:
  1185. product_str = "LSI53C1020A A1";
  1186. break;
  1187. default:
  1188. product_str = "LSI53C1030";
  1189. break;
  1190. }
  1191. break;
  1192. case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
  1193. switch (revision)
  1194. {
  1195. case 0x03:
  1196. product_str = "LSI53C1035 A2";
  1197. break;
  1198. case 0x04:
  1199. product_str = "LSI53C1035 B0";
  1200. break;
  1201. default:
  1202. product_str = "LSI53C1035";
  1203. break;
  1204. }
  1205. break;
  1206. case MPI_MANUFACTPAGE_DEVID_SAS1064:
  1207. switch (revision)
  1208. {
  1209. case 0x00:
  1210. product_str = "LSISAS1064 A1";
  1211. break;
  1212. case 0x01:
  1213. product_str = "LSISAS1064 A2";
  1214. break;
  1215. case 0x02:
  1216. product_str = "LSISAS1064 A3";
  1217. break;
  1218. case 0x03:
  1219. product_str = "LSISAS1064 A4";
  1220. break;
  1221. default:
  1222. product_str = "LSISAS1064";
  1223. break;
  1224. }
  1225. break;
  1226. case MPI_MANUFACTPAGE_DEVID_SAS1064E:
  1227. switch (revision)
  1228. {
  1229. case 0x00:
  1230. product_str = "LSISAS1064E A0";
  1231. break;
  1232. case 0x01:
  1233. product_str = "LSISAS1064E B0";
  1234. break;
  1235. case 0x02:
  1236. product_str = "LSISAS1064E B1";
  1237. break;
  1238. case 0x04:
  1239. product_str = "LSISAS1064E B2";
  1240. break;
  1241. case 0x08:
  1242. product_str = "LSISAS1064E B3";
  1243. break;
  1244. default:
  1245. product_str = "LSISAS1064E";
  1246. break;
  1247. }
  1248. break;
  1249. case MPI_MANUFACTPAGE_DEVID_SAS1068:
  1250. switch (revision)
  1251. {
  1252. case 0x00:
  1253. product_str = "LSISAS1068 A0";
  1254. break;
  1255. case 0x01:
  1256. product_str = "LSISAS1068 B0";
  1257. break;
  1258. case 0x02:
  1259. product_str = "LSISAS1068 B1";
  1260. break;
  1261. default:
  1262. product_str = "LSISAS1068";
  1263. break;
  1264. }
  1265. break;
  1266. case MPI_MANUFACTPAGE_DEVID_SAS1068E:
  1267. switch (revision)
  1268. {
  1269. case 0x00:
  1270. product_str = "LSISAS1068E A0";
  1271. break;
  1272. case 0x01:
  1273. product_str = "LSISAS1068E B0";
  1274. break;
  1275. case 0x02:
  1276. product_str = "LSISAS1068E B1";
  1277. break;
  1278. case 0x04:
  1279. product_str = "LSISAS1068E B2";
  1280. break;
  1281. case 0x08:
  1282. product_str = "LSISAS1068E B3";
  1283. break;
  1284. default:
  1285. product_str = "LSISAS1068E";
  1286. break;
  1287. }
  1288. break;
  1289. case MPI_MANUFACTPAGE_DEVID_SAS1078:
  1290. switch (revision)
  1291. {
  1292. case 0x00:
  1293. product_str = "LSISAS1078 A0";
  1294. break;
  1295. case 0x01:
  1296. product_str = "LSISAS1078 B0";
  1297. break;
  1298. case 0x02:
  1299. product_str = "LSISAS1078 C0";
  1300. break;
  1301. case 0x03:
  1302. product_str = "LSISAS1078 C1";
  1303. break;
  1304. case 0x04:
  1305. product_str = "LSISAS1078 C2";
  1306. break;
  1307. default:
  1308. product_str = "LSISAS1078";
  1309. break;
  1310. }
  1311. break;
  1312. }
  1313. out:
  1314. if (product_str)
  1315. sprintf(prod_name, "%s", product_str);
  1316. }
  1317. /**
  1318. * mpt_mapresources - map in memory mapped io
  1319. * @ioc: Pointer to pointer to IOC adapter
  1320. *
  1321. **/
  1322. static int
  1323. mpt_mapresources(MPT_ADAPTER *ioc)
  1324. {
  1325. u8 __iomem *mem;
  1326. int ii;
  1327. unsigned long mem_phys;
  1328. unsigned long port;
  1329. u32 msize;
  1330. u32 psize;
  1331. u8 revision;
  1332. int r = -ENODEV;
  1333. struct pci_dev *pdev;
  1334. pdev = ioc->pcidev;
  1335. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1336. if (pci_enable_device_mem(pdev)) {
  1337. printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
  1338. "failed\n", ioc->name);
  1339. return r;
  1340. }
  1341. if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
  1342. printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
  1343. "MEM failed\n", ioc->name);
  1344. return r;
  1345. }
  1346. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
  1347. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
  1348. && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
  1349. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  1350. ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
  1351. ioc->name));
  1352. } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)
  1353. && !pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
  1354. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  1355. ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
  1356. ioc->name));
  1357. } else {
  1358. printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
  1359. ioc->name, pci_name(pdev));
  1360. pci_release_selected_regions(pdev, ioc->bars);
  1361. return r;
  1362. }
  1363. mem_phys = msize = 0;
  1364. port = psize = 0;
  1365. for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
  1366. if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
  1367. if (psize)
  1368. continue;
  1369. /* Get I/O space! */
  1370. port = pci_resource_start(pdev, ii);
  1371. psize = pci_resource_len(pdev, ii);
  1372. } else {
  1373. if (msize)
  1374. continue;
  1375. /* Get memmap */
  1376. mem_phys = pci_resource_start(pdev, ii);
  1377. msize = pci_resource_len(pdev, ii);
  1378. }
  1379. }
  1380. ioc->mem_size = msize;
  1381. mem = NULL;
  1382. /* Get logical ptr for PciMem0 space */
  1383. /*mem = ioremap(mem_phys, msize);*/
  1384. mem = ioremap(mem_phys, msize);
  1385. if (mem == NULL) {
  1386. printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
  1387. " memory!\n", ioc->name);
  1388. return -EINVAL;
  1389. }
  1390. ioc->memmap = mem;
  1391. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %lx\n",
  1392. ioc->name, mem, mem_phys));
  1393. ioc->mem_phys = mem_phys;
  1394. ioc->chip = (SYSIF_REGS __iomem *)mem;
  1395. /* Save Port IO values in case we need to do downloadboot */
  1396. ioc->pio_mem_phys = port;
  1397. ioc->pio_chip = (SYSIF_REGS __iomem *)port;
  1398. return 0;
  1399. }
  1400. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1401. /**
  1402. * mpt_attach - Install a PCI intelligent MPT adapter.
  1403. * @pdev: Pointer to pci_dev structure
  1404. * @id: PCI device ID information
  1405. *
  1406. * This routine performs all the steps necessary to bring the IOC of
  1407. * a MPT adapter to a OPERATIONAL state. This includes registering
  1408. * memory regions, registering the interrupt, and allocating request
  1409. * and reply memory pools.
  1410. *
  1411. * This routine also pre-fetches the LAN MAC address of a Fibre Channel
  1412. * MPT adapter.
  1413. *
  1414. * Returns 0 for success, non-zero for failure.
  1415. *
  1416. * TODO: Add support for polled controllers
  1417. */
  1418. int
  1419. mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
  1420. {
  1421. MPT_ADAPTER *ioc;
  1422. u8 cb_idx;
  1423. int r = -ENODEV;
  1424. u8 revision;
  1425. u8 pcixcmd;
  1426. static int mpt_ids = 0;
  1427. #ifdef CONFIG_PROC_FS
  1428. struct proc_dir_entry *dent, *ent;
  1429. #endif
  1430. ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_ATOMIC);
  1431. if (ioc == NULL) {
  1432. printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
  1433. return -ENOMEM;
  1434. }
  1435. ioc->id = mpt_ids++;
  1436. sprintf(ioc->name, "ioc%d", ioc->id);
  1437. /*
  1438. * set initial debug level
  1439. * (refer to mptdebug.h)
  1440. *
  1441. */
  1442. ioc->debug_level = mpt_debug_level;
  1443. if (mpt_debug_level)
  1444. printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
  1445. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
  1446. ioc->pcidev = pdev;
  1447. if (mpt_mapresources(ioc)) {
  1448. kfree(ioc);
  1449. return r;
  1450. }
  1451. ioc->alloc_total = sizeof(MPT_ADAPTER);
  1452. ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
  1453. ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
  1454. ioc->pcidev = pdev;
  1455. ioc->diagPending = 0;
  1456. spin_lock_init(&ioc->diagLock);
  1457. spin_lock_init(&ioc->initializing_hba_lock);
  1458. /* Initialize the event logging.
  1459. */
  1460. ioc->eventTypes = 0; /* None */
  1461. ioc->eventContext = 0;
  1462. ioc->eventLogSize = 0;
  1463. ioc->events = NULL;
  1464. #ifdef MFCNT
  1465. ioc->mfcnt = 0;
  1466. #endif
  1467. ioc->cached_fw = NULL;
  1468. /* Initilize SCSI Config Data structure
  1469. */
  1470. memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
  1471. /* Initialize the running configQ head.
  1472. */
  1473. INIT_LIST_HEAD(&ioc->configQ);
  1474. /* Initialize the fc rport list head.
  1475. */
  1476. INIT_LIST_HEAD(&ioc->fc_rports);
  1477. /* Find lookup slot. */
  1478. INIT_LIST_HEAD(&ioc->list);
  1479. /* Initialize workqueue */
  1480. INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
  1481. spin_lock_init(&ioc->fault_reset_work_lock);
  1482. snprintf(ioc->reset_work_q_name, sizeof(ioc->reset_work_q_name),
  1483. "mpt_poll_%d", ioc->id);
  1484. ioc->reset_work_q =
  1485. create_singlethread_workqueue(ioc->reset_work_q_name);
  1486. if (!ioc->reset_work_q) {
  1487. printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
  1488. ioc->name);
  1489. pci_release_selected_regions(pdev, ioc->bars);
  1490. kfree(ioc);
  1491. return -ENOMEM;
  1492. }
  1493. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
  1494. ioc->name, &ioc->facts, &ioc->pfacts[0]));
  1495. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
  1496. mpt_get_product_name(pdev->vendor, pdev->device, revision, ioc->prod_name);
  1497. switch (pdev->device)
  1498. {
  1499. case MPI_MANUFACTPAGE_DEVICEID_FC939X:
  1500. case MPI_MANUFACTPAGE_DEVICEID_FC949X:
  1501. ioc->errata_flag_1064 = 1;
  1502. case MPI_MANUFACTPAGE_DEVICEID_FC909:
  1503. case MPI_MANUFACTPAGE_DEVICEID_FC929:
  1504. case MPI_MANUFACTPAGE_DEVICEID_FC919:
  1505. case MPI_MANUFACTPAGE_DEVICEID_FC949E:
  1506. ioc->bus_type = FC;
  1507. break;
  1508. case MPI_MANUFACTPAGE_DEVICEID_FC929X:
  1509. if (revision < XL_929) {
  1510. /* 929X Chip Fix. Set Split transactions level
  1511. * for PCIX. Set MOST bits to zero.
  1512. */
  1513. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1514. pcixcmd &= 0x8F;
  1515. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1516. } else {
  1517. /* 929XL Chip Fix. Set MMRBC to 0x08.
  1518. */
  1519. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1520. pcixcmd |= 0x08;
  1521. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1522. }
  1523. ioc->bus_type = FC;
  1524. break;
  1525. case MPI_MANUFACTPAGE_DEVICEID_FC919X:
  1526. /* 919X Chip Fix. Set Split transactions level
  1527. * for PCIX. Set MOST bits to zero.
  1528. */
  1529. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1530. pcixcmd &= 0x8F;
  1531. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1532. ioc->bus_type = FC;
  1533. break;
  1534. case MPI_MANUFACTPAGE_DEVID_53C1030:
  1535. /* 1030 Chip Fix. Disable Split transactions
  1536. * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
  1537. */
  1538. if (revision < C0_1030) {
  1539. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1540. pcixcmd &= 0x8F;
  1541. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1542. }
  1543. case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
  1544. ioc->bus_type = SPI;
  1545. break;
  1546. case MPI_MANUFACTPAGE_DEVID_SAS1064:
  1547. case MPI_MANUFACTPAGE_DEVID_SAS1068:
  1548. ioc->errata_flag_1064 = 1;
  1549. case MPI_MANUFACTPAGE_DEVID_SAS1064E:
  1550. case MPI_MANUFACTPAGE_DEVID_SAS1068E:
  1551. case MPI_MANUFACTPAGE_DEVID_SAS1078:
  1552. ioc->bus_type = SAS;
  1553. }
  1554. if (mpt_msi_enable == -1) {
  1555. /* Enable on SAS, disable on FC and SPI */
  1556. if (ioc->bus_type == SAS)
  1557. ioc->msi_enable = 1;
  1558. else
  1559. ioc->msi_enable = 0;
  1560. } else
  1561. /* follow flag: 0 - disable; 1 - enable */
  1562. ioc->msi_enable = mpt_msi_enable;
  1563. if (ioc->errata_flag_1064)
  1564. pci_disable_io_access(pdev);
  1565. spin_lock_init(&ioc->FreeQlock);
  1566. /* Disable all! */
  1567. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1568. ioc->active = 0;
  1569. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1570. /* Set IOC ptr in the pcidev's driver data. */
  1571. pci_set_drvdata(ioc->pcidev, ioc);
  1572. /* Set lookup ptr. */
  1573. list_add_tail(&ioc->list, &ioc_list);
  1574. /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
  1575. */
  1576. mpt_detect_bound_ports(ioc, pdev);
  1577. if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
  1578. CAN_SLEEP)) != 0){
  1579. printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
  1580. ioc->name, r);
  1581. list_del(&ioc->list);
  1582. if (ioc->alt_ioc)
  1583. ioc->alt_ioc->alt_ioc = NULL;
  1584. iounmap(ioc->memmap);
  1585. if (r != -5)
  1586. pci_release_selected_regions(pdev, ioc->bars);
  1587. destroy_workqueue(ioc->reset_work_q);
  1588. ioc->reset_work_q = NULL;
  1589. kfree(ioc);
  1590. pci_set_drvdata(pdev, NULL);
  1591. return r;
  1592. }
  1593. /* call per device driver probe entry point */
  1594. for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
  1595. if(MptDeviceDriverHandlers[cb_idx] &&
  1596. MptDeviceDriverHandlers[cb_idx]->probe) {
  1597. MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
  1598. }
  1599. }
  1600. #ifdef CONFIG_PROC_FS
  1601. /*
  1602. * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
  1603. */
  1604. dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
  1605. if (dent) {
  1606. ent = create_proc_entry("info", S_IFREG|S_IRUGO, dent);
  1607. if (ent) {
  1608. ent->read_proc = procmpt_iocinfo_read;
  1609. ent->data = ioc;
  1610. }
  1611. ent = create_proc_entry("summary", S_IFREG|S_IRUGO, dent);
  1612. if (ent) {
  1613. ent->read_proc = procmpt_summary_read;
  1614. ent->data = ioc;
  1615. }
  1616. }
  1617. #endif
  1618. if (!ioc->alt_ioc)
  1619. queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
  1620. msecs_to_jiffies(MPT_POLLING_INTERVAL));
  1621. return 0;
  1622. }
  1623. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1624. /**
  1625. * mpt_detach - Remove a PCI intelligent MPT adapter.
  1626. * @pdev: Pointer to pci_dev structure
  1627. */
  1628. void
  1629. mpt_detach(struct pci_dev *pdev)
  1630. {
  1631. MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
  1632. char pname[32];
  1633. u8 cb_idx;
  1634. unsigned long flags;
  1635. struct workqueue_struct *wq;
  1636. /*
  1637. * Stop polling ioc for fault condition
  1638. */
  1639. spin_lock_irqsave(&ioc->fault_reset_work_lock, flags);
  1640. wq = ioc->reset_work_q;
  1641. ioc->reset_work_q = NULL;
  1642. spin_unlock_irqrestore(&ioc->fault_reset_work_lock, flags);
  1643. cancel_delayed_work(&ioc->fault_reset_work);
  1644. destroy_workqueue(wq);
  1645. sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
  1646. remove_proc_entry(pname, NULL);
  1647. sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
  1648. remove_proc_entry(pname, NULL);
  1649. sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
  1650. remove_proc_entry(pname, NULL);
  1651. /* call per device driver remove entry point */
  1652. for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
  1653. if(MptDeviceDriverHandlers[cb_idx] &&
  1654. MptDeviceDriverHandlers[cb_idx]->remove) {
  1655. MptDeviceDriverHandlers[cb_idx]->remove(pdev);
  1656. }
  1657. }
  1658. /* Disable interrupts! */
  1659. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1660. ioc->active = 0;
  1661. synchronize_irq(pdev->irq);
  1662. /* Clear any lingering interrupt */
  1663. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1664. CHIPREG_READ32(&ioc->chip->IntStatus);
  1665. mpt_adapter_dispose(ioc);
  1666. pci_set_drvdata(pdev, NULL);
  1667. }
  1668. /**************************************************************************
  1669. * Power Management
  1670. */
  1671. #ifdef CONFIG_PM
  1672. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1673. /**
  1674. * mpt_suspend - Fusion MPT base driver suspend routine.
  1675. * @pdev: Pointer to pci_dev structure
  1676. * @state: new state to enter
  1677. */
  1678. int
  1679. mpt_suspend(struct pci_dev *pdev, pm_message_t state)
  1680. {
  1681. u32 device_state;
  1682. MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
  1683. device_state = pci_choose_state(pdev, state);
  1684. printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
  1685. "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
  1686. device_state);
  1687. /* put ioc into READY_STATE */
  1688. if(SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
  1689. printk(MYIOC_s_ERR_FMT
  1690. "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
  1691. }
  1692. /* disable interrupts */
  1693. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1694. ioc->active = 0;
  1695. /* Clear any lingering interrupt */
  1696. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1697. free_irq(ioc->pci_irq, ioc);
  1698. if (ioc->msi_enable)
  1699. pci_disable_msi(ioc->pcidev);
  1700. ioc->pci_irq = -1;
  1701. pci_save_state(pdev);
  1702. pci_disable_device(pdev);
  1703. pci_release_selected_regions(pdev, ioc->bars);
  1704. pci_set_power_state(pdev, device_state);
  1705. return 0;
  1706. }
  1707. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1708. /**
  1709. * mpt_resume - Fusion MPT base driver resume routine.
  1710. * @pdev: Pointer to pci_dev structure
  1711. */
  1712. int
  1713. mpt_resume(struct pci_dev *pdev)
  1714. {
  1715. MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
  1716. u32 device_state = pdev->current_state;
  1717. int recovery_state;
  1718. int err;
  1719. printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
  1720. "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
  1721. device_state);
  1722. pci_set_power_state(pdev, PCI_D0);
  1723. pci_enable_wake(pdev, PCI_D0, 0);
  1724. pci_restore_state(pdev);
  1725. ioc->pcidev = pdev;
  1726. err = mpt_mapresources(ioc);
  1727. if (err)
  1728. return err;
  1729. printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
  1730. ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
  1731. CHIPREG_READ32(&ioc->chip->Doorbell));
  1732. /*
  1733. * Errata workaround for SAS pci express:
  1734. * Upon returning to the D0 state, the contents of the doorbell will be
  1735. * stale data, and this will incorrectly signal to the host driver that
  1736. * the firmware is ready to process mpt commands. The workaround is
  1737. * to issue a diagnostic reset.
  1738. */
  1739. if (ioc->bus_type == SAS && (pdev->device ==
  1740. MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
  1741. MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
  1742. if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
  1743. printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
  1744. ioc->name);
  1745. goto out;
  1746. }
  1747. }
  1748. /* bring ioc to operational state */
  1749. printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
  1750. recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
  1751. CAN_SLEEP);
  1752. if (recovery_state != 0)
  1753. printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
  1754. "error:[%x]\n", ioc->name, recovery_state);
  1755. else
  1756. printk(MYIOC_s_INFO_FMT
  1757. "pci-resume: success\n", ioc->name);
  1758. out:
  1759. return 0;
  1760. }
  1761. #endif
  1762. static int
  1763. mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
  1764. {
  1765. if ((MptDriverClass[index] == MPTSPI_DRIVER &&
  1766. ioc->bus_type != SPI) ||
  1767. (MptDriverClass[index] == MPTFC_DRIVER &&
  1768. ioc->bus_type != FC) ||
  1769. (MptDriverClass[index] == MPTSAS_DRIVER &&
  1770. ioc->bus_type != SAS))
  1771. /* make sure we only call the relevant reset handler
  1772. * for the bus */
  1773. return 0;
  1774. return (MptResetHandlers[index])(ioc, reset_phase);
  1775. }
  1776. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1777. /**
  1778. * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
  1779. * @ioc: Pointer to MPT adapter structure
  1780. * @reason: Event word / reason
  1781. * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
  1782. *
  1783. * This routine performs all the steps necessary to bring the IOC
  1784. * to a OPERATIONAL state.
  1785. *
  1786. * This routine also pre-fetches the LAN MAC address of a Fibre Channel
  1787. * MPT adapter.
  1788. *
  1789. * Returns:
  1790. * 0 for success
  1791. * -1 if failed to get board READY
  1792. * -2 if READY but IOCFacts Failed
  1793. * -3 if READY but PrimeIOCFifos Failed
  1794. * -4 if READY but IOCInit Failed
  1795. * -5 if failed to enable_device and/or request_selected_regions
  1796. * -6 if failed to upload firmware
  1797. */
  1798. static int
  1799. mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
  1800. {
  1801. int hard_reset_done = 0;
  1802. int alt_ioc_ready = 0;
  1803. int hard;
  1804. int rc=0;
  1805. int ii;
  1806. u8 cb_idx;
  1807. int handlers;
  1808. int ret = 0;
  1809. int reset_alt_ioc_active = 0;
  1810. int irq_allocated = 0;
  1811. u8 *a;
  1812. printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
  1813. reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
  1814. /* Disable reply interrupts (also blocks FreeQ) */
  1815. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1816. ioc->active = 0;
  1817. if (ioc->alt_ioc) {
  1818. if (ioc->alt_ioc->active)
  1819. reset_alt_ioc_active = 1;
  1820. /* Disable alt-IOC's reply interrupts (and FreeQ) for a bit ... */
  1821. CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 0xFFFFFFFF);
  1822. ioc->alt_ioc->active = 0;
  1823. }
  1824. hard = 1;
  1825. if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
  1826. hard = 0;
  1827. if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
  1828. if (hard_reset_done == -4) {
  1829. printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
  1830. ioc->name);
  1831. if (reset_alt_ioc_active && ioc->alt_ioc) {
  1832. /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
  1833. dprintk(ioc, printk(MYIOC_s_INFO_FMT
  1834. "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
  1835. CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
  1836. ioc->alt_ioc->active = 1;
  1837. }
  1838. } else {
  1839. printk(MYIOC_s_WARN_FMT "NOT READY!\n", ioc->name);
  1840. }
  1841. return -1;
  1842. }
  1843. /* hard_reset_done = 0 if a soft reset was performed
  1844. * and 1 if a hard reset was performed.
  1845. */
  1846. if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
  1847. if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
  1848. alt_ioc_ready = 1;
  1849. else
  1850. printk(MYIOC_s_WARN_FMT "alt_ioc not ready!\n", ioc->alt_ioc->name);
  1851. }
  1852. for (ii=0; ii<5; ii++) {
  1853. /* Get IOC facts! Allow 5 retries */
  1854. if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
  1855. break;
  1856. }
  1857. if (ii == 5) {
  1858. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1859. "Retry IocFacts failed rc=%x\n", ioc->name, rc));
  1860. ret = -2;
  1861. } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  1862. MptDisplayIocCapabilities(ioc);
  1863. }
  1864. if (alt_ioc_ready) {
  1865. if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
  1866. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1867. "Initial Alt IocFacts failed rc=%x\n", ioc->name, rc));
  1868. /* Retry - alt IOC was initialized once
  1869. */
  1870. rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
  1871. }
  1872. if (rc) {
  1873. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1874. "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
  1875. alt_ioc_ready = 0;
  1876. reset_alt_ioc_active = 0;
  1877. } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  1878. MptDisplayIocCapabilities(ioc->alt_ioc);
  1879. }
  1880. }
  1881. if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
  1882. (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
  1883. pci_release_selected_regions(ioc->pcidev, ioc->bars);
  1884. ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
  1885. IORESOURCE_IO);
  1886. if (pci_enable_device(ioc->pcidev))
  1887. return -5;
  1888. if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
  1889. "mpt"))
  1890. return -5;
  1891. }
  1892. /*
  1893. * Device is reset now. It must have de-asserted the interrupt line
  1894. * (if it was asserted) and it should be safe to register for the
  1895. * interrupt now.
  1896. */
  1897. if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
  1898. ioc->pci_irq = -1;
  1899. if (ioc->pcidev->irq) {
  1900. if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
  1901. printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
  1902. ioc->name);
  1903. else
  1904. ioc->msi_enable = 0;
  1905. rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
  1906. IRQF_SHARED, ioc->name, ioc);
  1907. if (rc < 0) {
  1908. printk(MYIOC_s_ERR_FMT "Unable to allocate "
  1909. "interrupt %d!\n", ioc->name, ioc->pcidev->irq);
  1910. if (ioc->msi_enable)
  1911. pci_disable_msi(ioc->pcidev);
  1912. return -EBUSY;
  1913. }
  1914. irq_allocated = 1;
  1915. ioc->pci_irq = ioc->pcidev->irq;
  1916. pci_set_master(ioc->pcidev); /* ?? */
  1917. dprintk(ioc, printk(MYIOC_s_INFO_FMT "installed at interrupt "
  1918. "%d\n", ioc->name, ioc->pcidev->irq));
  1919. }
  1920. }
  1921. /* Prime reply & request queues!
  1922. * (mucho alloc's) Must be done prior to
  1923. * init as upper addresses are needed for init.
  1924. * If fails, continue with alt-ioc processing
  1925. */
  1926. if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
  1927. ret = -3;
  1928. /* May need to check/upload firmware & data here!
  1929. * If fails, continue with alt-ioc processing
  1930. */
  1931. if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
  1932. ret = -4;
  1933. // NEW!
  1934. if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
  1935. printk(MYIOC_s_WARN_FMT ": alt_ioc (%d) FIFO mgmt alloc!\n",
  1936. ioc->alt_ioc->name, rc);
  1937. alt_ioc_ready = 0;
  1938. reset_alt_ioc_active = 0;
  1939. }
  1940. if (alt_ioc_ready) {
  1941. if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
  1942. alt_ioc_ready = 0;
  1943. reset_alt_ioc_active = 0;
  1944. printk(MYIOC_s_WARN_FMT "alt_ioc (%d) init failure!\n",
  1945. ioc->alt_ioc->name, rc);
  1946. }
  1947. }
  1948. if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
  1949. if (ioc->upload_fw) {
  1950. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1951. "firmware upload required!\n", ioc->name));
  1952. /* Controller is not operational, cannot do upload
  1953. */
  1954. if (ret == 0) {
  1955. rc = mpt_do_upload(ioc, sleepFlag);
  1956. if (rc == 0) {
  1957. if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
  1958. /*
  1959. * Maintain only one pointer to FW memory
  1960. * so there will not be two attempt to
  1961. * downloadboot onboard dual function
  1962. * chips (mpt_adapter_disable,
  1963. * mpt_diag_reset)
  1964. */
  1965. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1966. "mpt_upload: alt_%s has cached_fw=%p \n",
  1967. ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
  1968. ioc->cached_fw = NULL;
  1969. }
  1970. } else {
  1971. printk(MYIOC_s_WARN_FMT
  1972. "firmware upload failure!\n", ioc->name);
  1973. ret = -6;
  1974. }
  1975. }
  1976. }
  1977. }
  1978. if (ret == 0) {
  1979. /* Enable! (reply interrupt) */
  1980. CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
  1981. ioc->active = 1;
  1982. }
  1983. if (reset_alt_ioc_active && ioc->alt_ioc) {
  1984. /* (re)Enable alt-IOC! (reply interrupt) */
  1985. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "alt_ioc reply irq re-enabled\n",
  1986. ioc->alt_ioc->name));
  1987. CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
  1988. ioc->alt_ioc->active = 1;
  1989. }
  1990. /* Enable MPT base driver management of EventNotification
  1991. * and EventAck handling.
  1992. */
  1993. if ((ret == 0) && (!ioc->facts.EventState))
  1994. (void) SendEventNotification(ioc, 1); /* 1=Enable EventNotification */
  1995. if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
  1996. (void) SendEventNotification(ioc->alt_ioc, 1); /* 1=Enable EventNotification */
  1997. /* Add additional "reason" check before call to GetLanConfigPages
  1998. * (combined with GetIoUnitPage2 call). This prevents a somewhat
  1999. * recursive scenario; GetLanConfigPages times out, timer expired
  2000. * routine calls HardResetHandler, which calls into here again,
  2001. * and we try GetLanConfigPages again...
  2002. */
  2003. if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
  2004. /*
  2005. * Initalize link list for inactive raid volumes.
  2006. */
  2007. mutex_init(&ioc->raid_data.inactive_list_mutex);
  2008. INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
  2009. if (ioc->bus_type == SAS) {
  2010. /* clear persistency table */
  2011. if(ioc->facts.IOCExceptions &
  2012. MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
  2013. ret = mptbase_sas_persist_operation(ioc,
  2014. MPI_SAS_OP_CLEAR_NOT_PRESENT);
  2015. if(ret != 0)
  2016. goto out;
  2017. }
  2018. /* Find IM volumes
  2019. */
  2020. mpt_findImVolumes(ioc);
  2021. } else if (ioc->bus_type == FC) {
  2022. if ((ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) &&
  2023. (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
  2024. /*
  2025. * Pre-fetch the ports LAN MAC address!
  2026. * (LANPage1_t stuff)
  2027. */
  2028. (void) GetLanConfigPages(ioc);
  2029. a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  2030. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2031. "LanAddr = %02X:%02X:%02X:%02X:%02X:%02X\n",
  2032. ioc->name, a[5], a[4], a[3], a[2], a[1], a[0]));
  2033. }
  2034. } else {
  2035. /* Get NVRAM and adapter maximums from SPP 0 and 2
  2036. */
  2037. mpt_GetScsiPortSettings(ioc, 0);
  2038. /* Get version and length of SDP 1
  2039. */
  2040. mpt_readScsiDevicePageHeaders(ioc, 0);
  2041. /* Find IM volumes
  2042. */
  2043. if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
  2044. mpt_findImVolumes(ioc);
  2045. /* Check, and possibly reset, the coalescing value
  2046. */
  2047. mpt_read_ioc_pg_1(ioc);
  2048. mpt_read_ioc_pg_4(ioc);
  2049. }
  2050. GetIoUnitPage2(ioc);
  2051. mpt_get_manufacturing_pg_0(ioc);
  2052. }
  2053. /*
  2054. * Call each currently registered protocol IOC reset handler
  2055. * with post-reset indication.
  2056. * NOTE: If we're doing _IOC_BRINGUP, there can be no
  2057. * MptResetHandlers[] registered yet.
  2058. */
  2059. if (hard_reset_done) {
  2060. rc = handlers = 0;
  2061. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  2062. if ((ret == 0) && MptResetHandlers[cb_idx]) {
  2063. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2064. "Calling IOC post_reset handler #%d\n",
  2065. ioc->name, cb_idx));
  2066. rc += mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
  2067. handlers++;
  2068. }
  2069. if (alt_ioc_ready && MptResetHandlers[cb_idx]) {
  2070. drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2071. "Calling IOC post_reset handler #%d\n",
  2072. ioc->alt_ioc->name, cb_idx));
  2073. rc += mpt_signal_reset(cb_idx, ioc->alt_ioc, MPT_IOC_POST_RESET);
  2074. handlers++;
  2075. }
  2076. }
  2077. /* FIXME? Examine results here? */
  2078. }
  2079. out:
  2080. if ((ret != 0) && irq_allocated) {
  2081. free_irq(ioc->pci_irq, ioc);
  2082. if (ioc->msi_enable)
  2083. pci_disable_msi(ioc->pcidev);
  2084. }
  2085. return ret;
  2086. }
  2087. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2088. /**
  2089. * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
  2090. * @ioc: Pointer to MPT adapter structure
  2091. * @pdev: Pointer to (struct pci_dev) structure
  2092. *
  2093. * Search for PCI bus/dev_function which matches
  2094. * PCI bus/dev_function (+/-1) for newly discovered 929,
  2095. * 929X, 1030 or 1035.
  2096. *
  2097. * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
  2098. * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
  2099. */
  2100. static void
  2101. mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
  2102. {
  2103. struct pci_dev *peer=NULL;
  2104. unsigned int slot = PCI_SLOT(pdev->devfn);
  2105. unsigned int func = PCI_FUNC(pdev->devfn);
  2106. MPT_ADAPTER *ioc_srch;
  2107. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
  2108. " searching for devfn match on %x or %x\n",
  2109. ioc->name, pci_name(pdev), pdev->bus->number,
  2110. pdev->devfn, func-1, func+1));
  2111. peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
  2112. if (!peer) {
  2113. peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
  2114. if (!peer)
  2115. return;
  2116. }
  2117. list_for_each_entry(ioc_srch, &ioc_list, list) {
  2118. struct pci_dev *_pcidev = ioc_srch->pcidev;
  2119. if (_pcidev == peer) {
  2120. /* Paranoia checks */
  2121. if (ioc->alt_ioc != NULL) {
  2122. printk(MYIOC_s_WARN_FMT "Oops, already bound to %s!\n",
  2123. ioc->name, ioc->alt_ioc->name);
  2124. break;
  2125. } else if (ioc_srch->alt_ioc != NULL) {
  2126. printk(MYIOC_s_WARN_FMT "Oops, already bound to %s!\n",
  2127. ioc_srch->name, ioc_srch->alt_ioc->name);
  2128. break;
  2129. }
  2130. dprintk(ioc, printk(MYIOC_s_INFO_FMT "FOUND! binding to %s\n",
  2131. ioc->name, ioc_srch->name));
  2132. ioc_srch->alt_ioc = ioc;
  2133. ioc->alt_ioc = ioc_srch;
  2134. }
  2135. }
  2136. pci_dev_put(peer);
  2137. }
  2138. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2139. /**
  2140. * mpt_adapter_disable - Disable misbehaving MPT adapter.
  2141. * @ioc: Pointer to MPT adapter structure
  2142. */
  2143. static void
  2144. mpt_adapter_disable(MPT_ADAPTER *ioc)
  2145. {
  2146. int sz;
  2147. int ret;
  2148. if (ioc->cached_fw != NULL) {
  2149. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: Pushing FW onto "
  2150. "adapter\n", __func__, ioc->name));
  2151. if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
  2152. ioc->cached_fw, CAN_SLEEP)) < 0) {
  2153. printk(MYIOC_s_WARN_FMT
  2154. ": firmware downloadboot failure (%d)!\n",
  2155. ioc->name, ret);
  2156. }
  2157. }
  2158. /* Disable adapter interrupts! */
  2159. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  2160. ioc->active = 0;
  2161. /* Clear any lingering interrupt */
  2162. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  2163. if (ioc->alloc != NULL) {
  2164. sz = ioc->alloc_sz;
  2165. dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
  2166. ioc->name, ioc->alloc, ioc->alloc_sz));
  2167. pci_free_consistent(ioc->pcidev, sz,
  2168. ioc->alloc, ioc->alloc_dma);
  2169. ioc->reply_frames = NULL;
  2170. ioc->req_frames = NULL;
  2171. ioc->alloc = NULL;
  2172. ioc->alloc_total -= sz;
  2173. }
  2174. if (ioc->sense_buf_pool != NULL) {
  2175. sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
  2176. pci_free_consistent(ioc->pcidev, sz,
  2177. ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
  2178. ioc->sense_buf_pool = NULL;
  2179. ioc->alloc_total -= sz;
  2180. }
  2181. if (ioc->events != NULL){
  2182. sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
  2183. kfree(ioc->events);
  2184. ioc->events = NULL;
  2185. ioc->alloc_total -= sz;
  2186. }
  2187. mpt_free_fw_memory(ioc);
  2188. kfree(ioc->spi_data.nvram);
  2189. mpt_inactive_raid_list_free(ioc);
  2190. kfree(ioc->raid_data.pIocPg2);
  2191. kfree(ioc->raid_data.pIocPg3);
  2192. ioc->spi_data.nvram = NULL;
  2193. ioc->raid_data.pIocPg3 = NULL;
  2194. if (ioc->spi_data.pIocPg4 != NULL) {
  2195. sz = ioc->spi_data.IocPg4Sz;
  2196. pci_free_consistent(ioc->pcidev, sz,
  2197. ioc->spi_data.pIocPg4,
  2198. ioc->spi_data.IocPg4_dma);
  2199. ioc->spi_data.pIocPg4 = NULL;
  2200. ioc->alloc_total -= sz;
  2201. }
  2202. if (ioc->ReqToChain != NULL) {
  2203. kfree(ioc->ReqToChain);
  2204. kfree(ioc->RequestNB);
  2205. ioc->ReqToChain = NULL;
  2206. }
  2207. kfree(ioc->ChainToChain);
  2208. ioc->ChainToChain = NULL;
  2209. if (ioc->HostPageBuffer != NULL) {
  2210. if((ret = mpt_host_page_access_control(ioc,
  2211. MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
  2212. printk(MYIOC_s_ERR_FMT
  2213. "host page buffers free failed (%d)!\n",
  2214. ioc->name, ret);
  2215. }
  2216. dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "HostPageBuffer free @ %p, sz=%d bytes\n",
  2217. ioc->name, ioc->HostPageBuffer, ioc->HostPageBuffer_sz));
  2218. pci_free_consistent(ioc->pcidev, ioc->HostPageBuffer_sz,
  2219. ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
  2220. ioc->HostPageBuffer = NULL;
  2221. ioc->HostPageBuffer_sz = 0;
  2222. ioc->alloc_total -= ioc->HostPageBuffer_sz;
  2223. }
  2224. }
  2225. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2226. /**
  2227. * mpt_adapter_dispose - Free all resources associated with an MPT adapter
  2228. * @ioc: Pointer to MPT adapter structure
  2229. *
  2230. * This routine unregisters h/w resources and frees all alloc'd memory
  2231. * associated with a MPT adapter structure.
  2232. */
  2233. static void
  2234. mpt_adapter_dispose(MPT_ADAPTER *ioc)
  2235. {
  2236. int sz_first, sz_last;
  2237. if (ioc == NULL)
  2238. return;
  2239. sz_first = ioc->alloc_total;
  2240. mpt_adapter_disable(ioc);
  2241. if (ioc->pci_irq != -1) {
  2242. free_irq(ioc->pci_irq, ioc);
  2243. if (ioc->msi_enable)
  2244. pci_disable_msi(ioc->pcidev);
  2245. ioc->pci_irq = -1;
  2246. }
  2247. if (ioc->memmap != NULL) {
  2248. iounmap(ioc->memmap);
  2249. ioc->memmap = NULL;
  2250. }
  2251. pci_disable_device(ioc->pcidev);
  2252. pci_release_selected_regions(ioc->pcidev, ioc->bars);
  2253. #if defined(CONFIG_MTRR) && 0
  2254. if (ioc->mtrr_reg > 0) {
  2255. mtrr_del(ioc->mtrr_reg, 0, 0);
  2256. dprintk(ioc, printk(MYIOC_s_INFO_FMT "MTRR region de-registered\n", ioc->name));
  2257. }
  2258. #endif
  2259. /* Zap the adapter lookup ptr! */
  2260. list_del(&ioc->list);
  2261. sz_last = ioc->alloc_total;
  2262. dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
  2263. ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
  2264. if (ioc->alt_ioc)
  2265. ioc->alt_ioc->alt_ioc = NULL;
  2266. kfree(ioc);
  2267. }
  2268. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2269. /**
  2270. * MptDisplayIocCapabilities - Disply IOC's capabilities.
  2271. * @ioc: Pointer to MPT adapter structure
  2272. */
  2273. static void
  2274. MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
  2275. {
  2276. int i = 0;
  2277. printk(KERN_INFO "%s: ", ioc->name);
  2278. if (ioc->prod_name)
  2279. printk("%s: ", ioc->prod_name);
  2280. printk("Capabilities={");
  2281. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
  2282. printk("Initiator");
  2283. i++;
  2284. }
  2285. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
  2286. printk("%sTarget", i ? "," : "");
  2287. i++;
  2288. }
  2289. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
  2290. printk("%sLAN", i ? "," : "");
  2291. i++;
  2292. }
  2293. #if 0
  2294. /*
  2295. * This would probably evoke more questions than it's worth
  2296. */
  2297. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
  2298. printk("%sLogBusAddr", i ? "," : "");
  2299. i++;
  2300. }
  2301. #endif
  2302. printk("}\n");
  2303. }
  2304. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2305. /**
  2306. * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
  2307. * @ioc: Pointer to MPT_ADAPTER structure
  2308. * @force: Force hard KickStart of IOC
  2309. * @sleepFlag: Specifies whether the process can sleep
  2310. *
  2311. * Returns:
  2312. * 1 - DIAG reset and READY
  2313. * 0 - READY initially OR soft reset and READY
  2314. * -1 - Any failure on KickStart
  2315. * -2 - Msg Unit Reset Failed
  2316. * -3 - IO Unit Reset Failed
  2317. * -4 - IOC owned by a PEER
  2318. */
  2319. static int
  2320. MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
  2321. {
  2322. u32 ioc_state;
  2323. int statefault = 0;
  2324. int cntdn;
  2325. int hard_reset_done = 0;
  2326. int r;
  2327. int ii;
  2328. int whoinit;
  2329. /* Get current [raw] IOC state */
  2330. ioc_state = mpt_GetIocState(ioc, 0);
  2331. dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
  2332. /*
  2333. * Check to see if IOC got left/stuck in doorbell handshake
  2334. * grip of death. If so, hard reset the IOC.
  2335. */
  2336. if (ioc_state & MPI_DOORBELL_ACTIVE) {
  2337. statefault = 1;
  2338. printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
  2339. ioc->name);
  2340. }
  2341. /* Is it already READY? */
  2342. if (!statefault && (ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)
  2343. return 0;
  2344. /*
  2345. * Check to see if IOC is in FAULT state.
  2346. */
  2347. if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
  2348. statefault = 2;
  2349. printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
  2350. ioc->name);
  2351. printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
  2352. ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
  2353. }
  2354. /*
  2355. * Hmmm... Did it get left operational?
  2356. */
  2357. if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
  2358. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
  2359. ioc->name));
  2360. /* Check WhoInit.
  2361. * If PCI Peer, exit.
  2362. * Else, if no fault conditions are present, issue a MessageUnitReset
  2363. * Else, fall through to KickStart case
  2364. */
  2365. whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
  2366. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  2367. "whoinit 0x%x statefault %d force %d\n",
  2368. ioc->name, whoinit, statefault, force));
  2369. if (whoinit == MPI_WHOINIT_PCI_PEER)
  2370. return -4;
  2371. else {
  2372. if ((statefault == 0 ) && (force == 0)) {
  2373. if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
  2374. return 0;
  2375. }
  2376. statefault = 3;
  2377. }
  2378. }
  2379. hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
  2380. if (hard_reset_done < 0)
  2381. return -1;
  2382. /*
  2383. * Loop here waiting for IOC to come READY.
  2384. */
  2385. ii = 0;
  2386. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
  2387. while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
  2388. if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
  2389. /*
  2390. * BIOS or previous driver load left IOC in OP state.
  2391. * Reset messaging FIFOs.
  2392. */
  2393. if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
  2394. printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
  2395. return -2;
  2396. }
  2397. } else if (ioc_state == MPI_IOC_STATE_RESET) {
  2398. /*
  2399. * Something is wrong. Try to get IOC back
  2400. * to a known state.
  2401. */
  2402. if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
  2403. printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
  2404. return -3;
  2405. }
  2406. }
  2407. ii++; cntdn--;
  2408. if (!cntdn) {
  2409. printk(MYIOC_s_ERR_FMT "Wait IOC_READY state timeout(%d)!\n",
  2410. ioc->name, (int)((ii+5)/HZ));
  2411. return -ETIME;
  2412. }
  2413. if (sleepFlag == CAN_SLEEP) {
  2414. msleep(1);
  2415. } else {
  2416. mdelay (1); /* 1 msec delay */
  2417. }
  2418. }
  2419. if (statefault < 3) {
  2420. printk(MYIOC_s_INFO_FMT "Recovered from %s\n",
  2421. ioc->name,
  2422. statefault==1 ? "stuck handshake" : "IOC FAULT");
  2423. }
  2424. return hard_reset_done;
  2425. }
  2426. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2427. /**
  2428. * mpt_GetIocState - Get the current state of a MPT adapter.
  2429. * @ioc: Pointer to MPT_ADAPTER structure
  2430. * @cooked: Request raw or cooked IOC state
  2431. *
  2432. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2433. * Doorbell bits in MPI_IOC_STATE_MASK.
  2434. */
  2435. u32
  2436. mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
  2437. {
  2438. u32 s, sc;
  2439. /* Get! */
  2440. s = CHIPREG_READ32(&ioc->chip->Doorbell);
  2441. sc = s & MPI_IOC_STATE_MASK;
  2442. /* Save! */
  2443. ioc->last_state = sc;
  2444. return cooked ? sc : s;
  2445. }
  2446. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2447. /**
  2448. * GetIocFacts - Send IOCFacts request to MPT adapter.
  2449. * @ioc: Pointer to MPT_ADAPTER structure
  2450. * @sleepFlag: Specifies whether the process can sleep
  2451. * @reason: If recovery, only update facts.
  2452. *
  2453. * Returns 0 for success, non-zero for failure.
  2454. */
  2455. static int
  2456. GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
  2457. {
  2458. IOCFacts_t get_facts;
  2459. IOCFactsReply_t *facts;
  2460. int r;
  2461. int req_sz;
  2462. int reply_sz;
  2463. int sz;
  2464. u32 status, vv;
  2465. u8 shiftFactor=1;
  2466. /* IOC *must* NOT be in RESET state! */
  2467. if (ioc->last_state == MPI_IOC_STATE_RESET) {
  2468. printk(MYIOC_s_ERR_FMT "Can't get IOCFacts NOT READY! (%08x)\n",
  2469. ioc->name, ioc->last_state );
  2470. return -44;
  2471. }
  2472. facts = &ioc->facts;
  2473. /* Destination (reply area)... */
  2474. reply_sz = sizeof(*facts);
  2475. memset(facts, 0, reply_sz);
  2476. /* Request area (get_facts on the stack right now!) */
  2477. req_sz = sizeof(get_facts);
  2478. memset(&get_facts, 0, req_sz);
  2479. get_facts.Function = MPI_FUNCTION_IOC_FACTS;
  2480. /* Assert: All other get_facts fields are zero! */
  2481. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2482. "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
  2483. ioc->name, req_sz, reply_sz));
  2484. /* No non-zero fields in the get_facts request are greater than
  2485. * 1 byte in size, so we can just fire it off as is.
  2486. */
  2487. r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
  2488. reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
  2489. if (r != 0)
  2490. return r;
  2491. /*
  2492. * Now byte swap (GRRR) the necessary fields before any further
  2493. * inspection of reply contents.
  2494. *
  2495. * But need to do some sanity checks on MsgLength (byte) field
  2496. * to make sure we don't zero IOC's req_sz!
  2497. */
  2498. /* Did we get a valid reply? */
  2499. if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
  2500. if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  2501. /*
  2502. * If not been here, done that, save off first WhoInit value
  2503. */
  2504. if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
  2505. ioc->FirstWhoInit = facts->WhoInit;
  2506. }
  2507. facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
  2508. facts->MsgContext = le32_to_cpu(facts->MsgContext);
  2509. facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
  2510. facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
  2511. facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
  2512. status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
  2513. /* CHECKME! IOCStatus, IOCLogInfo */
  2514. facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
  2515. facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
  2516. /*
  2517. * FC f/w version changed between 1.1 and 1.2
  2518. * Old: u16{Major(4),Minor(4),SubMinor(8)}
  2519. * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
  2520. */
  2521. if (facts->MsgVersion < 0x0102) {
  2522. /*
  2523. * Handle old FC f/w style, convert to new...
  2524. */
  2525. u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
  2526. facts->FWVersion.Word =
  2527. ((oldv<<12) & 0xFF000000) |
  2528. ((oldv<<8) & 0x000FFF00);
  2529. } else
  2530. facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
  2531. facts->ProductID = le16_to_cpu(facts->ProductID);
  2532. if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
  2533. > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
  2534. ioc->ir_firmware = 1;
  2535. facts->CurrentHostMfaHighAddr =
  2536. le32_to_cpu(facts->CurrentHostMfaHighAddr);
  2537. facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
  2538. facts->CurrentSenseBufferHighAddr =
  2539. le32_to_cpu(facts->CurrentSenseBufferHighAddr);
  2540. facts->CurReplyFrameSize =
  2541. le16_to_cpu(facts->CurReplyFrameSize);
  2542. facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
  2543. /*
  2544. * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
  2545. * Older MPI-1.00.xx struct had 13 dwords, and enlarged
  2546. * to 14 in MPI-1.01.0x.
  2547. */
  2548. if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
  2549. facts->MsgVersion > 0x0100) {
  2550. facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
  2551. }
  2552. sz = facts->FWImageSize;
  2553. if ( sz & 0x01 )
  2554. sz += 1;
  2555. if ( sz & 0x02 )
  2556. sz += 2;
  2557. facts->FWImageSize = sz;
  2558. if (!facts->RequestFrameSize) {
  2559. /* Something is wrong! */
  2560. printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
  2561. ioc->name);
  2562. return -55;
  2563. }
  2564. r = sz = facts->BlockSize;
  2565. vv = ((63 / (sz * 4)) + 1) & 0x03;
  2566. ioc->NB_for_64_byte_frame = vv;
  2567. while ( sz )
  2568. {
  2569. shiftFactor++;
  2570. sz = sz >> 1;
  2571. }
  2572. ioc->NBShiftFactor = shiftFactor;
  2573. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2574. "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
  2575. ioc->name, vv, shiftFactor, r));
  2576. if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  2577. /*
  2578. * Set values for this IOC's request & reply frame sizes,
  2579. * and request & reply queue depths...
  2580. */
  2581. ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
  2582. ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
  2583. ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
  2584. ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
  2585. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
  2586. ioc->name, ioc->reply_sz, ioc->reply_depth));
  2587. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
  2588. ioc->name, ioc->req_sz, ioc->req_depth));
  2589. /* Get port facts! */
  2590. if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
  2591. return r;
  2592. }
  2593. } else {
  2594. printk(MYIOC_s_ERR_FMT
  2595. "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
  2596. ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
  2597. RequestFrameSize)/sizeof(u32)));
  2598. return -66;
  2599. }
  2600. return 0;
  2601. }
  2602. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2603. /**
  2604. * GetPortFacts - Send PortFacts request to MPT adapter.
  2605. * @ioc: Pointer to MPT_ADAPTER structure
  2606. * @portnum: Port number
  2607. * @sleepFlag: Specifies whether the process can sleep
  2608. *
  2609. * Returns 0 for success, non-zero for failure.
  2610. */
  2611. static int
  2612. GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
  2613. {
  2614. PortFacts_t get_pfacts;
  2615. PortFactsReply_t *pfacts;
  2616. int ii;
  2617. int req_sz;
  2618. int reply_sz;
  2619. int max_id;
  2620. /* IOC *must* NOT be in RESET state! */
  2621. if (ioc->last_state == MPI_IOC_STATE_RESET) {
  2622. printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
  2623. ioc->name, ioc->last_state );
  2624. return -4;
  2625. }
  2626. pfacts = &ioc->pfacts[portnum];
  2627. /* Destination (reply area)... */
  2628. reply_sz = sizeof(*pfacts);
  2629. memset(pfacts, 0, reply_sz);
  2630. /* Request area (get_pfacts on the stack right now!) */
  2631. req_sz = sizeof(get_pfacts);
  2632. memset(&get_pfacts, 0, req_sz);
  2633. get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
  2634. get_pfacts.PortNumber = portnum;
  2635. /* Assert: All other get_pfacts fields are zero! */
  2636. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
  2637. ioc->name, portnum));
  2638. /* No non-zero fields in the get_pfacts request are greater than
  2639. * 1 byte in size, so we can just fire it off as is.
  2640. */
  2641. ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
  2642. reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
  2643. if (ii != 0)
  2644. return ii;
  2645. /* Did we get a valid reply? */
  2646. /* Now byte swap the necessary fields in the response. */
  2647. pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
  2648. pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
  2649. pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
  2650. pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
  2651. pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
  2652. pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
  2653. pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
  2654. pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
  2655. pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
  2656. max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
  2657. pfacts->MaxDevices;
  2658. ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
  2659. ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
  2660. /*
  2661. * Place all the devices on channels
  2662. *
  2663. * (for debuging)
  2664. */
  2665. if (mpt_channel_mapping) {
  2666. ioc->devices_per_bus = 1;
  2667. ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
  2668. }
  2669. return 0;
  2670. }
  2671. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2672. /**
  2673. * SendIocInit - Send IOCInit request to MPT adapter.
  2674. * @ioc: Pointer to MPT_ADAPTER structure
  2675. * @sleepFlag: Specifies whether the process can sleep
  2676. *
  2677. * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
  2678. *
  2679. * Returns 0 for success, non-zero for failure.
  2680. */
  2681. static int
  2682. SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
  2683. {
  2684. IOCInit_t ioc_init;
  2685. MPIDefaultReply_t init_reply;
  2686. u32 state;
  2687. int r;
  2688. int count;
  2689. int cntdn;
  2690. memset(&ioc_init, 0, sizeof(ioc_init));
  2691. memset(&init_reply, 0, sizeof(init_reply));
  2692. ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
  2693. ioc_init.Function = MPI_FUNCTION_IOC_INIT;
  2694. /* If we are in a recovery mode and we uploaded the FW image,
  2695. * then this pointer is not NULL. Skip the upload a second time.
  2696. * Set this flag if cached_fw set for either IOC.
  2697. */
  2698. if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
  2699. ioc->upload_fw = 1;
  2700. else
  2701. ioc->upload_fw = 0;
  2702. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
  2703. ioc->name, ioc->upload_fw, ioc->facts.Flags));
  2704. ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
  2705. ioc_init.MaxBuses = (U8)ioc->number_of_buses;
  2706. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
  2707. ioc->name, ioc->facts.MsgVersion));
  2708. if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
  2709. // set MsgVersion and HeaderVersion host driver was built with
  2710. ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
  2711. ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
  2712. if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
  2713. ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
  2714. } else if(mpt_host_page_alloc(ioc, &ioc_init))
  2715. return -99;
  2716. }
  2717. ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
  2718. if (sizeof(dma_addr_t) == sizeof(u64)) {
  2719. /* Save the upper 32-bits of the request
  2720. * (reply) and sense buffers.
  2721. */
  2722. ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
  2723. ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
  2724. } else {
  2725. /* Force 32-bit addressing */
  2726. ioc_init.HostMfaHighAddr = cpu_to_le32(0);
  2727. ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
  2728. }
  2729. ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
  2730. ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
  2731. ioc->facts.MaxDevices = ioc_init.MaxDevices;
  2732. ioc->facts.MaxBuses = ioc_init.MaxBuses;
  2733. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
  2734. ioc->name, &ioc_init));
  2735. r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
  2736. sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
  2737. if (r != 0) {
  2738. printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
  2739. return r;
  2740. }
  2741. /* No need to byte swap the multibyte fields in the reply
  2742. * since we don't even look at its contents.
  2743. */
  2744. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
  2745. ioc->name, &ioc_init));
  2746. if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
  2747. printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
  2748. return r;
  2749. }
  2750. /* YIKES! SUPER IMPORTANT!!!
  2751. * Poll IocState until _OPERATIONAL while IOC is doing
  2752. * LoopInit and TargetDiscovery!
  2753. */
  2754. count = 0;
  2755. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
  2756. state = mpt_GetIocState(ioc, 1);
  2757. while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
  2758. if (sleepFlag == CAN_SLEEP) {
  2759. msleep(1);
  2760. } else {
  2761. mdelay(1);
  2762. }
  2763. if (!cntdn) {
  2764. printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
  2765. ioc->name, (int)((count+5)/HZ));
  2766. return -9;
  2767. }
  2768. state = mpt_GetIocState(ioc, 1);
  2769. count++;
  2770. }
  2771. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
  2772. ioc->name, count));
  2773. ioc->aen_event_read_flag=0;
  2774. return r;
  2775. }
  2776. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2777. /**
  2778. * SendPortEnable - Send PortEnable request to MPT adapter port.
  2779. * @ioc: Pointer to MPT_ADAPTER structure
  2780. * @portnum: Port number to enable
  2781. * @sleepFlag: Specifies whether the process can sleep
  2782. *
  2783. * Send PortEnable to bring IOC to OPERATIONAL state.
  2784. *
  2785. * Returns 0 for success, non-zero for failure.
  2786. */
  2787. static int
  2788. SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
  2789. {
  2790. PortEnable_t port_enable;
  2791. MPIDefaultReply_t reply_buf;
  2792. int rc;
  2793. int req_sz;
  2794. int reply_sz;
  2795. /* Destination... */
  2796. reply_sz = sizeof(MPIDefaultReply_t);
  2797. memset(&reply_buf, 0, reply_sz);
  2798. req_sz = sizeof(PortEnable_t);
  2799. memset(&port_enable, 0, req_sz);
  2800. port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
  2801. port_enable.PortNumber = portnum;
  2802. /* port_enable.ChainOffset = 0; */
  2803. /* port_enable.MsgFlags = 0; */
  2804. /* port_enable.MsgContext = 0; */
  2805. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
  2806. ioc->name, portnum, &port_enable));
  2807. /* RAID FW may take a long time to enable
  2808. */
  2809. if (ioc->ir_firmware || ioc->bus_type == SAS) {
  2810. rc = mpt_handshake_req_reply_wait(ioc, req_sz,
  2811. (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
  2812. 300 /*seconds*/, sleepFlag);
  2813. } else {
  2814. rc = mpt_handshake_req_reply_wait(ioc, req_sz,
  2815. (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
  2816. 30 /*seconds*/, sleepFlag);
  2817. }
  2818. return rc;
  2819. }
  2820. /**
  2821. * mpt_alloc_fw_memory - allocate firmware memory
  2822. * @ioc: Pointer to MPT_ADAPTER structure
  2823. * @size: total FW bytes
  2824. *
  2825. * If memory has already been allocated, the same (cached) value
  2826. * is returned.
  2827. *
  2828. * Return 0 if successfull, or non-zero for failure
  2829. **/
  2830. int
  2831. mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
  2832. {
  2833. int rc;
  2834. if (ioc->cached_fw) {
  2835. rc = 0; /* use already allocated memory */
  2836. goto out;
  2837. }
  2838. else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
  2839. ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
  2840. ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
  2841. rc = 0;
  2842. goto out;
  2843. }
  2844. ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
  2845. if (!ioc->cached_fw) {
  2846. printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
  2847. ioc->name);
  2848. rc = -1;
  2849. } else {
  2850. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
  2851. ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
  2852. ioc->alloc_total += size;
  2853. rc = 0;
  2854. }
  2855. out:
  2856. return rc;
  2857. }
  2858. /**
  2859. * mpt_free_fw_memory - free firmware memory
  2860. * @ioc: Pointer to MPT_ADAPTER structure
  2861. *
  2862. * If alt_img is NULL, delete from ioc structure.
  2863. * Else, delete a secondary image in same format.
  2864. **/
  2865. void
  2866. mpt_free_fw_memory(MPT_ADAPTER *ioc)
  2867. {
  2868. int sz;
  2869. if (!ioc->cached_fw)
  2870. return;
  2871. sz = ioc->facts.FWImageSize;
  2872. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
  2873. ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
  2874. pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
  2875. ioc->alloc_total -= sz;
  2876. ioc->cached_fw = NULL;
  2877. }
  2878. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2879. /**
  2880. * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
  2881. * @ioc: Pointer to MPT_ADAPTER structure
  2882. * @sleepFlag: Specifies whether the process can sleep
  2883. *
  2884. * Returns 0 for success, >0 for handshake failure
  2885. * <0 for fw upload failure.
  2886. *
  2887. * Remark: If bound IOC and a successful FWUpload was performed
  2888. * on the bound IOC, the second image is discarded
  2889. * and memory is free'd. Both channels must upload to prevent
  2890. * IOC from running in degraded mode.
  2891. */
  2892. static int
  2893. mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
  2894. {
  2895. u8 reply[sizeof(FWUploadReply_t)];
  2896. FWUpload_t *prequest;
  2897. FWUploadReply_t *preply;
  2898. FWUploadTCSGE_t *ptcsge;
  2899. int sgeoffset;
  2900. u32 flagsLength;
  2901. int ii, sz, reply_sz;
  2902. int cmdStatus;
  2903. /* If the image size is 0, we are done.
  2904. */
  2905. if ((sz = ioc->facts.FWImageSize) == 0)
  2906. return 0;
  2907. if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
  2908. return -ENOMEM;
  2909. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
  2910. ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
  2911. prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
  2912. kzalloc(ioc->req_sz, GFP_KERNEL);
  2913. if (!prequest) {
  2914. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
  2915. "while allocating memory \n", ioc->name));
  2916. mpt_free_fw_memory(ioc);
  2917. return -ENOMEM;
  2918. }
  2919. preply = (FWUploadReply_t *)&reply;
  2920. reply_sz = sizeof(reply);
  2921. memset(preply, 0, reply_sz);
  2922. prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
  2923. prequest->Function = MPI_FUNCTION_FW_UPLOAD;
  2924. ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
  2925. ptcsge->DetailsLength = 12;
  2926. ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
  2927. ptcsge->ImageSize = cpu_to_le32(sz);
  2928. ptcsge++;
  2929. sgeoffset = sizeof(FWUpload_t) - sizeof(SGE_MPI_UNION) + sizeof(FWUploadTCSGE_t);
  2930. flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
  2931. mpt_add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
  2932. sgeoffset += sizeof(u32) + sizeof(dma_addr_t);
  2933. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": Sending FW Upload (req @ %p) sgeoffset=%d \n",
  2934. ioc->name, prequest, sgeoffset));
  2935. DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
  2936. ii = mpt_handshake_req_reply_wait(ioc, sgeoffset, (u32*)prequest,
  2937. reply_sz, (u16*)preply, 65 /*seconds*/, sleepFlag);
  2938. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Upload completed rc=%x \n", ioc->name, ii));
  2939. cmdStatus = -EFAULT;
  2940. if (ii == 0) {
  2941. /* Handshake transfer was complete and successful.
  2942. * Check the Reply Frame.
  2943. */
  2944. int status, transfer_sz;
  2945. status = le16_to_cpu(preply->IOCStatus);
  2946. if (status == MPI_IOCSTATUS_SUCCESS) {
  2947. transfer_sz = le32_to_cpu(preply->ActualImageSize);
  2948. if (transfer_sz == sz)
  2949. cmdStatus = 0;
  2950. }
  2951. }
  2952. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
  2953. ioc->name, cmdStatus));
  2954. if (cmdStatus) {
  2955. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": fw upload failed, freeing image \n",
  2956. ioc->name));
  2957. mpt_free_fw_memory(ioc);
  2958. }
  2959. kfree(prequest);
  2960. return cmdStatus;
  2961. }
  2962. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2963. /**
  2964. * mpt_downloadboot - DownloadBoot code
  2965. * @ioc: Pointer to MPT_ADAPTER structure
  2966. * @pFwHeader: Pointer to firmware header info
  2967. * @sleepFlag: Specifies whether the process can sleep
  2968. *
  2969. * FwDownloadBoot requires Programmed IO access.
  2970. *
  2971. * Returns 0 for success
  2972. * -1 FW Image size is 0
  2973. * -2 No valid cached_fw Pointer
  2974. * <0 for fw upload failure.
  2975. */
  2976. static int
  2977. mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
  2978. {
  2979. MpiExtImageHeader_t *pExtImage;
  2980. u32 fwSize;
  2981. u32 diag0val;
  2982. int count;
  2983. u32 *ptrFw;
  2984. u32 diagRwData;
  2985. u32 nextImage;
  2986. u32 load_addr;
  2987. u32 ioc_state=0;
  2988. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
  2989. ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
  2990. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  2991. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  2992. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  2993. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  2994. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  2995. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  2996. CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
  2997. /* wait 1 msec */
  2998. if (sleepFlag == CAN_SLEEP) {
  2999. msleep(1);
  3000. } else {
  3001. mdelay (1);
  3002. }
  3003. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3004. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
  3005. for (count = 0; count < 30; count ++) {
  3006. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3007. if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
  3008. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
  3009. ioc->name, count));
  3010. break;
  3011. }
  3012. /* wait .1 sec */
  3013. if (sleepFlag == CAN_SLEEP) {
  3014. msleep (100);
  3015. } else {
  3016. mdelay (100);
  3017. }
  3018. }
  3019. if ( count == 30 ) {
  3020. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
  3021. "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
  3022. ioc->name, diag0val));
  3023. return -3;
  3024. }
  3025. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3026. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3027. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3028. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3029. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3030. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3031. /* Set the DiagRwEn and Disable ARM bits */
  3032. CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
  3033. fwSize = (pFwHeader->ImageSize + 3)/4;
  3034. ptrFw = (u32 *) pFwHeader;
  3035. /* Write the LoadStartAddress to the DiagRw Address Register
  3036. * using Programmed IO
  3037. */
  3038. if (ioc->errata_flag_1064)
  3039. pci_enable_io_access(ioc->pcidev);
  3040. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
  3041. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
  3042. ioc->name, pFwHeader->LoadStartAddress));
  3043. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
  3044. ioc->name, fwSize*4, ptrFw));
  3045. while (fwSize--) {
  3046. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
  3047. }
  3048. nextImage = pFwHeader->NextImageHeaderOffset;
  3049. while (nextImage) {
  3050. pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
  3051. load_addr = pExtImage->LoadStartAddress;
  3052. fwSize = (pExtImage->ImageSize + 3) >> 2;
  3053. ptrFw = (u32 *)pExtImage;
  3054. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
  3055. ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
  3056. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
  3057. while (fwSize--) {
  3058. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
  3059. }
  3060. nextImage = pExtImage->NextImageHeaderOffset;
  3061. }
  3062. /* Write the IopResetVectorRegAddr */
  3063. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
  3064. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
  3065. /* Write the IopResetVectorValue */
  3066. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
  3067. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
  3068. /* Clear the internal flash bad bit - autoincrementing register,
  3069. * so must do two writes.
  3070. */
  3071. if (ioc->bus_type == SPI) {
  3072. /*
  3073. * 1030 and 1035 H/W errata, workaround to access
  3074. * the ClearFlashBadSignatureBit
  3075. */
  3076. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
  3077. diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
  3078. diagRwData |= 0x40000000;
  3079. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
  3080. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
  3081. } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
  3082. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3083. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
  3084. MPI_DIAG_CLEAR_FLASH_BAD_SIG);
  3085. /* wait 1 msec */
  3086. if (sleepFlag == CAN_SLEEP) {
  3087. msleep (1);
  3088. } else {
  3089. mdelay (1);
  3090. }
  3091. }
  3092. if (ioc->errata_flag_1064)
  3093. pci_disable_io_access(ioc->pcidev);
  3094. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3095. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
  3096. "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
  3097. ioc->name, diag0val));
  3098. diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
  3099. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
  3100. ioc->name, diag0val));
  3101. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
  3102. /* Write 0xFF to reset the sequencer */
  3103. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3104. if (ioc->bus_type == SAS) {
  3105. ioc_state = mpt_GetIocState(ioc, 0);
  3106. if ( (GetIocFacts(ioc, sleepFlag,
  3107. MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
  3108. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
  3109. ioc->name, ioc_state));
  3110. return -EFAULT;
  3111. }
  3112. }
  3113. for (count=0; count<HZ*20; count++) {
  3114. if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
  3115. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3116. "downloadboot successful! (count=%d) IocState=%x\n",
  3117. ioc->name, count, ioc_state));
  3118. if (ioc->bus_type == SAS) {
  3119. return 0;
  3120. }
  3121. if ((SendIocInit(ioc, sleepFlag)) != 0) {
  3122. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3123. "downloadboot: SendIocInit failed\n",
  3124. ioc->name));
  3125. return -EFAULT;
  3126. }
  3127. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3128. "downloadboot: SendIocInit successful\n",
  3129. ioc->name));
  3130. return 0;
  3131. }
  3132. if (sleepFlag == CAN_SLEEP) {
  3133. msleep (10);
  3134. } else {
  3135. mdelay (10);
  3136. }
  3137. }
  3138. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3139. "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
  3140. return -EFAULT;
  3141. }
  3142. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3143. /**
  3144. * KickStart - Perform hard reset of MPT adapter.
  3145. * @ioc: Pointer to MPT_ADAPTER structure
  3146. * @force: Force hard reset
  3147. * @sleepFlag: Specifies whether the process can sleep
  3148. *
  3149. * This routine places MPT adapter in diagnostic mode via the
  3150. * WriteSequence register, and then performs a hard reset of adapter
  3151. * via the Diagnostic register.
  3152. *
  3153. * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
  3154. * or NO_SLEEP (interrupt thread, use mdelay)
  3155. * force - 1 if doorbell active, board fault state
  3156. * board operational, IOC_RECOVERY or
  3157. * IOC_BRINGUP and there is an alt_ioc.
  3158. * 0 else
  3159. *
  3160. * Returns:
  3161. * 1 - hard reset, READY
  3162. * 0 - no reset due to History bit, READY
  3163. * -1 - no reset due to History bit but not READY
  3164. * OR reset but failed to come READY
  3165. * -2 - no reset, could not enter DIAG mode
  3166. * -3 - reset but bad FW bit
  3167. */
  3168. static int
  3169. KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
  3170. {
  3171. int hard_reset_done = 0;
  3172. u32 ioc_state=0;
  3173. int cnt,cntdn;
  3174. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
  3175. if (ioc->bus_type == SPI) {
  3176. /* Always issue a Msg Unit Reset first. This will clear some
  3177. * SCSI bus hang conditions.
  3178. */
  3179. SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
  3180. if (sleepFlag == CAN_SLEEP) {
  3181. msleep (1000);
  3182. } else {
  3183. mdelay (1000);
  3184. }
  3185. }
  3186. hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
  3187. if (hard_reset_done < 0)
  3188. return hard_reset_done;
  3189. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
  3190. ioc->name));
  3191. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
  3192. for (cnt=0; cnt<cntdn; cnt++) {
  3193. ioc_state = mpt_GetIocState(ioc, 1);
  3194. if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
  3195. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
  3196. ioc->name, cnt));
  3197. return hard_reset_done;
  3198. }
  3199. if (sleepFlag == CAN_SLEEP) {
  3200. msleep (10);
  3201. } else {
  3202. mdelay (10);
  3203. }
  3204. }
  3205. dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
  3206. ioc->name, mpt_GetIocState(ioc, 0)));
  3207. return -1;
  3208. }
  3209. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3210. /**
  3211. * mpt_diag_reset - Perform hard reset of the adapter.
  3212. * @ioc: Pointer to MPT_ADAPTER structure
  3213. * @ignore: Set if to honor and clear to ignore
  3214. * the reset history bit
  3215. * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
  3216. * else set to NO_SLEEP (use mdelay instead)
  3217. *
  3218. * This routine places the adapter in diagnostic mode via the
  3219. * WriteSequence register and then performs a hard reset of adapter
  3220. * via the Diagnostic register. Adapter should be in ready state
  3221. * upon successful completion.
  3222. *
  3223. * Returns: 1 hard reset successful
  3224. * 0 no reset performed because reset history bit set
  3225. * -2 enabling diagnostic mode failed
  3226. * -3 diagnostic reset failed
  3227. */
  3228. static int
  3229. mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
  3230. {
  3231. u32 diag0val;
  3232. u32 doorbell;
  3233. int hard_reset_done = 0;
  3234. int count = 0;
  3235. u32 diag1val = 0;
  3236. MpiFwHeader_t *cached_fw; /* Pointer to FW */
  3237. /* Clear any existing interrupts */
  3238. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  3239. if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
  3240. drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
  3241. "address=%p\n", ioc->name, __func__,
  3242. &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
  3243. CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
  3244. if (sleepFlag == CAN_SLEEP)
  3245. msleep(1);
  3246. else
  3247. mdelay(1);
  3248. for (count = 0; count < 60; count ++) {
  3249. doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
  3250. doorbell &= MPI_IOC_STATE_MASK;
  3251. drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3252. "looking for READY STATE: doorbell=%x"
  3253. " count=%d\n",
  3254. ioc->name, doorbell, count));
  3255. if (doorbell == MPI_IOC_STATE_READY) {
  3256. return 1;
  3257. }
  3258. /* wait 1 sec */
  3259. if (sleepFlag == CAN_SLEEP)
  3260. msleep(1000);
  3261. else
  3262. mdelay(1000);
  3263. }
  3264. return -1;
  3265. }
  3266. /* Use "Diagnostic reset" method! (only thing available!) */
  3267. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3268. if (ioc->debug_level & MPT_DEBUG) {
  3269. if (ioc->alt_ioc)
  3270. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3271. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
  3272. ioc->name, diag0val, diag1val));
  3273. }
  3274. /* Do the reset if we are told to ignore the reset history
  3275. * or if the reset history is 0
  3276. */
  3277. if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
  3278. while ((diag0val & MPI_DIAG_DRWE) == 0) {
  3279. /* Write magic sequence to WriteSequence register
  3280. * Loop until in diagnostic mode
  3281. */
  3282. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3283. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3284. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3285. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3286. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3287. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3288. /* wait 100 msec */
  3289. if (sleepFlag == CAN_SLEEP) {
  3290. msleep (100);
  3291. } else {
  3292. mdelay (100);
  3293. }
  3294. count++;
  3295. if (count > 20) {
  3296. printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
  3297. ioc->name, diag0val);
  3298. return -2;
  3299. }
  3300. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3301. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
  3302. ioc->name, diag0val));
  3303. }
  3304. if (ioc->debug_level & MPT_DEBUG) {
  3305. if (ioc->alt_ioc)
  3306. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3307. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
  3308. ioc->name, diag0val, diag1val));
  3309. }
  3310. /*
  3311. * Disable the ARM (Bug fix)
  3312. *
  3313. */
  3314. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
  3315. mdelay(1);
  3316. /*
  3317. * Now hit the reset bit in the Diagnostic register
  3318. * (THE BIG HAMMER!) (Clears DRWE bit).
  3319. */
  3320. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
  3321. hard_reset_done = 1;
  3322. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
  3323. ioc->name));
  3324. /*
  3325. * Call each currently registered protocol IOC reset handler
  3326. * with pre-reset indication.
  3327. * NOTE: If we're doing _IOC_BRINGUP, there can be no
  3328. * MptResetHandlers[] registered yet.
  3329. */
  3330. {
  3331. u8 cb_idx;
  3332. int r = 0;
  3333. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  3334. if (MptResetHandlers[cb_idx]) {
  3335. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3336. "Calling IOC pre_reset handler #%d\n",
  3337. ioc->name, cb_idx));
  3338. r += mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
  3339. if (ioc->alt_ioc) {
  3340. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3341. "Calling alt-%s pre_reset handler #%d\n",
  3342. ioc->name, ioc->alt_ioc->name, cb_idx));
  3343. r += mpt_signal_reset(cb_idx, ioc->alt_ioc, MPT_IOC_PRE_RESET);
  3344. }
  3345. }
  3346. }
  3347. /* FIXME? Examine results here? */
  3348. }
  3349. if (ioc->cached_fw)
  3350. cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
  3351. else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
  3352. cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
  3353. else
  3354. cached_fw = NULL;
  3355. if (cached_fw) {
  3356. /* If the DownloadBoot operation fails, the
  3357. * IOC will be left unusable. This is a fatal error
  3358. * case. _diag_reset will return < 0
  3359. */
  3360. for (count = 0; count < 30; count ++) {
  3361. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3362. if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
  3363. break;
  3364. }
  3365. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
  3366. ioc->name, diag0val, count));
  3367. /* wait 1 sec */
  3368. if (sleepFlag == CAN_SLEEP) {
  3369. msleep (1000);
  3370. } else {
  3371. mdelay (1000);
  3372. }
  3373. }
  3374. if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
  3375. printk(MYIOC_s_WARN_FMT
  3376. "firmware downloadboot failure (%d)!\n", ioc->name, count);
  3377. }
  3378. } else {
  3379. /* Wait for FW to reload and for board
  3380. * to go to the READY state.
  3381. * Maximum wait is 60 seconds.
  3382. * If fail, no error will check again
  3383. * with calling program.
  3384. */
  3385. for (count = 0; count < 60; count ++) {
  3386. doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
  3387. doorbell &= MPI_IOC_STATE_MASK;
  3388. if (doorbell == MPI_IOC_STATE_READY) {
  3389. break;
  3390. }
  3391. /* wait 1 sec */
  3392. if (sleepFlag == CAN_SLEEP) {
  3393. msleep (1000);
  3394. } else {
  3395. mdelay (1000);
  3396. }
  3397. }
  3398. }
  3399. }
  3400. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3401. if (ioc->debug_level & MPT_DEBUG) {
  3402. if (ioc->alt_ioc)
  3403. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3404. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
  3405. ioc->name, diag0val, diag1val));
  3406. }
  3407. /* Clear RESET_HISTORY bit! Place board in the
  3408. * diagnostic mode to update the diag register.
  3409. */
  3410. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3411. count = 0;
  3412. while ((diag0val & MPI_DIAG_DRWE) == 0) {
  3413. /* Write magic sequence to WriteSequence register
  3414. * Loop until in diagnostic mode
  3415. */
  3416. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3417. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3418. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3419. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3420. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3421. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3422. /* wait 100 msec */
  3423. if (sleepFlag == CAN_SLEEP) {
  3424. msleep (100);
  3425. } else {
  3426. mdelay (100);
  3427. }
  3428. count++;
  3429. if (count > 20) {
  3430. printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
  3431. ioc->name, diag0val);
  3432. break;
  3433. }
  3434. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3435. }
  3436. diag0val &= ~MPI_DIAG_RESET_HISTORY;
  3437. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
  3438. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3439. if (diag0val & MPI_DIAG_RESET_HISTORY) {
  3440. printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
  3441. ioc->name);
  3442. }
  3443. /* Disable Diagnostic Mode
  3444. */
  3445. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
  3446. /* Check FW reload status flags.
  3447. */
  3448. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3449. if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
  3450. printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
  3451. ioc->name, diag0val);
  3452. return -3;
  3453. }
  3454. if (ioc->debug_level & MPT_DEBUG) {
  3455. if (ioc->alt_ioc)
  3456. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3457. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
  3458. ioc->name, diag0val, diag1val));
  3459. }
  3460. /*
  3461. * Reset flag that says we've enabled event notification
  3462. */
  3463. ioc->facts.EventState = 0;
  3464. if (ioc->alt_ioc)
  3465. ioc->alt_ioc->facts.EventState = 0;
  3466. return hard_reset_done;
  3467. }
  3468. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3469. /**
  3470. * SendIocReset - Send IOCReset request to MPT adapter.
  3471. * @ioc: Pointer to MPT_ADAPTER structure
  3472. * @reset_type: reset type, expected values are
  3473. * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
  3474. * @sleepFlag: Specifies whether the process can sleep
  3475. *
  3476. * Send IOCReset request to the MPT adapter.
  3477. *
  3478. * Returns 0 for success, non-zero for failure.
  3479. */
  3480. static int
  3481. SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
  3482. {
  3483. int r;
  3484. u32 state;
  3485. int cntdn, count;
  3486. drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
  3487. ioc->name, reset_type));
  3488. CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
  3489. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
  3490. return r;
  3491. /* FW ACK'd request, wait for READY state
  3492. */
  3493. count = 0;
  3494. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
  3495. while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
  3496. cntdn--;
  3497. count++;
  3498. if (!cntdn) {
  3499. if (sleepFlag != CAN_SLEEP)
  3500. count *= 10;
  3501. printk(MYIOC_s_ERR_FMT "Wait IOC_READY state timeout(%d)!\n",
  3502. ioc->name, (int)((count+5)/HZ));
  3503. return -ETIME;
  3504. }
  3505. if (sleepFlag == CAN_SLEEP) {
  3506. msleep(1);
  3507. } else {
  3508. mdelay (1); /* 1 msec delay */
  3509. }
  3510. }
  3511. /* TODO!
  3512. * Cleanup all event stuff for this IOC; re-issue EventNotification
  3513. * request if needed.
  3514. */
  3515. if (ioc->facts.Function)
  3516. ioc->facts.EventState = 0;
  3517. return 0;
  3518. }
  3519. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3520. /**
  3521. * initChainBuffers - Allocate memory for and initialize chain buffers
  3522. * @ioc: Pointer to MPT_ADAPTER structure
  3523. *
  3524. * Allocates memory for and initializes chain buffers,
  3525. * chain buffer control arrays and spinlock.
  3526. */
  3527. static int
  3528. initChainBuffers(MPT_ADAPTER *ioc)
  3529. {
  3530. u8 *mem;
  3531. int sz, ii, num_chain;
  3532. int scale, num_sge, numSGE;
  3533. /* ReqToChain size must equal the req_depth
  3534. * index = req_idx
  3535. */
  3536. if (ioc->ReqToChain == NULL) {
  3537. sz = ioc->req_depth * sizeof(int);
  3538. mem = kmalloc(sz, GFP_ATOMIC);
  3539. if (mem == NULL)
  3540. return -1;
  3541. ioc->ReqToChain = (int *) mem;
  3542. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
  3543. ioc->name, mem, sz));
  3544. mem = kmalloc(sz, GFP_ATOMIC);
  3545. if (mem == NULL)
  3546. return -1;
  3547. ioc->RequestNB = (int *) mem;
  3548. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
  3549. ioc->name, mem, sz));
  3550. }
  3551. for (ii = 0; ii < ioc->req_depth; ii++) {
  3552. ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
  3553. }
  3554. /* ChainToChain size must equal the total number
  3555. * of chain buffers to be allocated.
  3556. * index = chain_idx
  3557. *
  3558. * Calculate the number of chain buffers needed(plus 1) per I/O
  3559. * then multiply the maximum number of simultaneous cmds
  3560. *
  3561. * num_sge = num sge in request frame + last chain buffer
  3562. * scale = num sge per chain buffer if no chain element
  3563. */
  3564. scale = ioc->req_sz/(sizeof(dma_addr_t) + sizeof(u32));
  3565. if (sizeof(dma_addr_t) == sizeof(u64))
  3566. num_sge = scale + (ioc->req_sz - 60) / (sizeof(dma_addr_t) + sizeof(u32));
  3567. else
  3568. num_sge = 1+ scale + (ioc->req_sz - 64) / (sizeof(dma_addr_t) + sizeof(u32));
  3569. if (sizeof(dma_addr_t) == sizeof(u64)) {
  3570. numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
  3571. (ioc->req_sz - 60) / (sizeof(dma_addr_t) + sizeof(u32));
  3572. } else {
  3573. numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
  3574. (ioc->req_sz - 64) / (sizeof(dma_addr_t) + sizeof(u32));
  3575. }
  3576. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
  3577. ioc->name, num_sge, numSGE));
  3578. if ( numSGE > MPT_SCSI_SG_DEPTH )
  3579. numSGE = MPT_SCSI_SG_DEPTH;
  3580. num_chain = 1;
  3581. while (numSGE - num_sge > 0) {
  3582. num_chain++;
  3583. num_sge += (scale - 1);
  3584. }
  3585. num_chain++;
  3586. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
  3587. ioc->name, numSGE, num_sge, num_chain));
  3588. if (ioc->bus_type == SPI)
  3589. num_chain *= MPT_SCSI_CAN_QUEUE;
  3590. else
  3591. num_chain *= MPT_FC_CAN_QUEUE;
  3592. ioc->num_chain = num_chain;
  3593. sz = num_chain * sizeof(int);
  3594. if (ioc->ChainToChain == NULL) {
  3595. mem = kmalloc(sz, GFP_ATOMIC);
  3596. if (mem == NULL)
  3597. return -1;
  3598. ioc->ChainToChain = (int *) mem;
  3599. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
  3600. ioc->name, mem, sz));
  3601. } else {
  3602. mem = (u8 *) ioc->ChainToChain;
  3603. }
  3604. memset(mem, 0xFF, sz);
  3605. return num_chain;
  3606. }
  3607. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3608. /**
  3609. * PrimeIocFifos - Initialize IOC request and reply FIFOs.
  3610. * @ioc: Pointer to MPT_ADAPTER structure
  3611. *
  3612. * This routine allocates memory for the MPT reply and request frame
  3613. * pools (if necessary), and primes the IOC reply FIFO with
  3614. * reply frames.
  3615. *
  3616. * Returns 0 for success, non-zero for failure.
  3617. */
  3618. static int
  3619. PrimeIocFifos(MPT_ADAPTER *ioc)
  3620. {
  3621. MPT_FRAME_HDR *mf;
  3622. unsigned long flags;
  3623. dma_addr_t alloc_dma;
  3624. u8 *mem;
  3625. int i, reply_sz, sz, total_size, num_chain;
  3626. /* Prime reply FIFO... */
  3627. if (ioc->reply_frames == NULL) {
  3628. if ( (num_chain = initChainBuffers(ioc)) < 0)
  3629. return -1;
  3630. total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
  3631. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
  3632. ioc->name, ioc->reply_sz, ioc->reply_depth));
  3633. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
  3634. ioc->name, reply_sz, reply_sz));
  3635. sz = (ioc->req_sz * ioc->req_depth);
  3636. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
  3637. ioc->name, ioc->req_sz, ioc->req_depth));
  3638. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
  3639. ioc->name, sz, sz));
  3640. total_size += sz;
  3641. sz = num_chain * ioc->req_sz; /* chain buffer pool size */
  3642. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
  3643. ioc->name, ioc->req_sz, num_chain));
  3644. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
  3645. ioc->name, sz, sz, num_chain));
  3646. total_size += sz;
  3647. mem = pci_alloc_consistent(ioc->pcidev, total_size, &alloc_dma);
  3648. if (mem == NULL) {
  3649. printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
  3650. ioc->name);
  3651. goto out_fail;
  3652. }
  3653. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
  3654. ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
  3655. memset(mem, 0, total_size);
  3656. ioc->alloc_total += total_size;
  3657. ioc->alloc = mem;
  3658. ioc->alloc_dma = alloc_dma;
  3659. ioc->alloc_sz = total_size;
  3660. ioc->reply_frames = (MPT_FRAME_HDR *) mem;
  3661. ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
  3662. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
  3663. ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
  3664. alloc_dma += reply_sz;
  3665. mem += reply_sz;
  3666. /* Request FIFO - WE manage this! */
  3667. ioc->req_frames = (MPT_FRAME_HDR *) mem;
  3668. ioc->req_frames_dma = alloc_dma;
  3669. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
  3670. ioc->name, mem, (void *)(ulong)alloc_dma));
  3671. ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
  3672. #if defined(CONFIG_MTRR) && 0
  3673. /*
  3674. * Enable Write Combining MTRR for IOC's memory region.
  3675. * (at least as much as we can; "size and base must be
  3676. * multiples of 4 kiB"
  3677. */
  3678. ioc->mtrr_reg = mtrr_add(ioc->req_frames_dma,
  3679. sz,
  3680. MTRR_TYPE_WRCOMB, 1);
  3681. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "MTRR region registered (base:size=%08x:%x)\n",
  3682. ioc->name, ioc->req_frames_dma, sz));
  3683. #endif
  3684. for (i = 0; i < ioc->req_depth; i++) {
  3685. alloc_dma += ioc->req_sz;
  3686. mem += ioc->req_sz;
  3687. }
  3688. ioc->ChainBuffer = mem;
  3689. ioc->ChainBufferDMA = alloc_dma;
  3690. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
  3691. ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
  3692. /* Initialize the free chain Q.
  3693. */
  3694. INIT_LIST_HEAD(&ioc->FreeChainQ);
  3695. /* Post the chain buffers to the FreeChainQ.
  3696. */
  3697. mem = (u8 *)ioc->ChainBuffer;
  3698. for (i=0; i < num_chain; i++) {
  3699. mf = (MPT_FRAME_HDR *) mem;
  3700. list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
  3701. mem += ioc->req_sz;
  3702. }
  3703. /* Initialize Request frames linked list
  3704. */
  3705. alloc_dma = ioc->req_frames_dma;
  3706. mem = (u8 *) ioc->req_frames;
  3707. spin_lock_irqsave(&ioc->FreeQlock, flags);
  3708. INIT_LIST_HEAD(&ioc->FreeQ);
  3709. for (i = 0; i < ioc->req_depth; i++) {
  3710. mf = (MPT_FRAME_HDR *) mem;
  3711. /* Queue REQUESTs *internally*! */
  3712. list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
  3713. mem += ioc->req_sz;
  3714. }
  3715. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  3716. sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
  3717. ioc->sense_buf_pool =
  3718. pci_alloc_consistent(ioc->pcidev, sz, &ioc->sense_buf_pool_dma);
  3719. if (ioc->sense_buf_pool == NULL) {
  3720. printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
  3721. ioc->name);
  3722. goto out_fail;
  3723. }
  3724. ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
  3725. ioc->alloc_total += sz;
  3726. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
  3727. ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
  3728. }
  3729. /* Post Reply frames to FIFO
  3730. */
  3731. alloc_dma = ioc->alloc_dma;
  3732. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
  3733. ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
  3734. for (i = 0; i < ioc->reply_depth; i++) {
  3735. /* Write each address to the IOC! */
  3736. CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
  3737. alloc_dma += ioc->reply_sz;
  3738. }
  3739. return 0;
  3740. out_fail:
  3741. if (ioc->alloc != NULL) {
  3742. sz = ioc->alloc_sz;
  3743. pci_free_consistent(ioc->pcidev,
  3744. sz,
  3745. ioc->alloc, ioc->alloc_dma);
  3746. ioc->reply_frames = NULL;
  3747. ioc->req_frames = NULL;
  3748. ioc->alloc_total -= sz;
  3749. }
  3750. if (ioc->sense_buf_pool != NULL) {
  3751. sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
  3752. pci_free_consistent(ioc->pcidev,
  3753. sz,
  3754. ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
  3755. ioc->sense_buf_pool = NULL;
  3756. }
  3757. return -1;
  3758. }
  3759. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3760. /**
  3761. * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
  3762. * from IOC via doorbell handshake method.
  3763. * @ioc: Pointer to MPT_ADAPTER structure
  3764. * @reqBytes: Size of the request in bytes
  3765. * @req: Pointer to MPT request frame
  3766. * @replyBytes: Expected size of the reply in bytes
  3767. * @u16reply: Pointer to area where reply should be written
  3768. * @maxwait: Max wait time for a reply (in seconds)
  3769. * @sleepFlag: Specifies whether the process can sleep
  3770. *
  3771. * NOTES: It is the callers responsibility to byte-swap fields in the
  3772. * request which are greater than 1 byte in size. It is also the
  3773. * callers responsibility to byte-swap response fields which are
  3774. * greater than 1 byte in size.
  3775. *
  3776. * Returns 0 for success, non-zero for failure.
  3777. */
  3778. static int
  3779. mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
  3780. int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
  3781. {
  3782. MPIDefaultReply_t *mptReply;
  3783. int failcnt = 0;
  3784. int t;
  3785. /*
  3786. * Get ready to cache a handshake reply
  3787. */
  3788. ioc->hs_reply_idx = 0;
  3789. mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
  3790. mptReply->MsgLength = 0;
  3791. /*
  3792. * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
  3793. * then tell IOC that we want to handshake a request of N words.
  3794. * (WRITE u32val to Doorbell reg).
  3795. */
  3796. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  3797. CHIPREG_WRITE32(&ioc->chip->Doorbell,
  3798. ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
  3799. ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
  3800. /*
  3801. * Wait for IOC's doorbell handshake int
  3802. */
  3803. if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  3804. failcnt++;
  3805. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
  3806. ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
  3807. /* Read doorbell and check for active bit */
  3808. if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
  3809. return -1;
  3810. /*
  3811. * Clear doorbell int (WRITE 0 to IntStatus reg),
  3812. * then wait for IOC to ACKnowledge that it's ready for
  3813. * our handshake request.
  3814. */
  3815. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  3816. if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
  3817. failcnt++;
  3818. if (!failcnt) {
  3819. int ii;
  3820. u8 *req_as_bytes = (u8 *) req;
  3821. /*
  3822. * Stuff request words via doorbell handshake,
  3823. * with ACK from IOC for each.
  3824. */
  3825. for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
  3826. u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
  3827. (req_as_bytes[(ii*4) + 1] << 8) |
  3828. (req_as_bytes[(ii*4) + 2] << 16) |
  3829. (req_as_bytes[(ii*4) + 3] << 24));
  3830. CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
  3831. if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
  3832. failcnt++;
  3833. }
  3834. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
  3835. DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
  3836. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
  3837. ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
  3838. /*
  3839. * Wait for completion of doorbell handshake reply from the IOC
  3840. */
  3841. if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
  3842. failcnt++;
  3843. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
  3844. ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
  3845. /*
  3846. * Copy out the cached reply...
  3847. */
  3848. for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
  3849. u16reply[ii] = ioc->hs_reply[ii];
  3850. } else {
  3851. return -99;
  3852. }
  3853. return -failcnt;
  3854. }
  3855. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3856. /**
  3857. * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
  3858. * @ioc: Pointer to MPT_ADAPTER structure
  3859. * @howlong: How long to wait (in seconds)
  3860. * @sleepFlag: Specifies whether the process can sleep
  3861. *
  3862. * This routine waits (up to ~2 seconds max) for IOC doorbell
  3863. * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
  3864. * bit in its IntStatus register being clear.
  3865. *
  3866. * Returns a negative value on failure, else wait loop count.
  3867. */
  3868. static int
  3869. WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
  3870. {
  3871. int cntdn;
  3872. int count = 0;
  3873. u32 intstat=0;
  3874. cntdn = 1000 * howlong;
  3875. if (sleepFlag == CAN_SLEEP) {
  3876. while (--cntdn) {
  3877. msleep (1);
  3878. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  3879. if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
  3880. break;
  3881. count++;
  3882. }
  3883. } else {
  3884. while (--cntdn) {
  3885. udelay (1000);
  3886. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  3887. if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
  3888. break;
  3889. count++;
  3890. }
  3891. }
  3892. if (cntdn) {
  3893. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
  3894. ioc->name, count));
  3895. return count;
  3896. }
  3897. printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
  3898. ioc->name, count, intstat);
  3899. return -1;
  3900. }
  3901. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3902. /**
  3903. * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
  3904. * @ioc: Pointer to MPT_ADAPTER structure
  3905. * @howlong: How long to wait (in seconds)
  3906. * @sleepFlag: Specifies whether the process can sleep
  3907. *
  3908. * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
  3909. * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
  3910. *
  3911. * Returns a negative value on failure, else wait loop count.
  3912. */
  3913. static int
  3914. WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
  3915. {
  3916. int cntdn;
  3917. int count = 0;
  3918. u32 intstat=0;
  3919. cntdn = 1000 * howlong;
  3920. if (sleepFlag == CAN_SLEEP) {
  3921. while (--cntdn) {
  3922. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  3923. if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
  3924. break;
  3925. msleep(1);
  3926. count++;
  3927. }
  3928. } else {
  3929. while (--cntdn) {
  3930. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  3931. if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
  3932. break;
  3933. udelay (1000);
  3934. count++;
  3935. }
  3936. }
  3937. if (cntdn) {
  3938. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
  3939. ioc->name, count, howlong));
  3940. return count;
  3941. }
  3942. printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
  3943. ioc->name, count, intstat);
  3944. return -1;
  3945. }
  3946. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3947. /**
  3948. * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
  3949. * @ioc: Pointer to MPT_ADAPTER structure
  3950. * @howlong: How long to wait (in seconds)
  3951. * @sleepFlag: Specifies whether the process can sleep
  3952. *
  3953. * This routine polls the IOC for a handshake reply, 16 bits at a time.
  3954. * Reply is cached to IOC private area large enough to hold a maximum
  3955. * of 128 bytes of reply data.
  3956. *
  3957. * Returns a negative value on failure, else size of reply in WORDS.
  3958. */
  3959. static int
  3960. WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
  3961. {
  3962. int u16cnt = 0;
  3963. int failcnt = 0;
  3964. int t;
  3965. u16 *hs_reply = ioc->hs_reply;
  3966. volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
  3967. u16 hword;
  3968. hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
  3969. /*
  3970. * Get first two u16's so we can look at IOC's intended reply MsgLength
  3971. */
  3972. u16cnt=0;
  3973. if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
  3974. failcnt++;
  3975. } else {
  3976. hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
  3977. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  3978. if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  3979. failcnt++;
  3980. else {
  3981. hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
  3982. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  3983. }
  3984. }
  3985. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
  3986. ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
  3987. failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
  3988. /*
  3989. * If no error (and IOC said MsgLength is > 0), piece together
  3990. * reply 16 bits at a time.
  3991. */
  3992. for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
  3993. if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  3994. failcnt++;
  3995. hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
  3996. /* don't overflow our IOC hs_reply[] buffer! */
  3997. if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
  3998. hs_reply[u16cnt] = hword;
  3999. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4000. }
  4001. if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  4002. failcnt++;
  4003. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4004. if (failcnt) {
  4005. printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
  4006. ioc->name);
  4007. return -failcnt;
  4008. }
  4009. #if 0
  4010. else if (u16cnt != (2 * mptReply->MsgLength)) {
  4011. return -101;
  4012. }
  4013. else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
  4014. return -102;
  4015. }
  4016. #endif
  4017. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
  4018. DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
  4019. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
  4020. ioc->name, t, u16cnt/2));
  4021. return u16cnt/2;
  4022. }
  4023. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4024. /**
  4025. * GetLanConfigPages - Fetch LANConfig pages.
  4026. * @ioc: Pointer to MPT_ADAPTER structure
  4027. *
  4028. * Return: 0 for success
  4029. * -ENOMEM if no memory available
  4030. * -EPERM if not allowed due to ISR context
  4031. * -EAGAIN if no msg frames currently available
  4032. * -EFAULT for non-successful reply or no reply (timeout)
  4033. */
  4034. static int
  4035. GetLanConfigPages(MPT_ADAPTER *ioc)
  4036. {
  4037. ConfigPageHeader_t hdr;
  4038. CONFIGPARMS cfg;
  4039. LANPage0_t *ppage0_alloc;
  4040. dma_addr_t page0_dma;
  4041. LANPage1_t *ppage1_alloc;
  4042. dma_addr_t page1_dma;
  4043. int rc = 0;
  4044. int data_sz;
  4045. int copy_sz;
  4046. /* Get LAN Page 0 header */
  4047. hdr.PageVersion = 0;
  4048. hdr.PageLength = 0;
  4049. hdr.PageNumber = 0;
  4050. hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
  4051. cfg.cfghdr.hdr = &hdr;
  4052. cfg.physAddr = -1;
  4053. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4054. cfg.dir = 0;
  4055. cfg.pageAddr = 0;
  4056. cfg.timeout = 0;
  4057. if ((rc = mpt_config(ioc, &cfg)) != 0)
  4058. return rc;
  4059. if (hdr.PageLength > 0) {
  4060. data_sz = hdr.PageLength * 4;
  4061. ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
  4062. rc = -ENOMEM;
  4063. if (ppage0_alloc) {
  4064. memset((u8 *)ppage0_alloc, 0, data_sz);
  4065. cfg.physAddr = page0_dma;
  4066. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4067. if ((rc = mpt_config(ioc, &cfg)) == 0) {
  4068. /* save the data */
  4069. copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
  4070. memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
  4071. }
  4072. pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
  4073. /* FIXME!
  4074. * Normalize endianness of structure data,
  4075. * by byte-swapping all > 1 byte fields!
  4076. */
  4077. }
  4078. if (rc)
  4079. return rc;
  4080. }
  4081. /* Get LAN Page 1 header */
  4082. hdr.PageVersion = 0;
  4083. hdr.PageLength = 0;
  4084. hdr.PageNumber = 1;
  4085. hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
  4086. cfg.cfghdr.hdr = &hdr;
  4087. cfg.physAddr = -1;
  4088. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4089. cfg.dir = 0;
  4090. cfg.pageAddr = 0;
  4091. if ((rc = mpt_config(ioc, &cfg)) != 0)
  4092. return rc;
  4093. if (hdr.PageLength == 0)
  4094. return 0;
  4095. data_sz = hdr.PageLength * 4;
  4096. rc = -ENOMEM;
  4097. ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
  4098. if (ppage1_alloc) {
  4099. memset((u8 *)ppage1_alloc, 0, data_sz);
  4100. cfg.physAddr = page1_dma;
  4101. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4102. if ((rc = mpt_config(ioc, &cfg)) == 0) {
  4103. /* save the data */
  4104. copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
  4105. memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
  4106. }
  4107. pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
  4108. /* FIXME!
  4109. * Normalize endianness of structure data,
  4110. * by byte-swapping all > 1 byte fields!
  4111. */
  4112. }
  4113. return rc;
  4114. }
  4115. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4116. /**
  4117. * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
  4118. * @ioc: Pointer to MPT_ADAPTER structure
  4119. * @persist_opcode: see below
  4120. *
  4121. * MPI_SAS_OP_CLEAR_NOT_PRESENT - Free all persist TargetID mappings for
  4122. * devices not currently present.
  4123. * MPI_SAS_OP_CLEAR_ALL_PERSISTENT - Clear al persist TargetID mappings
  4124. *
  4125. * NOTE: Don't use not this function during interrupt time.
  4126. *
  4127. * Returns 0 for success, non-zero error
  4128. */
  4129. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4130. int
  4131. mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
  4132. {
  4133. SasIoUnitControlRequest_t *sasIoUnitCntrReq;
  4134. SasIoUnitControlReply_t *sasIoUnitCntrReply;
  4135. MPT_FRAME_HDR *mf = NULL;
  4136. MPIHeader_t *mpi_hdr;
  4137. /* insure garbage is not sent to fw */
  4138. switch(persist_opcode) {
  4139. case MPI_SAS_OP_CLEAR_NOT_PRESENT:
  4140. case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
  4141. break;
  4142. default:
  4143. return -1;
  4144. break;
  4145. }
  4146. printk("%s: persist_opcode=%x\n",__func__, persist_opcode);
  4147. /* Get a MF for this command.
  4148. */
  4149. if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
  4150. printk("%s: no msg frames!\n",__func__);
  4151. return -1;
  4152. }
  4153. mpi_hdr = (MPIHeader_t *) mf;
  4154. sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
  4155. memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
  4156. sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
  4157. sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
  4158. sasIoUnitCntrReq->Operation = persist_opcode;
  4159. init_timer(&ioc->persist_timer);
  4160. ioc->persist_timer.data = (unsigned long) ioc;
  4161. ioc->persist_timer.function = mpt_timer_expired;
  4162. ioc->persist_timer.expires = jiffies + HZ*10 /* 10 sec */;
  4163. ioc->persist_wait_done=0;
  4164. add_timer(&ioc->persist_timer);
  4165. mpt_put_msg_frame(mpt_base_index, ioc, mf);
  4166. wait_event(mpt_waitq, ioc->persist_wait_done);
  4167. sasIoUnitCntrReply =
  4168. (SasIoUnitControlReply_t *)ioc->persist_reply_frame;
  4169. if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
  4170. printk("%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
  4171. __func__,
  4172. sasIoUnitCntrReply->IOCStatus,
  4173. sasIoUnitCntrReply->IOCLogInfo);
  4174. return -1;
  4175. }
  4176. printk("%s: success\n",__func__);
  4177. return 0;
  4178. }
  4179. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4180. static void
  4181. mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
  4182. MpiEventDataRaid_t * pRaidEventData)
  4183. {
  4184. int volume;
  4185. int reason;
  4186. int disk;
  4187. int status;
  4188. int flags;
  4189. int state;
  4190. volume = pRaidEventData->VolumeID;
  4191. reason = pRaidEventData->ReasonCode;
  4192. disk = pRaidEventData->PhysDiskNum;
  4193. status = le32_to_cpu(pRaidEventData->SettingsStatus);
  4194. flags = (status >> 0) & 0xff;
  4195. state = (status >> 8) & 0xff;
  4196. if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
  4197. return;
  4198. }
  4199. if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
  4200. reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
  4201. (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
  4202. printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
  4203. ioc->name, disk, volume);
  4204. } else {
  4205. printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
  4206. ioc->name, volume);
  4207. }
  4208. switch(reason) {
  4209. case MPI_EVENT_RAID_RC_VOLUME_CREATED:
  4210. printk(MYIOC_s_INFO_FMT " volume has been created\n",
  4211. ioc->name);
  4212. break;
  4213. case MPI_EVENT_RAID_RC_VOLUME_DELETED:
  4214. printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
  4215. ioc->name);
  4216. break;
  4217. case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
  4218. printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
  4219. ioc->name);
  4220. break;
  4221. case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
  4222. printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
  4223. ioc->name,
  4224. state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
  4225. ? "optimal"
  4226. : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
  4227. ? "degraded"
  4228. : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
  4229. ? "failed"
  4230. : "state unknown",
  4231. flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
  4232. ? ", enabled" : "",
  4233. flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
  4234. ? ", quiesced" : "",
  4235. flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
  4236. ? ", resync in progress" : "" );
  4237. break;
  4238. case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
  4239. printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
  4240. ioc->name, disk);
  4241. break;
  4242. case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
  4243. printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
  4244. ioc->name);
  4245. break;
  4246. case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
  4247. printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
  4248. ioc->name);
  4249. break;
  4250. case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
  4251. printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
  4252. ioc->name);
  4253. break;
  4254. case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
  4255. printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
  4256. ioc->name,
  4257. state == MPI_PHYSDISK0_STATUS_ONLINE
  4258. ? "online"
  4259. : state == MPI_PHYSDISK0_STATUS_MISSING
  4260. ? "missing"
  4261. : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
  4262. ? "not compatible"
  4263. : state == MPI_PHYSDISK0_STATUS_FAILED
  4264. ? "failed"
  4265. : state == MPI_PHYSDISK0_STATUS_INITIALIZING
  4266. ? "initializing"
  4267. : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
  4268. ? "offline requested"
  4269. : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
  4270. ? "failed requested"
  4271. : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
  4272. ? "offline"
  4273. : "state unknown",
  4274. flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
  4275. ? ", out of sync" : "",
  4276. flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
  4277. ? ", quiesced" : "" );
  4278. break;
  4279. case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
  4280. printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
  4281. ioc->name, disk);
  4282. break;
  4283. case MPI_EVENT_RAID_RC_SMART_DATA:
  4284. printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
  4285. ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
  4286. break;
  4287. case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
  4288. printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
  4289. ioc->name, disk);
  4290. break;
  4291. }
  4292. }
  4293. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4294. /**
  4295. * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
  4296. * @ioc: Pointer to MPT_ADAPTER structure
  4297. *
  4298. * Returns: 0 for success
  4299. * -ENOMEM if no memory available
  4300. * -EPERM if not allowed due to ISR context
  4301. * -EAGAIN if no msg frames currently available
  4302. * -EFAULT for non-successful reply or no reply (timeout)
  4303. */
  4304. static int
  4305. GetIoUnitPage2(MPT_ADAPTER *ioc)
  4306. {
  4307. ConfigPageHeader_t hdr;
  4308. CONFIGPARMS cfg;
  4309. IOUnitPage2_t *ppage_alloc;
  4310. dma_addr_t page_dma;
  4311. int data_sz;
  4312. int rc;
  4313. /* Get the page header */
  4314. hdr.PageVersion = 0;
  4315. hdr.PageLength = 0;
  4316. hdr.PageNumber = 2;
  4317. hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
  4318. cfg.cfghdr.hdr = &hdr;
  4319. cfg.physAddr = -1;
  4320. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4321. cfg.dir = 0;
  4322. cfg.pageAddr = 0;
  4323. cfg.timeout = 0;
  4324. if ((rc = mpt_config(ioc, &cfg)) != 0)
  4325. return rc;
  4326. if (hdr.PageLength == 0)
  4327. return 0;
  4328. /* Read the config page */
  4329. data_sz = hdr.PageLength * 4;
  4330. rc = -ENOMEM;
  4331. ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
  4332. if (ppage_alloc) {
  4333. memset((u8 *)ppage_alloc, 0, data_sz);
  4334. cfg.physAddr = page_dma;
  4335. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4336. /* If Good, save data */
  4337. if ((rc = mpt_config(ioc, &cfg)) == 0)
  4338. ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
  4339. pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
  4340. }
  4341. return rc;
  4342. }
  4343. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4344. /**
  4345. * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
  4346. * @ioc: Pointer to a Adapter Strucutre
  4347. * @portnum: IOC port number
  4348. *
  4349. * Return: -EFAULT if read of config page header fails
  4350. * or if no nvram
  4351. * If read of SCSI Port Page 0 fails,
  4352. * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
  4353. * Adapter settings: async, narrow
  4354. * Return 1
  4355. * If read of SCSI Port Page 2 fails,
  4356. * Adapter settings valid
  4357. * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
  4358. * Return 1
  4359. * Else
  4360. * Both valid
  4361. * Return 0
  4362. * CHECK - what type of locking mechanisms should be used????
  4363. */
  4364. static int
  4365. mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
  4366. {
  4367. u8 *pbuf;
  4368. dma_addr_t buf_dma;
  4369. CONFIGPARMS cfg;
  4370. ConfigPageHeader_t header;
  4371. int ii;
  4372. int data, rc = 0;
  4373. /* Allocate memory
  4374. */
  4375. if (!ioc->spi_data.nvram) {
  4376. int sz;
  4377. u8 *mem;
  4378. sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
  4379. mem = kmalloc(sz, GFP_ATOMIC);
  4380. if (mem == NULL)
  4381. return -EFAULT;
  4382. ioc->spi_data.nvram = (int *) mem;
  4383. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
  4384. ioc->name, ioc->spi_data.nvram, sz));
  4385. }
  4386. /* Invalidate NVRAM information
  4387. */
  4388. for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
  4389. ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
  4390. }
  4391. /* Read SPP0 header, allocate memory, then read page.
  4392. */
  4393. header.PageVersion = 0;
  4394. header.PageLength = 0;
  4395. header.PageNumber = 0;
  4396. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
  4397. cfg.cfghdr.hdr = &header;
  4398. cfg.physAddr = -1;
  4399. cfg.pageAddr = portnum;
  4400. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4401. cfg.dir = 0;
  4402. cfg.timeout = 0; /* use default */
  4403. if (mpt_config(ioc, &cfg) != 0)
  4404. return -EFAULT;
  4405. if (header.PageLength > 0) {
  4406. pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
  4407. if (pbuf) {
  4408. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4409. cfg.physAddr = buf_dma;
  4410. if (mpt_config(ioc, &cfg) != 0) {
  4411. ioc->spi_data.maxBusWidth = MPT_NARROW;
  4412. ioc->spi_data.maxSyncOffset = 0;
  4413. ioc->spi_data.minSyncFactor = MPT_ASYNC;
  4414. ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
  4415. rc = 1;
  4416. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4417. "Unable to read PortPage0 minSyncFactor=%x\n",
  4418. ioc->name, ioc->spi_data.minSyncFactor));
  4419. } else {
  4420. /* Save the Port Page 0 data
  4421. */
  4422. SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
  4423. pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
  4424. pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
  4425. if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
  4426. ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
  4427. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4428. "noQas due to Capabilities=%x\n",
  4429. ioc->name, pPP0->Capabilities));
  4430. }
  4431. ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
  4432. data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
  4433. if (data) {
  4434. ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
  4435. data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
  4436. ioc->spi_data.minSyncFactor = (u8) (data >> 8);
  4437. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4438. "PortPage0 minSyncFactor=%x\n",
  4439. ioc->name, ioc->spi_data.minSyncFactor));
  4440. } else {
  4441. ioc->spi_data.maxSyncOffset = 0;
  4442. ioc->spi_data.minSyncFactor = MPT_ASYNC;
  4443. }
  4444. ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
  4445. /* Update the minSyncFactor based on bus type.
  4446. */
  4447. if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
  4448. (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
  4449. if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
  4450. ioc->spi_data.minSyncFactor = MPT_ULTRA;
  4451. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4452. "HVD or SE detected, minSyncFactor=%x\n",
  4453. ioc->name, ioc->spi_data.minSyncFactor));
  4454. }
  4455. }
  4456. }
  4457. if (pbuf) {
  4458. pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
  4459. }
  4460. }
  4461. }
  4462. /* SCSI Port Page 2 - Read the header then the page.
  4463. */
  4464. header.PageVersion = 0;
  4465. header.PageLength = 0;
  4466. header.PageNumber = 2;
  4467. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
  4468. cfg.cfghdr.hdr = &header;
  4469. cfg.physAddr = -1;
  4470. cfg.pageAddr = portnum;
  4471. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4472. cfg.dir = 0;
  4473. if (mpt_config(ioc, &cfg) != 0)
  4474. return -EFAULT;
  4475. if (header.PageLength > 0) {
  4476. /* Allocate memory and read SCSI Port Page 2
  4477. */
  4478. pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
  4479. if (pbuf) {
  4480. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
  4481. cfg.physAddr = buf_dma;
  4482. if (mpt_config(ioc, &cfg) != 0) {
  4483. /* Nvram data is left with INVALID mark
  4484. */
  4485. rc = 1;
  4486. } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
  4487. /* This is an ATTO adapter, read Page2 accordingly
  4488. */
  4489. ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
  4490. ATTODeviceInfo_t *pdevice = NULL;
  4491. u16 ATTOFlags;
  4492. /* Save the Port Page 2 data
  4493. * (reformat into a 32bit quantity)
  4494. */
  4495. for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
  4496. pdevice = &pPP2->DeviceSettings[ii];
  4497. ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
  4498. data = 0;
  4499. /* Translate ATTO device flags to LSI format
  4500. */
  4501. if (ATTOFlags & ATTOFLAG_DISC)
  4502. data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
  4503. if (ATTOFlags & ATTOFLAG_ID_ENB)
  4504. data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
  4505. if (ATTOFlags & ATTOFLAG_LUN_ENB)
  4506. data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
  4507. if (ATTOFlags & ATTOFLAG_TAGGED)
  4508. data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
  4509. if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
  4510. data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
  4511. data = (data << 16) | (pdevice->Period << 8) | 10;
  4512. ioc->spi_data.nvram[ii] = data;
  4513. }
  4514. } else {
  4515. SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
  4516. MpiDeviceInfo_t *pdevice = NULL;
  4517. /*
  4518. * Save "Set to Avoid SCSI Bus Resets" flag
  4519. */
  4520. ioc->spi_data.bus_reset =
  4521. (le32_to_cpu(pPP2->PortFlags) &
  4522. MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
  4523. 0 : 1 ;
  4524. /* Save the Port Page 2 data
  4525. * (reformat into a 32bit quantity)
  4526. */
  4527. data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
  4528. ioc->spi_data.PortFlags = data;
  4529. for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
  4530. pdevice = &pPP2->DeviceSettings[ii];
  4531. data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
  4532. (pdevice->SyncFactor << 8) | pdevice->Timeout;
  4533. ioc->spi_data.nvram[ii] = data;
  4534. }
  4535. }
  4536. pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
  4537. }
  4538. }
  4539. /* Update Adapter limits with those from NVRAM
  4540. * Comment: Don't need to do this. Target performance
  4541. * parameters will never exceed the adapters limits.
  4542. */
  4543. return rc;
  4544. }
  4545. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4546. /**
  4547. * mpt_readScsiDevicePageHeaders - save version and length of SDP1
  4548. * @ioc: Pointer to a Adapter Strucutre
  4549. * @portnum: IOC port number
  4550. *
  4551. * Return: -EFAULT if read of config page header fails
  4552. * or 0 if success.
  4553. */
  4554. static int
  4555. mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
  4556. {
  4557. CONFIGPARMS cfg;
  4558. ConfigPageHeader_t header;
  4559. /* Read the SCSI Device Page 1 header
  4560. */
  4561. header.PageVersion = 0;
  4562. header.PageLength = 0;
  4563. header.PageNumber = 1;
  4564. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
  4565. cfg.cfghdr.hdr = &header;
  4566. cfg.physAddr = -1;
  4567. cfg.pageAddr = portnum;
  4568. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4569. cfg.dir = 0;
  4570. cfg.timeout = 0;
  4571. if (mpt_config(ioc, &cfg) != 0)
  4572. return -EFAULT;
  4573. ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
  4574. ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
  4575. header.PageVersion = 0;
  4576. header.PageLength = 0;
  4577. header.PageNumber = 0;
  4578. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
  4579. if (mpt_config(ioc, &cfg) != 0)
  4580. return -EFAULT;
  4581. ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
  4582. ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
  4583. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
  4584. ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
  4585. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
  4586. ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
  4587. return 0;
  4588. }
  4589. /**
  4590. * mpt_inactive_raid_list_free - This clears this link list.
  4591. * @ioc : pointer to per adapter structure
  4592. **/
  4593. static void
  4594. mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
  4595. {
  4596. struct inactive_raid_component_info *component_info, *pNext;
  4597. if (list_empty(&ioc->raid_data.inactive_list))
  4598. return;
  4599. mutex_lock(&ioc->raid_data.inactive_list_mutex);
  4600. list_for_each_entry_safe(component_info, pNext,
  4601. &ioc->raid_data.inactive_list, list) {
  4602. list_del(&component_info->list);
  4603. kfree(component_info);
  4604. }
  4605. mutex_unlock(&ioc->raid_data.inactive_list_mutex);
  4606. }
  4607. /**
  4608. * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
  4609. *
  4610. * @ioc : pointer to per adapter structure
  4611. * @channel : volume channel
  4612. * @id : volume target id
  4613. **/
  4614. static void
  4615. mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
  4616. {
  4617. CONFIGPARMS cfg;
  4618. ConfigPageHeader_t hdr;
  4619. dma_addr_t dma_handle;
  4620. pRaidVolumePage0_t buffer = NULL;
  4621. int i;
  4622. RaidPhysDiskPage0_t phys_disk;
  4623. struct inactive_raid_component_info *component_info;
  4624. int handle_inactive_volumes;
  4625. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  4626. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  4627. hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
  4628. cfg.pageAddr = (channel << 8) + id;
  4629. cfg.cfghdr.hdr = &hdr;
  4630. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4631. if (mpt_config(ioc, &cfg) != 0)
  4632. goto out;
  4633. if (!hdr.PageLength)
  4634. goto out;
  4635. buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
  4636. &dma_handle);
  4637. if (!buffer)
  4638. goto out;
  4639. cfg.physAddr = dma_handle;
  4640. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4641. if (mpt_config(ioc, &cfg) != 0)
  4642. goto out;
  4643. if (!buffer->NumPhysDisks)
  4644. goto out;
  4645. handle_inactive_volumes =
  4646. (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
  4647. (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
  4648. buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
  4649. buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
  4650. if (!handle_inactive_volumes)
  4651. goto out;
  4652. mutex_lock(&ioc->raid_data.inactive_list_mutex);
  4653. for (i = 0; i < buffer->NumPhysDisks; i++) {
  4654. if(mpt_raid_phys_disk_pg0(ioc,
  4655. buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
  4656. continue;
  4657. if ((component_info = kmalloc(sizeof (*component_info),
  4658. GFP_KERNEL)) == NULL)
  4659. continue;
  4660. component_info->volumeID = id;
  4661. component_info->volumeBus = channel;
  4662. component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
  4663. component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
  4664. component_info->d.PhysDiskID = phys_disk.PhysDiskID;
  4665. component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
  4666. list_add_tail(&component_info->list,
  4667. &ioc->raid_data.inactive_list);
  4668. }
  4669. mutex_unlock(&ioc->raid_data.inactive_list_mutex);
  4670. out:
  4671. if (buffer)
  4672. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
  4673. dma_handle);
  4674. }
  4675. /**
  4676. * mpt_raid_phys_disk_pg0 - returns phys disk page zero
  4677. * @ioc: Pointer to a Adapter Structure
  4678. * @phys_disk_num: io unit unique phys disk num generated by the ioc
  4679. * @phys_disk: requested payload data returned
  4680. *
  4681. * Return:
  4682. * 0 on success
  4683. * -EFAULT if read of config page header fails or data pointer not NULL
  4684. * -ENOMEM if pci_alloc failed
  4685. **/
  4686. int
  4687. mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, pRaidPhysDiskPage0_t phys_disk)
  4688. {
  4689. CONFIGPARMS cfg;
  4690. ConfigPageHeader_t hdr;
  4691. dma_addr_t dma_handle;
  4692. pRaidPhysDiskPage0_t buffer = NULL;
  4693. int rc;
  4694. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  4695. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  4696. hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
  4697. cfg.cfghdr.hdr = &hdr;
  4698. cfg.physAddr = -1;
  4699. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4700. if (mpt_config(ioc, &cfg) != 0) {
  4701. rc = -EFAULT;
  4702. goto out;
  4703. }
  4704. if (!hdr.PageLength) {
  4705. rc = -EFAULT;
  4706. goto out;
  4707. }
  4708. buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
  4709. &dma_handle);
  4710. if (!buffer) {
  4711. rc = -ENOMEM;
  4712. goto out;
  4713. }
  4714. cfg.physAddr = dma_handle;
  4715. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4716. cfg.pageAddr = phys_disk_num;
  4717. if (mpt_config(ioc, &cfg) != 0) {
  4718. rc = -EFAULT;
  4719. goto out;
  4720. }
  4721. rc = 0;
  4722. memcpy(phys_disk, buffer, sizeof(*buffer));
  4723. phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
  4724. out:
  4725. if (buffer)
  4726. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
  4727. dma_handle);
  4728. return rc;
  4729. }
  4730. /**
  4731. * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
  4732. * @ioc: Pointer to a Adapter Strucutre
  4733. *
  4734. * Return:
  4735. * 0 on success
  4736. * -EFAULT if read of config page header fails or data pointer not NULL
  4737. * -ENOMEM if pci_alloc failed
  4738. **/
  4739. int
  4740. mpt_findImVolumes(MPT_ADAPTER *ioc)
  4741. {
  4742. IOCPage2_t *pIoc2;
  4743. u8 *mem;
  4744. dma_addr_t ioc2_dma;
  4745. CONFIGPARMS cfg;
  4746. ConfigPageHeader_t header;
  4747. int rc = 0;
  4748. int iocpage2sz;
  4749. int i;
  4750. if (!ioc->ir_firmware)
  4751. return 0;
  4752. /* Free the old page
  4753. */
  4754. kfree(ioc->raid_data.pIocPg2);
  4755. ioc->raid_data.pIocPg2 = NULL;
  4756. mpt_inactive_raid_list_free(ioc);
  4757. /* Read IOCP2 header then the page.
  4758. */
  4759. header.PageVersion = 0;
  4760. header.PageLength = 0;
  4761. header.PageNumber = 2;
  4762. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  4763. cfg.cfghdr.hdr = &header;
  4764. cfg.physAddr = -1;
  4765. cfg.pageAddr = 0;
  4766. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4767. cfg.dir = 0;
  4768. cfg.timeout = 0;
  4769. if (mpt_config(ioc, &cfg) != 0)
  4770. return -EFAULT;
  4771. if (header.PageLength == 0)
  4772. return -EFAULT;
  4773. iocpage2sz = header.PageLength * 4;
  4774. pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
  4775. if (!pIoc2)
  4776. return -ENOMEM;
  4777. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4778. cfg.physAddr = ioc2_dma;
  4779. if (mpt_config(ioc, &cfg) != 0)
  4780. goto out;
  4781. mem = kmalloc(iocpage2sz, GFP_KERNEL);
  4782. if (!mem)
  4783. goto out;
  4784. memcpy(mem, (u8 *)pIoc2, iocpage2sz);
  4785. ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
  4786. mpt_read_ioc_pg_3(ioc);
  4787. for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
  4788. mpt_inactive_raid_volumes(ioc,
  4789. pIoc2->RaidVolume[i].VolumeBus,
  4790. pIoc2->RaidVolume[i].VolumeID);
  4791. out:
  4792. pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
  4793. return rc;
  4794. }
  4795. static int
  4796. mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
  4797. {
  4798. IOCPage3_t *pIoc3;
  4799. u8 *mem;
  4800. CONFIGPARMS cfg;
  4801. ConfigPageHeader_t header;
  4802. dma_addr_t ioc3_dma;
  4803. int iocpage3sz = 0;
  4804. /* Free the old page
  4805. */
  4806. kfree(ioc->raid_data.pIocPg3);
  4807. ioc->raid_data.pIocPg3 = NULL;
  4808. /* There is at least one physical disk.
  4809. * Read and save IOC Page 3
  4810. */
  4811. header.PageVersion = 0;
  4812. header.PageLength = 0;
  4813. header.PageNumber = 3;
  4814. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  4815. cfg.cfghdr.hdr = &header;
  4816. cfg.physAddr = -1;
  4817. cfg.pageAddr = 0;
  4818. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4819. cfg.dir = 0;
  4820. cfg.timeout = 0;
  4821. if (mpt_config(ioc, &cfg) != 0)
  4822. return 0;
  4823. if (header.PageLength == 0)
  4824. return 0;
  4825. /* Read Header good, alloc memory
  4826. */
  4827. iocpage3sz = header.PageLength * 4;
  4828. pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
  4829. if (!pIoc3)
  4830. return 0;
  4831. /* Read the Page and save the data
  4832. * into malloc'd memory.
  4833. */
  4834. cfg.physAddr = ioc3_dma;
  4835. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4836. if (mpt_config(ioc, &cfg) == 0) {
  4837. mem = kmalloc(iocpage3sz, GFP_KERNEL);
  4838. if (mem) {
  4839. memcpy(mem, (u8 *)pIoc3, iocpage3sz);
  4840. ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
  4841. }
  4842. }
  4843. pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
  4844. return 0;
  4845. }
  4846. static void
  4847. mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
  4848. {
  4849. IOCPage4_t *pIoc4;
  4850. CONFIGPARMS cfg;
  4851. ConfigPageHeader_t header;
  4852. dma_addr_t ioc4_dma;
  4853. int iocpage4sz;
  4854. /* Read and save IOC Page 4
  4855. */
  4856. header.PageVersion = 0;
  4857. header.PageLength = 0;
  4858. header.PageNumber = 4;
  4859. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  4860. cfg.cfghdr.hdr = &header;
  4861. cfg.physAddr = -1;
  4862. cfg.pageAddr = 0;
  4863. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4864. cfg.dir = 0;
  4865. cfg.timeout = 0;
  4866. if (mpt_config(ioc, &cfg) != 0)
  4867. return;
  4868. if (header.PageLength == 0)
  4869. return;
  4870. if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
  4871. iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
  4872. pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
  4873. if (!pIoc4)
  4874. return;
  4875. ioc->alloc_total += iocpage4sz;
  4876. } else {
  4877. ioc4_dma = ioc->spi_data.IocPg4_dma;
  4878. iocpage4sz = ioc->spi_data.IocPg4Sz;
  4879. }
  4880. /* Read the Page into dma memory.
  4881. */
  4882. cfg.physAddr = ioc4_dma;
  4883. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4884. if (mpt_config(ioc, &cfg) == 0) {
  4885. ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
  4886. ioc->spi_data.IocPg4_dma = ioc4_dma;
  4887. ioc->spi_data.IocPg4Sz = iocpage4sz;
  4888. } else {
  4889. pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
  4890. ioc->spi_data.pIocPg4 = NULL;
  4891. ioc->alloc_total -= iocpage4sz;
  4892. }
  4893. }
  4894. static void
  4895. mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
  4896. {
  4897. IOCPage1_t *pIoc1;
  4898. CONFIGPARMS cfg;
  4899. ConfigPageHeader_t header;
  4900. dma_addr_t ioc1_dma;
  4901. int iocpage1sz = 0;
  4902. u32 tmp;
  4903. /* Check the Coalescing Timeout in IOC Page 1
  4904. */
  4905. header.PageVersion = 0;
  4906. header.PageLength = 0;
  4907. header.PageNumber = 1;
  4908. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  4909. cfg.cfghdr.hdr = &header;
  4910. cfg.physAddr = -1;
  4911. cfg.pageAddr = 0;
  4912. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4913. cfg.dir = 0;
  4914. cfg.timeout = 0;
  4915. if (mpt_config(ioc, &cfg) != 0)
  4916. return;
  4917. if (header.PageLength == 0)
  4918. return;
  4919. /* Read Header good, alloc memory
  4920. */
  4921. iocpage1sz = header.PageLength * 4;
  4922. pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
  4923. if (!pIoc1)
  4924. return;
  4925. /* Read the Page and check coalescing timeout
  4926. */
  4927. cfg.physAddr = ioc1_dma;
  4928. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4929. if (mpt_config(ioc, &cfg) == 0) {
  4930. tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
  4931. if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
  4932. tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
  4933. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
  4934. ioc->name, tmp));
  4935. if (tmp > MPT_COALESCING_TIMEOUT) {
  4936. pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
  4937. /* Write NVRAM and current
  4938. */
  4939. cfg.dir = 1;
  4940. cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
  4941. if (mpt_config(ioc, &cfg) == 0) {
  4942. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
  4943. ioc->name, MPT_COALESCING_TIMEOUT));
  4944. cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
  4945. if (mpt_config(ioc, &cfg) == 0) {
  4946. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4947. "Reset NVRAM Coalescing Timeout to = %d\n",
  4948. ioc->name, MPT_COALESCING_TIMEOUT));
  4949. } else {
  4950. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4951. "Reset NVRAM Coalescing Timeout Failed\n",
  4952. ioc->name));
  4953. }
  4954. } else {
  4955. dprintk(ioc, printk(MYIOC_s_WARN_FMT
  4956. "Reset of Current Coalescing Timeout Failed!\n",
  4957. ioc->name));
  4958. }
  4959. }
  4960. } else {
  4961. dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
  4962. }
  4963. }
  4964. pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
  4965. return;
  4966. }
  4967. static void
  4968. mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
  4969. {
  4970. CONFIGPARMS cfg;
  4971. ConfigPageHeader_t hdr;
  4972. dma_addr_t buf_dma;
  4973. ManufacturingPage0_t *pbuf = NULL;
  4974. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  4975. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  4976. hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
  4977. cfg.cfghdr.hdr = &hdr;
  4978. cfg.physAddr = -1;
  4979. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4980. cfg.timeout = 10;
  4981. if (mpt_config(ioc, &cfg) != 0)
  4982. goto out;
  4983. if (!cfg.cfghdr.hdr->PageLength)
  4984. goto out;
  4985. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4986. pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
  4987. if (!pbuf)
  4988. goto out;
  4989. cfg.physAddr = buf_dma;
  4990. if (mpt_config(ioc, &cfg) != 0)
  4991. goto out;
  4992. memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
  4993. memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
  4994. memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
  4995. out:
  4996. if (pbuf)
  4997. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
  4998. }
  4999. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5000. /**
  5001. * SendEventNotification - Send EventNotification (on or off) request to adapter
  5002. * @ioc: Pointer to MPT_ADAPTER structure
  5003. * @EvSwitch: Event switch flags
  5004. */
  5005. static int
  5006. SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch)
  5007. {
  5008. EventNotification_t *evnp;
  5009. evnp = (EventNotification_t *) mpt_get_msg_frame(mpt_base_index, ioc);
  5010. if (evnp == NULL) {
  5011. devtverboseprintk(ioc, printk(MYIOC_s_WARN_FMT "Unable to allocate event request frame!\n",
  5012. ioc->name));
  5013. return 0;
  5014. }
  5015. memset(evnp, 0, sizeof(*evnp));
  5016. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventNotification (%d) request %p\n", ioc->name, EvSwitch, evnp));
  5017. evnp->Function = MPI_FUNCTION_EVENT_NOTIFICATION;
  5018. evnp->ChainOffset = 0;
  5019. evnp->MsgFlags = 0;
  5020. evnp->Switch = EvSwitch;
  5021. mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)evnp);
  5022. return 0;
  5023. }
  5024. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5025. /**
  5026. * SendEventAck - Send EventAck request to MPT adapter.
  5027. * @ioc: Pointer to MPT_ADAPTER structure
  5028. * @evnp: Pointer to original EventNotification request
  5029. */
  5030. static int
  5031. SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
  5032. {
  5033. EventAck_t *pAck;
  5034. if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
  5035. dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
  5036. ioc->name,__func__));
  5037. return -1;
  5038. }
  5039. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
  5040. pAck->Function = MPI_FUNCTION_EVENT_ACK;
  5041. pAck->ChainOffset = 0;
  5042. pAck->Reserved[0] = pAck->Reserved[1] = 0;
  5043. pAck->MsgFlags = 0;
  5044. pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
  5045. pAck->Event = evnp->Event;
  5046. pAck->EventContext = evnp->EventContext;
  5047. mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
  5048. return 0;
  5049. }
  5050. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5051. /**
  5052. * mpt_config - Generic function to issue config message
  5053. * @ioc: Pointer to an adapter structure
  5054. * @pCfg: Pointer to a configuration structure. Struct contains
  5055. * action, page address, direction, physical address
  5056. * and pointer to a configuration page header
  5057. * Page header is updated.
  5058. *
  5059. * Returns 0 for success
  5060. * -EPERM if not allowed due to ISR context
  5061. * -EAGAIN if no msg frames currently available
  5062. * -EFAULT for non-successful reply or no reply (timeout)
  5063. */
  5064. int
  5065. mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
  5066. {
  5067. Config_t *pReq;
  5068. ConfigExtendedPageHeader_t *pExtHdr = NULL;
  5069. MPT_FRAME_HDR *mf;
  5070. unsigned long flags;
  5071. int ii, rc;
  5072. int flagsLength;
  5073. int in_isr;
  5074. /* Prevent calling wait_event() (below), if caller happens
  5075. * to be in ISR context, because that is fatal!
  5076. */
  5077. in_isr = in_interrupt();
  5078. if (in_isr) {
  5079. dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
  5080. ioc->name));
  5081. return -EPERM;
  5082. }
  5083. /* Get and Populate a free Frame
  5084. */
  5085. if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
  5086. dcprintk(ioc, printk(MYIOC_s_WARN_FMT "mpt_config: no msg frames!\n",
  5087. ioc->name));
  5088. return -EAGAIN;
  5089. }
  5090. pReq = (Config_t *)mf;
  5091. pReq->Action = pCfg->action;
  5092. pReq->Reserved = 0;
  5093. pReq->ChainOffset = 0;
  5094. pReq->Function = MPI_FUNCTION_CONFIG;
  5095. /* Assume page type is not extended and clear "reserved" fields. */
  5096. pReq->ExtPageLength = 0;
  5097. pReq->ExtPageType = 0;
  5098. pReq->MsgFlags = 0;
  5099. for (ii=0; ii < 8; ii++)
  5100. pReq->Reserved2[ii] = 0;
  5101. pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
  5102. pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
  5103. pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
  5104. pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
  5105. if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
  5106. pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
  5107. pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
  5108. pReq->ExtPageType = pExtHdr->ExtPageType;
  5109. pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
  5110. /* Page Length must be treated as a reserved field for the extended header. */
  5111. pReq->Header.PageLength = 0;
  5112. }
  5113. pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
  5114. /* Add a SGE to the config request.
  5115. */
  5116. if (pCfg->dir)
  5117. flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
  5118. else
  5119. flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
  5120. if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
  5121. flagsLength |= pExtHdr->ExtPageLength * 4;
  5122. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Config request type %d, page %d and action %d\n",
  5123. ioc->name, pReq->ExtPageType, pReq->Header.PageNumber, pReq->Action));
  5124. }
  5125. else {
  5126. flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
  5127. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Config request type %d, page %d and action %d\n",
  5128. ioc->name, pReq->Header.PageType, pReq->Header.PageNumber, pReq->Action));
  5129. }
  5130. mpt_add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
  5131. /* Append pCfg pointer to end of mf
  5132. */
  5133. *((void **) (((u8 *) mf) + (ioc->req_sz - sizeof(void *)))) = (void *) pCfg;
  5134. /* Initalize the timer
  5135. */
  5136. init_timer(&pCfg->timer);
  5137. pCfg->timer.data = (unsigned long) ioc;
  5138. pCfg->timer.function = mpt_timer_expired;
  5139. pCfg->wait_done = 0;
  5140. /* Set the timer; ensure 10 second minimum */
  5141. if (pCfg->timeout < 10)
  5142. pCfg->timer.expires = jiffies + HZ*10;
  5143. else
  5144. pCfg->timer.expires = jiffies + HZ*pCfg->timeout;
  5145. /* Add to end of Q, set timer and then issue this command */
  5146. spin_lock_irqsave(&ioc->FreeQlock, flags);
  5147. list_add_tail(&pCfg->linkage, &ioc->configQ);
  5148. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  5149. add_timer(&pCfg->timer);
  5150. mpt_put_msg_frame(mpt_base_index, ioc, mf);
  5151. wait_event(mpt_waitq, pCfg->wait_done);
  5152. /* mf has been freed - do not access */
  5153. rc = pCfg->status;
  5154. return rc;
  5155. }
  5156. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5157. /**
  5158. * mpt_timer_expired - Callback for timer process.
  5159. * Used only internal config functionality.
  5160. * @data: Pointer to MPT_SCSI_HOST recast as an unsigned long
  5161. */
  5162. static void
  5163. mpt_timer_expired(unsigned long data)
  5164. {
  5165. MPT_ADAPTER *ioc = (MPT_ADAPTER *) data;
  5166. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_timer_expired! \n", ioc->name));
  5167. /* Perform a FW reload */
  5168. if (mpt_HardResetHandler(ioc, NO_SLEEP) < 0)
  5169. printk(MYIOC_s_WARN_FMT "Firmware Reload FAILED!\n", ioc->name);
  5170. /* No more processing.
  5171. * Hard reset clean-up will wake up
  5172. * process and free all resources.
  5173. */
  5174. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_timer_expired complete!\n", ioc->name));
  5175. return;
  5176. }
  5177. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5178. /**
  5179. * mpt_ioc_reset - Base cleanup for hard reset
  5180. * @ioc: Pointer to the adapter structure
  5181. * @reset_phase: Indicates pre- or post-reset functionality
  5182. *
  5183. * Remark: Frees resources with internally generated commands.
  5184. */
  5185. static int
  5186. mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
  5187. {
  5188. CONFIGPARMS *pCfg;
  5189. unsigned long flags;
  5190. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5191. ": IOC %s_reset routed to MPT base driver!\n",
  5192. ioc->name, reset_phase==MPT_IOC_SETUP_RESET ? "setup" : (
  5193. reset_phase==MPT_IOC_PRE_RESET ? "pre" : "post")));
  5194. if (reset_phase == MPT_IOC_SETUP_RESET) {
  5195. ;
  5196. } else if (reset_phase == MPT_IOC_PRE_RESET) {
  5197. /* If the internal config Q is not empty -
  5198. * delete timer. MF resources will be freed when
  5199. * the FIFO's are primed.
  5200. */
  5201. spin_lock_irqsave(&ioc->FreeQlock, flags);
  5202. list_for_each_entry(pCfg, &ioc->configQ, linkage)
  5203. del_timer(&pCfg->timer);
  5204. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  5205. } else {
  5206. CONFIGPARMS *pNext;
  5207. /* Search the configQ for internal commands.
  5208. * Flush the Q, and wake up all suspended threads.
  5209. */
  5210. spin_lock_irqsave(&ioc->FreeQlock, flags);
  5211. list_for_each_entry_safe(pCfg, pNext, &ioc->configQ, linkage) {
  5212. list_del(&pCfg->linkage);
  5213. pCfg->status = MPT_CONFIG_ERROR;
  5214. pCfg->wait_done = 1;
  5215. wake_up(&mpt_waitq);
  5216. }
  5217. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  5218. }
  5219. return 1; /* currently means nothing really */
  5220. }
  5221. #ifdef CONFIG_PROC_FS /* { */
  5222. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5223. /*
  5224. * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
  5225. */
  5226. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5227. /**
  5228. * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
  5229. *
  5230. * Returns 0 for success, non-zero for failure.
  5231. */
  5232. static int
  5233. procmpt_create(void)
  5234. {
  5235. struct proc_dir_entry *ent;
  5236. mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
  5237. if (mpt_proc_root_dir == NULL)
  5238. return -ENOTDIR;
  5239. ent = create_proc_entry("summary", S_IFREG|S_IRUGO, mpt_proc_root_dir);
  5240. if (ent)
  5241. ent->read_proc = procmpt_summary_read;
  5242. ent = create_proc_entry("version", S_IFREG|S_IRUGO, mpt_proc_root_dir);
  5243. if (ent)
  5244. ent->read_proc = procmpt_version_read;
  5245. return 0;
  5246. }
  5247. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5248. /**
  5249. * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
  5250. *
  5251. * Returns 0 for success, non-zero for failure.
  5252. */
  5253. static void
  5254. procmpt_destroy(void)
  5255. {
  5256. remove_proc_entry("version", mpt_proc_root_dir);
  5257. remove_proc_entry("summary", mpt_proc_root_dir);
  5258. remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
  5259. }
  5260. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5261. /**
  5262. * procmpt_summary_read - Handle read request of a summary file
  5263. * @buf: Pointer to area to write information
  5264. * @start: Pointer to start pointer
  5265. * @offset: Offset to start writing
  5266. * @request: Amount of read data requested
  5267. * @eof: Pointer to EOF integer
  5268. * @data: Pointer
  5269. *
  5270. * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
  5271. * Returns number of characters written to process performing the read.
  5272. */
  5273. static int
  5274. procmpt_summary_read(char *buf, char **start, off_t offset, int request, int *eof, void *data)
  5275. {
  5276. MPT_ADAPTER *ioc;
  5277. char *out = buf;
  5278. int len;
  5279. if (data) {
  5280. int more = 0;
  5281. ioc = data;
  5282. mpt_print_ioc_summary(ioc, out, &more, 0, 1);
  5283. out += more;
  5284. } else {
  5285. list_for_each_entry(ioc, &ioc_list, list) {
  5286. int more = 0;
  5287. mpt_print_ioc_summary(ioc, out, &more, 0, 1);
  5288. out += more;
  5289. if ((out-buf) >= request)
  5290. break;
  5291. }
  5292. }
  5293. len = out - buf;
  5294. MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len);
  5295. }
  5296. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5297. /**
  5298. * procmpt_version_read - Handle read request from /proc/mpt/version.
  5299. * @buf: Pointer to area to write information
  5300. * @start: Pointer to start pointer
  5301. * @offset: Offset to start writing
  5302. * @request: Amount of read data requested
  5303. * @eof: Pointer to EOF integer
  5304. * @data: Pointer
  5305. *
  5306. * Returns number of characters written to process performing the read.
  5307. */
  5308. static int
  5309. procmpt_version_read(char *buf, char **start, off_t offset, int request, int *eof, void *data)
  5310. {
  5311. u8 cb_idx;
  5312. int scsi, fc, sas, lan, ctl, targ, dmp;
  5313. char *drvname;
  5314. int len;
  5315. len = sprintf(buf, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
  5316. len += sprintf(buf+len, " Fusion MPT base driver\n");
  5317. scsi = fc = sas = lan = ctl = targ = dmp = 0;
  5318. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  5319. drvname = NULL;
  5320. if (MptCallbacks[cb_idx]) {
  5321. switch (MptDriverClass[cb_idx]) {
  5322. case MPTSPI_DRIVER:
  5323. if (!scsi++) drvname = "SPI host";
  5324. break;
  5325. case MPTFC_DRIVER:
  5326. if (!fc++) drvname = "FC host";
  5327. break;
  5328. case MPTSAS_DRIVER:
  5329. if (!sas++) drvname = "SAS host";
  5330. break;
  5331. case MPTLAN_DRIVER:
  5332. if (!lan++) drvname = "LAN";
  5333. break;
  5334. case MPTSTM_DRIVER:
  5335. if (!targ++) drvname = "SCSI target";
  5336. break;
  5337. case MPTCTL_DRIVER:
  5338. if (!ctl++) drvname = "ioctl";
  5339. break;
  5340. }
  5341. if (drvname)
  5342. len += sprintf(buf+len, " Fusion MPT %s driver\n", drvname);
  5343. }
  5344. }
  5345. MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len);
  5346. }
  5347. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5348. /**
  5349. * procmpt_iocinfo_read - Handle read request from /proc/mpt/iocN/info.
  5350. * @buf: Pointer to area to write information
  5351. * @start: Pointer to start pointer
  5352. * @offset: Offset to start writing
  5353. * @request: Amount of read data requested
  5354. * @eof: Pointer to EOF integer
  5355. * @data: Pointer
  5356. *
  5357. * Returns number of characters written to process performing the read.
  5358. */
  5359. static int
  5360. procmpt_iocinfo_read(char *buf, char **start, off_t offset, int request, int *eof, void *data)
  5361. {
  5362. MPT_ADAPTER *ioc = data;
  5363. int len;
  5364. char expVer[32];
  5365. int sz;
  5366. int p;
  5367. mpt_get_fw_exp_ver(expVer, ioc);
  5368. len = sprintf(buf, "%s:", ioc->name);
  5369. if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
  5370. len += sprintf(buf+len, " (f/w download boot flag set)");
  5371. // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
  5372. // len += sprintf(buf+len, " CONFIG_CHECKSUM_FAIL!");
  5373. len += sprintf(buf+len, "\n ProductID = 0x%04x (%s)\n",
  5374. ioc->facts.ProductID,
  5375. ioc->prod_name);
  5376. len += sprintf(buf+len, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
  5377. if (ioc->facts.FWImageSize)
  5378. len += sprintf(buf+len, " (fw_size=%d)", ioc->facts.FWImageSize);
  5379. len += sprintf(buf+len, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
  5380. len += sprintf(buf+len, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
  5381. len += sprintf(buf+len, " EventState = 0x%02x\n", ioc->facts.EventState);
  5382. len += sprintf(buf+len, " CurrentHostMfaHighAddr = 0x%08x\n",
  5383. ioc->facts.CurrentHostMfaHighAddr);
  5384. len += sprintf(buf+len, " CurrentSenseBufferHighAddr = 0x%08x\n",
  5385. ioc->facts.CurrentSenseBufferHighAddr);
  5386. len += sprintf(buf+len, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
  5387. len += sprintf(buf+len, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
  5388. len += sprintf(buf+len, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
  5389. (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
  5390. /*
  5391. * Rounding UP to nearest 4-kB boundary here...
  5392. */
  5393. sz = (ioc->req_sz * ioc->req_depth) + 128;
  5394. sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
  5395. len += sprintf(buf+len, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
  5396. ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
  5397. len += sprintf(buf+len, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
  5398. 4*ioc->facts.RequestFrameSize,
  5399. ioc->facts.GlobalCredits);
  5400. len += sprintf(buf+len, " Frames @ 0x%p (Dma @ 0x%p)\n",
  5401. (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
  5402. sz = (ioc->reply_sz * ioc->reply_depth) + 128;
  5403. len += sprintf(buf+len, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
  5404. ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
  5405. len += sprintf(buf+len, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
  5406. ioc->facts.CurReplyFrameSize,
  5407. ioc->facts.ReplyQueueDepth);
  5408. len += sprintf(buf+len, " MaxDevices = %d\n",
  5409. (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
  5410. len += sprintf(buf+len, " MaxBuses = %d\n", ioc->facts.MaxBuses);
  5411. /* per-port info */
  5412. for (p=0; p < ioc->facts.NumberOfPorts; p++) {
  5413. len += sprintf(buf+len, " PortNumber = %d (of %d)\n",
  5414. p+1,
  5415. ioc->facts.NumberOfPorts);
  5416. if (ioc->bus_type == FC) {
  5417. if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
  5418. u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  5419. len += sprintf(buf+len, " LanAddr = %02X:%02X:%02X:%02X:%02X:%02X\n",
  5420. a[5], a[4], a[3], a[2], a[1], a[0]);
  5421. }
  5422. len += sprintf(buf+len, " WWN = %08X%08X:%08X%08X\n",
  5423. ioc->fc_port_page0[p].WWNN.High,
  5424. ioc->fc_port_page0[p].WWNN.Low,
  5425. ioc->fc_port_page0[p].WWPN.High,
  5426. ioc->fc_port_page0[p].WWPN.Low);
  5427. }
  5428. }
  5429. MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len);
  5430. }
  5431. #endif /* CONFIG_PROC_FS } */
  5432. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5433. static void
  5434. mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
  5435. {
  5436. buf[0] ='\0';
  5437. if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
  5438. sprintf(buf, " (Exp %02d%02d)",
  5439. (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
  5440. (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
  5441. /* insider hack! */
  5442. if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
  5443. strcat(buf, " [MDBG]");
  5444. }
  5445. }
  5446. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5447. /**
  5448. * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
  5449. * @ioc: Pointer to MPT_ADAPTER structure
  5450. * @buffer: Pointer to buffer where IOC summary info should be written
  5451. * @size: Pointer to number of bytes we wrote (set by this routine)
  5452. * @len: Offset at which to start writing in buffer
  5453. * @showlan: Display LAN stuff?
  5454. *
  5455. * This routine writes (english readable) ASCII text, which represents
  5456. * a summary of IOC information, to a buffer.
  5457. */
  5458. void
  5459. mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
  5460. {
  5461. char expVer[32];
  5462. int y;
  5463. mpt_get_fw_exp_ver(expVer, ioc);
  5464. /*
  5465. * Shorter summary of attached ioc's...
  5466. */
  5467. y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
  5468. ioc->name,
  5469. ioc->prod_name,
  5470. MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
  5471. ioc->facts.FWVersion.Word,
  5472. expVer,
  5473. ioc->facts.NumberOfPorts,
  5474. ioc->req_depth);
  5475. if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
  5476. u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  5477. y += sprintf(buffer+len+y, ", LanAddr=%02X:%02X:%02X:%02X:%02X:%02X",
  5478. a[5], a[4], a[3], a[2], a[1], a[0]);
  5479. }
  5480. y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
  5481. if (!ioc->active)
  5482. y += sprintf(buffer+len+y, " (disabled)");
  5483. y += sprintf(buffer+len+y, "\n");
  5484. *size = y;
  5485. }
  5486. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5487. /*
  5488. * Reset Handling
  5489. */
  5490. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5491. /**
  5492. * mpt_HardResetHandler - Generic reset handler
  5493. * @ioc: Pointer to MPT_ADAPTER structure
  5494. * @sleepFlag: Indicates if sleep or schedule must be called.
  5495. *
  5496. * Issues SCSI Task Management call based on input arg values.
  5497. * If TaskMgmt fails, returns associated SCSI request.
  5498. *
  5499. * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
  5500. * or a non-interrupt thread. In the former, must not call schedule().
  5501. *
  5502. * Note: A return of -1 is a FATAL error case, as it means a
  5503. * FW reload/initialization failed.
  5504. *
  5505. * Returns 0 for SUCCESS or -1 if FAILED.
  5506. */
  5507. int
  5508. mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
  5509. {
  5510. int rc;
  5511. unsigned long flags;
  5512. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
  5513. #ifdef MFCNT
  5514. printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
  5515. printk("MF count 0x%x !\n", ioc->mfcnt);
  5516. #endif
  5517. /* Reset the adapter. Prevent more than 1 call to
  5518. * mpt_do_ioc_recovery at any instant in time.
  5519. */
  5520. spin_lock_irqsave(&ioc->diagLock, flags);
  5521. if ((ioc->diagPending) || (ioc->alt_ioc && ioc->alt_ioc->diagPending)){
  5522. spin_unlock_irqrestore(&ioc->diagLock, flags);
  5523. return 0;
  5524. } else {
  5525. ioc->diagPending = 1;
  5526. }
  5527. spin_unlock_irqrestore(&ioc->diagLock, flags);
  5528. /* FIXME: If do_ioc_recovery fails, repeat....
  5529. */
  5530. /* The SCSI driver needs to adjust timeouts on all current
  5531. * commands prior to the diagnostic reset being issued.
  5532. * Prevents timeouts occurring during a diagnostic reset...very bad.
  5533. * For all other protocol drivers, this is a no-op.
  5534. */
  5535. {
  5536. u8 cb_idx;
  5537. int r = 0;
  5538. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  5539. if (MptResetHandlers[cb_idx]) {
  5540. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Calling IOC reset_setup handler #%d\n",
  5541. ioc->name, cb_idx));
  5542. r += mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
  5543. if (ioc->alt_ioc) {
  5544. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Calling alt-%s setup reset handler #%d\n",
  5545. ioc->name, ioc->alt_ioc->name, cb_idx));
  5546. r += mpt_signal_reset(cb_idx, ioc->alt_ioc, MPT_IOC_SETUP_RESET);
  5547. }
  5548. }
  5549. }
  5550. }
  5551. if ((rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag)) != 0) {
  5552. printk(MYIOC_s_WARN_FMT "Cannot recover rc = %d!\n", ioc->name, rc);
  5553. }
  5554. ioc->reload_fw = 0;
  5555. if (ioc->alt_ioc)
  5556. ioc->alt_ioc->reload_fw = 0;
  5557. spin_lock_irqsave(&ioc->diagLock, flags);
  5558. ioc->diagPending = 0;
  5559. if (ioc->alt_ioc)
  5560. ioc->alt_ioc->diagPending = 0;
  5561. spin_unlock_irqrestore(&ioc->diagLock, flags);
  5562. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler rc = %d!\n", ioc->name, rc));
  5563. return rc;
  5564. }
  5565. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5566. static void
  5567. EventDescriptionStr(u8 event, u32 evData0, char *evStr)
  5568. {
  5569. char *ds = NULL;
  5570. switch(event) {
  5571. case MPI_EVENT_NONE:
  5572. ds = "None";
  5573. break;
  5574. case MPI_EVENT_LOG_DATA:
  5575. ds = "Log Data";
  5576. break;
  5577. case MPI_EVENT_STATE_CHANGE:
  5578. ds = "State Change";
  5579. break;
  5580. case MPI_EVENT_UNIT_ATTENTION:
  5581. ds = "Unit Attention";
  5582. break;
  5583. case MPI_EVENT_IOC_BUS_RESET:
  5584. ds = "IOC Bus Reset";
  5585. break;
  5586. case MPI_EVENT_EXT_BUS_RESET:
  5587. ds = "External Bus Reset";
  5588. break;
  5589. case MPI_EVENT_RESCAN:
  5590. ds = "Bus Rescan Event";
  5591. break;
  5592. case MPI_EVENT_LINK_STATUS_CHANGE:
  5593. if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
  5594. ds = "Link Status(FAILURE) Change";
  5595. else
  5596. ds = "Link Status(ACTIVE) Change";
  5597. break;
  5598. case MPI_EVENT_LOOP_STATE_CHANGE:
  5599. if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
  5600. ds = "Loop State(LIP) Change";
  5601. else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
  5602. ds = "Loop State(LPE) Change"; /* ??? */
  5603. else
  5604. ds = "Loop State(LPB) Change"; /* ??? */
  5605. break;
  5606. case MPI_EVENT_LOGOUT:
  5607. ds = "Logout";
  5608. break;
  5609. case MPI_EVENT_EVENT_CHANGE:
  5610. if (evData0)
  5611. ds = "Events ON";
  5612. else
  5613. ds = "Events OFF";
  5614. break;
  5615. case MPI_EVENT_INTEGRATED_RAID:
  5616. {
  5617. u8 ReasonCode = (u8)(evData0 >> 16);
  5618. switch (ReasonCode) {
  5619. case MPI_EVENT_RAID_RC_VOLUME_CREATED :
  5620. ds = "Integrated Raid: Volume Created";
  5621. break;
  5622. case MPI_EVENT_RAID_RC_VOLUME_DELETED :
  5623. ds = "Integrated Raid: Volume Deleted";
  5624. break;
  5625. case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
  5626. ds = "Integrated Raid: Volume Settings Changed";
  5627. break;
  5628. case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
  5629. ds = "Integrated Raid: Volume Status Changed";
  5630. break;
  5631. case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
  5632. ds = "Integrated Raid: Volume Physdisk Changed";
  5633. break;
  5634. case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
  5635. ds = "Integrated Raid: Physdisk Created";
  5636. break;
  5637. case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
  5638. ds = "Integrated Raid: Physdisk Deleted";
  5639. break;
  5640. case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
  5641. ds = "Integrated Raid: Physdisk Settings Changed";
  5642. break;
  5643. case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
  5644. ds = "Integrated Raid: Physdisk Status Changed";
  5645. break;
  5646. case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
  5647. ds = "Integrated Raid: Domain Validation Needed";
  5648. break;
  5649. case MPI_EVENT_RAID_RC_SMART_DATA :
  5650. ds = "Integrated Raid; Smart Data";
  5651. break;
  5652. case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
  5653. ds = "Integrated Raid: Replace Action Started";
  5654. break;
  5655. default:
  5656. ds = "Integrated Raid";
  5657. break;
  5658. }
  5659. break;
  5660. }
  5661. case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
  5662. ds = "SCSI Device Status Change";
  5663. break;
  5664. case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
  5665. {
  5666. u8 id = (u8)(evData0);
  5667. u8 channel = (u8)(evData0 >> 8);
  5668. u8 ReasonCode = (u8)(evData0 >> 16);
  5669. switch (ReasonCode) {
  5670. case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
  5671. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5672. "SAS Device Status Change: Added: "
  5673. "id=%d channel=%d", id, channel);
  5674. break;
  5675. case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
  5676. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5677. "SAS Device Status Change: Deleted: "
  5678. "id=%d channel=%d", id, channel);
  5679. break;
  5680. case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
  5681. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5682. "SAS Device Status Change: SMART Data: "
  5683. "id=%d channel=%d", id, channel);
  5684. break;
  5685. case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
  5686. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5687. "SAS Device Status Change: No Persistancy: "
  5688. "id=%d channel=%d", id, channel);
  5689. break;
  5690. case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
  5691. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5692. "SAS Device Status Change: Unsupported Device "
  5693. "Discovered : id=%d channel=%d", id, channel);
  5694. break;
  5695. case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
  5696. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5697. "SAS Device Status Change: Internal Device "
  5698. "Reset : id=%d channel=%d", id, channel);
  5699. break;
  5700. case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
  5701. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5702. "SAS Device Status Change: Internal Task "
  5703. "Abort : id=%d channel=%d", id, channel);
  5704. break;
  5705. case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
  5706. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5707. "SAS Device Status Change: Internal Abort "
  5708. "Task Set : id=%d channel=%d", id, channel);
  5709. break;
  5710. case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
  5711. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5712. "SAS Device Status Change: Internal Clear "
  5713. "Task Set : id=%d channel=%d", id, channel);
  5714. break;
  5715. case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
  5716. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5717. "SAS Device Status Change: Internal Query "
  5718. "Task : id=%d channel=%d", id, channel);
  5719. break;
  5720. default:
  5721. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5722. "SAS Device Status Change: Unknown: "
  5723. "id=%d channel=%d", id, channel);
  5724. break;
  5725. }
  5726. break;
  5727. }
  5728. case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
  5729. ds = "Bus Timer Expired";
  5730. break;
  5731. case MPI_EVENT_QUEUE_FULL:
  5732. {
  5733. u16 curr_depth = (u16)(evData0 >> 16);
  5734. u8 channel = (u8)(evData0 >> 8);
  5735. u8 id = (u8)(evData0);
  5736. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5737. "Queue Full: channel=%d id=%d depth=%d",
  5738. channel, id, curr_depth);
  5739. break;
  5740. }
  5741. case MPI_EVENT_SAS_SES:
  5742. ds = "SAS SES Event";
  5743. break;
  5744. case MPI_EVENT_PERSISTENT_TABLE_FULL:
  5745. ds = "Persistent Table Full";
  5746. break;
  5747. case MPI_EVENT_SAS_PHY_LINK_STATUS:
  5748. {
  5749. u8 LinkRates = (u8)(evData0 >> 8);
  5750. u8 PhyNumber = (u8)(evData0);
  5751. LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
  5752. MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
  5753. switch (LinkRates) {
  5754. case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
  5755. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5756. "SAS PHY Link Status: Phy=%d:"
  5757. " Rate Unknown",PhyNumber);
  5758. break;
  5759. case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
  5760. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5761. "SAS PHY Link Status: Phy=%d:"
  5762. " Phy Disabled",PhyNumber);
  5763. break;
  5764. case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
  5765. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5766. "SAS PHY Link Status: Phy=%d:"
  5767. " Failed Speed Nego",PhyNumber);
  5768. break;
  5769. case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
  5770. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5771. "SAS PHY Link Status: Phy=%d:"
  5772. " Sata OOB Completed",PhyNumber);
  5773. break;
  5774. case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
  5775. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5776. "SAS PHY Link Status: Phy=%d:"
  5777. " Rate 1.5 Gbps",PhyNumber);
  5778. break;
  5779. case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
  5780. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5781. "SAS PHY Link Status: Phy=%d:"
  5782. " Rate 3.0 Gpbs",PhyNumber);
  5783. break;
  5784. default:
  5785. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5786. "SAS PHY Link Status: Phy=%d", PhyNumber);
  5787. break;
  5788. }
  5789. break;
  5790. }
  5791. case MPI_EVENT_SAS_DISCOVERY_ERROR:
  5792. ds = "SAS Discovery Error";
  5793. break;
  5794. case MPI_EVENT_IR_RESYNC_UPDATE:
  5795. {
  5796. u8 resync_complete = (u8)(evData0 >> 16);
  5797. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5798. "IR Resync Update: Complete = %d:",resync_complete);
  5799. break;
  5800. }
  5801. case MPI_EVENT_IR2:
  5802. {
  5803. u8 ReasonCode = (u8)(evData0 >> 16);
  5804. switch (ReasonCode) {
  5805. case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
  5806. ds = "IR2: LD State Changed";
  5807. break;
  5808. case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
  5809. ds = "IR2: PD State Changed";
  5810. break;
  5811. case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
  5812. ds = "IR2: Bad Block Table Full";
  5813. break;
  5814. case MPI_EVENT_IR2_RC_PD_INSERTED:
  5815. ds = "IR2: PD Inserted";
  5816. break;
  5817. case MPI_EVENT_IR2_RC_PD_REMOVED:
  5818. ds = "IR2: PD Removed";
  5819. break;
  5820. case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
  5821. ds = "IR2: Foreign CFG Detected";
  5822. break;
  5823. case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
  5824. ds = "IR2: Rebuild Medium Error";
  5825. break;
  5826. default:
  5827. ds = "IR2";
  5828. break;
  5829. }
  5830. break;
  5831. }
  5832. case MPI_EVENT_SAS_DISCOVERY:
  5833. {
  5834. if (evData0)
  5835. ds = "SAS Discovery: Start";
  5836. else
  5837. ds = "SAS Discovery: Stop";
  5838. break;
  5839. }
  5840. case MPI_EVENT_LOG_ENTRY_ADDED:
  5841. ds = "SAS Log Entry Added";
  5842. break;
  5843. case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
  5844. {
  5845. u8 phy_num = (u8)(evData0);
  5846. u8 port_num = (u8)(evData0 >> 8);
  5847. u8 port_width = (u8)(evData0 >> 16);
  5848. u8 primative = (u8)(evData0 >> 24);
  5849. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5850. "SAS Broadcase Primative: phy=%d port=%d "
  5851. "width=%d primative=0x%02x",
  5852. phy_num, port_num, port_width, primative);
  5853. break;
  5854. }
  5855. case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  5856. {
  5857. u8 reason = (u8)(evData0);
  5858. u8 port_num = (u8)(evData0 >> 8);
  5859. u16 handle = le16_to_cpu(evData0 >> 16);
  5860. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5861. "SAS Initiator Device Status Change: reason=0x%02x "
  5862. "port=%d handle=0x%04x",
  5863. reason, port_num, handle);
  5864. break;
  5865. }
  5866. case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
  5867. {
  5868. u8 max_init = (u8)(evData0);
  5869. u8 current_init = (u8)(evData0 >> 8);
  5870. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5871. "SAS Initiator Device Table Overflow: max initiators=%02d "
  5872. "current initators=%02d",
  5873. max_init, current_init);
  5874. break;
  5875. }
  5876. case MPI_EVENT_SAS_SMP_ERROR:
  5877. {
  5878. u8 status = (u8)(evData0);
  5879. u8 port_num = (u8)(evData0 >> 8);
  5880. u8 result = (u8)(evData0 >> 16);
  5881. if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
  5882. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5883. "SAS SMP Error: port=%d result=0x%02x",
  5884. port_num, result);
  5885. else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
  5886. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5887. "SAS SMP Error: port=%d : CRC Error",
  5888. port_num);
  5889. else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
  5890. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5891. "SAS SMP Error: port=%d : Timeout",
  5892. port_num);
  5893. else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
  5894. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5895. "SAS SMP Error: port=%d : No Destination",
  5896. port_num);
  5897. else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
  5898. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5899. "SAS SMP Error: port=%d : Bad Destination",
  5900. port_num);
  5901. else
  5902. snprintf(evStr, EVENT_DESCR_STR_SZ,
  5903. "SAS SMP Error: port=%d : status=0x%02x",
  5904. port_num, status);
  5905. break;
  5906. }
  5907. /*
  5908. * MPT base "custom" events may be added here...
  5909. */
  5910. default:
  5911. ds = "Unknown";
  5912. break;
  5913. }
  5914. if (ds)
  5915. strncpy(evStr, ds, EVENT_DESCR_STR_SZ);
  5916. }
  5917. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5918. /**
  5919. * ProcessEventNotification - Route EventNotificationReply to all event handlers
  5920. * @ioc: Pointer to MPT_ADAPTER structure
  5921. * @pEventReply: Pointer to EventNotification reply frame
  5922. * @evHandlers: Pointer to integer, number of event handlers
  5923. *
  5924. * Routes a received EventNotificationReply to all currently registered
  5925. * event handlers.
  5926. * Returns sum of event handlers return values.
  5927. */
  5928. static int
  5929. ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
  5930. {
  5931. u16 evDataLen;
  5932. u32 evData0 = 0;
  5933. // u32 evCtx;
  5934. int ii;
  5935. u8 cb_idx;
  5936. int r = 0;
  5937. int handlers = 0;
  5938. char evStr[EVENT_DESCR_STR_SZ];
  5939. u8 event;
  5940. /*
  5941. * Do platform normalization of values
  5942. */
  5943. event = le32_to_cpu(pEventReply->Event) & 0xFF;
  5944. // evCtx = le32_to_cpu(pEventReply->EventContext);
  5945. evDataLen = le16_to_cpu(pEventReply->EventDataLength);
  5946. if (evDataLen) {
  5947. evData0 = le32_to_cpu(pEventReply->Data[0]);
  5948. }
  5949. EventDescriptionStr(event, evData0, evStr);
  5950. devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "MPT event:(%02Xh) : %s\n",
  5951. ioc->name,
  5952. event,
  5953. evStr));
  5954. #ifdef CONFIG_FUSION_LOGGING
  5955. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5956. ": Event data:\n", ioc->name));
  5957. for (ii = 0; ii < evDataLen; ii++)
  5958. devtverboseprintk(ioc, printk(" %08x",
  5959. le32_to_cpu(pEventReply->Data[ii])));
  5960. devtverboseprintk(ioc, printk("\n"));
  5961. #endif
  5962. /*
  5963. * Do general / base driver event processing
  5964. */
  5965. switch(event) {
  5966. case MPI_EVENT_EVENT_CHANGE: /* 0A */
  5967. if (evDataLen) {
  5968. u8 evState = evData0 & 0xFF;
  5969. /* CHECKME! What if evState unexpectedly says OFF (0)? */
  5970. /* Update EventState field in cached IocFacts */
  5971. if (ioc->facts.Function) {
  5972. ioc->facts.EventState = evState;
  5973. }
  5974. }
  5975. break;
  5976. case MPI_EVENT_INTEGRATED_RAID:
  5977. mptbase_raid_process_event_data(ioc,
  5978. (MpiEventDataRaid_t *)pEventReply->Data);
  5979. break;
  5980. default:
  5981. break;
  5982. }
  5983. /*
  5984. * Should this event be logged? Events are written sequentially.
  5985. * When buffer is full, start again at the top.
  5986. */
  5987. if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
  5988. int idx;
  5989. idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
  5990. ioc->events[idx].event = event;
  5991. ioc->events[idx].eventContext = ioc->eventContext;
  5992. for (ii = 0; ii < 2; ii++) {
  5993. if (ii < evDataLen)
  5994. ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
  5995. else
  5996. ioc->events[idx].data[ii] = 0;
  5997. }
  5998. ioc->eventContext++;
  5999. }
  6000. /*
  6001. * Call each currently registered protocol event handler.
  6002. */
  6003. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6004. if (MptEvHandlers[cb_idx]) {
  6005. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Routing Event to event handler #%d\n",
  6006. ioc->name, cb_idx));
  6007. r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
  6008. handlers++;
  6009. }
  6010. }
  6011. /* FIXME? Examine results here? */
  6012. /*
  6013. * If needed, send (a single) EventAck.
  6014. */
  6015. if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
  6016. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6017. "EventAck required\n",ioc->name));
  6018. if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
  6019. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
  6020. ioc->name, ii));
  6021. }
  6022. }
  6023. *evHandlers = handlers;
  6024. return r;
  6025. }
  6026. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6027. /**
  6028. * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
  6029. * @ioc: Pointer to MPT_ADAPTER structure
  6030. * @log_info: U32 LogInfo reply word from the IOC
  6031. *
  6032. * Refer to lsi/mpi_log_fc.h.
  6033. */
  6034. static void
  6035. mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
  6036. {
  6037. char *desc = "unknown";
  6038. switch (log_info & 0xFF000000) {
  6039. case MPI_IOCLOGINFO_FC_INIT_BASE:
  6040. desc = "FCP Initiator";
  6041. break;
  6042. case MPI_IOCLOGINFO_FC_TARGET_BASE:
  6043. desc = "FCP Target";
  6044. break;
  6045. case MPI_IOCLOGINFO_FC_LAN_BASE:
  6046. desc = "LAN";
  6047. break;
  6048. case MPI_IOCLOGINFO_FC_MSG_BASE:
  6049. desc = "MPI Message Layer";
  6050. break;
  6051. case MPI_IOCLOGINFO_FC_LINK_BASE:
  6052. desc = "FC Link";
  6053. break;
  6054. case MPI_IOCLOGINFO_FC_CTX_BASE:
  6055. desc = "Context Manager";
  6056. break;
  6057. case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
  6058. desc = "Invalid Field Offset";
  6059. break;
  6060. case MPI_IOCLOGINFO_FC_STATE_CHANGE:
  6061. desc = "State Change Info";
  6062. break;
  6063. }
  6064. printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
  6065. ioc->name, log_info, desc, (log_info & 0xFFFFFF));
  6066. }
  6067. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6068. /**
  6069. * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
  6070. * @ioc: Pointer to MPT_ADAPTER structure
  6071. * @log_info: U32 LogInfo word from the IOC
  6072. *
  6073. * Refer to lsi/sp_log.h.
  6074. */
  6075. static void
  6076. mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
  6077. {
  6078. u32 info = log_info & 0x00FF0000;
  6079. char *desc = "unknown";
  6080. switch (info) {
  6081. case 0x00010000:
  6082. desc = "bug! MID not found";
  6083. if (ioc->reload_fw == 0)
  6084. ioc->reload_fw++;
  6085. break;
  6086. case 0x00020000:
  6087. desc = "Parity Error";
  6088. break;
  6089. case 0x00030000:
  6090. desc = "ASYNC Outbound Overrun";
  6091. break;
  6092. case 0x00040000:
  6093. desc = "SYNC Offset Error";
  6094. break;
  6095. case 0x00050000:
  6096. desc = "BM Change";
  6097. break;
  6098. case 0x00060000:
  6099. desc = "Msg In Overflow";
  6100. break;
  6101. case 0x00070000:
  6102. desc = "DMA Error";
  6103. break;
  6104. case 0x00080000:
  6105. desc = "Outbound DMA Overrun";
  6106. break;
  6107. case 0x00090000:
  6108. desc = "Task Management";
  6109. break;
  6110. case 0x000A0000:
  6111. desc = "Device Problem";
  6112. break;
  6113. case 0x000B0000:
  6114. desc = "Invalid Phase Change";
  6115. break;
  6116. case 0x000C0000:
  6117. desc = "Untagged Table Size";
  6118. break;
  6119. }
  6120. printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
  6121. }
  6122. /* strings for sas loginfo */
  6123. static char *originator_str[] = {
  6124. "IOP", /* 00h */
  6125. "PL", /* 01h */
  6126. "IR" /* 02h */
  6127. };
  6128. static char *iop_code_str[] = {
  6129. NULL, /* 00h */
  6130. "Invalid SAS Address", /* 01h */
  6131. NULL, /* 02h */
  6132. "Invalid Page", /* 03h */
  6133. "Diag Message Error", /* 04h */
  6134. "Task Terminated", /* 05h */
  6135. "Enclosure Management", /* 06h */
  6136. "Target Mode" /* 07h */
  6137. };
  6138. static char *pl_code_str[] = {
  6139. NULL, /* 00h */
  6140. "Open Failure", /* 01h */
  6141. "Invalid Scatter Gather List", /* 02h */
  6142. "Wrong Relative Offset or Frame Length", /* 03h */
  6143. "Frame Transfer Error", /* 04h */
  6144. "Transmit Frame Connected Low", /* 05h */
  6145. "SATA Non-NCQ RW Error Bit Set", /* 06h */
  6146. "SATA Read Log Receive Data Error", /* 07h */
  6147. "SATA NCQ Fail All Commands After Error", /* 08h */
  6148. "SATA Error in Receive Set Device Bit FIS", /* 09h */
  6149. "Receive Frame Invalid Message", /* 0Ah */
  6150. "Receive Context Message Valid Error", /* 0Bh */
  6151. "Receive Frame Current Frame Error", /* 0Ch */
  6152. "SATA Link Down", /* 0Dh */
  6153. "Discovery SATA Init W IOS", /* 0Eh */
  6154. "Config Invalid Page", /* 0Fh */
  6155. "Discovery SATA Init Timeout", /* 10h */
  6156. "Reset", /* 11h */
  6157. "Abort", /* 12h */
  6158. "IO Not Yet Executed", /* 13h */
  6159. "IO Executed", /* 14h */
  6160. "Persistent Reservation Out Not Affiliation "
  6161. "Owner", /* 15h */
  6162. "Open Transmit DMA Abort", /* 16h */
  6163. "IO Device Missing Delay Retry", /* 17h */
  6164. "IO Cancelled Due to Recieve Error", /* 18h */
  6165. NULL, /* 19h */
  6166. NULL, /* 1Ah */
  6167. NULL, /* 1Bh */
  6168. NULL, /* 1Ch */
  6169. NULL, /* 1Dh */
  6170. NULL, /* 1Eh */
  6171. NULL, /* 1Fh */
  6172. "Enclosure Management" /* 20h */
  6173. };
  6174. static char *ir_code_str[] = {
  6175. "Raid Action Error", /* 00h */
  6176. NULL, /* 00h */
  6177. NULL, /* 01h */
  6178. NULL, /* 02h */
  6179. NULL, /* 03h */
  6180. NULL, /* 04h */
  6181. NULL, /* 05h */
  6182. NULL, /* 06h */
  6183. NULL /* 07h */
  6184. };
  6185. static char *raid_sub_code_str[] = {
  6186. NULL, /* 00h */
  6187. "Volume Creation Failed: Data Passed too "
  6188. "Large", /* 01h */
  6189. "Volume Creation Failed: Duplicate Volumes "
  6190. "Attempted", /* 02h */
  6191. "Volume Creation Failed: Max Number "
  6192. "Supported Volumes Exceeded", /* 03h */
  6193. "Volume Creation Failed: DMA Error", /* 04h */
  6194. "Volume Creation Failed: Invalid Volume Type", /* 05h */
  6195. "Volume Creation Failed: Error Reading "
  6196. "MFG Page 4", /* 06h */
  6197. "Volume Creation Failed: Creating Internal "
  6198. "Structures", /* 07h */
  6199. NULL, /* 08h */
  6200. NULL, /* 09h */
  6201. NULL, /* 0Ah */
  6202. NULL, /* 0Bh */
  6203. NULL, /* 0Ch */
  6204. NULL, /* 0Dh */
  6205. NULL, /* 0Eh */
  6206. NULL, /* 0Fh */
  6207. "Activation failed: Already Active Volume", /* 10h */
  6208. "Activation failed: Unsupported Volume Type", /* 11h */
  6209. "Activation failed: Too Many Active Volumes", /* 12h */
  6210. "Activation failed: Volume ID in Use", /* 13h */
  6211. "Activation failed: Reported Failure", /* 14h */
  6212. "Activation failed: Importing a Volume", /* 15h */
  6213. NULL, /* 16h */
  6214. NULL, /* 17h */
  6215. NULL, /* 18h */
  6216. NULL, /* 19h */
  6217. NULL, /* 1Ah */
  6218. NULL, /* 1Bh */
  6219. NULL, /* 1Ch */
  6220. NULL, /* 1Dh */
  6221. NULL, /* 1Eh */
  6222. NULL, /* 1Fh */
  6223. "Phys Disk failed: Too Many Phys Disks", /* 20h */
  6224. "Phys Disk failed: Data Passed too Large", /* 21h */
  6225. "Phys Disk failed: DMA Error", /* 22h */
  6226. "Phys Disk failed: Invalid <channel:id>", /* 23h */
  6227. "Phys Disk failed: Creating Phys Disk Config "
  6228. "Page", /* 24h */
  6229. NULL, /* 25h */
  6230. NULL, /* 26h */
  6231. NULL, /* 27h */
  6232. NULL, /* 28h */
  6233. NULL, /* 29h */
  6234. NULL, /* 2Ah */
  6235. NULL, /* 2Bh */
  6236. NULL, /* 2Ch */
  6237. NULL, /* 2Dh */
  6238. NULL, /* 2Eh */
  6239. NULL, /* 2Fh */
  6240. "Compatibility Error: IR Disabled", /* 30h */
  6241. "Compatibility Error: Inquiry Comand Failed", /* 31h */
  6242. "Compatibility Error: Device not Direct Access "
  6243. "Device ", /* 32h */
  6244. "Compatibility Error: Removable Device Found", /* 33h */
  6245. "Compatibility Error: Device SCSI Version not "
  6246. "2 or Higher", /* 34h */
  6247. "Compatibility Error: SATA Device, 48 BIT LBA "
  6248. "not Supported", /* 35h */
  6249. "Compatibility Error: Device doesn't have "
  6250. "512 Byte Block Sizes", /* 36h */
  6251. "Compatibility Error: Volume Type Check Failed", /* 37h */
  6252. "Compatibility Error: Volume Type is "
  6253. "Unsupported by FW", /* 38h */
  6254. "Compatibility Error: Disk Drive too Small for "
  6255. "use in Volume", /* 39h */
  6256. "Compatibility Error: Phys Disk for Create "
  6257. "Volume not Found", /* 3Ah */
  6258. "Compatibility Error: Too Many or too Few "
  6259. "Disks for Volume Type", /* 3Bh */
  6260. "Compatibility Error: Disk stripe Sizes "
  6261. "Must be 64KB", /* 3Ch */
  6262. "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
  6263. };
  6264. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6265. /**
  6266. * mpt_sas_log_info - Log information returned from SAS IOC.
  6267. * @ioc: Pointer to MPT_ADAPTER structure
  6268. * @log_info: U32 LogInfo reply word from the IOC
  6269. *
  6270. * Refer to lsi/mpi_log_sas.h.
  6271. **/
  6272. static void
  6273. mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info)
  6274. {
  6275. union loginfo_type {
  6276. u32 loginfo;
  6277. struct {
  6278. u32 subcode:16;
  6279. u32 code:8;
  6280. u32 originator:4;
  6281. u32 bus_type:4;
  6282. }dw;
  6283. };
  6284. union loginfo_type sas_loginfo;
  6285. char *originator_desc = NULL;
  6286. char *code_desc = NULL;
  6287. char *sub_code_desc = NULL;
  6288. sas_loginfo.loginfo = log_info;
  6289. if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
  6290. (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
  6291. return;
  6292. originator_desc = originator_str[sas_loginfo.dw.originator];
  6293. switch (sas_loginfo.dw.originator) {
  6294. case 0: /* IOP */
  6295. if (sas_loginfo.dw.code <
  6296. ARRAY_SIZE(iop_code_str))
  6297. code_desc = iop_code_str[sas_loginfo.dw.code];
  6298. break;
  6299. case 1: /* PL */
  6300. if (sas_loginfo.dw.code <
  6301. ARRAY_SIZE(pl_code_str))
  6302. code_desc = pl_code_str[sas_loginfo.dw.code];
  6303. break;
  6304. case 2: /* IR */
  6305. if (sas_loginfo.dw.code >=
  6306. ARRAY_SIZE(ir_code_str))
  6307. break;
  6308. code_desc = ir_code_str[sas_loginfo.dw.code];
  6309. if (sas_loginfo.dw.subcode >=
  6310. ARRAY_SIZE(raid_sub_code_str))
  6311. break;
  6312. if (sas_loginfo.dw.code == 0)
  6313. sub_code_desc =
  6314. raid_sub_code_str[sas_loginfo.dw.subcode];
  6315. break;
  6316. default:
  6317. return;
  6318. }
  6319. if (sub_code_desc != NULL)
  6320. printk(MYIOC_s_INFO_FMT
  6321. "LogInfo(0x%08x): Originator={%s}, Code={%s},"
  6322. " SubCode={%s}\n",
  6323. ioc->name, log_info, originator_desc, code_desc,
  6324. sub_code_desc);
  6325. else if (code_desc != NULL)
  6326. printk(MYIOC_s_INFO_FMT
  6327. "LogInfo(0x%08x): Originator={%s}, Code={%s},"
  6328. " SubCode(0x%04x)\n",
  6329. ioc->name, log_info, originator_desc, code_desc,
  6330. sas_loginfo.dw.subcode);
  6331. else
  6332. printk(MYIOC_s_INFO_FMT
  6333. "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
  6334. " SubCode(0x%04x)\n",
  6335. ioc->name, log_info, originator_desc,
  6336. sas_loginfo.dw.code, sas_loginfo.dw.subcode);
  6337. }
  6338. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6339. /**
  6340. * mpt_iocstatus_info_config - IOCSTATUS information for config pages
  6341. * @ioc: Pointer to MPT_ADAPTER structure
  6342. * @ioc_status: U32 IOCStatus word from IOC
  6343. * @mf: Pointer to MPT request frame
  6344. *
  6345. * Refer to lsi/mpi.h.
  6346. **/
  6347. static void
  6348. mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
  6349. {
  6350. Config_t *pReq = (Config_t *)mf;
  6351. char extend_desc[EVENT_DESCR_STR_SZ];
  6352. char *desc = NULL;
  6353. u32 form;
  6354. u8 page_type;
  6355. if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
  6356. page_type = pReq->ExtPageType;
  6357. else
  6358. page_type = pReq->Header.PageType;
  6359. /*
  6360. * ignore invalid page messages for GET_NEXT_HANDLE
  6361. */
  6362. form = le32_to_cpu(pReq->PageAddress);
  6363. if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
  6364. if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
  6365. page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
  6366. page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
  6367. if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
  6368. MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
  6369. return;
  6370. }
  6371. if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
  6372. if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
  6373. MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
  6374. return;
  6375. }
  6376. snprintf(extend_desc, EVENT_DESCR_STR_SZ,
  6377. "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
  6378. page_type, pReq->Header.PageNumber, pReq->Action, form);
  6379. switch (ioc_status) {
  6380. case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
  6381. desc = "Config Page Invalid Action";
  6382. break;
  6383. case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
  6384. desc = "Config Page Invalid Type";
  6385. break;
  6386. case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
  6387. desc = "Config Page Invalid Page";
  6388. break;
  6389. case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
  6390. desc = "Config Page Invalid Data";
  6391. break;
  6392. case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
  6393. desc = "Config Page No Defaults";
  6394. break;
  6395. case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
  6396. desc = "Config Page Can't Commit";
  6397. break;
  6398. }
  6399. if (!desc)
  6400. return;
  6401. dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
  6402. ioc->name, ioc_status, desc, extend_desc));
  6403. }
  6404. /**
  6405. * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
  6406. * @ioc: Pointer to MPT_ADAPTER structure
  6407. * @ioc_status: U32 IOCStatus word from IOC
  6408. * @mf: Pointer to MPT request frame
  6409. *
  6410. * Refer to lsi/mpi.h.
  6411. **/
  6412. static void
  6413. mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
  6414. {
  6415. u32 status = ioc_status & MPI_IOCSTATUS_MASK;
  6416. char *desc = NULL;
  6417. switch (status) {
  6418. /****************************************************************************/
  6419. /* Common IOCStatus values for all replies */
  6420. /****************************************************************************/
  6421. case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
  6422. desc = "Invalid Function";
  6423. break;
  6424. case MPI_IOCSTATUS_BUSY: /* 0x0002 */
  6425. desc = "Busy";
  6426. break;
  6427. case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
  6428. desc = "Invalid SGL";
  6429. break;
  6430. case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
  6431. desc = "Internal Error";
  6432. break;
  6433. case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
  6434. desc = "Reserved";
  6435. break;
  6436. case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
  6437. desc = "Insufficient Resources";
  6438. break;
  6439. case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
  6440. desc = "Invalid Field";
  6441. break;
  6442. case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
  6443. desc = "Invalid State";
  6444. break;
  6445. /****************************************************************************/
  6446. /* Config IOCStatus values */
  6447. /****************************************************************************/
  6448. case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
  6449. case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
  6450. case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
  6451. case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
  6452. case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
  6453. case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
  6454. mpt_iocstatus_info_config(ioc, status, mf);
  6455. break;
  6456. /****************************************************************************/
  6457. /* SCSIIO Reply (SPI, FCP, SAS) initiator values */
  6458. /* */
  6459. /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
  6460. /* */
  6461. /****************************************************************************/
  6462. case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
  6463. case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
  6464. case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
  6465. case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
  6466. case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
  6467. case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
  6468. case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
  6469. case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
  6470. case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
  6471. case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
  6472. case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
  6473. case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
  6474. case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
  6475. break;
  6476. /****************************************************************************/
  6477. /* SCSI Target values */
  6478. /****************************************************************************/
  6479. case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
  6480. desc = "Target: Priority IO";
  6481. break;
  6482. case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
  6483. desc = "Target: Invalid Port";
  6484. break;
  6485. case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
  6486. desc = "Target Invalid IO Index:";
  6487. break;
  6488. case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
  6489. desc = "Target: Aborted";
  6490. break;
  6491. case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
  6492. desc = "Target: No Conn Retryable";
  6493. break;
  6494. case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
  6495. desc = "Target: No Connection";
  6496. break;
  6497. case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
  6498. desc = "Target: Transfer Count Mismatch";
  6499. break;
  6500. case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
  6501. desc = "Target: STS Data not Sent";
  6502. break;
  6503. case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
  6504. desc = "Target: Data Offset Error";
  6505. break;
  6506. case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
  6507. desc = "Target: Too Much Write Data";
  6508. break;
  6509. case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
  6510. desc = "Target: IU Too Short";
  6511. break;
  6512. case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
  6513. desc = "Target: ACK NAK Timeout";
  6514. break;
  6515. case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
  6516. desc = "Target: Nak Received";
  6517. break;
  6518. /****************************************************************************/
  6519. /* Fibre Channel Direct Access values */
  6520. /****************************************************************************/
  6521. case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
  6522. desc = "FC: Aborted";
  6523. break;
  6524. case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
  6525. desc = "FC: RX ID Invalid";
  6526. break;
  6527. case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
  6528. desc = "FC: DID Invalid";
  6529. break;
  6530. case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
  6531. desc = "FC: Node Logged Out";
  6532. break;
  6533. case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
  6534. desc = "FC: Exchange Canceled";
  6535. break;
  6536. /****************************************************************************/
  6537. /* LAN values */
  6538. /****************************************************************************/
  6539. case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
  6540. desc = "LAN: Device not Found";
  6541. break;
  6542. case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
  6543. desc = "LAN: Device Failure";
  6544. break;
  6545. case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
  6546. desc = "LAN: Transmit Error";
  6547. break;
  6548. case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
  6549. desc = "LAN: Transmit Aborted";
  6550. break;
  6551. case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
  6552. desc = "LAN: Receive Error";
  6553. break;
  6554. case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
  6555. desc = "LAN: Receive Aborted";
  6556. break;
  6557. case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
  6558. desc = "LAN: Partial Packet";
  6559. break;
  6560. case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
  6561. desc = "LAN: Canceled";
  6562. break;
  6563. /****************************************************************************/
  6564. /* Serial Attached SCSI values */
  6565. /****************************************************************************/
  6566. case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
  6567. desc = "SAS: SMP Request Failed";
  6568. break;
  6569. case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
  6570. desc = "SAS: SMP Data Overrun";
  6571. break;
  6572. default:
  6573. desc = "Others";
  6574. break;
  6575. }
  6576. if (!desc)
  6577. return;
  6578. dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
  6579. ioc->name, status, desc));
  6580. }
  6581. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6582. EXPORT_SYMBOL(mpt_attach);
  6583. EXPORT_SYMBOL(mpt_detach);
  6584. #ifdef CONFIG_PM
  6585. EXPORT_SYMBOL(mpt_resume);
  6586. EXPORT_SYMBOL(mpt_suspend);
  6587. #endif
  6588. EXPORT_SYMBOL(ioc_list);
  6589. EXPORT_SYMBOL(mpt_register);
  6590. EXPORT_SYMBOL(mpt_deregister);
  6591. EXPORT_SYMBOL(mpt_event_register);
  6592. EXPORT_SYMBOL(mpt_event_deregister);
  6593. EXPORT_SYMBOL(mpt_reset_register);
  6594. EXPORT_SYMBOL(mpt_reset_deregister);
  6595. EXPORT_SYMBOL(mpt_device_driver_register);
  6596. EXPORT_SYMBOL(mpt_device_driver_deregister);
  6597. EXPORT_SYMBOL(mpt_get_msg_frame);
  6598. EXPORT_SYMBOL(mpt_put_msg_frame);
  6599. EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
  6600. EXPORT_SYMBOL(mpt_free_msg_frame);
  6601. EXPORT_SYMBOL(mpt_add_sge);
  6602. EXPORT_SYMBOL(mpt_send_handshake_request);
  6603. EXPORT_SYMBOL(mpt_verify_adapter);
  6604. EXPORT_SYMBOL(mpt_GetIocState);
  6605. EXPORT_SYMBOL(mpt_print_ioc_summary);
  6606. EXPORT_SYMBOL(mpt_HardResetHandler);
  6607. EXPORT_SYMBOL(mpt_config);
  6608. EXPORT_SYMBOL(mpt_findImVolumes);
  6609. EXPORT_SYMBOL(mpt_alloc_fw_memory);
  6610. EXPORT_SYMBOL(mpt_free_fw_memory);
  6611. EXPORT_SYMBOL(mptbase_sas_persist_operation);
  6612. EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
  6613. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6614. /**
  6615. * fusion_init - Fusion MPT base driver initialization routine.
  6616. *
  6617. * Returns 0 for success, non-zero for failure.
  6618. */
  6619. static int __init
  6620. fusion_init(void)
  6621. {
  6622. u8 cb_idx;
  6623. show_mptmod_ver(my_NAME, my_VERSION);
  6624. printk(KERN_INFO COPYRIGHT "\n");
  6625. for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
  6626. MptCallbacks[cb_idx] = NULL;
  6627. MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
  6628. MptEvHandlers[cb_idx] = NULL;
  6629. MptResetHandlers[cb_idx] = NULL;
  6630. }
  6631. /* Register ourselves (mptbase) in order to facilitate
  6632. * EventNotification handling.
  6633. */
  6634. mpt_base_index = mpt_register(mpt_base_reply, MPTBASE_DRIVER);
  6635. /* Register for hard reset handling callbacks.
  6636. */
  6637. mpt_reset_register(mpt_base_index, mpt_ioc_reset);
  6638. #ifdef CONFIG_PROC_FS
  6639. (void) procmpt_create();
  6640. #endif
  6641. return 0;
  6642. }
  6643. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6644. /**
  6645. * fusion_exit - Perform driver unload cleanup.
  6646. *
  6647. * This routine frees all resources associated with each MPT adapter
  6648. * and removes all %MPT_PROCFS_MPTBASEDIR entries.
  6649. */
  6650. static void __exit
  6651. fusion_exit(void)
  6652. {
  6653. mpt_reset_deregister(mpt_base_index);
  6654. #ifdef CONFIG_PROC_FS
  6655. procmpt_destroy();
  6656. #endif
  6657. }
  6658. module_init(fusion_init);
  6659. module_exit(fusion_exit);