mcbsp.c 8.0 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/mcbsp.c
  3. *
  4. * Copyright (C) 2008 Instituto Nokia de Tecnologia
  5. * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Multichannel mode not supported.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/platform_device.h>
  19. #include <mach/irqs.h>
  20. #include <mach/dma.h>
  21. #include <mach/irqs.h>
  22. #include <mach/mux.h>
  23. #include <mach/cpu.h>
  24. #include <mach/mcbsp.h>
  25. struct mcbsp_internal_clk {
  26. struct clk clk;
  27. struct clk **childs;
  28. int n_childs;
  29. };
  30. #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  31. static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
  32. {
  33. const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
  34. int i;
  35. mclk->n_childs = ARRAY_SIZE(clk_names);
  36. mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
  37. GFP_KERNEL);
  38. for (i = 0; i < mclk->n_childs; i++) {
  39. /* We fake a platform device to get correct device id */
  40. struct platform_device pdev;
  41. pdev.dev.bus = &platform_bus_type;
  42. pdev.id = mclk->clk.id;
  43. mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
  44. if (IS_ERR(mclk->childs[i]))
  45. printk(KERN_ERR "Could not get clock %s (%d).\n",
  46. clk_names[i], mclk->clk.id);
  47. }
  48. }
  49. static int omap_mcbsp_clk_enable(struct clk *clk)
  50. {
  51. struct mcbsp_internal_clk *mclk = container_of(clk,
  52. struct mcbsp_internal_clk, clk);
  53. int i;
  54. for (i = 0; i < mclk->n_childs; i++)
  55. clk_enable(mclk->childs[i]);
  56. return 0;
  57. }
  58. static void omap_mcbsp_clk_disable(struct clk *clk)
  59. {
  60. struct mcbsp_internal_clk *mclk = container_of(clk,
  61. struct mcbsp_internal_clk, clk);
  62. int i;
  63. for (i = 0; i < mclk->n_childs; i++)
  64. clk_disable(mclk->childs[i]);
  65. }
  66. static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
  67. {
  68. .clk = {
  69. .name = "mcbsp_clk",
  70. .id = 1,
  71. .enable = omap_mcbsp_clk_enable,
  72. .disable = omap_mcbsp_clk_disable,
  73. },
  74. },
  75. {
  76. .clk = {
  77. .name = "mcbsp_clk",
  78. .id = 2,
  79. .enable = omap_mcbsp_clk_enable,
  80. .disable = omap_mcbsp_clk_disable,
  81. },
  82. },
  83. {
  84. .clk = {
  85. .name = "mcbsp_clk",
  86. .id = 3,
  87. .enable = omap_mcbsp_clk_enable,
  88. .disable = omap_mcbsp_clk_disable,
  89. },
  90. },
  91. {
  92. .clk = {
  93. .name = "mcbsp_clk",
  94. .id = 4,
  95. .enable = omap_mcbsp_clk_enable,
  96. .disable = omap_mcbsp_clk_disable,
  97. },
  98. },
  99. {
  100. .clk = {
  101. .name = "mcbsp_clk",
  102. .id = 5,
  103. .enable = omap_mcbsp_clk_enable,
  104. .disable = omap_mcbsp_clk_disable,
  105. },
  106. },
  107. };
  108. #define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
  109. #else
  110. #define omap_mcbsp_clks_size 0
  111. static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
  112. static inline void omap_mcbsp_clk_init(struct clk *clk)
  113. { }
  114. #endif
  115. static void omap2_mcbsp2_mux_setup(void)
  116. {
  117. omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
  118. omap_cfg_reg(R14_24XX_MCBSP2_FSX);
  119. omap_cfg_reg(W15_24XX_MCBSP2_DR);
  120. omap_cfg_reg(V15_24XX_MCBSP2_DX);
  121. omap_cfg_reg(V14_24XX_GPIO117);
  122. /*
  123. * TODO: Need to add MUX settings for OMAP 2430 SDP
  124. */
  125. }
  126. static void omap2_mcbsp_request(unsigned int id)
  127. {
  128. if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
  129. omap2_mcbsp2_mux_setup();
  130. }
  131. static struct omap_mcbsp_ops omap2_mcbsp_ops = {
  132. .request = omap2_mcbsp_request,
  133. };
  134. #ifdef CONFIG_ARCH_OMAP2420
  135. static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
  136. {
  137. .phys_base = OMAP24XX_MCBSP1_BASE,
  138. .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
  139. .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
  140. .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
  141. .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
  142. .ops = &omap2_mcbsp_ops,
  143. .clk_name = "mcbsp_clk",
  144. },
  145. {
  146. .phys_base = OMAP24XX_MCBSP2_BASE,
  147. .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
  148. .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
  149. .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
  150. .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
  151. .ops = &omap2_mcbsp_ops,
  152. .clk_name = "mcbsp_clk",
  153. },
  154. };
  155. #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
  156. #else
  157. #define omap2420_mcbsp_pdata NULL
  158. #define OMAP2420_MCBSP_PDATA_SZ 0
  159. #endif
  160. #ifdef CONFIG_ARCH_OMAP2430
  161. static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
  162. {
  163. .phys_base = OMAP24XX_MCBSP1_BASE,
  164. .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
  165. .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
  166. .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
  167. .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
  168. .ops = &omap2_mcbsp_ops,
  169. .clk_name = "mcbsp_clk",
  170. },
  171. {
  172. .phys_base = OMAP24XX_MCBSP2_BASE,
  173. .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
  174. .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
  175. .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
  176. .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
  177. .ops = &omap2_mcbsp_ops,
  178. .clk_name = "mcbsp_clk",
  179. },
  180. {
  181. .phys_base = OMAP2430_MCBSP3_BASE,
  182. .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
  183. .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
  184. .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
  185. .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
  186. .ops = &omap2_mcbsp_ops,
  187. .clk_name = "mcbsp_clk",
  188. },
  189. {
  190. .phys_base = OMAP2430_MCBSP4_BASE,
  191. .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
  192. .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
  193. .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
  194. .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
  195. .ops = &omap2_mcbsp_ops,
  196. .clk_name = "mcbsp_clk",
  197. },
  198. {
  199. .phys_base = OMAP2430_MCBSP5_BASE,
  200. .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
  201. .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
  202. .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
  203. .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
  204. .ops = &omap2_mcbsp_ops,
  205. .clk_name = "mcbsp_clk",
  206. },
  207. };
  208. #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
  209. #else
  210. #define omap2430_mcbsp_pdata NULL
  211. #define OMAP2430_MCBSP_PDATA_SZ 0
  212. #endif
  213. #ifdef CONFIG_ARCH_OMAP34XX
  214. static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
  215. {
  216. .phys_base = OMAP34XX_MCBSP1_BASE,
  217. .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
  218. .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
  219. .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
  220. .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
  221. .ops = &omap2_mcbsp_ops,
  222. .clk_name = "mcbsp_clk",
  223. },
  224. {
  225. .phys_base = OMAP34XX_MCBSP2_BASE,
  226. .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
  227. .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
  228. .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
  229. .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
  230. .ops = &omap2_mcbsp_ops,
  231. .clk_name = "mcbsp_clk",
  232. },
  233. {
  234. .phys_base = OMAP34XX_MCBSP3_BASE,
  235. .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
  236. .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
  237. .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
  238. .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
  239. .ops = &omap2_mcbsp_ops,
  240. .clk_name = "mcbsp_clk",
  241. },
  242. {
  243. .phys_base = OMAP34XX_MCBSP4_BASE,
  244. .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
  245. .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
  246. .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
  247. .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
  248. .ops = &omap2_mcbsp_ops,
  249. .clk_name = "mcbsp_clk",
  250. },
  251. {
  252. .phys_base = OMAP34XX_MCBSP5_BASE,
  253. .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
  254. .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
  255. .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
  256. .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
  257. .ops = &omap2_mcbsp_ops,
  258. .clk_name = "mcbsp_clk",
  259. },
  260. };
  261. #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
  262. #else
  263. #define omap34xx_mcbsp_pdata NULL
  264. #define OMAP34XX_MCBSP_PDATA_SZ 0
  265. #endif
  266. static int __init omap2_mcbsp_init(void)
  267. {
  268. int i;
  269. for (i = 0; i < omap_mcbsp_clks_size; i++) {
  270. /* Once we call clk_get inside init, we do not register it */
  271. omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
  272. clk_register(&omap_mcbsp_clks[i].clk);
  273. }
  274. if (cpu_is_omap2420())
  275. omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
  276. if (cpu_is_omap2430())
  277. omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
  278. if (cpu_is_omap34xx())
  279. omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
  280. mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
  281. GFP_KERNEL);
  282. if (!mcbsp_ptr)
  283. return -ENOMEM;
  284. if (cpu_is_omap2420())
  285. omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
  286. OMAP2420_MCBSP_PDATA_SZ);
  287. if (cpu_is_omap2430())
  288. omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
  289. OMAP2430_MCBSP_PDATA_SZ);
  290. if (cpu_is_omap34xx())
  291. omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
  292. OMAP34XX_MCBSP_PDATA_SZ);
  293. return omap_mcbsp_init();
  294. }
  295. arch_initcall(omap2_mcbsp_init);