io_apic.c 103 KB

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  1. /*
  2. * Intel IO-APIC support for multi-Pentium hosts.
  3. *
  4. * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
  5. *
  6. * Many thanks to Stig Venaas for trying out countless experimental
  7. * patches and reporting/debugging problems patiently!
  8. *
  9. * (c) 1999, Multiple IO-APIC support, developed by
  10. * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11. * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12. * further tested and cleaned up by Zach Brown <zab@redhat.com>
  13. * and Ingo Molnar <mingo@redhat.com>
  14. *
  15. * Fixes
  16. * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
  17. * thanks to Eric Gilmore
  18. * and Rolf G. Tews
  19. * for testing these extensively
  20. * Paul Diefenbaugh : Added full ACPI support
  21. */
  22. #include <linux/mm.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/sched.h>
  27. #include <linux/pci.h>
  28. #include <linux/mc146818rtc.h>
  29. #include <linux/compiler.h>
  30. #include <linux/acpi.h>
  31. #include <linux/module.h>
  32. #include <linux/sysdev.h>
  33. #include <linux/msi.h>
  34. #include <linux/htirq.h>
  35. #include <linux/freezer.h>
  36. #include <linux/kthread.h>
  37. #include <linux/jiffies.h> /* time_after() */
  38. #include <linux/slab.h>
  39. #ifdef CONFIG_ACPI
  40. #include <acpi/acpi_bus.h>
  41. #endif
  42. #include <linux/bootmem.h>
  43. #include <linux/dmar.h>
  44. #include <linux/hpet.h>
  45. #include <asm/idle.h>
  46. #include <asm/io.h>
  47. #include <asm/smp.h>
  48. #include <asm/cpu.h>
  49. #include <asm/desc.h>
  50. #include <asm/proto.h>
  51. #include <asm/acpi.h>
  52. #include <asm/dma.h>
  53. #include <asm/timer.h>
  54. #include <asm/i8259.h>
  55. #include <asm/nmi.h>
  56. #include <asm/msidef.h>
  57. #include <asm/hypertransport.h>
  58. #include <asm/setup.h>
  59. #include <asm/irq_remapping.h>
  60. #include <asm/hpet.h>
  61. #include <asm/hw_irq.h>
  62. #include <asm/apic.h>
  63. #define __apicdebuginit(type) static type __init
  64. #define for_each_irq_pin(entry, head) \
  65. for (entry = head; entry; entry = entry->next)
  66. /*
  67. * Is the SiS APIC rmw bug present ?
  68. * -1 = don't know, 0 = no, 1 = yes
  69. */
  70. int sis_apic_bug = -1;
  71. static DEFINE_RAW_SPINLOCK(ioapic_lock);
  72. static DEFINE_RAW_SPINLOCK(vector_lock);
  73. /*
  74. * # of IRQ routing registers
  75. */
  76. int nr_ioapic_registers[MAX_IO_APICS];
  77. /* I/O APIC entries */
  78. struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  79. int nr_ioapics;
  80. /* IO APIC gsi routing info */
  81. struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
  82. /* The one past the highest gsi number used */
  83. u32 gsi_top;
  84. /* MP IRQ source entries */
  85. struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  86. /* # of MP IRQ source entries */
  87. int mp_irq_entries;
  88. /* GSI interrupts */
  89. static int nr_irqs_gsi = NR_IRQS_LEGACY;
  90. #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  91. int mp_bus_id_to_type[MAX_MP_BUSSES];
  92. #endif
  93. DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  94. int skip_ioapic_setup;
  95. void arch_disable_smp_support(void)
  96. {
  97. #ifdef CONFIG_PCI
  98. noioapicquirk = 1;
  99. noioapicreroute = -1;
  100. #endif
  101. skip_ioapic_setup = 1;
  102. }
  103. static int __init parse_noapic(char *str)
  104. {
  105. /* disable IO-APIC */
  106. arch_disable_smp_support();
  107. return 0;
  108. }
  109. early_param("noapic", parse_noapic);
  110. struct irq_pin_list {
  111. int apic, pin;
  112. struct irq_pin_list *next;
  113. };
  114. static struct irq_pin_list *get_one_free_irq_2_pin(int node)
  115. {
  116. struct irq_pin_list *pin;
  117. pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
  118. return pin;
  119. }
  120. /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
  121. #ifdef CONFIG_SPARSE_IRQ
  122. static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
  123. #else
  124. static struct irq_cfg irq_cfgx[NR_IRQS];
  125. #endif
  126. int __init arch_early_irq_init(void)
  127. {
  128. struct irq_cfg *cfg;
  129. struct irq_desc *desc;
  130. int count;
  131. int node;
  132. int i;
  133. if (!legacy_pic->nr_legacy_irqs) {
  134. nr_irqs_gsi = 0;
  135. io_apic_irqs = ~0UL;
  136. }
  137. cfg = irq_cfgx;
  138. count = ARRAY_SIZE(irq_cfgx);
  139. node = cpu_to_node(0);
  140. for (i = 0; i < count; i++) {
  141. desc = irq_to_desc(i);
  142. desc->chip_data = &cfg[i];
  143. zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
  144. zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
  145. /*
  146. * For legacy IRQ's, start with assigning irq0 to irq15 to
  147. * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
  148. */
  149. if (i < legacy_pic->nr_legacy_irqs) {
  150. cfg[i].vector = IRQ0_VECTOR + i;
  151. cpumask_set_cpu(0, cfg[i].domain);
  152. }
  153. }
  154. return 0;
  155. }
  156. #ifdef CONFIG_SPARSE_IRQ
  157. struct irq_cfg *irq_cfg(unsigned int irq)
  158. {
  159. struct irq_cfg *cfg = NULL;
  160. struct irq_desc *desc;
  161. desc = irq_to_desc(irq);
  162. if (desc)
  163. cfg = get_irq_desc_chip_data(desc);
  164. return cfg;
  165. }
  166. static struct irq_cfg *get_one_free_irq_cfg(int node)
  167. {
  168. struct irq_cfg *cfg;
  169. cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
  170. if (cfg) {
  171. if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
  172. kfree(cfg);
  173. cfg = NULL;
  174. } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
  175. GFP_ATOMIC, node)) {
  176. free_cpumask_var(cfg->domain);
  177. kfree(cfg);
  178. cfg = NULL;
  179. }
  180. }
  181. return cfg;
  182. }
  183. int arch_init_chip_data(struct irq_desc *desc, int node)
  184. {
  185. struct irq_cfg *cfg;
  186. cfg = get_irq_desc_chip_data(desc);
  187. if (!cfg) {
  188. cfg = get_one_free_irq_cfg(node);
  189. desc->chip_data = cfg;
  190. if (!cfg) {
  191. printk(KERN_ERR "can not alloc irq_cfg\n");
  192. BUG_ON(1);
  193. }
  194. }
  195. return 0;
  196. }
  197. /* for move_irq_desc */
  198. static void
  199. init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
  200. {
  201. struct irq_pin_list *old_entry, *head, *tail, *entry;
  202. cfg->irq_2_pin = NULL;
  203. old_entry = old_cfg->irq_2_pin;
  204. if (!old_entry)
  205. return;
  206. entry = get_one_free_irq_2_pin(node);
  207. if (!entry)
  208. return;
  209. entry->apic = old_entry->apic;
  210. entry->pin = old_entry->pin;
  211. head = entry;
  212. tail = entry;
  213. old_entry = old_entry->next;
  214. while (old_entry) {
  215. entry = get_one_free_irq_2_pin(node);
  216. if (!entry) {
  217. entry = head;
  218. while (entry) {
  219. head = entry->next;
  220. kfree(entry);
  221. entry = head;
  222. }
  223. /* still use the old one */
  224. return;
  225. }
  226. entry->apic = old_entry->apic;
  227. entry->pin = old_entry->pin;
  228. tail->next = entry;
  229. tail = entry;
  230. old_entry = old_entry->next;
  231. }
  232. tail->next = NULL;
  233. cfg->irq_2_pin = head;
  234. }
  235. static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
  236. {
  237. struct irq_pin_list *entry, *next;
  238. if (old_cfg->irq_2_pin == cfg->irq_2_pin)
  239. return;
  240. entry = old_cfg->irq_2_pin;
  241. while (entry) {
  242. next = entry->next;
  243. kfree(entry);
  244. entry = next;
  245. }
  246. old_cfg->irq_2_pin = NULL;
  247. }
  248. void arch_init_copy_chip_data(struct irq_desc *old_desc,
  249. struct irq_desc *desc, int node)
  250. {
  251. struct irq_cfg *cfg;
  252. struct irq_cfg *old_cfg;
  253. cfg = get_one_free_irq_cfg(node);
  254. if (!cfg)
  255. return;
  256. desc->chip_data = cfg;
  257. old_cfg = old_desc->chip_data;
  258. cfg->vector = old_cfg->vector;
  259. cfg->move_in_progress = old_cfg->move_in_progress;
  260. cpumask_copy(cfg->domain, old_cfg->domain);
  261. cpumask_copy(cfg->old_domain, old_cfg->old_domain);
  262. init_copy_irq_2_pin(old_cfg, cfg, node);
  263. }
  264. static void free_irq_cfg(struct irq_cfg *cfg)
  265. {
  266. free_cpumask_var(cfg->domain);
  267. free_cpumask_var(cfg->old_domain);
  268. kfree(cfg);
  269. }
  270. void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
  271. {
  272. struct irq_cfg *old_cfg, *cfg;
  273. old_cfg = get_irq_desc_chip_data(old_desc);
  274. cfg = get_irq_desc_chip_data(desc);
  275. if (old_cfg == cfg)
  276. return;
  277. if (old_cfg) {
  278. free_irq_2_pin(old_cfg, cfg);
  279. free_irq_cfg(old_cfg);
  280. old_desc->chip_data = NULL;
  281. }
  282. }
  283. /* end for move_irq_desc */
  284. #else
  285. struct irq_cfg *irq_cfg(unsigned int irq)
  286. {
  287. return irq < nr_irqs ? irq_cfgx + irq : NULL;
  288. }
  289. #endif
  290. struct io_apic {
  291. unsigned int index;
  292. unsigned int unused[3];
  293. unsigned int data;
  294. unsigned int unused2[11];
  295. unsigned int eoi;
  296. };
  297. static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
  298. {
  299. return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
  300. + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
  301. }
  302. static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
  303. {
  304. struct io_apic __iomem *io_apic = io_apic_base(apic);
  305. writel(vector, &io_apic->eoi);
  306. }
  307. static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
  308. {
  309. struct io_apic __iomem *io_apic = io_apic_base(apic);
  310. writel(reg, &io_apic->index);
  311. return readl(&io_apic->data);
  312. }
  313. static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
  314. {
  315. struct io_apic __iomem *io_apic = io_apic_base(apic);
  316. writel(reg, &io_apic->index);
  317. writel(value, &io_apic->data);
  318. }
  319. /*
  320. * Re-write a value: to be used for read-modify-write
  321. * cycles where the read already set up the index register.
  322. *
  323. * Older SiS APIC requires we rewrite the index register
  324. */
  325. static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
  326. {
  327. struct io_apic __iomem *io_apic = io_apic_base(apic);
  328. if (sis_apic_bug)
  329. writel(reg, &io_apic->index);
  330. writel(value, &io_apic->data);
  331. }
  332. static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
  333. {
  334. struct irq_pin_list *entry;
  335. unsigned long flags;
  336. raw_spin_lock_irqsave(&ioapic_lock, flags);
  337. for_each_irq_pin(entry, cfg->irq_2_pin) {
  338. unsigned int reg;
  339. int pin;
  340. pin = entry->pin;
  341. reg = io_apic_read(entry->apic, 0x10 + pin*2);
  342. /* Is the remote IRR bit set? */
  343. if (reg & IO_APIC_REDIR_REMOTE_IRR) {
  344. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  345. return true;
  346. }
  347. }
  348. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  349. return false;
  350. }
  351. union entry_union {
  352. struct { u32 w1, w2; };
  353. struct IO_APIC_route_entry entry;
  354. };
  355. static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
  356. {
  357. union entry_union eu;
  358. unsigned long flags;
  359. raw_spin_lock_irqsave(&ioapic_lock, flags);
  360. eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
  361. eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
  362. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  363. return eu.entry;
  364. }
  365. /*
  366. * When we write a new IO APIC routing entry, we need to write the high
  367. * word first! If the mask bit in the low word is clear, we will enable
  368. * the interrupt, and we need to make sure the entry is fully populated
  369. * before that happens.
  370. */
  371. static void
  372. __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
  373. {
  374. union entry_union eu = {{0, 0}};
  375. eu.entry = e;
  376. io_apic_write(apic, 0x11 + 2*pin, eu.w2);
  377. io_apic_write(apic, 0x10 + 2*pin, eu.w1);
  378. }
  379. void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
  380. {
  381. unsigned long flags;
  382. raw_spin_lock_irqsave(&ioapic_lock, flags);
  383. __ioapic_write_entry(apic, pin, e);
  384. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  385. }
  386. /*
  387. * When we mask an IO APIC routing entry, we need to write the low
  388. * word first, in order to set the mask bit before we change the
  389. * high bits!
  390. */
  391. static void ioapic_mask_entry(int apic, int pin)
  392. {
  393. unsigned long flags;
  394. union entry_union eu = { .entry.mask = 1 };
  395. raw_spin_lock_irqsave(&ioapic_lock, flags);
  396. io_apic_write(apic, 0x10 + 2*pin, eu.w1);
  397. io_apic_write(apic, 0x11 + 2*pin, eu.w2);
  398. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  399. }
  400. /*
  401. * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  402. * shared ISA-space IRQs, so we have to support them. We are super
  403. * fast in the common case, and fast for shared ISA-space IRQs.
  404. */
  405. static int
  406. add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
  407. {
  408. struct irq_pin_list **last, *entry;
  409. /* don't allow duplicates */
  410. last = &cfg->irq_2_pin;
  411. for_each_irq_pin(entry, cfg->irq_2_pin) {
  412. if (entry->apic == apic && entry->pin == pin)
  413. return 0;
  414. last = &entry->next;
  415. }
  416. entry = get_one_free_irq_2_pin(node);
  417. if (!entry) {
  418. printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
  419. node, apic, pin);
  420. return -ENOMEM;
  421. }
  422. entry->apic = apic;
  423. entry->pin = pin;
  424. *last = entry;
  425. return 0;
  426. }
  427. static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
  428. {
  429. if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
  430. panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
  431. }
  432. /*
  433. * Reroute an IRQ to a different pin.
  434. */
  435. static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
  436. int oldapic, int oldpin,
  437. int newapic, int newpin)
  438. {
  439. struct irq_pin_list *entry;
  440. for_each_irq_pin(entry, cfg->irq_2_pin) {
  441. if (entry->apic == oldapic && entry->pin == oldpin) {
  442. entry->apic = newapic;
  443. entry->pin = newpin;
  444. /* every one is different, right? */
  445. return;
  446. }
  447. }
  448. /* old apic/pin didn't exist, so just add new ones */
  449. add_pin_to_irq_node(cfg, node, newapic, newpin);
  450. }
  451. static void __io_apic_modify_irq(struct irq_pin_list *entry,
  452. int mask_and, int mask_or,
  453. void (*final)(struct irq_pin_list *entry))
  454. {
  455. unsigned int reg, pin;
  456. pin = entry->pin;
  457. reg = io_apic_read(entry->apic, 0x10 + pin * 2);
  458. reg &= mask_and;
  459. reg |= mask_or;
  460. io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
  461. if (final)
  462. final(entry);
  463. }
  464. static void io_apic_modify_irq(struct irq_cfg *cfg,
  465. int mask_and, int mask_or,
  466. void (*final)(struct irq_pin_list *entry))
  467. {
  468. struct irq_pin_list *entry;
  469. for_each_irq_pin(entry, cfg->irq_2_pin)
  470. __io_apic_modify_irq(entry, mask_and, mask_or, final);
  471. }
  472. static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
  473. {
  474. __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
  475. IO_APIC_REDIR_MASKED, NULL);
  476. }
  477. static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
  478. {
  479. __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
  480. IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
  481. }
  482. static void io_apic_sync(struct irq_pin_list *entry)
  483. {
  484. /*
  485. * Synchronize the IO-APIC and the CPU by doing
  486. * a dummy read from the IO-APIC
  487. */
  488. struct io_apic __iomem *io_apic;
  489. io_apic = io_apic_base(entry->apic);
  490. readl(&io_apic->data);
  491. }
  492. static void mask_ioapic(struct irq_cfg *cfg)
  493. {
  494. unsigned long flags;
  495. raw_spin_lock_irqsave(&ioapic_lock, flags);
  496. io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
  497. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  498. }
  499. static void mask_ioapic_irq(unsigned int irq)
  500. {
  501. struct irq_cfg *cfg = get_irq_chip_data(irq);
  502. mask_ioapic(cfg);
  503. }
  504. static void __unmask_ioapic(struct irq_cfg *cfg)
  505. {
  506. io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
  507. }
  508. static void unmask_ioapic(struct irq_cfg *cfg)
  509. {
  510. unsigned long flags;
  511. raw_spin_lock_irqsave(&ioapic_lock, flags);
  512. __unmask_ioapic(cfg);
  513. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  514. }
  515. static void unmask_ioapic_irq(unsigned int irq)
  516. {
  517. struct irq_cfg *cfg = get_irq_chip_data(irq);
  518. unmask_ioapic(cfg);
  519. }
  520. static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
  521. {
  522. struct IO_APIC_route_entry entry;
  523. /* Check delivery_mode to be sure we're not clearing an SMI pin */
  524. entry = ioapic_read_entry(apic, pin);
  525. if (entry.delivery_mode == dest_SMI)
  526. return;
  527. /*
  528. * Disable it in the IO-APIC irq-routing table:
  529. */
  530. ioapic_mask_entry(apic, pin);
  531. }
  532. static void clear_IO_APIC (void)
  533. {
  534. int apic, pin;
  535. for (apic = 0; apic < nr_ioapics; apic++)
  536. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
  537. clear_IO_APIC_pin(apic, pin);
  538. }
  539. #ifdef CONFIG_X86_32
  540. /*
  541. * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
  542. * specific CPU-side IRQs.
  543. */
  544. #define MAX_PIRQS 8
  545. static int pirq_entries[MAX_PIRQS] = {
  546. [0 ... MAX_PIRQS - 1] = -1
  547. };
  548. static int __init ioapic_pirq_setup(char *str)
  549. {
  550. int i, max;
  551. int ints[MAX_PIRQS+1];
  552. get_options(str, ARRAY_SIZE(ints), ints);
  553. apic_printk(APIC_VERBOSE, KERN_INFO
  554. "PIRQ redirection, working around broken MP-BIOS.\n");
  555. max = MAX_PIRQS;
  556. if (ints[0] < MAX_PIRQS)
  557. max = ints[0];
  558. for (i = 0; i < max; i++) {
  559. apic_printk(APIC_VERBOSE, KERN_DEBUG
  560. "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
  561. /*
  562. * PIRQs are mapped upside down, usually.
  563. */
  564. pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
  565. }
  566. return 1;
  567. }
  568. __setup("pirq=", ioapic_pirq_setup);
  569. #endif /* CONFIG_X86_32 */
  570. struct IO_APIC_route_entry **alloc_ioapic_entries(void)
  571. {
  572. int apic;
  573. struct IO_APIC_route_entry **ioapic_entries;
  574. ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
  575. GFP_ATOMIC);
  576. if (!ioapic_entries)
  577. return 0;
  578. for (apic = 0; apic < nr_ioapics; apic++) {
  579. ioapic_entries[apic] =
  580. kzalloc(sizeof(struct IO_APIC_route_entry) *
  581. nr_ioapic_registers[apic], GFP_ATOMIC);
  582. if (!ioapic_entries[apic])
  583. goto nomem;
  584. }
  585. return ioapic_entries;
  586. nomem:
  587. while (--apic >= 0)
  588. kfree(ioapic_entries[apic]);
  589. kfree(ioapic_entries);
  590. return 0;
  591. }
  592. /*
  593. * Saves all the IO-APIC RTE's
  594. */
  595. int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
  596. {
  597. int apic, pin;
  598. if (!ioapic_entries)
  599. return -ENOMEM;
  600. for (apic = 0; apic < nr_ioapics; apic++) {
  601. if (!ioapic_entries[apic])
  602. return -ENOMEM;
  603. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
  604. ioapic_entries[apic][pin] =
  605. ioapic_read_entry(apic, pin);
  606. }
  607. return 0;
  608. }
  609. /*
  610. * Mask all IO APIC entries.
  611. */
  612. void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
  613. {
  614. int apic, pin;
  615. if (!ioapic_entries)
  616. return;
  617. for (apic = 0; apic < nr_ioapics; apic++) {
  618. if (!ioapic_entries[apic])
  619. break;
  620. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  621. struct IO_APIC_route_entry entry;
  622. entry = ioapic_entries[apic][pin];
  623. if (!entry.mask) {
  624. entry.mask = 1;
  625. ioapic_write_entry(apic, pin, entry);
  626. }
  627. }
  628. }
  629. }
  630. /*
  631. * Restore IO APIC entries which was saved in ioapic_entries.
  632. */
  633. int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
  634. {
  635. int apic, pin;
  636. if (!ioapic_entries)
  637. return -ENOMEM;
  638. for (apic = 0; apic < nr_ioapics; apic++) {
  639. if (!ioapic_entries[apic])
  640. return -ENOMEM;
  641. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
  642. ioapic_write_entry(apic, pin,
  643. ioapic_entries[apic][pin]);
  644. }
  645. return 0;
  646. }
  647. void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
  648. {
  649. int apic;
  650. for (apic = 0; apic < nr_ioapics; apic++)
  651. kfree(ioapic_entries[apic]);
  652. kfree(ioapic_entries);
  653. }
  654. /*
  655. * Find the IRQ entry number of a certain pin.
  656. */
  657. static int find_irq_entry(int apic, int pin, int type)
  658. {
  659. int i;
  660. for (i = 0; i < mp_irq_entries; i++)
  661. if (mp_irqs[i].irqtype == type &&
  662. (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
  663. mp_irqs[i].dstapic == MP_APIC_ALL) &&
  664. mp_irqs[i].dstirq == pin)
  665. return i;
  666. return -1;
  667. }
  668. /*
  669. * Find the pin to which IRQ[irq] (ISA) is connected
  670. */
  671. static int __init find_isa_irq_pin(int irq, int type)
  672. {
  673. int i;
  674. for (i = 0; i < mp_irq_entries; i++) {
  675. int lbus = mp_irqs[i].srcbus;
  676. if (test_bit(lbus, mp_bus_not_pci) &&
  677. (mp_irqs[i].irqtype == type) &&
  678. (mp_irqs[i].srcbusirq == irq))
  679. return mp_irqs[i].dstirq;
  680. }
  681. return -1;
  682. }
  683. static int __init find_isa_irq_apic(int irq, int type)
  684. {
  685. int i;
  686. for (i = 0; i < mp_irq_entries; i++) {
  687. int lbus = mp_irqs[i].srcbus;
  688. if (test_bit(lbus, mp_bus_not_pci) &&
  689. (mp_irqs[i].irqtype == type) &&
  690. (mp_irqs[i].srcbusirq == irq))
  691. break;
  692. }
  693. if (i < mp_irq_entries) {
  694. int apic;
  695. for(apic = 0; apic < nr_ioapics; apic++) {
  696. if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
  697. return apic;
  698. }
  699. }
  700. return -1;
  701. }
  702. #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
  703. /*
  704. * EISA Edge/Level control register, ELCR
  705. */
  706. static int EISA_ELCR(unsigned int irq)
  707. {
  708. if (irq < legacy_pic->nr_legacy_irqs) {
  709. unsigned int port = 0x4d0 + (irq >> 3);
  710. return (inb(port) >> (irq & 7)) & 1;
  711. }
  712. apic_printk(APIC_VERBOSE, KERN_INFO
  713. "Broken MPtable reports ISA irq %d\n", irq);
  714. return 0;
  715. }
  716. #endif
  717. /* ISA interrupts are always polarity zero edge triggered,
  718. * when listed as conforming in the MP table. */
  719. #define default_ISA_trigger(idx) (0)
  720. #define default_ISA_polarity(idx) (0)
  721. /* EISA interrupts are always polarity zero and can be edge or level
  722. * trigger depending on the ELCR value. If an interrupt is listed as
  723. * EISA conforming in the MP table, that means its trigger type must
  724. * be read in from the ELCR */
  725. #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
  726. #define default_EISA_polarity(idx) default_ISA_polarity(idx)
  727. /* PCI interrupts are always polarity one level triggered,
  728. * when listed as conforming in the MP table. */
  729. #define default_PCI_trigger(idx) (1)
  730. #define default_PCI_polarity(idx) (1)
  731. /* MCA interrupts are always polarity zero level triggered,
  732. * when listed as conforming in the MP table. */
  733. #define default_MCA_trigger(idx) (1)
  734. #define default_MCA_polarity(idx) default_ISA_polarity(idx)
  735. static int MPBIOS_polarity(int idx)
  736. {
  737. int bus = mp_irqs[idx].srcbus;
  738. int polarity;
  739. /*
  740. * Determine IRQ line polarity (high active or low active):
  741. */
  742. switch (mp_irqs[idx].irqflag & 3)
  743. {
  744. case 0: /* conforms, ie. bus-type dependent polarity */
  745. if (test_bit(bus, mp_bus_not_pci))
  746. polarity = default_ISA_polarity(idx);
  747. else
  748. polarity = default_PCI_polarity(idx);
  749. break;
  750. case 1: /* high active */
  751. {
  752. polarity = 0;
  753. break;
  754. }
  755. case 2: /* reserved */
  756. {
  757. printk(KERN_WARNING "broken BIOS!!\n");
  758. polarity = 1;
  759. break;
  760. }
  761. case 3: /* low active */
  762. {
  763. polarity = 1;
  764. break;
  765. }
  766. default: /* invalid */
  767. {
  768. printk(KERN_WARNING "broken BIOS!!\n");
  769. polarity = 1;
  770. break;
  771. }
  772. }
  773. return polarity;
  774. }
  775. static int MPBIOS_trigger(int idx)
  776. {
  777. int bus = mp_irqs[idx].srcbus;
  778. int trigger;
  779. /*
  780. * Determine IRQ trigger mode (edge or level sensitive):
  781. */
  782. switch ((mp_irqs[idx].irqflag>>2) & 3)
  783. {
  784. case 0: /* conforms, ie. bus-type dependent */
  785. if (test_bit(bus, mp_bus_not_pci))
  786. trigger = default_ISA_trigger(idx);
  787. else
  788. trigger = default_PCI_trigger(idx);
  789. #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
  790. switch (mp_bus_id_to_type[bus]) {
  791. case MP_BUS_ISA: /* ISA pin */
  792. {
  793. /* set before the switch */
  794. break;
  795. }
  796. case MP_BUS_EISA: /* EISA pin */
  797. {
  798. trigger = default_EISA_trigger(idx);
  799. break;
  800. }
  801. case MP_BUS_PCI: /* PCI pin */
  802. {
  803. /* set before the switch */
  804. break;
  805. }
  806. case MP_BUS_MCA: /* MCA pin */
  807. {
  808. trigger = default_MCA_trigger(idx);
  809. break;
  810. }
  811. default:
  812. {
  813. printk(KERN_WARNING "broken BIOS!!\n");
  814. trigger = 1;
  815. break;
  816. }
  817. }
  818. #endif
  819. break;
  820. case 1: /* edge */
  821. {
  822. trigger = 0;
  823. break;
  824. }
  825. case 2: /* reserved */
  826. {
  827. printk(KERN_WARNING "broken BIOS!!\n");
  828. trigger = 1;
  829. break;
  830. }
  831. case 3: /* level */
  832. {
  833. trigger = 1;
  834. break;
  835. }
  836. default: /* invalid */
  837. {
  838. printk(KERN_WARNING "broken BIOS!!\n");
  839. trigger = 0;
  840. break;
  841. }
  842. }
  843. return trigger;
  844. }
  845. static inline int irq_polarity(int idx)
  846. {
  847. return MPBIOS_polarity(idx);
  848. }
  849. static inline int irq_trigger(int idx)
  850. {
  851. return MPBIOS_trigger(idx);
  852. }
  853. static int pin_2_irq(int idx, int apic, int pin)
  854. {
  855. int irq;
  856. int bus = mp_irqs[idx].srcbus;
  857. /*
  858. * Debugging check, we are in big trouble if this message pops up!
  859. */
  860. if (mp_irqs[idx].dstirq != pin)
  861. printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
  862. if (test_bit(bus, mp_bus_not_pci)) {
  863. irq = mp_irqs[idx].srcbusirq;
  864. } else {
  865. u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
  866. if (gsi >= NR_IRQS_LEGACY)
  867. irq = gsi;
  868. else
  869. irq = gsi_top + gsi;
  870. }
  871. #ifdef CONFIG_X86_32
  872. /*
  873. * PCI IRQ command line redirection. Yes, limits are hardcoded.
  874. */
  875. if ((pin >= 16) && (pin <= 23)) {
  876. if (pirq_entries[pin-16] != -1) {
  877. if (!pirq_entries[pin-16]) {
  878. apic_printk(APIC_VERBOSE, KERN_DEBUG
  879. "disabling PIRQ%d\n", pin-16);
  880. } else {
  881. irq = pirq_entries[pin-16];
  882. apic_printk(APIC_VERBOSE, KERN_DEBUG
  883. "using PIRQ%d -> IRQ %d\n",
  884. pin-16, irq);
  885. }
  886. }
  887. }
  888. #endif
  889. return irq;
  890. }
  891. /*
  892. * Find a specific PCI IRQ entry.
  893. * Not an __init, possibly needed by modules
  894. */
  895. int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
  896. struct io_apic_irq_attr *irq_attr)
  897. {
  898. int apic, i, best_guess = -1;
  899. apic_printk(APIC_DEBUG,
  900. "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
  901. bus, slot, pin);
  902. if (test_bit(bus, mp_bus_not_pci)) {
  903. apic_printk(APIC_VERBOSE,
  904. "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
  905. return -1;
  906. }
  907. for (i = 0; i < mp_irq_entries; i++) {
  908. int lbus = mp_irqs[i].srcbus;
  909. for (apic = 0; apic < nr_ioapics; apic++)
  910. if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
  911. mp_irqs[i].dstapic == MP_APIC_ALL)
  912. break;
  913. if (!test_bit(lbus, mp_bus_not_pci) &&
  914. !mp_irqs[i].irqtype &&
  915. (bus == lbus) &&
  916. (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
  917. int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
  918. if (!(apic || IO_APIC_IRQ(irq)))
  919. continue;
  920. if (pin == (mp_irqs[i].srcbusirq & 3)) {
  921. set_io_apic_irq_attr(irq_attr, apic,
  922. mp_irqs[i].dstirq,
  923. irq_trigger(i),
  924. irq_polarity(i));
  925. return irq;
  926. }
  927. /*
  928. * Use the first all-but-pin matching entry as a
  929. * best-guess fuzzy result for broken mptables.
  930. */
  931. if (best_guess < 0) {
  932. set_io_apic_irq_attr(irq_attr, apic,
  933. mp_irqs[i].dstirq,
  934. irq_trigger(i),
  935. irq_polarity(i));
  936. best_guess = irq;
  937. }
  938. }
  939. }
  940. return best_guess;
  941. }
  942. EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
  943. void lock_vector_lock(void)
  944. {
  945. /* Used to the online set of cpus does not change
  946. * during assign_irq_vector.
  947. */
  948. raw_spin_lock(&vector_lock);
  949. }
  950. void unlock_vector_lock(void)
  951. {
  952. raw_spin_unlock(&vector_lock);
  953. }
  954. static int
  955. __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
  956. {
  957. /*
  958. * NOTE! The local APIC isn't very good at handling
  959. * multiple interrupts at the same interrupt level.
  960. * As the interrupt level is determined by taking the
  961. * vector number and shifting that right by 4, we
  962. * want to spread these out a bit so that they don't
  963. * all fall in the same interrupt level.
  964. *
  965. * Also, we've got to be careful not to trash gate
  966. * 0x80, because int 0x80 is hm, kind of importantish. ;)
  967. */
  968. static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
  969. static int current_offset = VECTOR_OFFSET_START % 8;
  970. unsigned int old_vector;
  971. int cpu, err;
  972. cpumask_var_t tmp_mask;
  973. if (cfg->move_in_progress)
  974. return -EBUSY;
  975. if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
  976. return -ENOMEM;
  977. old_vector = cfg->vector;
  978. if (old_vector) {
  979. cpumask_and(tmp_mask, mask, cpu_online_mask);
  980. cpumask_and(tmp_mask, cfg->domain, tmp_mask);
  981. if (!cpumask_empty(tmp_mask)) {
  982. free_cpumask_var(tmp_mask);
  983. return 0;
  984. }
  985. }
  986. /* Only try and allocate irqs on cpus that are present */
  987. err = -ENOSPC;
  988. for_each_cpu_and(cpu, mask, cpu_online_mask) {
  989. int new_cpu;
  990. int vector, offset;
  991. apic->vector_allocation_domain(cpu, tmp_mask);
  992. vector = current_vector;
  993. offset = current_offset;
  994. next:
  995. vector += 8;
  996. if (vector >= first_system_vector) {
  997. /* If out of vectors on large boxen, must share them. */
  998. offset = (offset + 1) % 8;
  999. vector = FIRST_EXTERNAL_VECTOR + offset;
  1000. }
  1001. if (unlikely(current_vector == vector))
  1002. continue;
  1003. if (test_bit(vector, used_vectors))
  1004. goto next;
  1005. for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
  1006. if (per_cpu(vector_irq, new_cpu)[vector] != -1)
  1007. goto next;
  1008. /* Found one! */
  1009. current_vector = vector;
  1010. current_offset = offset;
  1011. if (old_vector) {
  1012. cfg->move_in_progress = 1;
  1013. cpumask_copy(cfg->old_domain, cfg->domain);
  1014. }
  1015. for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
  1016. per_cpu(vector_irq, new_cpu)[vector] = irq;
  1017. cfg->vector = vector;
  1018. cpumask_copy(cfg->domain, tmp_mask);
  1019. err = 0;
  1020. break;
  1021. }
  1022. free_cpumask_var(tmp_mask);
  1023. return err;
  1024. }
  1025. int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
  1026. {
  1027. int err;
  1028. unsigned long flags;
  1029. raw_spin_lock_irqsave(&vector_lock, flags);
  1030. err = __assign_irq_vector(irq, cfg, mask);
  1031. raw_spin_unlock_irqrestore(&vector_lock, flags);
  1032. return err;
  1033. }
  1034. static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
  1035. {
  1036. int cpu, vector;
  1037. BUG_ON(!cfg->vector);
  1038. vector = cfg->vector;
  1039. for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
  1040. per_cpu(vector_irq, cpu)[vector] = -1;
  1041. cfg->vector = 0;
  1042. cpumask_clear(cfg->domain);
  1043. if (likely(!cfg->move_in_progress))
  1044. return;
  1045. for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
  1046. for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
  1047. vector++) {
  1048. if (per_cpu(vector_irq, cpu)[vector] != irq)
  1049. continue;
  1050. per_cpu(vector_irq, cpu)[vector] = -1;
  1051. break;
  1052. }
  1053. }
  1054. cfg->move_in_progress = 0;
  1055. }
  1056. void __setup_vector_irq(int cpu)
  1057. {
  1058. /* Initialize vector_irq on a new cpu */
  1059. int irq, vector;
  1060. struct irq_cfg *cfg;
  1061. struct irq_desc *desc;
  1062. /*
  1063. * vector_lock will make sure that we don't run into irq vector
  1064. * assignments that might be happening on another cpu in parallel,
  1065. * while we setup our initial vector to irq mappings.
  1066. */
  1067. raw_spin_lock(&vector_lock);
  1068. /* Mark the inuse vectors */
  1069. for_each_irq_desc(irq, desc) {
  1070. cfg = get_irq_desc_chip_data(desc);
  1071. /*
  1072. * If it is a legacy IRQ handled by the legacy PIC, this cpu
  1073. * will be part of the irq_cfg's domain.
  1074. */
  1075. if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
  1076. cpumask_set_cpu(cpu, cfg->domain);
  1077. if (!cpumask_test_cpu(cpu, cfg->domain))
  1078. continue;
  1079. vector = cfg->vector;
  1080. per_cpu(vector_irq, cpu)[vector] = irq;
  1081. }
  1082. /* Mark the free vectors */
  1083. for (vector = 0; vector < NR_VECTORS; ++vector) {
  1084. irq = per_cpu(vector_irq, cpu)[vector];
  1085. if (irq < 0)
  1086. continue;
  1087. cfg = irq_cfg(irq);
  1088. if (!cpumask_test_cpu(cpu, cfg->domain))
  1089. per_cpu(vector_irq, cpu)[vector] = -1;
  1090. }
  1091. raw_spin_unlock(&vector_lock);
  1092. }
  1093. static struct irq_chip ioapic_chip;
  1094. static struct irq_chip ir_ioapic_chip;
  1095. #define IOAPIC_AUTO -1
  1096. #define IOAPIC_EDGE 0
  1097. #define IOAPIC_LEVEL 1
  1098. #ifdef CONFIG_X86_32
  1099. static inline int IO_APIC_irq_trigger(int irq)
  1100. {
  1101. int apic, idx, pin;
  1102. for (apic = 0; apic < nr_ioapics; apic++) {
  1103. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  1104. idx = find_irq_entry(apic, pin, mp_INT);
  1105. if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
  1106. return irq_trigger(idx);
  1107. }
  1108. }
  1109. /*
  1110. * nonexistent IRQs are edge default
  1111. */
  1112. return 0;
  1113. }
  1114. #else
  1115. static inline int IO_APIC_irq_trigger(int irq)
  1116. {
  1117. return 1;
  1118. }
  1119. #endif
  1120. static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
  1121. {
  1122. if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
  1123. trigger == IOAPIC_LEVEL)
  1124. desc->status |= IRQ_LEVEL;
  1125. else
  1126. desc->status &= ~IRQ_LEVEL;
  1127. if (irq_remapped(irq)) {
  1128. desc->status |= IRQ_MOVE_PCNTXT;
  1129. if (trigger)
  1130. set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
  1131. handle_fasteoi_irq,
  1132. "fasteoi");
  1133. else
  1134. set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
  1135. handle_edge_irq, "edge");
  1136. return;
  1137. }
  1138. if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
  1139. trigger == IOAPIC_LEVEL)
  1140. set_irq_chip_and_handler_name(irq, &ioapic_chip,
  1141. handle_fasteoi_irq,
  1142. "fasteoi");
  1143. else
  1144. set_irq_chip_and_handler_name(irq, &ioapic_chip,
  1145. handle_edge_irq, "edge");
  1146. }
  1147. int setup_ioapic_entry(int apic_id, int irq,
  1148. struct IO_APIC_route_entry *entry,
  1149. unsigned int destination, int trigger,
  1150. int polarity, int vector, int pin)
  1151. {
  1152. /*
  1153. * add it to the IO-APIC irq-routing table:
  1154. */
  1155. memset(entry,0,sizeof(*entry));
  1156. if (intr_remapping_enabled) {
  1157. struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
  1158. struct irte irte;
  1159. struct IR_IO_APIC_route_entry *ir_entry =
  1160. (struct IR_IO_APIC_route_entry *) entry;
  1161. int index;
  1162. if (!iommu)
  1163. panic("No mapping iommu for ioapic %d\n", apic_id);
  1164. index = alloc_irte(iommu, irq, 1);
  1165. if (index < 0)
  1166. panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
  1167. prepare_irte(&irte, vector, destination);
  1168. /* Set source-id of interrupt request */
  1169. set_ioapic_sid(&irte, apic_id);
  1170. modify_irte(irq, &irte);
  1171. ir_entry->index2 = (index >> 15) & 0x1;
  1172. ir_entry->zero = 0;
  1173. ir_entry->format = 1;
  1174. ir_entry->index = (index & 0x7fff);
  1175. /*
  1176. * IO-APIC RTE will be configured with virtual vector.
  1177. * irq handler will do the explicit EOI to the io-apic.
  1178. */
  1179. ir_entry->vector = pin;
  1180. } else {
  1181. entry->delivery_mode = apic->irq_delivery_mode;
  1182. entry->dest_mode = apic->irq_dest_mode;
  1183. entry->dest = destination;
  1184. entry->vector = vector;
  1185. }
  1186. entry->mask = 0; /* enable IRQ */
  1187. entry->trigger = trigger;
  1188. entry->polarity = polarity;
  1189. /* Mask level triggered irqs.
  1190. * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
  1191. */
  1192. if (trigger)
  1193. entry->mask = 1;
  1194. return 0;
  1195. }
  1196. static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
  1197. int trigger, int polarity)
  1198. {
  1199. struct irq_cfg *cfg;
  1200. struct IO_APIC_route_entry entry;
  1201. unsigned int dest;
  1202. if (!IO_APIC_IRQ(irq))
  1203. return;
  1204. cfg = get_irq_desc_chip_data(desc);
  1205. /*
  1206. * For legacy irqs, cfg->domain starts with cpu 0 for legacy
  1207. * controllers like 8259. Now that IO-APIC can handle this irq, update
  1208. * the cfg->domain.
  1209. */
  1210. if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
  1211. apic->vector_allocation_domain(0, cfg->domain);
  1212. if (assign_irq_vector(irq, cfg, apic->target_cpus()))
  1213. return;
  1214. dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
  1215. apic_printk(APIC_VERBOSE,KERN_DEBUG
  1216. "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
  1217. "IRQ %d Mode:%i Active:%i)\n",
  1218. apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
  1219. irq, trigger, polarity);
  1220. if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
  1221. dest, trigger, polarity, cfg->vector, pin)) {
  1222. printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
  1223. mp_ioapics[apic_id].apicid, pin);
  1224. __clear_irq_vector(irq, cfg);
  1225. return;
  1226. }
  1227. ioapic_register_intr(irq, desc, trigger);
  1228. if (irq < legacy_pic->nr_legacy_irqs)
  1229. legacy_pic->mask(irq);
  1230. ioapic_write_entry(apic_id, pin, entry);
  1231. }
  1232. static struct {
  1233. DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
  1234. } mp_ioapic_routing[MAX_IO_APICS];
  1235. static void __init setup_IO_APIC_irqs(void)
  1236. {
  1237. int apic_id, pin, idx, irq;
  1238. int notcon = 0;
  1239. struct irq_desc *desc;
  1240. struct irq_cfg *cfg;
  1241. int node = cpu_to_node(0);
  1242. apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
  1243. for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
  1244. for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
  1245. idx = find_irq_entry(apic_id, pin, mp_INT);
  1246. if (idx == -1) {
  1247. if (!notcon) {
  1248. notcon = 1;
  1249. apic_printk(APIC_VERBOSE,
  1250. KERN_DEBUG " %d-%d",
  1251. mp_ioapics[apic_id].apicid, pin);
  1252. } else
  1253. apic_printk(APIC_VERBOSE, " %d-%d",
  1254. mp_ioapics[apic_id].apicid, pin);
  1255. continue;
  1256. }
  1257. if (notcon) {
  1258. apic_printk(APIC_VERBOSE,
  1259. " (apicid-pin) not connected\n");
  1260. notcon = 0;
  1261. }
  1262. irq = pin_2_irq(idx, apic_id, pin);
  1263. if ((apic_id > 0) && (irq > 16))
  1264. continue;
  1265. /*
  1266. * Skip the timer IRQ if there's a quirk handler
  1267. * installed and if it returns 1:
  1268. */
  1269. if (apic->multi_timer_check &&
  1270. apic->multi_timer_check(apic_id, irq))
  1271. continue;
  1272. desc = irq_to_desc_alloc_node(irq, node);
  1273. if (!desc) {
  1274. printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  1275. continue;
  1276. }
  1277. cfg = get_irq_desc_chip_data(desc);
  1278. add_pin_to_irq_node(cfg, node, apic_id, pin);
  1279. /*
  1280. * don't mark it in pin_programmed, so later acpi could
  1281. * set it correctly when irq < 16
  1282. */
  1283. setup_IO_APIC_irq(apic_id, pin, irq, desc,
  1284. irq_trigger(idx), irq_polarity(idx));
  1285. }
  1286. if (notcon)
  1287. apic_printk(APIC_VERBOSE,
  1288. " (apicid-pin) not connected\n");
  1289. }
  1290. /*
  1291. * for the gsit that is not in first ioapic
  1292. * but could not use acpi_register_gsi()
  1293. * like some special sci in IBM x3330
  1294. */
  1295. void setup_IO_APIC_irq_extra(u32 gsi)
  1296. {
  1297. int apic_id = 0, pin, idx, irq;
  1298. int node = cpu_to_node(0);
  1299. struct irq_desc *desc;
  1300. struct irq_cfg *cfg;
  1301. /*
  1302. * Convert 'gsi' to 'ioapic.pin'.
  1303. */
  1304. apic_id = mp_find_ioapic(gsi);
  1305. if (apic_id < 0)
  1306. return;
  1307. pin = mp_find_ioapic_pin(apic_id, gsi);
  1308. idx = find_irq_entry(apic_id, pin, mp_INT);
  1309. if (idx == -1)
  1310. return;
  1311. irq = pin_2_irq(idx, apic_id, pin);
  1312. #ifdef CONFIG_SPARSE_IRQ
  1313. desc = irq_to_desc(irq);
  1314. if (desc)
  1315. return;
  1316. #endif
  1317. desc = irq_to_desc_alloc_node(irq, node);
  1318. if (!desc) {
  1319. printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  1320. return;
  1321. }
  1322. cfg = get_irq_desc_chip_data(desc);
  1323. add_pin_to_irq_node(cfg, node, apic_id, pin);
  1324. if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
  1325. pr_debug("Pin %d-%d already programmed\n",
  1326. mp_ioapics[apic_id].apicid, pin);
  1327. return;
  1328. }
  1329. set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
  1330. setup_IO_APIC_irq(apic_id, pin, irq, desc,
  1331. irq_trigger(idx), irq_polarity(idx));
  1332. }
  1333. /*
  1334. * Set up the timer pin, possibly with the 8259A-master behind.
  1335. */
  1336. static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
  1337. int vector)
  1338. {
  1339. struct IO_APIC_route_entry entry;
  1340. if (intr_remapping_enabled)
  1341. return;
  1342. memset(&entry, 0, sizeof(entry));
  1343. /*
  1344. * We use logical delivery to get the timer IRQ
  1345. * to the first CPU.
  1346. */
  1347. entry.dest_mode = apic->irq_dest_mode;
  1348. entry.mask = 0; /* don't mask IRQ for edge */
  1349. entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
  1350. entry.delivery_mode = apic->irq_delivery_mode;
  1351. entry.polarity = 0;
  1352. entry.trigger = 0;
  1353. entry.vector = vector;
  1354. /*
  1355. * The timer IRQ doesn't have to know that behind the
  1356. * scene we may have a 8259A-master in AEOI mode ...
  1357. */
  1358. set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
  1359. /*
  1360. * Add it to the IO-APIC irq-routing table:
  1361. */
  1362. ioapic_write_entry(apic_id, pin, entry);
  1363. }
  1364. __apicdebuginit(void) print_IO_APIC(void)
  1365. {
  1366. int apic, i;
  1367. union IO_APIC_reg_00 reg_00;
  1368. union IO_APIC_reg_01 reg_01;
  1369. union IO_APIC_reg_02 reg_02;
  1370. union IO_APIC_reg_03 reg_03;
  1371. unsigned long flags;
  1372. struct irq_cfg *cfg;
  1373. struct irq_desc *desc;
  1374. unsigned int irq;
  1375. printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
  1376. for (i = 0; i < nr_ioapics; i++)
  1377. printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
  1378. mp_ioapics[i].apicid, nr_ioapic_registers[i]);
  1379. /*
  1380. * We are a bit conservative about what we expect. We have to
  1381. * know about every hardware change ASAP.
  1382. */
  1383. printk(KERN_INFO "testing the IO APIC.......................\n");
  1384. for (apic = 0; apic < nr_ioapics; apic++) {
  1385. raw_spin_lock_irqsave(&ioapic_lock, flags);
  1386. reg_00.raw = io_apic_read(apic, 0);
  1387. reg_01.raw = io_apic_read(apic, 1);
  1388. if (reg_01.bits.version >= 0x10)
  1389. reg_02.raw = io_apic_read(apic, 2);
  1390. if (reg_01.bits.version >= 0x20)
  1391. reg_03.raw = io_apic_read(apic, 3);
  1392. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  1393. printk("\n");
  1394. printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
  1395. printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
  1396. printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
  1397. printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
  1398. printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
  1399. printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
  1400. printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
  1401. printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
  1402. printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
  1403. /*
  1404. * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
  1405. * but the value of reg_02 is read as the previous read register
  1406. * value, so ignore it if reg_02 == reg_01.
  1407. */
  1408. if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
  1409. printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
  1410. printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
  1411. }
  1412. /*
  1413. * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
  1414. * or reg_03, but the value of reg_0[23] is read as the previous read
  1415. * register value, so ignore it if reg_03 == reg_0[12].
  1416. */
  1417. if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
  1418. reg_03.raw != reg_01.raw) {
  1419. printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
  1420. printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
  1421. }
  1422. printk(KERN_DEBUG ".... IRQ redirection table:\n");
  1423. printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
  1424. " Stat Dmod Deli Vect:\n");
  1425. for (i = 0; i <= reg_01.bits.entries; i++) {
  1426. struct IO_APIC_route_entry entry;
  1427. entry = ioapic_read_entry(apic, i);
  1428. printk(KERN_DEBUG " %02x %03X ",
  1429. i,
  1430. entry.dest
  1431. );
  1432. printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
  1433. entry.mask,
  1434. entry.trigger,
  1435. entry.irr,
  1436. entry.polarity,
  1437. entry.delivery_status,
  1438. entry.dest_mode,
  1439. entry.delivery_mode,
  1440. entry.vector
  1441. );
  1442. }
  1443. }
  1444. printk(KERN_DEBUG "IRQ to pin mappings:\n");
  1445. for_each_irq_desc(irq, desc) {
  1446. struct irq_pin_list *entry;
  1447. cfg = get_irq_desc_chip_data(desc);
  1448. if (!cfg)
  1449. continue;
  1450. entry = cfg->irq_2_pin;
  1451. if (!entry)
  1452. continue;
  1453. printk(KERN_DEBUG "IRQ%d ", irq);
  1454. for_each_irq_pin(entry, cfg->irq_2_pin)
  1455. printk("-> %d:%d", entry->apic, entry->pin);
  1456. printk("\n");
  1457. }
  1458. printk(KERN_INFO ".................................... done.\n");
  1459. return;
  1460. }
  1461. __apicdebuginit(void) print_APIC_field(int base)
  1462. {
  1463. int i;
  1464. printk(KERN_DEBUG);
  1465. for (i = 0; i < 8; i++)
  1466. printk(KERN_CONT "%08x", apic_read(base + i*0x10));
  1467. printk(KERN_CONT "\n");
  1468. }
  1469. __apicdebuginit(void) print_local_APIC(void *dummy)
  1470. {
  1471. unsigned int i, v, ver, maxlvt;
  1472. u64 icr;
  1473. printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
  1474. smp_processor_id(), hard_smp_processor_id());
  1475. v = apic_read(APIC_ID);
  1476. printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
  1477. v = apic_read(APIC_LVR);
  1478. printk(KERN_INFO "... APIC VERSION: %08x\n", v);
  1479. ver = GET_APIC_VERSION(v);
  1480. maxlvt = lapic_get_maxlvt();
  1481. v = apic_read(APIC_TASKPRI);
  1482. printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
  1483. if (APIC_INTEGRATED(ver)) { /* !82489DX */
  1484. if (!APIC_XAPIC(ver)) {
  1485. v = apic_read(APIC_ARBPRI);
  1486. printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
  1487. v & APIC_ARBPRI_MASK);
  1488. }
  1489. v = apic_read(APIC_PROCPRI);
  1490. printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
  1491. }
  1492. /*
  1493. * Remote read supported only in the 82489DX and local APIC for
  1494. * Pentium processors.
  1495. */
  1496. if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
  1497. v = apic_read(APIC_RRR);
  1498. printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
  1499. }
  1500. v = apic_read(APIC_LDR);
  1501. printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
  1502. if (!x2apic_enabled()) {
  1503. v = apic_read(APIC_DFR);
  1504. printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
  1505. }
  1506. v = apic_read(APIC_SPIV);
  1507. printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
  1508. printk(KERN_DEBUG "... APIC ISR field:\n");
  1509. print_APIC_field(APIC_ISR);
  1510. printk(KERN_DEBUG "... APIC TMR field:\n");
  1511. print_APIC_field(APIC_TMR);
  1512. printk(KERN_DEBUG "... APIC IRR field:\n");
  1513. print_APIC_field(APIC_IRR);
  1514. if (APIC_INTEGRATED(ver)) { /* !82489DX */
  1515. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  1516. apic_write(APIC_ESR, 0);
  1517. v = apic_read(APIC_ESR);
  1518. printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
  1519. }
  1520. icr = apic_icr_read();
  1521. printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
  1522. printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
  1523. v = apic_read(APIC_LVTT);
  1524. printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
  1525. if (maxlvt > 3) { /* PC is LVT#4. */
  1526. v = apic_read(APIC_LVTPC);
  1527. printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
  1528. }
  1529. v = apic_read(APIC_LVT0);
  1530. printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
  1531. v = apic_read(APIC_LVT1);
  1532. printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
  1533. if (maxlvt > 2) { /* ERR is LVT#3. */
  1534. v = apic_read(APIC_LVTERR);
  1535. printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
  1536. }
  1537. v = apic_read(APIC_TMICT);
  1538. printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
  1539. v = apic_read(APIC_TMCCT);
  1540. printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
  1541. v = apic_read(APIC_TDCR);
  1542. printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
  1543. if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
  1544. v = apic_read(APIC_EFEAT);
  1545. maxlvt = (v >> 16) & 0xff;
  1546. printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
  1547. v = apic_read(APIC_ECTRL);
  1548. printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
  1549. for (i = 0; i < maxlvt; i++) {
  1550. v = apic_read(APIC_EILVTn(i));
  1551. printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
  1552. }
  1553. }
  1554. printk("\n");
  1555. }
  1556. __apicdebuginit(void) print_local_APICs(int maxcpu)
  1557. {
  1558. int cpu;
  1559. if (!maxcpu)
  1560. return;
  1561. preempt_disable();
  1562. for_each_online_cpu(cpu) {
  1563. if (cpu >= maxcpu)
  1564. break;
  1565. smp_call_function_single(cpu, print_local_APIC, NULL, 1);
  1566. }
  1567. preempt_enable();
  1568. }
  1569. __apicdebuginit(void) print_PIC(void)
  1570. {
  1571. unsigned int v;
  1572. unsigned long flags;
  1573. if (!legacy_pic->nr_legacy_irqs)
  1574. return;
  1575. printk(KERN_DEBUG "\nprinting PIC contents\n");
  1576. raw_spin_lock_irqsave(&i8259A_lock, flags);
  1577. v = inb(0xa1) << 8 | inb(0x21);
  1578. printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
  1579. v = inb(0xa0) << 8 | inb(0x20);
  1580. printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
  1581. outb(0x0b,0xa0);
  1582. outb(0x0b,0x20);
  1583. v = inb(0xa0) << 8 | inb(0x20);
  1584. outb(0x0a,0xa0);
  1585. outb(0x0a,0x20);
  1586. raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  1587. printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
  1588. v = inb(0x4d1) << 8 | inb(0x4d0);
  1589. printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
  1590. }
  1591. static int __initdata show_lapic = 1;
  1592. static __init int setup_show_lapic(char *arg)
  1593. {
  1594. int num = -1;
  1595. if (strcmp(arg, "all") == 0) {
  1596. show_lapic = CONFIG_NR_CPUS;
  1597. } else {
  1598. get_option(&arg, &num);
  1599. if (num >= 0)
  1600. show_lapic = num;
  1601. }
  1602. return 1;
  1603. }
  1604. __setup("show_lapic=", setup_show_lapic);
  1605. __apicdebuginit(int) print_ICs(void)
  1606. {
  1607. if (apic_verbosity == APIC_QUIET)
  1608. return 0;
  1609. print_PIC();
  1610. /* don't print out if apic is not there */
  1611. if (!cpu_has_apic && !apic_from_smp_config())
  1612. return 0;
  1613. print_local_APICs(show_lapic);
  1614. print_IO_APIC();
  1615. return 0;
  1616. }
  1617. fs_initcall(print_ICs);
  1618. /* Where if anywhere is the i8259 connect in external int mode */
  1619. static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  1620. void __init enable_IO_APIC(void)
  1621. {
  1622. int i8259_apic, i8259_pin;
  1623. int apic;
  1624. if (!legacy_pic->nr_legacy_irqs)
  1625. return;
  1626. for(apic = 0; apic < nr_ioapics; apic++) {
  1627. int pin;
  1628. /* See if any of the pins is in ExtINT mode */
  1629. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  1630. struct IO_APIC_route_entry entry;
  1631. entry = ioapic_read_entry(apic, pin);
  1632. /* If the interrupt line is enabled and in ExtInt mode
  1633. * I have found the pin where the i8259 is connected.
  1634. */
  1635. if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
  1636. ioapic_i8259.apic = apic;
  1637. ioapic_i8259.pin = pin;
  1638. goto found_i8259;
  1639. }
  1640. }
  1641. }
  1642. found_i8259:
  1643. /* Look to see what if the MP table has reported the ExtINT */
  1644. /* If we could not find the appropriate pin by looking at the ioapic
  1645. * the i8259 probably is not connected the ioapic but give the
  1646. * mptable a chance anyway.
  1647. */
  1648. i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
  1649. i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
  1650. /* Trust the MP table if nothing is setup in the hardware */
  1651. if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
  1652. printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
  1653. ioapic_i8259.pin = i8259_pin;
  1654. ioapic_i8259.apic = i8259_apic;
  1655. }
  1656. /* Complain if the MP table and the hardware disagree */
  1657. if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
  1658. (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
  1659. {
  1660. printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
  1661. }
  1662. /*
  1663. * Do not trust the IO-APIC being empty at bootup
  1664. */
  1665. clear_IO_APIC();
  1666. }
  1667. /*
  1668. * Not an __init, needed by the reboot code
  1669. */
  1670. void disable_IO_APIC(void)
  1671. {
  1672. /*
  1673. * Clear the IO-APIC before rebooting:
  1674. */
  1675. clear_IO_APIC();
  1676. if (!legacy_pic->nr_legacy_irqs)
  1677. return;
  1678. /*
  1679. * If the i8259 is routed through an IOAPIC
  1680. * Put that IOAPIC in virtual wire mode
  1681. * so legacy interrupts can be delivered.
  1682. *
  1683. * With interrupt-remapping, for now we will use virtual wire A mode,
  1684. * as virtual wire B is little complex (need to configure both
  1685. * IOAPIC RTE aswell as interrupt-remapping table entry).
  1686. * As this gets called during crash dump, keep this simple for now.
  1687. */
  1688. if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
  1689. struct IO_APIC_route_entry entry;
  1690. memset(&entry, 0, sizeof(entry));
  1691. entry.mask = 0; /* Enabled */
  1692. entry.trigger = 0; /* Edge */
  1693. entry.irr = 0;
  1694. entry.polarity = 0; /* High */
  1695. entry.delivery_status = 0;
  1696. entry.dest_mode = 0; /* Physical */
  1697. entry.delivery_mode = dest_ExtINT; /* ExtInt */
  1698. entry.vector = 0;
  1699. entry.dest = read_apic_id();
  1700. /*
  1701. * Add it to the IO-APIC irq-routing table:
  1702. */
  1703. ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
  1704. }
  1705. /*
  1706. * Use virtual wire A mode when interrupt remapping is enabled.
  1707. */
  1708. if (cpu_has_apic || apic_from_smp_config())
  1709. disconnect_bsp_APIC(!intr_remapping_enabled &&
  1710. ioapic_i8259.pin != -1);
  1711. }
  1712. #ifdef CONFIG_X86_32
  1713. /*
  1714. * function to set the IO-APIC physical IDs based on the
  1715. * values stored in the MPC table.
  1716. *
  1717. * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
  1718. */
  1719. void __init setup_ioapic_ids_from_mpc(void)
  1720. {
  1721. union IO_APIC_reg_00 reg_00;
  1722. physid_mask_t phys_id_present_map;
  1723. int apic_id;
  1724. int i;
  1725. unsigned char old_id;
  1726. unsigned long flags;
  1727. if (acpi_ioapic)
  1728. return;
  1729. /*
  1730. * Don't check I/O APIC IDs for xAPIC systems. They have
  1731. * no meaning without the serial APIC bus.
  1732. */
  1733. if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
  1734. || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
  1735. return;
  1736. /*
  1737. * This is broken; anything with a real cpu count has to
  1738. * circumvent this idiocy regardless.
  1739. */
  1740. apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
  1741. /*
  1742. * Set the IOAPIC ID to the value stored in the MPC table.
  1743. */
  1744. for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
  1745. /* Read the register 0 value */
  1746. raw_spin_lock_irqsave(&ioapic_lock, flags);
  1747. reg_00.raw = io_apic_read(apic_id, 0);
  1748. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  1749. old_id = mp_ioapics[apic_id].apicid;
  1750. if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
  1751. printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
  1752. apic_id, mp_ioapics[apic_id].apicid);
  1753. printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  1754. reg_00.bits.ID);
  1755. mp_ioapics[apic_id].apicid = reg_00.bits.ID;
  1756. }
  1757. /*
  1758. * Sanity check, is the ID really free? Every APIC in a
  1759. * system must have a unique ID or we get lots of nice
  1760. * 'stuck on smp_invalidate_needed IPI wait' messages.
  1761. */
  1762. if (apic->check_apicid_used(&phys_id_present_map,
  1763. mp_ioapics[apic_id].apicid)) {
  1764. printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
  1765. apic_id, mp_ioapics[apic_id].apicid);
  1766. for (i = 0; i < get_physical_broadcast(); i++)
  1767. if (!physid_isset(i, phys_id_present_map))
  1768. break;
  1769. if (i >= get_physical_broadcast())
  1770. panic("Max APIC ID exceeded!\n");
  1771. printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  1772. i);
  1773. physid_set(i, phys_id_present_map);
  1774. mp_ioapics[apic_id].apicid = i;
  1775. } else {
  1776. physid_mask_t tmp;
  1777. apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
  1778. apic_printk(APIC_VERBOSE, "Setting %d in the "
  1779. "phys_id_present_map\n",
  1780. mp_ioapics[apic_id].apicid);
  1781. physids_or(phys_id_present_map, phys_id_present_map, tmp);
  1782. }
  1783. /*
  1784. * We need to adjust the IRQ routing table
  1785. * if the ID changed.
  1786. */
  1787. if (old_id != mp_ioapics[apic_id].apicid)
  1788. for (i = 0; i < mp_irq_entries; i++)
  1789. if (mp_irqs[i].dstapic == old_id)
  1790. mp_irqs[i].dstapic
  1791. = mp_ioapics[apic_id].apicid;
  1792. /*
  1793. * Read the right value from the MPC table and
  1794. * write it into the ID register.
  1795. */
  1796. apic_printk(APIC_VERBOSE, KERN_INFO
  1797. "...changing IO-APIC physical APIC ID to %d ...",
  1798. mp_ioapics[apic_id].apicid);
  1799. reg_00.bits.ID = mp_ioapics[apic_id].apicid;
  1800. raw_spin_lock_irqsave(&ioapic_lock, flags);
  1801. io_apic_write(apic_id, 0, reg_00.raw);
  1802. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  1803. /*
  1804. * Sanity check
  1805. */
  1806. raw_spin_lock_irqsave(&ioapic_lock, flags);
  1807. reg_00.raw = io_apic_read(apic_id, 0);
  1808. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  1809. if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
  1810. printk("could not set ID!\n");
  1811. else
  1812. apic_printk(APIC_VERBOSE, " ok.\n");
  1813. }
  1814. }
  1815. #endif
  1816. int no_timer_check __initdata;
  1817. static int __init notimercheck(char *s)
  1818. {
  1819. no_timer_check = 1;
  1820. return 1;
  1821. }
  1822. __setup("no_timer_check", notimercheck);
  1823. /*
  1824. * There is a nasty bug in some older SMP boards, their mptable lies
  1825. * about the timer IRQ. We do the following to work around the situation:
  1826. *
  1827. * - timer IRQ defaults to IO-APIC IRQ
  1828. * - if this function detects that timer IRQs are defunct, then we fall
  1829. * back to ISA timer IRQs
  1830. */
  1831. static int __init timer_irq_works(void)
  1832. {
  1833. unsigned long t1 = jiffies;
  1834. unsigned long flags;
  1835. if (no_timer_check)
  1836. return 1;
  1837. local_save_flags(flags);
  1838. local_irq_enable();
  1839. /* Let ten ticks pass... */
  1840. mdelay((10 * 1000) / HZ);
  1841. local_irq_restore(flags);
  1842. /*
  1843. * Expect a few ticks at least, to be sure some possible
  1844. * glue logic does not lock up after one or two first
  1845. * ticks in a non-ExtINT mode. Also the local APIC
  1846. * might have cached one ExtINT interrupt. Finally, at
  1847. * least one tick may be lost due to delays.
  1848. */
  1849. /* jiffies wrap? */
  1850. if (time_after(jiffies, t1 + 4))
  1851. return 1;
  1852. return 0;
  1853. }
  1854. /*
  1855. * In the SMP+IOAPIC case it might happen that there are an unspecified
  1856. * number of pending IRQ events unhandled. These cases are very rare,
  1857. * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
  1858. * better to do it this way as thus we do not have to be aware of
  1859. * 'pending' interrupts in the IRQ path, except at this point.
  1860. */
  1861. /*
  1862. * Edge triggered needs to resend any interrupt
  1863. * that was delayed but this is now handled in the device
  1864. * independent code.
  1865. */
  1866. /*
  1867. * Starting up a edge-triggered IO-APIC interrupt is
  1868. * nasty - we need to make sure that we get the edge.
  1869. * If it is already asserted for some reason, we need
  1870. * return 1 to indicate that is was pending.
  1871. *
  1872. * This is not complete - we should be able to fake
  1873. * an edge even if it isn't on the 8259A...
  1874. */
  1875. static unsigned int startup_ioapic_irq(unsigned int irq)
  1876. {
  1877. int was_pending = 0;
  1878. unsigned long flags;
  1879. struct irq_cfg *cfg;
  1880. raw_spin_lock_irqsave(&ioapic_lock, flags);
  1881. if (irq < legacy_pic->nr_legacy_irqs) {
  1882. legacy_pic->mask(irq);
  1883. if (legacy_pic->irq_pending(irq))
  1884. was_pending = 1;
  1885. }
  1886. cfg = irq_cfg(irq);
  1887. __unmask_ioapic(cfg);
  1888. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  1889. return was_pending;
  1890. }
  1891. static int ioapic_retrigger_irq(unsigned int irq)
  1892. {
  1893. struct irq_cfg *cfg = irq_cfg(irq);
  1894. unsigned long flags;
  1895. raw_spin_lock_irqsave(&vector_lock, flags);
  1896. apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
  1897. raw_spin_unlock_irqrestore(&vector_lock, flags);
  1898. return 1;
  1899. }
  1900. /*
  1901. * Level and edge triggered IO-APIC interrupts need different handling,
  1902. * so we use two separate IRQ descriptors. Edge triggered IRQs can be
  1903. * handled with the level-triggered descriptor, but that one has slightly
  1904. * more overhead. Level-triggered interrupts cannot be handled with the
  1905. * edge-triggered handler, without risking IRQ storms and other ugly
  1906. * races.
  1907. */
  1908. #ifdef CONFIG_SMP
  1909. void send_cleanup_vector(struct irq_cfg *cfg)
  1910. {
  1911. cpumask_var_t cleanup_mask;
  1912. if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
  1913. unsigned int i;
  1914. for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
  1915. apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
  1916. } else {
  1917. cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
  1918. apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
  1919. free_cpumask_var(cleanup_mask);
  1920. }
  1921. cfg->move_in_progress = 0;
  1922. }
  1923. static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
  1924. {
  1925. int apic, pin;
  1926. struct irq_pin_list *entry;
  1927. u8 vector = cfg->vector;
  1928. for_each_irq_pin(entry, cfg->irq_2_pin) {
  1929. unsigned int reg;
  1930. apic = entry->apic;
  1931. pin = entry->pin;
  1932. /*
  1933. * With interrupt-remapping, destination information comes
  1934. * from interrupt-remapping table entry.
  1935. */
  1936. if (!irq_remapped(irq))
  1937. io_apic_write(apic, 0x11 + pin*2, dest);
  1938. reg = io_apic_read(apic, 0x10 + pin*2);
  1939. reg &= ~IO_APIC_REDIR_VECTOR_MASK;
  1940. reg |= vector;
  1941. io_apic_modify(apic, 0x10 + pin*2, reg);
  1942. }
  1943. }
  1944. /*
  1945. * Either sets desc->affinity to a valid value, and returns
  1946. * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
  1947. * leaves desc->affinity untouched.
  1948. */
  1949. unsigned int
  1950. set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
  1951. unsigned int *dest_id)
  1952. {
  1953. struct irq_cfg *cfg;
  1954. unsigned int irq;
  1955. if (!cpumask_intersects(mask, cpu_online_mask))
  1956. return -1;
  1957. irq = desc->irq;
  1958. cfg = get_irq_desc_chip_data(desc);
  1959. if (assign_irq_vector(irq, cfg, mask))
  1960. return -1;
  1961. cpumask_copy(desc->affinity, mask);
  1962. *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
  1963. return 0;
  1964. }
  1965. static int
  1966. set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
  1967. {
  1968. struct irq_cfg *cfg;
  1969. unsigned long flags;
  1970. unsigned int dest;
  1971. unsigned int irq;
  1972. int ret = -1;
  1973. irq = desc->irq;
  1974. cfg = get_irq_desc_chip_data(desc);
  1975. raw_spin_lock_irqsave(&ioapic_lock, flags);
  1976. ret = set_desc_affinity(desc, mask, &dest);
  1977. if (!ret) {
  1978. /* Only the high 8 bits are valid. */
  1979. dest = SET_APIC_LOGICAL_ID(dest);
  1980. __target_IO_APIC_irq(irq, dest, cfg);
  1981. }
  1982. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  1983. return ret;
  1984. }
  1985. static int
  1986. set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
  1987. {
  1988. struct irq_desc *desc;
  1989. desc = irq_to_desc(irq);
  1990. return set_ioapic_affinity_irq_desc(desc, mask);
  1991. }
  1992. #ifdef CONFIG_INTR_REMAP
  1993. /*
  1994. * Migrate the IO-APIC irq in the presence of intr-remapping.
  1995. *
  1996. * For both level and edge triggered, irq migration is a simple atomic
  1997. * update(of vector and cpu destination) of IRTE and flush the hardware cache.
  1998. *
  1999. * For level triggered, we eliminate the io-apic RTE modification (with the
  2000. * updated vector information), by using a virtual vector (io-apic pin number).
  2001. * Real vector that is used for interrupting cpu will be coming from
  2002. * the interrupt-remapping table entry.
  2003. */
  2004. static int
  2005. migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
  2006. {
  2007. struct irq_cfg *cfg;
  2008. struct irte irte;
  2009. unsigned int dest;
  2010. unsigned int irq;
  2011. int ret = -1;
  2012. if (!cpumask_intersects(mask, cpu_online_mask))
  2013. return ret;
  2014. irq = desc->irq;
  2015. if (get_irte(irq, &irte))
  2016. return ret;
  2017. cfg = get_irq_desc_chip_data(desc);
  2018. if (assign_irq_vector(irq, cfg, mask))
  2019. return ret;
  2020. dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
  2021. irte.vector = cfg->vector;
  2022. irte.dest_id = IRTE_DEST(dest);
  2023. /*
  2024. * Modified the IRTE and flushes the Interrupt entry cache.
  2025. */
  2026. modify_irte(irq, &irte);
  2027. if (cfg->move_in_progress)
  2028. send_cleanup_vector(cfg);
  2029. cpumask_copy(desc->affinity, mask);
  2030. return 0;
  2031. }
  2032. /*
  2033. * Migrates the IRQ destination in the process context.
  2034. */
  2035. static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
  2036. const struct cpumask *mask)
  2037. {
  2038. return migrate_ioapic_irq_desc(desc, mask);
  2039. }
  2040. static int set_ir_ioapic_affinity_irq(unsigned int irq,
  2041. const struct cpumask *mask)
  2042. {
  2043. struct irq_desc *desc = irq_to_desc(irq);
  2044. return set_ir_ioapic_affinity_irq_desc(desc, mask);
  2045. }
  2046. #else
  2047. static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
  2048. const struct cpumask *mask)
  2049. {
  2050. return 0;
  2051. }
  2052. #endif
  2053. asmlinkage void smp_irq_move_cleanup_interrupt(void)
  2054. {
  2055. unsigned vector, me;
  2056. ack_APIC_irq();
  2057. exit_idle();
  2058. irq_enter();
  2059. me = smp_processor_id();
  2060. for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
  2061. unsigned int irq;
  2062. unsigned int irr;
  2063. struct irq_desc *desc;
  2064. struct irq_cfg *cfg;
  2065. irq = __get_cpu_var(vector_irq)[vector];
  2066. if (irq == -1)
  2067. continue;
  2068. desc = irq_to_desc(irq);
  2069. if (!desc)
  2070. continue;
  2071. cfg = irq_cfg(irq);
  2072. raw_spin_lock(&desc->lock);
  2073. /*
  2074. * Check if the irq migration is in progress. If so, we
  2075. * haven't received the cleanup request yet for this irq.
  2076. */
  2077. if (cfg->move_in_progress)
  2078. goto unlock;
  2079. if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
  2080. goto unlock;
  2081. irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
  2082. /*
  2083. * Check if the vector that needs to be cleanedup is
  2084. * registered at the cpu's IRR. If so, then this is not
  2085. * the best time to clean it up. Lets clean it up in the
  2086. * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
  2087. * to myself.
  2088. */
  2089. if (irr & (1 << (vector % 32))) {
  2090. apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
  2091. goto unlock;
  2092. }
  2093. __get_cpu_var(vector_irq)[vector] = -1;
  2094. unlock:
  2095. raw_spin_unlock(&desc->lock);
  2096. }
  2097. irq_exit();
  2098. }
  2099. static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
  2100. {
  2101. unsigned me;
  2102. if (likely(!cfg->move_in_progress))
  2103. return;
  2104. me = smp_processor_id();
  2105. if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
  2106. send_cleanup_vector(cfg);
  2107. }
  2108. static void irq_complete_move(struct irq_cfg *cfg)
  2109. {
  2110. __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
  2111. }
  2112. void irq_force_complete_move(int irq)
  2113. {
  2114. struct irq_cfg *cfg = get_irq_chip_data(irq);
  2115. if (!cfg)
  2116. return;
  2117. __irq_complete_move(cfg, cfg->vector);
  2118. }
  2119. #else
  2120. static inline void irq_complete_move(struct irq_cfg *cfg) { }
  2121. #endif
  2122. static void ack_apic_edge(unsigned int irq)
  2123. {
  2124. struct irq_cfg *cfg = get_irq_chip_data(irq);
  2125. irq_complete_move(cfg);
  2126. move_native_irq(irq);
  2127. ack_APIC_irq();
  2128. }
  2129. atomic_t irq_mis_count;
  2130. /*
  2131. * IO-APIC versions below 0x20 don't support EOI register.
  2132. * For the record, here is the information about various versions:
  2133. * 0Xh 82489DX
  2134. * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
  2135. * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
  2136. * 30h-FFh Reserved
  2137. *
  2138. * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
  2139. * version as 0x2. This is an error with documentation and these ICH chips
  2140. * use io-apic's of version 0x20.
  2141. *
  2142. * For IO-APIC's with EOI register, we use that to do an explicit EOI.
  2143. * Otherwise, we simulate the EOI message manually by changing the trigger
  2144. * mode to edge and then back to level, with RTE being masked during this.
  2145. */
  2146. static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
  2147. {
  2148. struct irq_pin_list *entry;
  2149. unsigned long flags;
  2150. raw_spin_lock_irqsave(&ioapic_lock, flags);
  2151. for_each_irq_pin(entry, cfg->irq_2_pin) {
  2152. if (mp_ioapics[entry->apic].apicver >= 0x20) {
  2153. /*
  2154. * Intr-remapping uses pin number as the virtual vector
  2155. * in the RTE. Actual vector is programmed in
  2156. * intr-remapping table entry. Hence for the io-apic
  2157. * EOI we use the pin number.
  2158. */
  2159. if (irq_remapped(irq))
  2160. io_apic_eoi(entry->apic, entry->pin);
  2161. else
  2162. io_apic_eoi(entry->apic, cfg->vector);
  2163. } else {
  2164. __mask_and_edge_IO_APIC_irq(entry);
  2165. __unmask_and_level_IO_APIC_irq(entry);
  2166. }
  2167. }
  2168. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  2169. }
  2170. static void ack_apic_level(unsigned int irq)
  2171. {
  2172. struct irq_desc *desc = irq_to_desc(irq);
  2173. struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
  2174. int i, do_unmask_irq = 0;
  2175. unsigned long v;
  2176. irq_complete_move(cfg);
  2177. #ifdef CONFIG_GENERIC_PENDING_IRQ
  2178. /* If we are moving the irq we need to mask it */
  2179. if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
  2180. do_unmask_irq = 1;
  2181. mask_ioapic(cfg);
  2182. }
  2183. #endif
  2184. /*
  2185. * It appears there is an erratum which affects at least version 0x11
  2186. * of I/O APIC (that's the 82093AA and cores integrated into various
  2187. * chipsets). Under certain conditions a level-triggered interrupt is
  2188. * erroneously delivered as edge-triggered one but the respective IRR
  2189. * bit gets set nevertheless. As a result the I/O unit expects an EOI
  2190. * message but it will never arrive and further interrupts are blocked
  2191. * from the source. The exact reason is so far unknown, but the
  2192. * phenomenon was observed when two consecutive interrupt requests
  2193. * from a given source get delivered to the same CPU and the source is
  2194. * temporarily disabled in between.
  2195. *
  2196. * A workaround is to simulate an EOI message manually. We achieve it
  2197. * by setting the trigger mode to edge and then to level when the edge
  2198. * trigger mode gets detected in the TMR of a local APIC for a
  2199. * level-triggered interrupt. We mask the source for the time of the
  2200. * operation to prevent an edge-triggered interrupt escaping meanwhile.
  2201. * The idea is from Manfred Spraul. --macro
  2202. *
  2203. * Also in the case when cpu goes offline, fixup_irqs() will forward
  2204. * any unhandled interrupt on the offlined cpu to the new cpu
  2205. * destination that is handling the corresponding interrupt. This
  2206. * interrupt forwarding is done via IPI's. Hence, in this case also
  2207. * level-triggered io-apic interrupt will be seen as an edge
  2208. * interrupt in the IRR. And we can't rely on the cpu's EOI
  2209. * to be broadcasted to the IO-APIC's which will clear the remoteIRR
  2210. * corresponding to the level-triggered interrupt. Hence on IO-APIC's
  2211. * supporting EOI register, we do an explicit EOI to clear the
  2212. * remote IRR and on IO-APIC's which don't have an EOI register,
  2213. * we use the above logic (mask+edge followed by unmask+level) from
  2214. * Manfred Spraul to clear the remote IRR.
  2215. */
  2216. i = cfg->vector;
  2217. v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
  2218. /*
  2219. * We must acknowledge the irq before we move it or the acknowledge will
  2220. * not propagate properly.
  2221. */
  2222. ack_APIC_irq();
  2223. /*
  2224. * Tail end of clearing remote IRR bit (either by delivering the EOI
  2225. * message via io-apic EOI register write or simulating it using
  2226. * mask+edge followed by unnask+level logic) manually when the
  2227. * level triggered interrupt is seen as the edge triggered interrupt
  2228. * at the cpu.
  2229. */
  2230. if (!(v & (1 << (i & 0x1f)))) {
  2231. atomic_inc(&irq_mis_count);
  2232. eoi_ioapic_irq(irq, cfg);
  2233. }
  2234. /* Now we can move and renable the irq */
  2235. if (unlikely(do_unmask_irq)) {
  2236. /* Only migrate the irq if the ack has been received.
  2237. *
  2238. * On rare occasions the broadcast level triggered ack gets
  2239. * delayed going to ioapics, and if we reprogram the
  2240. * vector while Remote IRR is still set the irq will never
  2241. * fire again.
  2242. *
  2243. * To prevent this scenario we read the Remote IRR bit
  2244. * of the ioapic. This has two effects.
  2245. * - On any sane system the read of the ioapic will
  2246. * flush writes (and acks) going to the ioapic from
  2247. * this cpu.
  2248. * - We get to see if the ACK has actually been delivered.
  2249. *
  2250. * Based on failed experiments of reprogramming the
  2251. * ioapic entry from outside of irq context starting
  2252. * with masking the ioapic entry and then polling until
  2253. * Remote IRR was clear before reprogramming the
  2254. * ioapic I don't trust the Remote IRR bit to be
  2255. * completey accurate.
  2256. *
  2257. * However there appears to be no other way to plug
  2258. * this race, so if the Remote IRR bit is not
  2259. * accurate and is causing problems then it is a hardware bug
  2260. * and you can go talk to the chipset vendor about it.
  2261. */
  2262. if (!io_apic_level_ack_pending(cfg))
  2263. move_masked_irq(irq);
  2264. unmask_ioapic(cfg);
  2265. }
  2266. }
  2267. #ifdef CONFIG_INTR_REMAP
  2268. static void ir_ack_apic_edge(unsigned int irq)
  2269. {
  2270. ack_APIC_irq();
  2271. }
  2272. static void ir_ack_apic_level(unsigned int irq)
  2273. {
  2274. struct irq_cfg *cfg = get_irq_chip_data(irq);
  2275. ack_APIC_irq();
  2276. eoi_ioapic_irq(irq, cfg);
  2277. }
  2278. #endif /* CONFIG_INTR_REMAP */
  2279. static struct irq_chip ioapic_chip __read_mostly = {
  2280. .name = "IO-APIC",
  2281. .startup = startup_ioapic_irq,
  2282. .mask = mask_ioapic_irq,
  2283. .unmask = unmask_ioapic_irq,
  2284. .ack = ack_apic_edge,
  2285. .eoi = ack_apic_level,
  2286. #ifdef CONFIG_SMP
  2287. .set_affinity = set_ioapic_affinity_irq,
  2288. #endif
  2289. .retrigger = ioapic_retrigger_irq,
  2290. };
  2291. static struct irq_chip ir_ioapic_chip __read_mostly = {
  2292. .name = "IR-IO-APIC",
  2293. .startup = startup_ioapic_irq,
  2294. .mask = mask_ioapic_irq,
  2295. .unmask = unmask_ioapic_irq,
  2296. #ifdef CONFIG_INTR_REMAP
  2297. .ack = ir_ack_apic_edge,
  2298. .eoi = ir_ack_apic_level,
  2299. #ifdef CONFIG_SMP
  2300. .set_affinity = set_ir_ioapic_affinity_irq,
  2301. #endif
  2302. #endif
  2303. .retrigger = ioapic_retrigger_irq,
  2304. };
  2305. static inline void init_IO_APIC_traps(void)
  2306. {
  2307. int irq;
  2308. struct irq_desc *desc;
  2309. struct irq_cfg *cfg;
  2310. /*
  2311. * NOTE! The local APIC isn't very good at handling
  2312. * multiple interrupts at the same interrupt level.
  2313. * As the interrupt level is determined by taking the
  2314. * vector number and shifting that right by 4, we
  2315. * want to spread these out a bit so that they don't
  2316. * all fall in the same interrupt level.
  2317. *
  2318. * Also, we've got to be careful not to trash gate
  2319. * 0x80, because int 0x80 is hm, kind of importantish. ;)
  2320. */
  2321. for_each_irq_desc(irq, desc) {
  2322. cfg = get_irq_desc_chip_data(desc);
  2323. if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
  2324. /*
  2325. * Hmm.. We don't have an entry for this,
  2326. * so default to an old-fashioned 8259
  2327. * interrupt if we can..
  2328. */
  2329. if (irq < legacy_pic->nr_legacy_irqs)
  2330. legacy_pic->make_irq(irq);
  2331. else
  2332. /* Strange. Oh, well.. */
  2333. desc->chip = &no_irq_chip;
  2334. }
  2335. }
  2336. }
  2337. /*
  2338. * The local APIC irq-chip implementation:
  2339. */
  2340. static void mask_lapic_irq(unsigned int irq)
  2341. {
  2342. unsigned long v;
  2343. v = apic_read(APIC_LVT0);
  2344. apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
  2345. }
  2346. static void unmask_lapic_irq(unsigned int irq)
  2347. {
  2348. unsigned long v;
  2349. v = apic_read(APIC_LVT0);
  2350. apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
  2351. }
  2352. static void ack_lapic_irq(unsigned int irq)
  2353. {
  2354. ack_APIC_irq();
  2355. }
  2356. static struct irq_chip lapic_chip __read_mostly = {
  2357. .name = "local-APIC",
  2358. .mask = mask_lapic_irq,
  2359. .unmask = unmask_lapic_irq,
  2360. .ack = ack_lapic_irq,
  2361. };
  2362. static void lapic_register_intr(int irq, struct irq_desc *desc)
  2363. {
  2364. desc->status &= ~IRQ_LEVEL;
  2365. set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
  2366. "edge");
  2367. }
  2368. static void __init setup_nmi(void)
  2369. {
  2370. /*
  2371. * Dirty trick to enable the NMI watchdog ...
  2372. * We put the 8259A master into AEOI mode and
  2373. * unmask on all local APICs LVT0 as NMI.
  2374. *
  2375. * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
  2376. * is from Maciej W. Rozycki - so we do not have to EOI from
  2377. * the NMI handler or the timer interrupt.
  2378. */
  2379. apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
  2380. enable_NMI_through_LVT0();
  2381. apic_printk(APIC_VERBOSE, " done.\n");
  2382. }
  2383. /*
  2384. * This looks a bit hackish but it's about the only one way of sending
  2385. * a few INTA cycles to 8259As and any associated glue logic. ICR does
  2386. * not support the ExtINT mode, unfortunately. We need to send these
  2387. * cycles as some i82489DX-based boards have glue logic that keeps the
  2388. * 8259A interrupt line asserted until INTA. --macro
  2389. */
  2390. static inline void __init unlock_ExtINT_logic(void)
  2391. {
  2392. int apic, pin, i;
  2393. struct IO_APIC_route_entry entry0, entry1;
  2394. unsigned char save_control, save_freq_select;
  2395. pin = find_isa_irq_pin(8, mp_INT);
  2396. if (pin == -1) {
  2397. WARN_ON_ONCE(1);
  2398. return;
  2399. }
  2400. apic = find_isa_irq_apic(8, mp_INT);
  2401. if (apic == -1) {
  2402. WARN_ON_ONCE(1);
  2403. return;
  2404. }
  2405. entry0 = ioapic_read_entry(apic, pin);
  2406. clear_IO_APIC_pin(apic, pin);
  2407. memset(&entry1, 0, sizeof(entry1));
  2408. entry1.dest_mode = 0; /* physical delivery */
  2409. entry1.mask = 0; /* unmask IRQ now */
  2410. entry1.dest = hard_smp_processor_id();
  2411. entry1.delivery_mode = dest_ExtINT;
  2412. entry1.polarity = entry0.polarity;
  2413. entry1.trigger = 0;
  2414. entry1.vector = 0;
  2415. ioapic_write_entry(apic, pin, entry1);
  2416. save_control = CMOS_READ(RTC_CONTROL);
  2417. save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
  2418. CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
  2419. RTC_FREQ_SELECT);
  2420. CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
  2421. i = 100;
  2422. while (i-- > 0) {
  2423. mdelay(10);
  2424. if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
  2425. i -= 10;
  2426. }
  2427. CMOS_WRITE(save_control, RTC_CONTROL);
  2428. CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
  2429. clear_IO_APIC_pin(apic, pin);
  2430. ioapic_write_entry(apic, pin, entry0);
  2431. }
  2432. static int disable_timer_pin_1 __initdata;
  2433. /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
  2434. static int __init disable_timer_pin_setup(char *arg)
  2435. {
  2436. disable_timer_pin_1 = 1;
  2437. return 0;
  2438. }
  2439. early_param("disable_timer_pin_1", disable_timer_pin_setup);
  2440. int timer_through_8259 __initdata;
  2441. /*
  2442. * This code may look a bit paranoid, but it's supposed to cooperate with
  2443. * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
  2444. * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
  2445. * fanatically on his truly buggy board.
  2446. *
  2447. * FIXME: really need to revamp this for all platforms.
  2448. */
  2449. static inline void __init check_timer(void)
  2450. {
  2451. struct irq_desc *desc = irq_to_desc(0);
  2452. struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
  2453. int node = cpu_to_node(0);
  2454. int apic1, pin1, apic2, pin2;
  2455. unsigned long flags;
  2456. int no_pin1 = 0;
  2457. local_irq_save(flags);
  2458. /*
  2459. * get/set the timer IRQ vector:
  2460. */
  2461. legacy_pic->mask(0);
  2462. assign_irq_vector(0, cfg, apic->target_cpus());
  2463. /*
  2464. * As IRQ0 is to be enabled in the 8259A, the virtual
  2465. * wire has to be disabled in the local APIC. Also
  2466. * timer interrupts need to be acknowledged manually in
  2467. * the 8259A for the i82489DX when using the NMI
  2468. * watchdog as that APIC treats NMIs as level-triggered.
  2469. * The AEOI mode will finish them in the 8259A
  2470. * automatically.
  2471. */
  2472. apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  2473. legacy_pic->init(1);
  2474. #ifdef CONFIG_X86_32
  2475. {
  2476. unsigned int ver;
  2477. ver = apic_read(APIC_LVR);
  2478. ver = GET_APIC_VERSION(ver);
  2479. timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
  2480. }
  2481. #endif
  2482. pin1 = find_isa_irq_pin(0, mp_INT);
  2483. apic1 = find_isa_irq_apic(0, mp_INT);
  2484. pin2 = ioapic_i8259.pin;
  2485. apic2 = ioapic_i8259.apic;
  2486. apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
  2487. "apic1=%d pin1=%d apic2=%d pin2=%d\n",
  2488. cfg->vector, apic1, pin1, apic2, pin2);
  2489. /*
  2490. * Some BIOS writers are clueless and report the ExtINTA
  2491. * I/O APIC input from the cascaded 8259A as the timer
  2492. * interrupt input. So just in case, if only one pin
  2493. * was found above, try it both directly and through the
  2494. * 8259A.
  2495. */
  2496. if (pin1 == -1) {
  2497. if (intr_remapping_enabled)
  2498. panic("BIOS bug: timer not connected to IO-APIC");
  2499. pin1 = pin2;
  2500. apic1 = apic2;
  2501. no_pin1 = 1;
  2502. } else if (pin2 == -1) {
  2503. pin2 = pin1;
  2504. apic2 = apic1;
  2505. }
  2506. if (pin1 != -1) {
  2507. /*
  2508. * Ok, does IRQ0 through the IOAPIC work?
  2509. */
  2510. if (no_pin1) {
  2511. add_pin_to_irq_node(cfg, node, apic1, pin1);
  2512. setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
  2513. } else {
  2514. /* for edge trigger, setup_IO_APIC_irq already
  2515. * leave it unmasked.
  2516. * so only need to unmask if it is level-trigger
  2517. * do we really have level trigger timer?
  2518. */
  2519. int idx;
  2520. idx = find_irq_entry(apic1, pin1, mp_INT);
  2521. if (idx != -1 && irq_trigger(idx))
  2522. unmask_ioapic(cfg);
  2523. }
  2524. if (timer_irq_works()) {
  2525. if (nmi_watchdog == NMI_IO_APIC) {
  2526. setup_nmi();
  2527. legacy_pic->unmask(0);
  2528. }
  2529. if (disable_timer_pin_1 > 0)
  2530. clear_IO_APIC_pin(0, pin1);
  2531. goto out;
  2532. }
  2533. if (intr_remapping_enabled)
  2534. panic("timer doesn't work through Interrupt-remapped IO-APIC");
  2535. local_irq_disable();
  2536. clear_IO_APIC_pin(apic1, pin1);
  2537. if (!no_pin1)
  2538. apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
  2539. "8254 timer not connected to IO-APIC\n");
  2540. apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
  2541. "(IRQ0) through the 8259A ...\n");
  2542. apic_printk(APIC_QUIET, KERN_INFO
  2543. "..... (found apic %d pin %d) ...\n", apic2, pin2);
  2544. /*
  2545. * legacy devices should be connected to IO APIC #0
  2546. */
  2547. replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
  2548. setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
  2549. legacy_pic->unmask(0);
  2550. if (timer_irq_works()) {
  2551. apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
  2552. timer_through_8259 = 1;
  2553. if (nmi_watchdog == NMI_IO_APIC) {
  2554. legacy_pic->mask(0);
  2555. setup_nmi();
  2556. legacy_pic->unmask(0);
  2557. }
  2558. goto out;
  2559. }
  2560. /*
  2561. * Cleanup, just in case ...
  2562. */
  2563. local_irq_disable();
  2564. legacy_pic->mask(0);
  2565. clear_IO_APIC_pin(apic2, pin2);
  2566. apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
  2567. }
  2568. if (nmi_watchdog == NMI_IO_APIC) {
  2569. apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
  2570. "through the IO-APIC - disabling NMI Watchdog!\n");
  2571. nmi_watchdog = NMI_NONE;
  2572. }
  2573. #ifdef CONFIG_X86_32
  2574. timer_ack = 0;
  2575. #endif
  2576. apic_printk(APIC_QUIET, KERN_INFO
  2577. "...trying to set up timer as Virtual Wire IRQ...\n");
  2578. lapic_register_intr(0, desc);
  2579. apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
  2580. legacy_pic->unmask(0);
  2581. if (timer_irq_works()) {
  2582. apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
  2583. goto out;
  2584. }
  2585. local_irq_disable();
  2586. legacy_pic->mask(0);
  2587. apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
  2588. apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
  2589. apic_printk(APIC_QUIET, KERN_INFO
  2590. "...trying to set up timer as ExtINT IRQ...\n");
  2591. legacy_pic->init(0);
  2592. legacy_pic->make_irq(0);
  2593. apic_write(APIC_LVT0, APIC_DM_EXTINT);
  2594. unlock_ExtINT_logic();
  2595. if (timer_irq_works()) {
  2596. apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
  2597. goto out;
  2598. }
  2599. local_irq_disable();
  2600. apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
  2601. panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
  2602. "report. Then try booting with the 'noapic' option.\n");
  2603. out:
  2604. local_irq_restore(flags);
  2605. }
  2606. /*
  2607. * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
  2608. * to devices. However there may be an I/O APIC pin available for
  2609. * this interrupt regardless. The pin may be left unconnected, but
  2610. * typically it will be reused as an ExtINT cascade interrupt for
  2611. * the master 8259A. In the MPS case such a pin will normally be
  2612. * reported as an ExtINT interrupt in the MP table. With ACPI
  2613. * there is no provision for ExtINT interrupts, and in the absence
  2614. * of an override it would be treated as an ordinary ISA I/O APIC
  2615. * interrupt, that is edge-triggered and unmasked by default. We
  2616. * used to do this, but it caused problems on some systems because
  2617. * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
  2618. * the same ExtINT cascade interrupt to drive the local APIC of the
  2619. * bootstrap processor. Therefore we refrain from routing IRQ2 to
  2620. * the I/O APIC in all cases now. No actual device should request
  2621. * it anyway. --macro
  2622. */
  2623. #define PIC_IRQS (1UL << PIC_CASCADE_IR)
  2624. void __init setup_IO_APIC(void)
  2625. {
  2626. /*
  2627. * calling enable_IO_APIC() is moved to setup_local_APIC for BP
  2628. */
  2629. io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
  2630. apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
  2631. /*
  2632. * Set up IO-APIC IRQ routing.
  2633. */
  2634. x86_init.mpparse.setup_ioapic_ids();
  2635. sync_Arb_IDs();
  2636. setup_IO_APIC_irqs();
  2637. init_IO_APIC_traps();
  2638. if (legacy_pic->nr_legacy_irqs)
  2639. check_timer();
  2640. }
  2641. /*
  2642. * Called after all the initialization is done. If we didnt find any
  2643. * APIC bugs then we can allow the modify fast path
  2644. */
  2645. static int __init io_apic_bug_finalize(void)
  2646. {
  2647. if (sis_apic_bug == -1)
  2648. sis_apic_bug = 0;
  2649. return 0;
  2650. }
  2651. late_initcall(io_apic_bug_finalize);
  2652. struct sysfs_ioapic_data {
  2653. struct sys_device dev;
  2654. struct IO_APIC_route_entry entry[0];
  2655. };
  2656. static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
  2657. static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
  2658. {
  2659. struct IO_APIC_route_entry *entry;
  2660. struct sysfs_ioapic_data *data;
  2661. int i;
  2662. data = container_of(dev, struct sysfs_ioapic_data, dev);
  2663. entry = data->entry;
  2664. for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
  2665. *entry = ioapic_read_entry(dev->id, i);
  2666. return 0;
  2667. }
  2668. static int ioapic_resume(struct sys_device *dev)
  2669. {
  2670. struct IO_APIC_route_entry *entry;
  2671. struct sysfs_ioapic_data *data;
  2672. unsigned long flags;
  2673. union IO_APIC_reg_00 reg_00;
  2674. int i;
  2675. data = container_of(dev, struct sysfs_ioapic_data, dev);
  2676. entry = data->entry;
  2677. raw_spin_lock_irqsave(&ioapic_lock, flags);
  2678. reg_00.raw = io_apic_read(dev->id, 0);
  2679. if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
  2680. reg_00.bits.ID = mp_ioapics[dev->id].apicid;
  2681. io_apic_write(dev->id, 0, reg_00.raw);
  2682. }
  2683. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  2684. for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
  2685. ioapic_write_entry(dev->id, i, entry[i]);
  2686. return 0;
  2687. }
  2688. static struct sysdev_class ioapic_sysdev_class = {
  2689. .name = "ioapic",
  2690. .suspend = ioapic_suspend,
  2691. .resume = ioapic_resume,
  2692. };
  2693. static int __init ioapic_init_sysfs(void)
  2694. {
  2695. struct sys_device * dev;
  2696. int i, size, error;
  2697. error = sysdev_class_register(&ioapic_sysdev_class);
  2698. if (error)
  2699. return error;
  2700. for (i = 0; i < nr_ioapics; i++ ) {
  2701. size = sizeof(struct sys_device) + nr_ioapic_registers[i]
  2702. * sizeof(struct IO_APIC_route_entry);
  2703. mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
  2704. if (!mp_ioapic_data[i]) {
  2705. printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
  2706. continue;
  2707. }
  2708. dev = &mp_ioapic_data[i]->dev;
  2709. dev->id = i;
  2710. dev->cls = &ioapic_sysdev_class;
  2711. error = sysdev_register(dev);
  2712. if (error) {
  2713. kfree(mp_ioapic_data[i]);
  2714. mp_ioapic_data[i] = NULL;
  2715. printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
  2716. continue;
  2717. }
  2718. }
  2719. return 0;
  2720. }
  2721. device_initcall(ioapic_init_sysfs);
  2722. /*
  2723. * Dynamic irq allocate and deallocation
  2724. */
  2725. unsigned int create_irq_nr(unsigned int irq_want, int node)
  2726. {
  2727. /* Allocate an unused irq */
  2728. unsigned int irq;
  2729. unsigned int new;
  2730. unsigned long flags;
  2731. struct irq_cfg *cfg_new = NULL;
  2732. struct irq_desc *desc_new = NULL;
  2733. irq = 0;
  2734. if (irq_want < nr_irqs_gsi)
  2735. irq_want = nr_irqs_gsi;
  2736. raw_spin_lock_irqsave(&vector_lock, flags);
  2737. for (new = irq_want; new < nr_irqs; new++) {
  2738. desc_new = irq_to_desc_alloc_node(new, node);
  2739. if (!desc_new) {
  2740. printk(KERN_INFO "can not get irq_desc for %d\n", new);
  2741. continue;
  2742. }
  2743. cfg_new = get_irq_desc_chip_data(desc_new);
  2744. if (cfg_new->vector != 0)
  2745. continue;
  2746. desc_new = move_irq_desc(desc_new, node);
  2747. cfg_new = get_irq_desc_chip_data(desc_new);
  2748. if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
  2749. irq = new;
  2750. break;
  2751. }
  2752. raw_spin_unlock_irqrestore(&vector_lock, flags);
  2753. if (irq > 0)
  2754. dynamic_irq_init_keep_chip_data(irq);
  2755. return irq;
  2756. }
  2757. int create_irq(void)
  2758. {
  2759. int node = cpu_to_node(0);
  2760. unsigned int irq_want;
  2761. int irq;
  2762. irq_want = nr_irqs_gsi;
  2763. irq = create_irq_nr(irq_want, node);
  2764. if (irq == 0)
  2765. irq = -1;
  2766. return irq;
  2767. }
  2768. void destroy_irq(unsigned int irq)
  2769. {
  2770. unsigned long flags;
  2771. dynamic_irq_cleanup_keep_chip_data(irq);
  2772. free_irte(irq);
  2773. raw_spin_lock_irqsave(&vector_lock, flags);
  2774. __clear_irq_vector(irq, get_irq_chip_data(irq));
  2775. raw_spin_unlock_irqrestore(&vector_lock, flags);
  2776. }
  2777. /*
  2778. * MSI message composition
  2779. */
  2780. #ifdef CONFIG_PCI_MSI
  2781. static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
  2782. struct msi_msg *msg, u8 hpet_id)
  2783. {
  2784. struct irq_cfg *cfg;
  2785. int err;
  2786. unsigned dest;
  2787. if (disable_apic)
  2788. return -ENXIO;
  2789. cfg = irq_cfg(irq);
  2790. err = assign_irq_vector(irq, cfg, apic->target_cpus());
  2791. if (err)
  2792. return err;
  2793. dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
  2794. if (irq_remapped(irq)) {
  2795. struct irte irte;
  2796. int ir_index;
  2797. u16 sub_handle;
  2798. ir_index = map_irq_to_irte_handle(irq, &sub_handle);
  2799. BUG_ON(ir_index == -1);
  2800. prepare_irte(&irte, cfg->vector, dest);
  2801. /* Set source-id of interrupt request */
  2802. if (pdev)
  2803. set_msi_sid(&irte, pdev);
  2804. else
  2805. set_hpet_sid(&irte, hpet_id);
  2806. modify_irte(irq, &irte);
  2807. msg->address_hi = MSI_ADDR_BASE_HI;
  2808. msg->data = sub_handle;
  2809. msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
  2810. MSI_ADDR_IR_SHV |
  2811. MSI_ADDR_IR_INDEX1(ir_index) |
  2812. MSI_ADDR_IR_INDEX2(ir_index);
  2813. } else {
  2814. if (x2apic_enabled())
  2815. msg->address_hi = MSI_ADDR_BASE_HI |
  2816. MSI_ADDR_EXT_DEST_ID(dest);
  2817. else
  2818. msg->address_hi = MSI_ADDR_BASE_HI;
  2819. msg->address_lo =
  2820. MSI_ADDR_BASE_LO |
  2821. ((apic->irq_dest_mode == 0) ?
  2822. MSI_ADDR_DEST_MODE_PHYSICAL:
  2823. MSI_ADDR_DEST_MODE_LOGICAL) |
  2824. ((apic->irq_delivery_mode != dest_LowestPrio) ?
  2825. MSI_ADDR_REDIRECTION_CPU:
  2826. MSI_ADDR_REDIRECTION_LOWPRI) |
  2827. MSI_ADDR_DEST_ID(dest);
  2828. msg->data =
  2829. MSI_DATA_TRIGGER_EDGE |
  2830. MSI_DATA_LEVEL_ASSERT |
  2831. ((apic->irq_delivery_mode != dest_LowestPrio) ?
  2832. MSI_DATA_DELIVERY_FIXED:
  2833. MSI_DATA_DELIVERY_LOWPRI) |
  2834. MSI_DATA_VECTOR(cfg->vector);
  2835. }
  2836. return err;
  2837. }
  2838. #ifdef CONFIG_SMP
  2839. static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
  2840. {
  2841. struct irq_desc *desc = irq_to_desc(irq);
  2842. struct irq_cfg *cfg;
  2843. struct msi_msg msg;
  2844. unsigned int dest;
  2845. if (set_desc_affinity(desc, mask, &dest))
  2846. return -1;
  2847. cfg = get_irq_desc_chip_data(desc);
  2848. __get_cached_msi_msg(desc->irq_data.msi_desc, &msg);
  2849. msg.data &= ~MSI_DATA_VECTOR_MASK;
  2850. msg.data |= MSI_DATA_VECTOR(cfg->vector);
  2851. msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
  2852. msg.address_lo |= MSI_ADDR_DEST_ID(dest);
  2853. __write_msi_msg(desc->irq_data.msi_desc, &msg);
  2854. return 0;
  2855. }
  2856. #ifdef CONFIG_INTR_REMAP
  2857. /*
  2858. * Migrate the MSI irq to another cpumask. This migration is
  2859. * done in the process context using interrupt-remapping hardware.
  2860. */
  2861. static int
  2862. ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
  2863. {
  2864. struct irq_desc *desc = irq_to_desc(irq);
  2865. struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
  2866. unsigned int dest;
  2867. struct irte irte;
  2868. if (get_irte(irq, &irte))
  2869. return -1;
  2870. if (set_desc_affinity(desc, mask, &dest))
  2871. return -1;
  2872. irte.vector = cfg->vector;
  2873. irte.dest_id = IRTE_DEST(dest);
  2874. /*
  2875. * atomically update the IRTE with the new destination and vector.
  2876. */
  2877. modify_irte(irq, &irte);
  2878. /*
  2879. * After this point, all the interrupts will start arriving
  2880. * at the new destination. So, time to cleanup the previous
  2881. * vector allocation.
  2882. */
  2883. if (cfg->move_in_progress)
  2884. send_cleanup_vector(cfg);
  2885. return 0;
  2886. }
  2887. #endif
  2888. #endif /* CONFIG_SMP */
  2889. /*
  2890. * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
  2891. * which implement the MSI or MSI-X Capability Structure.
  2892. */
  2893. static struct irq_chip msi_chip = {
  2894. .name = "PCI-MSI",
  2895. .irq_unmask = unmask_msi_irq,
  2896. .irq_mask = mask_msi_irq,
  2897. .ack = ack_apic_edge,
  2898. #ifdef CONFIG_SMP
  2899. .set_affinity = set_msi_irq_affinity,
  2900. #endif
  2901. .retrigger = ioapic_retrigger_irq,
  2902. };
  2903. static struct irq_chip msi_ir_chip = {
  2904. .name = "IR-PCI-MSI",
  2905. .irq_unmask = unmask_msi_irq,
  2906. .irq_mask = mask_msi_irq,
  2907. #ifdef CONFIG_INTR_REMAP
  2908. .ack = ir_ack_apic_edge,
  2909. #ifdef CONFIG_SMP
  2910. .set_affinity = ir_set_msi_irq_affinity,
  2911. #endif
  2912. #endif
  2913. .retrigger = ioapic_retrigger_irq,
  2914. };
  2915. /*
  2916. * Map the PCI dev to the corresponding remapping hardware unit
  2917. * and allocate 'nvec' consecutive interrupt-remapping table entries
  2918. * in it.
  2919. */
  2920. static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
  2921. {
  2922. struct intel_iommu *iommu;
  2923. int index;
  2924. iommu = map_dev_to_ir(dev);
  2925. if (!iommu) {
  2926. printk(KERN_ERR
  2927. "Unable to map PCI %s to iommu\n", pci_name(dev));
  2928. return -ENOENT;
  2929. }
  2930. index = alloc_irte(iommu, irq, nvec);
  2931. if (index < 0) {
  2932. printk(KERN_ERR
  2933. "Unable to allocate %d IRTE for PCI %s\n", nvec,
  2934. pci_name(dev));
  2935. return -ENOSPC;
  2936. }
  2937. return index;
  2938. }
  2939. static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
  2940. {
  2941. int ret;
  2942. struct msi_msg msg;
  2943. ret = msi_compose_msg(dev, irq, &msg, -1);
  2944. if (ret < 0)
  2945. return ret;
  2946. set_irq_msi(irq, msidesc);
  2947. write_msi_msg(irq, &msg);
  2948. if (irq_remapped(irq)) {
  2949. struct irq_desc *desc = irq_to_desc(irq);
  2950. /*
  2951. * irq migration in process context
  2952. */
  2953. desc->status |= IRQ_MOVE_PCNTXT;
  2954. set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
  2955. } else
  2956. set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
  2957. dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
  2958. return 0;
  2959. }
  2960. int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  2961. {
  2962. unsigned int irq;
  2963. int ret, sub_handle;
  2964. struct msi_desc *msidesc;
  2965. unsigned int irq_want;
  2966. struct intel_iommu *iommu = NULL;
  2967. int index = 0;
  2968. int node;
  2969. /* x86 doesn't support multiple MSI yet */
  2970. if (type == PCI_CAP_ID_MSI && nvec > 1)
  2971. return 1;
  2972. node = dev_to_node(&dev->dev);
  2973. irq_want = nr_irqs_gsi;
  2974. sub_handle = 0;
  2975. list_for_each_entry(msidesc, &dev->msi_list, list) {
  2976. irq = create_irq_nr(irq_want, node);
  2977. if (irq == 0)
  2978. return -1;
  2979. irq_want = irq + 1;
  2980. if (!intr_remapping_enabled)
  2981. goto no_ir;
  2982. if (!sub_handle) {
  2983. /*
  2984. * allocate the consecutive block of IRTE's
  2985. * for 'nvec'
  2986. */
  2987. index = msi_alloc_irte(dev, irq, nvec);
  2988. if (index < 0) {
  2989. ret = index;
  2990. goto error;
  2991. }
  2992. } else {
  2993. iommu = map_dev_to_ir(dev);
  2994. if (!iommu) {
  2995. ret = -ENOENT;
  2996. goto error;
  2997. }
  2998. /*
  2999. * setup the mapping between the irq and the IRTE
  3000. * base index, the sub_handle pointing to the
  3001. * appropriate interrupt remap table entry.
  3002. */
  3003. set_irte_irq(irq, iommu, index, sub_handle);
  3004. }
  3005. no_ir:
  3006. ret = setup_msi_irq(dev, msidesc, irq);
  3007. if (ret < 0)
  3008. goto error;
  3009. sub_handle++;
  3010. }
  3011. return 0;
  3012. error:
  3013. destroy_irq(irq);
  3014. return ret;
  3015. }
  3016. void arch_teardown_msi_irq(unsigned int irq)
  3017. {
  3018. destroy_irq(irq);
  3019. }
  3020. #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
  3021. #ifdef CONFIG_SMP
  3022. static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
  3023. {
  3024. struct irq_desc *desc = irq_to_desc(irq);
  3025. struct irq_cfg *cfg;
  3026. struct msi_msg msg;
  3027. unsigned int dest;
  3028. if (set_desc_affinity(desc, mask, &dest))
  3029. return -1;
  3030. cfg = get_irq_desc_chip_data(desc);
  3031. dmar_msi_read(irq, &msg);
  3032. msg.data &= ~MSI_DATA_VECTOR_MASK;
  3033. msg.data |= MSI_DATA_VECTOR(cfg->vector);
  3034. msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
  3035. msg.address_lo |= MSI_ADDR_DEST_ID(dest);
  3036. dmar_msi_write(irq, &msg);
  3037. return 0;
  3038. }
  3039. #endif /* CONFIG_SMP */
  3040. static struct irq_chip dmar_msi_type = {
  3041. .name = "DMAR_MSI",
  3042. .unmask = dmar_msi_unmask,
  3043. .mask = dmar_msi_mask,
  3044. .ack = ack_apic_edge,
  3045. #ifdef CONFIG_SMP
  3046. .set_affinity = dmar_msi_set_affinity,
  3047. #endif
  3048. .retrigger = ioapic_retrigger_irq,
  3049. };
  3050. int arch_setup_dmar_msi(unsigned int irq)
  3051. {
  3052. int ret;
  3053. struct msi_msg msg;
  3054. ret = msi_compose_msg(NULL, irq, &msg, -1);
  3055. if (ret < 0)
  3056. return ret;
  3057. dmar_msi_write(irq, &msg);
  3058. set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
  3059. "edge");
  3060. return 0;
  3061. }
  3062. #endif
  3063. #ifdef CONFIG_HPET_TIMER
  3064. #ifdef CONFIG_SMP
  3065. static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
  3066. {
  3067. struct irq_desc *desc = irq_to_desc(irq);
  3068. struct irq_cfg *cfg;
  3069. struct msi_msg msg;
  3070. unsigned int dest;
  3071. if (set_desc_affinity(desc, mask, &dest))
  3072. return -1;
  3073. cfg = get_irq_desc_chip_data(desc);
  3074. hpet_msi_read(irq, &msg);
  3075. msg.data &= ~MSI_DATA_VECTOR_MASK;
  3076. msg.data |= MSI_DATA_VECTOR(cfg->vector);
  3077. msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
  3078. msg.address_lo |= MSI_ADDR_DEST_ID(dest);
  3079. hpet_msi_write(irq, &msg);
  3080. return 0;
  3081. }
  3082. #endif /* CONFIG_SMP */
  3083. static struct irq_chip ir_hpet_msi_type = {
  3084. .name = "IR-HPET_MSI",
  3085. .unmask = hpet_msi_unmask,
  3086. .mask = hpet_msi_mask,
  3087. #ifdef CONFIG_INTR_REMAP
  3088. .ack = ir_ack_apic_edge,
  3089. #ifdef CONFIG_SMP
  3090. .set_affinity = ir_set_msi_irq_affinity,
  3091. #endif
  3092. #endif
  3093. .retrigger = ioapic_retrigger_irq,
  3094. };
  3095. static struct irq_chip hpet_msi_type = {
  3096. .name = "HPET_MSI",
  3097. .unmask = hpet_msi_unmask,
  3098. .mask = hpet_msi_mask,
  3099. .ack = ack_apic_edge,
  3100. #ifdef CONFIG_SMP
  3101. .set_affinity = hpet_msi_set_affinity,
  3102. #endif
  3103. .retrigger = ioapic_retrigger_irq,
  3104. };
  3105. int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
  3106. {
  3107. int ret;
  3108. struct msi_msg msg;
  3109. struct irq_desc *desc = irq_to_desc(irq);
  3110. if (intr_remapping_enabled) {
  3111. struct intel_iommu *iommu = map_hpet_to_ir(id);
  3112. int index;
  3113. if (!iommu)
  3114. return -1;
  3115. index = alloc_irte(iommu, irq, 1);
  3116. if (index < 0)
  3117. return -1;
  3118. }
  3119. ret = msi_compose_msg(NULL, irq, &msg, id);
  3120. if (ret < 0)
  3121. return ret;
  3122. hpet_msi_write(irq, &msg);
  3123. desc->status |= IRQ_MOVE_PCNTXT;
  3124. if (irq_remapped(irq))
  3125. set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
  3126. handle_edge_irq, "edge");
  3127. else
  3128. set_irq_chip_and_handler_name(irq, &hpet_msi_type,
  3129. handle_edge_irq, "edge");
  3130. return 0;
  3131. }
  3132. #endif
  3133. #endif /* CONFIG_PCI_MSI */
  3134. /*
  3135. * Hypertransport interrupt support
  3136. */
  3137. #ifdef CONFIG_HT_IRQ
  3138. #ifdef CONFIG_SMP
  3139. static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
  3140. {
  3141. struct ht_irq_msg msg;
  3142. fetch_ht_irq_msg(irq, &msg);
  3143. msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
  3144. msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
  3145. msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
  3146. msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
  3147. write_ht_irq_msg(irq, &msg);
  3148. }
  3149. static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
  3150. {
  3151. struct irq_desc *desc = irq_to_desc(irq);
  3152. struct irq_cfg *cfg;
  3153. unsigned int dest;
  3154. if (set_desc_affinity(desc, mask, &dest))
  3155. return -1;
  3156. cfg = get_irq_desc_chip_data(desc);
  3157. target_ht_irq(irq, dest, cfg->vector);
  3158. return 0;
  3159. }
  3160. #endif
  3161. static struct irq_chip ht_irq_chip = {
  3162. .name = "PCI-HT",
  3163. .mask = mask_ht_irq,
  3164. .unmask = unmask_ht_irq,
  3165. .ack = ack_apic_edge,
  3166. #ifdef CONFIG_SMP
  3167. .set_affinity = set_ht_irq_affinity,
  3168. #endif
  3169. .retrigger = ioapic_retrigger_irq,
  3170. };
  3171. int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
  3172. {
  3173. struct irq_cfg *cfg;
  3174. int err;
  3175. if (disable_apic)
  3176. return -ENXIO;
  3177. cfg = irq_cfg(irq);
  3178. err = assign_irq_vector(irq, cfg, apic->target_cpus());
  3179. if (!err) {
  3180. struct ht_irq_msg msg;
  3181. unsigned dest;
  3182. dest = apic->cpu_mask_to_apicid_and(cfg->domain,
  3183. apic->target_cpus());
  3184. msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
  3185. msg.address_lo =
  3186. HT_IRQ_LOW_BASE |
  3187. HT_IRQ_LOW_DEST_ID(dest) |
  3188. HT_IRQ_LOW_VECTOR(cfg->vector) |
  3189. ((apic->irq_dest_mode == 0) ?
  3190. HT_IRQ_LOW_DM_PHYSICAL :
  3191. HT_IRQ_LOW_DM_LOGICAL) |
  3192. HT_IRQ_LOW_RQEOI_EDGE |
  3193. ((apic->irq_delivery_mode != dest_LowestPrio) ?
  3194. HT_IRQ_LOW_MT_FIXED :
  3195. HT_IRQ_LOW_MT_ARBITRATED) |
  3196. HT_IRQ_LOW_IRQ_MASKED;
  3197. write_ht_irq_msg(irq, &msg);
  3198. set_irq_chip_and_handler_name(irq, &ht_irq_chip,
  3199. handle_edge_irq, "edge");
  3200. dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
  3201. }
  3202. return err;
  3203. }
  3204. #endif /* CONFIG_HT_IRQ */
  3205. int __init io_apic_get_redir_entries (int ioapic)
  3206. {
  3207. union IO_APIC_reg_01 reg_01;
  3208. unsigned long flags;
  3209. raw_spin_lock_irqsave(&ioapic_lock, flags);
  3210. reg_01.raw = io_apic_read(ioapic, 1);
  3211. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  3212. /* The register returns the maximum index redir index
  3213. * supported, which is one less than the total number of redir
  3214. * entries.
  3215. */
  3216. return reg_01.bits.entries + 1;
  3217. }
  3218. void __init probe_nr_irqs_gsi(void)
  3219. {
  3220. int nr;
  3221. nr = gsi_top + NR_IRQS_LEGACY;
  3222. if (nr > nr_irqs_gsi)
  3223. nr_irqs_gsi = nr;
  3224. printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
  3225. }
  3226. #ifdef CONFIG_SPARSE_IRQ
  3227. int __init arch_probe_nr_irqs(void)
  3228. {
  3229. int nr;
  3230. if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
  3231. nr_irqs = NR_VECTORS * nr_cpu_ids;
  3232. nr = nr_irqs_gsi + 8 * nr_cpu_ids;
  3233. #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
  3234. /*
  3235. * for MSI and HT dyn irq
  3236. */
  3237. nr += nr_irqs_gsi * 16;
  3238. #endif
  3239. if (nr < nr_irqs)
  3240. nr_irqs = nr;
  3241. return NR_IRQS_LEGACY;
  3242. }
  3243. #endif
  3244. static int __io_apic_set_pci_routing(struct device *dev, int irq,
  3245. struct io_apic_irq_attr *irq_attr)
  3246. {
  3247. struct irq_desc *desc;
  3248. struct irq_cfg *cfg;
  3249. int node;
  3250. int ioapic, pin;
  3251. int trigger, polarity;
  3252. ioapic = irq_attr->ioapic;
  3253. if (!IO_APIC_IRQ(irq)) {
  3254. apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
  3255. ioapic);
  3256. return -EINVAL;
  3257. }
  3258. if (dev)
  3259. node = dev_to_node(dev);
  3260. else
  3261. node = cpu_to_node(0);
  3262. desc = irq_to_desc_alloc_node(irq, node);
  3263. if (!desc) {
  3264. printk(KERN_INFO "can not get irq_desc %d\n", irq);
  3265. return 0;
  3266. }
  3267. pin = irq_attr->ioapic_pin;
  3268. trigger = irq_attr->trigger;
  3269. polarity = irq_attr->polarity;
  3270. /*
  3271. * IRQs < 16 are already in the irq_2_pin[] map
  3272. */
  3273. if (irq >= legacy_pic->nr_legacy_irqs) {
  3274. cfg = get_irq_desc_chip_data(desc);
  3275. if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
  3276. printk(KERN_INFO "can not add pin %d for irq %d\n",
  3277. pin, irq);
  3278. return 0;
  3279. }
  3280. }
  3281. setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
  3282. return 0;
  3283. }
  3284. int io_apic_set_pci_routing(struct device *dev, int irq,
  3285. struct io_apic_irq_attr *irq_attr)
  3286. {
  3287. int ioapic, pin;
  3288. /*
  3289. * Avoid pin reprogramming. PRTs typically include entries
  3290. * with redundant pin->gsi mappings (but unique PCI devices);
  3291. * we only program the IOAPIC on the first.
  3292. */
  3293. ioapic = irq_attr->ioapic;
  3294. pin = irq_attr->ioapic_pin;
  3295. if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
  3296. pr_debug("Pin %d-%d already programmed\n",
  3297. mp_ioapics[ioapic].apicid, pin);
  3298. return 0;
  3299. }
  3300. set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
  3301. return __io_apic_set_pci_routing(dev, irq, irq_attr);
  3302. }
  3303. u8 __init io_apic_unique_id(u8 id)
  3304. {
  3305. #ifdef CONFIG_X86_32
  3306. if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
  3307. !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
  3308. return io_apic_get_unique_id(nr_ioapics, id);
  3309. else
  3310. return id;
  3311. #else
  3312. int i;
  3313. DECLARE_BITMAP(used, 256);
  3314. bitmap_zero(used, 256);
  3315. for (i = 0; i < nr_ioapics; i++) {
  3316. struct mpc_ioapic *ia = &mp_ioapics[i];
  3317. __set_bit(ia->apicid, used);
  3318. }
  3319. if (!test_bit(id, used))
  3320. return id;
  3321. return find_first_zero_bit(used, 256);
  3322. #endif
  3323. }
  3324. #ifdef CONFIG_X86_32
  3325. int __init io_apic_get_unique_id(int ioapic, int apic_id)
  3326. {
  3327. union IO_APIC_reg_00 reg_00;
  3328. static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
  3329. physid_mask_t tmp;
  3330. unsigned long flags;
  3331. int i = 0;
  3332. /*
  3333. * The P4 platform supports up to 256 APIC IDs on two separate APIC
  3334. * buses (one for LAPICs, one for IOAPICs), where predecessors only
  3335. * supports up to 16 on one shared APIC bus.
  3336. *
  3337. * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
  3338. * advantage of new APIC bus architecture.
  3339. */
  3340. if (physids_empty(apic_id_map))
  3341. apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
  3342. raw_spin_lock_irqsave(&ioapic_lock, flags);
  3343. reg_00.raw = io_apic_read(ioapic, 0);
  3344. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  3345. if (apic_id >= get_physical_broadcast()) {
  3346. printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
  3347. "%d\n", ioapic, apic_id, reg_00.bits.ID);
  3348. apic_id = reg_00.bits.ID;
  3349. }
  3350. /*
  3351. * Every APIC in a system must have a unique ID or we get lots of nice
  3352. * 'stuck on smp_invalidate_needed IPI wait' messages.
  3353. */
  3354. if (apic->check_apicid_used(&apic_id_map, apic_id)) {
  3355. for (i = 0; i < get_physical_broadcast(); i++) {
  3356. if (!apic->check_apicid_used(&apic_id_map, i))
  3357. break;
  3358. }
  3359. if (i == get_physical_broadcast())
  3360. panic("Max apic_id exceeded!\n");
  3361. printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
  3362. "trying %d\n", ioapic, apic_id, i);
  3363. apic_id = i;
  3364. }
  3365. apic->apicid_to_cpu_present(apic_id, &tmp);
  3366. physids_or(apic_id_map, apic_id_map, tmp);
  3367. if (reg_00.bits.ID != apic_id) {
  3368. reg_00.bits.ID = apic_id;
  3369. raw_spin_lock_irqsave(&ioapic_lock, flags);
  3370. io_apic_write(ioapic, 0, reg_00.raw);
  3371. reg_00.raw = io_apic_read(ioapic, 0);
  3372. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  3373. /* Sanity check */
  3374. if (reg_00.bits.ID != apic_id) {
  3375. printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
  3376. return -1;
  3377. }
  3378. }
  3379. apic_printk(APIC_VERBOSE, KERN_INFO
  3380. "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
  3381. return apic_id;
  3382. }
  3383. #endif
  3384. int __init io_apic_get_version(int ioapic)
  3385. {
  3386. union IO_APIC_reg_01 reg_01;
  3387. unsigned long flags;
  3388. raw_spin_lock_irqsave(&ioapic_lock, flags);
  3389. reg_01.raw = io_apic_read(ioapic, 1);
  3390. raw_spin_unlock_irqrestore(&ioapic_lock, flags);
  3391. return reg_01.bits.version;
  3392. }
  3393. int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
  3394. {
  3395. int ioapic, pin, idx;
  3396. if (skip_ioapic_setup)
  3397. return -1;
  3398. ioapic = mp_find_ioapic(gsi);
  3399. if (ioapic < 0)
  3400. return -1;
  3401. pin = mp_find_ioapic_pin(ioapic, gsi);
  3402. if (pin < 0)
  3403. return -1;
  3404. idx = find_irq_entry(ioapic, pin, mp_INT);
  3405. if (idx < 0)
  3406. return -1;
  3407. *trigger = irq_trigger(idx);
  3408. *polarity = irq_polarity(idx);
  3409. return 0;
  3410. }
  3411. /*
  3412. * This function currently is only a helper for the i386 smp boot process where
  3413. * we need to reprogram the ioredtbls to cater for the cpus which have come online
  3414. * so mask in all cases should simply be apic->target_cpus()
  3415. */
  3416. #ifdef CONFIG_SMP
  3417. void __init setup_ioapic_dest(void)
  3418. {
  3419. int pin, ioapic, irq, irq_entry;
  3420. struct irq_desc *desc;
  3421. const struct cpumask *mask;
  3422. if (skip_ioapic_setup == 1)
  3423. return;
  3424. for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
  3425. for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
  3426. irq_entry = find_irq_entry(ioapic, pin, mp_INT);
  3427. if (irq_entry == -1)
  3428. continue;
  3429. irq = pin_2_irq(irq_entry, ioapic, pin);
  3430. if ((ioapic > 0) && (irq > 16))
  3431. continue;
  3432. desc = irq_to_desc(irq);
  3433. /*
  3434. * Honour affinities which have been set in early boot
  3435. */
  3436. if (desc->status &
  3437. (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
  3438. mask = desc->affinity;
  3439. else
  3440. mask = apic->target_cpus();
  3441. if (intr_remapping_enabled)
  3442. set_ir_ioapic_affinity_irq_desc(desc, mask);
  3443. else
  3444. set_ioapic_affinity_irq_desc(desc, mask);
  3445. }
  3446. }
  3447. #endif
  3448. #define IOAPIC_RESOURCE_NAME_SIZE 11
  3449. static struct resource *ioapic_resources;
  3450. static struct resource * __init ioapic_setup_resources(int nr_ioapics)
  3451. {
  3452. unsigned long n;
  3453. struct resource *res;
  3454. char *mem;
  3455. int i;
  3456. if (nr_ioapics <= 0)
  3457. return NULL;
  3458. n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
  3459. n *= nr_ioapics;
  3460. mem = alloc_bootmem(n);
  3461. res = (void *)mem;
  3462. mem += sizeof(struct resource) * nr_ioapics;
  3463. for (i = 0; i < nr_ioapics; i++) {
  3464. res[i].name = mem;
  3465. res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  3466. snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
  3467. mem += IOAPIC_RESOURCE_NAME_SIZE;
  3468. }
  3469. ioapic_resources = res;
  3470. return res;
  3471. }
  3472. void __init ioapic_init_mappings(void)
  3473. {
  3474. unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
  3475. struct resource *ioapic_res;
  3476. int i;
  3477. ioapic_res = ioapic_setup_resources(nr_ioapics);
  3478. for (i = 0; i < nr_ioapics; i++) {
  3479. if (smp_found_config) {
  3480. ioapic_phys = mp_ioapics[i].apicaddr;
  3481. #ifdef CONFIG_X86_32
  3482. if (!ioapic_phys) {
  3483. printk(KERN_ERR
  3484. "WARNING: bogus zero IO-APIC "
  3485. "address found in MPTABLE, "
  3486. "disabling IO/APIC support!\n");
  3487. smp_found_config = 0;
  3488. skip_ioapic_setup = 1;
  3489. goto fake_ioapic_page;
  3490. }
  3491. #endif
  3492. } else {
  3493. #ifdef CONFIG_X86_32
  3494. fake_ioapic_page:
  3495. #endif
  3496. ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
  3497. ioapic_phys = __pa(ioapic_phys);
  3498. }
  3499. set_fixmap_nocache(idx, ioapic_phys);
  3500. apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
  3501. __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
  3502. ioapic_phys);
  3503. idx++;
  3504. ioapic_res->start = ioapic_phys;
  3505. ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
  3506. ioapic_res++;
  3507. }
  3508. }
  3509. void __init ioapic_insert_resources(void)
  3510. {
  3511. int i;
  3512. struct resource *r = ioapic_resources;
  3513. if (!r) {
  3514. if (nr_ioapics > 0)
  3515. printk(KERN_ERR
  3516. "IO APIC resources couldn't be allocated.\n");
  3517. return;
  3518. }
  3519. for (i = 0; i < nr_ioapics; i++) {
  3520. insert_resource(&iomem_resource, r);
  3521. r++;
  3522. }
  3523. }
  3524. int mp_find_ioapic(u32 gsi)
  3525. {
  3526. int i = 0;
  3527. /* Find the IOAPIC that manages this GSI. */
  3528. for (i = 0; i < nr_ioapics; i++) {
  3529. if ((gsi >= mp_gsi_routing[i].gsi_base)
  3530. && (gsi <= mp_gsi_routing[i].gsi_end))
  3531. return i;
  3532. }
  3533. printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
  3534. return -1;
  3535. }
  3536. int mp_find_ioapic_pin(int ioapic, u32 gsi)
  3537. {
  3538. if (WARN_ON(ioapic == -1))
  3539. return -1;
  3540. if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
  3541. return -1;
  3542. return gsi - mp_gsi_routing[ioapic].gsi_base;
  3543. }
  3544. static int bad_ioapic(unsigned long address)
  3545. {
  3546. if (nr_ioapics >= MAX_IO_APICS) {
  3547. printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
  3548. "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
  3549. return 1;
  3550. }
  3551. if (!address) {
  3552. printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
  3553. " found in table, skipping!\n");
  3554. return 1;
  3555. }
  3556. return 0;
  3557. }
  3558. void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
  3559. {
  3560. int idx = 0;
  3561. int entries;
  3562. if (bad_ioapic(address))
  3563. return;
  3564. idx = nr_ioapics;
  3565. mp_ioapics[idx].type = MP_IOAPIC;
  3566. mp_ioapics[idx].flags = MPC_APIC_USABLE;
  3567. mp_ioapics[idx].apicaddr = address;
  3568. set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
  3569. mp_ioapics[idx].apicid = io_apic_unique_id(id);
  3570. mp_ioapics[idx].apicver = io_apic_get_version(idx);
  3571. /*
  3572. * Build basic GSI lookup table to facilitate gsi->io_apic lookups
  3573. * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
  3574. */
  3575. entries = io_apic_get_redir_entries(idx);
  3576. mp_gsi_routing[idx].gsi_base = gsi_base;
  3577. mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
  3578. /*
  3579. * The number of IO-APIC IRQ registers (== #pins):
  3580. */
  3581. nr_ioapic_registers[idx] = entries;
  3582. if (mp_gsi_routing[idx].gsi_end >= gsi_top)
  3583. gsi_top = mp_gsi_routing[idx].gsi_end + 1;
  3584. printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
  3585. "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
  3586. mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
  3587. mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
  3588. nr_ioapics++;
  3589. }
  3590. /* Enable IOAPIC early just for system timer */
  3591. void __init pre_init_apic_IRQ0(void)
  3592. {
  3593. struct irq_cfg *cfg;
  3594. struct irq_desc *desc;
  3595. printk(KERN_INFO "Early APIC setup for system timer0\n");
  3596. #ifndef CONFIG_SMP
  3597. phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
  3598. #endif
  3599. desc = irq_to_desc_alloc_node(0, 0);
  3600. setup_local_APIC();
  3601. cfg = irq_cfg(0);
  3602. add_pin_to_irq_node(cfg, 0, 0, 0);
  3603. set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
  3604. setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);
  3605. }