intel_display.c 305 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include <drm/drm_dp_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <linux/dma_remapping.h>
  42. static void intel_increase_pllclock(struct drm_crtc *crtc);
  43. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  44. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  45. struct intel_crtc_config *pipe_config);
  46. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  47. struct intel_crtc_config *pipe_config);
  48. static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  49. int x, int y, struct drm_framebuffer *old_fb);
  50. typedef struct {
  51. int min, max;
  52. } intel_range_t;
  53. typedef struct {
  54. int dot_limit;
  55. int p2_slow, p2_fast;
  56. } intel_p2_t;
  57. typedef struct intel_limit intel_limit_t;
  58. struct intel_limit {
  59. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  60. intel_p2_t p2;
  61. };
  62. int
  63. intel_pch_rawclk(struct drm_device *dev)
  64. {
  65. struct drm_i915_private *dev_priv = dev->dev_private;
  66. WARN_ON(!HAS_PCH_SPLIT(dev));
  67. return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  68. }
  69. static inline u32 /* units of 100MHz */
  70. intel_fdi_link_freq(struct drm_device *dev)
  71. {
  72. if (IS_GEN5(dev)) {
  73. struct drm_i915_private *dev_priv = dev->dev_private;
  74. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  75. } else
  76. return 27;
  77. }
  78. static const intel_limit_t intel_limits_i8xx_dac = {
  79. .dot = { .min = 25000, .max = 350000 },
  80. .vco = { .min = 930000, .max = 1400000 },
  81. .n = { .min = 3, .max = 16 },
  82. .m = { .min = 96, .max = 140 },
  83. .m1 = { .min = 18, .max = 26 },
  84. .m2 = { .min = 6, .max = 16 },
  85. .p = { .min = 4, .max = 128 },
  86. .p1 = { .min = 2, .max = 33 },
  87. .p2 = { .dot_limit = 165000,
  88. .p2_slow = 4, .p2_fast = 2 },
  89. };
  90. static const intel_limit_t intel_limits_i8xx_dvo = {
  91. .dot = { .min = 25000, .max = 350000 },
  92. .vco = { .min = 930000, .max = 1400000 },
  93. .n = { .min = 3, .max = 16 },
  94. .m = { .min = 96, .max = 140 },
  95. .m1 = { .min = 18, .max = 26 },
  96. .m2 = { .min = 6, .max = 16 },
  97. .p = { .min = 4, .max = 128 },
  98. .p1 = { .min = 2, .max = 33 },
  99. .p2 = { .dot_limit = 165000,
  100. .p2_slow = 4, .p2_fast = 4 },
  101. };
  102. static const intel_limit_t intel_limits_i8xx_lvds = {
  103. .dot = { .min = 25000, .max = 350000 },
  104. .vco = { .min = 930000, .max = 1400000 },
  105. .n = { .min = 3, .max = 16 },
  106. .m = { .min = 96, .max = 140 },
  107. .m1 = { .min = 18, .max = 26 },
  108. .m2 = { .min = 6, .max = 16 },
  109. .p = { .min = 4, .max = 128 },
  110. .p1 = { .min = 1, .max = 6 },
  111. .p2 = { .dot_limit = 165000,
  112. .p2_slow = 14, .p2_fast = 7 },
  113. };
  114. static const intel_limit_t intel_limits_i9xx_sdvo = {
  115. .dot = { .min = 20000, .max = 400000 },
  116. .vco = { .min = 1400000, .max = 2800000 },
  117. .n = { .min = 1, .max = 6 },
  118. .m = { .min = 70, .max = 120 },
  119. .m1 = { .min = 8, .max = 18 },
  120. .m2 = { .min = 3, .max = 7 },
  121. .p = { .min = 5, .max = 80 },
  122. .p1 = { .min = 1, .max = 8 },
  123. .p2 = { .dot_limit = 200000,
  124. .p2_slow = 10, .p2_fast = 5 },
  125. };
  126. static const intel_limit_t intel_limits_i9xx_lvds = {
  127. .dot = { .min = 20000, .max = 400000 },
  128. .vco = { .min = 1400000, .max = 2800000 },
  129. .n = { .min = 1, .max = 6 },
  130. .m = { .min = 70, .max = 120 },
  131. .m1 = { .min = 8, .max = 18 },
  132. .m2 = { .min = 3, .max = 7 },
  133. .p = { .min = 7, .max = 98 },
  134. .p1 = { .min = 1, .max = 8 },
  135. .p2 = { .dot_limit = 112000,
  136. .p2_slow = 14, .p2_fast = 7 },
  137. };
  138. static const intel_limit_t intel_limits_g4x_sdvo = {
  139. .dot = { .min = 25000, .max = 270000 },
  140. .vco = { .min = 1750000, .max = 3500000},
  141. .n = { .min = 1, .max = 4 },
  142. .m = { .min = 104, .max = 138 },
  143. .m1 = { .min = 17, .max = 23 },
  144. .m2 = { .min = 5, .max = 11 },
  145. .p = { .min = 10, .max = 30 },
  146. .p1 = { .min = 1, .max = 3},
  147. .p2 = { .dot_limit = 270000,
  148. .p2_slow = 10,
  149. .p2_fast = 10
  150. },
  151. };
  152. static const intel_limit_t intel_limits_g4x_hdmi = {
  153. .dot = { .min = 22000, .max = 400000 },
  154. .vco = { .min = 1750000, .max = 3500000},
  155. .n = { .min = 1, .max = 4 },
  156. .m = { .min = 104, .max = 138 },
  157. .m1 = { .min = 16, .max = 23 },
  158. .m2 = { .min = 5, .max = 11 },
  159. .p = { .min = 5, .max = 80 },
  160. .p1 = { .min = 1, .max = 8},
  161. .p2 = { .dot_limit = 165000,
  162. .p2_slow = 10, .p2_fast = 5 },
  163. };
  164. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  165. .dot = { .min = 20000, .max = 115000 },
  166. .vco = { .min = 1750000, .max = 3500000 },
  167. .n = { .min = 1, .max = 3 },
  168. .m = { .min = 104, .max = 138 },
  169. .m1 = { .min = 17, .max = 23 },
  170. .m2 = { .min = 5, .max = 11 },
  171. .p = { .min = 28, .max = 112 },
  172. .p1 = { .min = 2, .max = 8 },
  173. .p2 = { .dot_limit = 0,
  174. .p2_slow = 14, .p2_fast = 14
  175. },
  176. };
  177. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  178. .dot = { .min = 80000, .max = 224000 },
  179. .vco = { .min = 1750000, .max = 3500000 },
  180. .n = { .min = 1, .max = 3 },
  181. .m = { .min = 104, .max = 138 },
  182. .m1 = { .min = 17, .max = 23 },
  183. .m2 = { .min = 5, .max = 11 },
  184. .p = { .min = 14, .max = 42 },
  185. .p1 = { .min = 2, .max = 6 },
  186. .p2 = { .dot_limit = 0,
  187. .p2_slow = 7, .p2_fast = 7
  188. },
  189. };
  190. static const intel_limit_t intel_limits_pineview_sdvo = {
  191. .dot = { .min = 20000, .max = 400000},
  192. .vco = { .min = 1700000, .max = 3500000 },
  193. /* Pineview's Ncounter is a ring counter */
  194. .n = { .min = 3, .max = 6 },
  195. .m = { .min = 2, .max = 256 },
  196. /* Pineview only has one combined m divider, which we treat as m2. */
  197. .m1 = { .min = 0, .max = 0 },
  198. .m2 = { .min = 0, .max = 254 },
  199. .p = { .min = 5, .max = 80 },
  200. .p1 = { .min = 1, .max = 8 },
  201. .p2 = { .dot_limit = 200000,
  202. .p2_slow = 10, .p2_fast = 5 },
  203. };
  204. static const intel_limit_t intel_limits_pineview_lvds = {
  205. .dot = { .min = 20000, .max = 400000 },
  206. .vco = { .min = 1700000, .max = 3500000 },
  207. .n = { .min = 3, .max = 6 },
  208. .m = { .min = 2, .max = 256 },
  209. .m1 = { .min = 0, .max = 0 },
  210. .m2 = { .min = 0, .max = 254 },
  211. .p = { .min = 7, .max = 112 },
  212. .p1 = { .min = 1, .max = 8 },
  213. .p2 = { .dot_limit = 112000,
  214. .p2_slow = 14, .p2_fast = 14 },
  215. };
  216. /* Ironlake / Sandybridge
  217. *
  218. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  219. * the range value for them is (actual_value - 2).
  220. */
  221. static const intel_limit_t intel_limits_ironlake_dac = {
  222. .dot = { .min = 25000, .max = 350000 },
  223. .vco = { .min = 1760000, .max = 3510000 },
  224. .n = { .min = 1, .max = 5 },
  225. .m = { .min = 79, .max = 127 },
  226. .m1 = { .min = 12, .max = 22 },
  227. .m2 = { .min = 5, .max = 9 },
  228. .p = { .min = 5, .max = 80 },
  229. .p1 = { .min = 1, .max = 8 },
  230. .p2 = { .dot_limit = 225000,
  231. .p2_slow = 10, .p2_fast = 5 },
  232. };
  233. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  234. .dot = { .min = 25000, .max = 350000 },
  235. .vco = { .min = 1760000, .max = 3510000 },
  236. .n = { .min = 1, .max = 3 },
  237. .m = { .min = 79, .max = 118 },
  238. .m1 = { .min = 12, .max = 22 },
  239. .m2 = { .min = 5, .max = 9 },
  240. .p = { .min = 28, .max = 112 },
  241. .p1 = { .min = 2, .max = 8 },
  242. .p2 = { .dot_limit = 225000,
  243. .p2_slow = 14, .p2_fast = 14 },
  244. };
  245. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  246. .dot = { .min = 25000, .max = 350000 },
  247. .vco = { .min = 1760000, .max = 3510000 },
  248. .n = { .min = 1, .max = 3 },
  249. .m = { .min = 79, .max = 127 },
  250. .m1 = { .min = 12, .max = 22 },
  251. .m2 = { .min = 5, .max = 9 },
  252. .p = { .min = 14, .max = 56 },
  253. .p1 = { .min = 2, .max = 8 },
  254. .p2 = { .dot_limit = 225000,
  255. .p2_slow = 7, .p2_fast = 7 },
  256. };
  257. /* LVDS 100mhz refclk limits. */
  258. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  259. .dot = { .min = 25000, .max = 350000 },
  260. .vco = { .min = 1760000, .max = 3510000 },
  261. .n = { .min = 1, .max = 2 },
  262. .m = { .min = 79, .max = 126 },
  263. .m1 = { .min = 12, .max = 22 },
  264. .m2 = { .min = 5, .max = 9 },
  265. .p = { .min = 28, .max = 112 },
  266. .p1 = { .min = 2, .max = 8 },
  267. .p2 = { .dot_limit = 225000,
  268. .p2_slow = 14, .p2_fast = 14 },
  269. };
  270. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  271. .dot = { .min = 25000, .max = 350000 },
  272. .vco = { .min = 1760000, .max = 3510000 },
  273. .n = { .min = 1, .max = 3 },
  274. .m = { .min = 79, .max = 126 },
  275. .m1 = { .min = 12, .max = 22 },
  276. .m2 = { .min = 5, .max = 9 },
  277. .p = { .min = 14, .max = 42 },
  278. .p1 = { .min = 2, .max = 6 },
  279. .p2 = { .dot_limit = 225000,
  280. .p2_slow = 7, .p2_fast = 7 },
  281. };
  282. static const intel_limit_t intel_limits_vlv = {
  283. /*
  284. * These are the data rate limits (measured in fast clocks)
  285. * since those are the strictest limits we have. The fast
  286. * clock and actual rate limits are more relaxed, so checking
  287. * them would make no difference.
  288. */
  289. .dot = { .min = 25000 * 5, .max = 270000 * 5 },
  290. .vco = { .min = 4000000, .max = 6000000 },
  291. .n = { .min = 1, .max = 7 },
  292. .m1 = { .min = 2, .max = 3 },
  293. .m2 = { .min = 11, .max = 156 },
  294. .p1 = { .min = 2, .max = 3 },
  295. .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
  296. };
  297. static void vlv_clock(int refclk, intel_clock_t *clock)
  298. {
  299. clock->m = clock->m1 * clock->m2;
  300. clock->p = clock->p1 * clock->p2;
  301. clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
  302. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  303. }
  304. /**
  305. * Returns whether any output on the specified pipe is of the specified type
  306. */
  307. static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  308. {
  309. struct drm_device *dev = crtc->dev;
  310. struct intel_encoder *encoder;
  311. for_each_encoder_on_crtc(dev, crtc, encoder)
  312. if (encoder->type == type)
  313. return true;
  314. return false;
  315. }
  316. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  317. int refclk)
  318. {
  319. struct drm_device *dev = crtc->dev;
  320. const intel_limit_t *limit;
  321. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  322. if (intel_is_dual_link_lvds(dev)) {
  323. if (refclk == 100000)
  324. limit = &intel_limits_ironlake_dual_lvds_100m;
  325. else
  326. limit = &intel_limits_ironlake_dual_lvds;
  327. } else {
  328. if (refclk == 100000)
  329. limit = &intel_limits_ironlake_single_lvds_100m;
  330. else
  331. limit = &intel_limits_ironlake_single_lvds;
  332. }
  333. } else
  334. limit = &intel_limits_ironlake_dac;
  335. return limit;
  336. }
  337. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  338. {
  339. struct drm_device *dev = crtc->dev;
  340. const intel_limit_t *limit;
  341. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  342. if (intel_is_dual_link_lvds(dev))
  343. limit = &intel_limits_g4x_dual_channel_lvds;
  344. else
  345. limit = &intel_limits_g4x_single_channel_lvds;
  346. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  347. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  348. limit = &intel_limits_g4x_hdmi;
  349. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  350. limit = &intel_limits_g4x_sdvo;
  351. } else /* The option is for other outputs */
  352. limit = &intel_limits_i9xx_sdvo;
  353. return limit;
  354. }
  355. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  356. {
  357. struct drm_device *dev = crtc->dev;
  358. const intel_limit_t *limit;
  359. if (HAS_PCH_SPLIT(dev))
  360. limit = intel_ironlake_limit(crtc, refclk);
  361. else if (IS_G4X(dev)) {
  362. limit = intel_g4x_limit(crtc);
  363. } else if (IS_PINEVIEW(dev)) {
  364. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  365. limit = &intel_limits_pineview_lvds;
  366. else
  367. limit = &intel_limits_pineview_sdvo;
  368. } else if (IS_VALLEYVIEW(dev)) {
  369. limit = &intel_limits_vlv;
  370. } else if (!IS_GEN2(dev)) {
  371. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  372. limit = &intel_limits_i9xx_lvds;
  373. else
  374. limit = &intel_limits_i9xx_sdvo;
  375. } else {
  376. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  377. limit = &intel_limits_i8xx_lvds;
  378. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
  379. limit = &intel_limits_i8xx_dvo;
  380. else
  381. limit = &intel_limits_i8xx_dac;
  382. }
  383. return limit;
  384. }
  385. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  386. static void pineview_clock(int refclk, intel_clock_t *clock)
  387. {
  388. clock->m = clock->m2 + 2;
  389. clock->p = clock->p1 * clock->p2;
  390. clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
  391. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  392. }
  393. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  394. {
  395. return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  396. }
  397. static void i9xx_clock(int refclk, intel_clock_t *clock)
  398. {
  399. clock->m = i9xx_dpll_compute_m(clock);
  400. clock->p = clock->p1 * clock->p2;
  401. clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
  402. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  403. }
  404. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  405. /**
  406. * Returns whether the given set of divisors are valid for a given refclk with
  407. * the given connectors.
  408. */
  409. static bool intel_PLL_is_valid(struct drm_device *dev,
  410. const intel_limit_t *limit,
  411. const intel_clock_t *clock)
  412. {
  413. if (clock->n < limit->n.min || limit->n.max < clock->n)
  414. INTELPllInvalid("n out of range\n");
  415. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  416. INTELPllInvalid("p1 out of range\n");
  417. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  418. INTELPllInvalid("m2 out of range\n");
  419. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  420. INTELPllInvalid("m1 out of range\n");
  421. if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
  422. if (clock->m1 <= clock->m2)
  423. INTELPllInvalid("m1 <= m2\n");
  424. if (!IS_VALLEYVIEW(dev)) {
  425. if (clock->p < limit->p.min || limit->p.max < clock->p)
  426. INTELPllInvalid("p out of range\n");
  427. if (clock->m < limit->m.min || limit->m.max < clock->m)
  428. INTELPllInvalid("m out of range\n");
  429. }
  430. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  431. INTELPllInvalid("vco out of range\n");
  432. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  433. * connector, etc., rather than just a single range.
  434. */
  435. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  436. INTELPllInvalid("dot out of range\n");
  437. return true;
  438. }
  439. static bool
  440. i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  441. int target, int refclk, intel_clock_t *match_clock,
  442. intel_clock_t *best_clock)
  443. {
  444. struct drm_device *dev = crtc->dev;
  445. intel_clock_t clock;
  446. int err = target;
  447. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  448. /*
  449. * For LVDS just rely on its current settings for dual-channel.
  450. * We haven't figured out how to reliably set up different
  451. * single/dual channel state, if we even can.
  452. */
  453. if (intel_is_dual_link_lvds(dev))
  454. clock.p2 = limit->p2.p2_fast;
  455. else
  456. clock.p2 = limit->p2.p2_slow;
  457. } else {
  458. if (target < limit->p2.dot_limit)
  459. clock.p2 = limit->p2.p2_slow;
  460. else
  461. clock.p2 = limit->p2.p2_fast;
  462. }
  463. memset(best_clock, 0, sizeof(*best_clock));
  464. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  465. clock.m1++) {
  466. for (clock.m2 = limit->m2.min;
  467. clock.m2 <= limit->m2.max; clock.m2++) {
  468. if (clock.m2 >= clock.m1)
  469. break;
  470. for (clock.n = limit->n.min;
  471. clock.n <= limit->n.max; clock.n++) {
  472. for (clock.p1 = limit->p1.min;
  473. clock.p1 <= limit->p1.max; clock.p1++) {
  474. int this_err;
  475. i9xx_clock(refclk, &clock);
  476. if (!intel_PLL_is_valid(dev, limit,
  477. &clock))
  478. continue;
  479. if (match_clock &&
  480. clock.p != match_clock->p)
  481. continue;
  482. this_err = abs(clock.dot - target);
  483. if (this_err < err) {
  484. *best_clock = clock;
  485. err = this_err;
  486. }
  487. }
  488. }
  489. }
  490. }
  491. return (err != target);
  492. }
  493. static bool
  494. pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  495. int target, int refclk, intel_clock_t *match_clock,
  496. intel_clock_t *best_clock)
  497. {
  498. struct drm_device *dev = crtc->dev;
  499. intel_clock_t clock;
  500. int err = target;
  501. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  502. /*
  503. * For LVDS just rely on its current settings for dual-channel.
  504. * We haven't figured out how to reliably set up different
  505. * single/dual channel state, if we even can.
  506. */
  507. if (intel_is_dual_link_lvds(dev))
  508. clock.p2 = limit->p2.p2_fast;
  509. else
  510. clock.p2 = limit->p2.p2_slow;
  511. } else {
  512. if (target < limit->p2.dot_limit)
  513. clock.p2 = limit->p2.p2_slow;
  514. else
  515. clock.p2 = limit->p2.p2_fast;
  516. }
  517. memset(best_clock, 0, sizeof(*best_clock));
  518. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  519. clock.m1++) {
  520. for (clock.m2 = limit->m2.min;
  521. clock.m2 <= limit->m2.max; clock.m2++) {
  522. for (clock.n = limit->n.min;
  523. clock.n <= limit->n.max; clock.n++) {
  524. for (clock.p1 = limit->p1.min;
  525. clock.p1 <= limit->p1.max; clock.p1++) {
  526. int this_err;
  527. pineview_clock(refclk, &clock);
  528. if (!intel_PLL_is_valid(dev, limit,
  529. &clock))
  530. continue;
  531. if (match_clock &&
  532. clock.p != match_clock->p)
  533. continue;
  534. this_err = abs(clock.dot - target);
  535. if (this_err < err) {
  536. *best_clock = clock;
  537. err = this_err;
  538. }
  539. }
  540. }
  541. }
  542. }
  543. return (err != target);
  544. }
  545. static bool
  546. g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  547. int target, int refclk, intel_clock_t *match_clock,
  548. intel_clock_t *best_clock)
  549. {
  550. struct drm_device *dev = crtc->dev;
  551. intel_clock_t clock;
  552. int max_n;
  553. bool found;
  554. /* approximately equals target * 0.00585 */
  555. int err_most = (target >> 8) + (target >> 9);
  556. found = false;
  557. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  558. if (intel_is_dual_link_lvds(dev))
  559. clock.p2 = limit->p2.p2_fast;
  560. else
  561. clock.p2 = limit->p2.p2_slow;
  562. } else {
  563. if (target < limit->p2.dot_limit)
  564. clock.p2 = limit->p2.p2_slow;
  565. else
  566. clock.p2 = limit->p2.p2_fast;
  567. }
  568. memset(best_clock, 0, sizeof(*best_clock));
  569. max_n = limit->n.max;
  570. /* based on hardware requirement, prefer smaller n to precision */
  571. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  572. /* based on hardware requirement, prefere larger m1,m2 */
  573. for (clock.m1 = limit->m1.max;
  574. clock.m1 >= limit->m1.min; clock.m1--) {
  575. for (clock.m2 = limit->m2.max;
  576. clock.m2 >= limit->m2.min; clock.m2--) {
  577. for (clock.p1 = limit->p1.max;
  578. clock.p1 >= limit->p1.min; clock.p1--) {
  579. int this_err;
  580. i9xx_clock(refclk, &clock);
  581. if (!intel_PLL_is_valid(dev, limit,
  582. &clock))
  583. continue;
  584. this_err = abs(clock.dot - target);
  585. if (this_err < err_most) {
  586. *best_clock = clock;
  587. err_most = this_err;
  588. max_n = clock.n;
  589. found = true;
  590. }
  591. }
  592. }
  593. }
  594. }
  595. return found;
  596. }
  597. static bool
  598. vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  599. int target, int refclk, intel_clock_t *match_clock,
  600. intel_clock_t *best_clock)
  601. {
  602. struct drm_device *dev = crtc->dev;
  603. intel_clock_t clock;
  604. unsigned int bestppm = 1000000;
  605. /* min update 19.2 MHz */
  606. int max_n = min(limit->n.max, refclk / 19200);
  607. bool found = false;
  608. target *= 5; /* fast clock */
  609. memset(best_clock, 0, sizeof(*best_clock));
  610. /* based on hardware requirement, prefer smaller n to precision */
  611. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  612. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  613. for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
  614. clock.p2 -= clock.p2 > 10 ? 2 : 1) {
  615. clock.p = clock.p1 * clock.p2;
  616. /* based on hardware requirement, prefer bigger m1,m2 values */
  617. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  618. unsigned int ppm, diff;
  619. clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
  620. refclk * clock.m1);
  621. vlv_clock(refclk, &clock);
  622. if (!intel_PLL_is_valid(dev, limit,
  623. &clock))
  624. continue;
  625. diff = abs(clock.dot - target);
  626. ppm = div_u64(1000000ULL * diff, target);
  627. if (ppm < 100 && clock.p > best_clock->p) {
  628. bestppm = 0;
  629. *best_clock = clock;
  630. found = true;
  631. }
  632. if (bestppm >= 10 && ppm < bestppm - 10) {
  633. bestppm = ppm;
  634. *best_clock = clock;
  635. found = true;
  636. }
  637. }
  638. }
  639. }
  640. }
  641. return found;
  642. }
  643. bool intel_crtc_active(struct drm_crtc *crtc)
  644. {
  645. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  646. /* Be paranoid as we can arrive here with only partial
  647. * state retrieved from the hardware during setup.
  648. *
  649. * We can ditch the adjusted_mode.crtc_clock check as soon
  650. * as Haswell has gained clock readout/fastboot support.
  651. *
  652. * We can ditch the crtc->fb check as soon as we can
  653. * properly reconstruct framebuffers.
  654. */
  655. return intel_crtc->active && crtc->fb &&
  656. intel_crtc->config.adjusted_mode.crtc_clock;
  657. }
  658. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  659. enum pipe pipe)
  660. {
  661. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  662. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  663. return intel_crtc->config.cpu_transcoder;
  664. }
  665. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  666. {
  667. struct drm_i915_private *dev_priv = dev->dev_private;
  668. u32 frame, frame_reg = PIPEFRAME(pipe);
  669. frame = I915_READ(frame_reg);
  670. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  671. DRM_DEBUG_KMS("vblank wait timed out\n");
  672. }
  673. /**
  674. * intel_wait_for_vblank - wait for vblank on a given pipe
  675. * @dev: drm device
  676. * @pipe: pipe to wait for
  677. *
  678. * Wait for vblank to occur on a given pipe. Needed for various bits of
  679. * mode setting code.
  680. */
  681. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  682. {
  683. struct drm_i915_private *dev_priv = dev->dev_private;
  684. int pipestat_reg = PIPESTAT(pipe);
  685. if (INTEL_INFO(dev)->gen >= 5) {
  686. ironlake_wait_for_vblank(dev, pipe);
  687. return;
  688. }
  689. /* Clear existing vblank status. Note this will clear any other
  690. * sticky status fields as well.
  691. *
  692. * This races with i915_driver_irq_handler() with the result
  693. * that either function could miss a vblank event. Here it is not
  694. * fatal, as we will either wait upon the next vblank interrupt or
  695. * timeout. Generally speaking intel_wait_for_vblank() is only
  696. * called during modeset at which time the GPU should be idle and
  697. * should *not* be performing page flips and thus not waiting on
  698. * vblanks...
  699. * Currently, the result of us stealing a vblank from the irq
  700. * handler is that a single frame will be skipped during swapbuffers.
  701. */
  702. I915_WRITE(pipestat_reg,
  703. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  704. /* Wait for vblank interrupt bit to set */
  705. if (wait_for(I915_READ(pipestat_reg) &
  706. PIPE_VBLANK_INTERRUPT_STATUS,
  707. 50))
  708. DRM_DEBUG_KMS("vblank wait timed out\n");
  709. }
  710. static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
  711. {
  712. struct drm_i915_private *dev_priv = dev->dev_private;
  713. u32 reg = PIPEDSL(pipe);
  714. u32 line1, line2;
  715. u32 line_mask;
  716. if (IS_GEN2(dev))
  717. line_mask = DSL_LINEMASK_GEN2;
  718. else
  719. line_mask = DSL_LINEMASK_GEN3;
  720. line1 = I915_READ(reg) & line_mask;
  721. mdelay(5);
  722. line2 = I915_READ(reg) & line_mask;
  723. return line1 == line2;
  724. }
  725. /*
  726. * intel_wait_for_pipe_off - wait for pipe to turn off
  727. * @dev: drm device
  728. * @pipe: pipe to wait for
  729. *
  730. * After disabling a pipe, we can't wait for vblank in the usual way,
  731. * spinning on the vblank interrupt status bit, since we won't actually
  732. * see an interrupt when the pipe is disabled.
  733. *
  734. * On Gen4 and above:
  735. * wait for the pipe register state bit to turn off
  736. *
  737. * Otherwise:
  738. * wait for the display line value to settle (it usually
  739. * ends up stopping at the start of the next frame).
  740. *
  741. */
  742. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  743. {
  744. struct drm_i915_private *dev_priv = dev->dev_private;
  745. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  746. pipe);
  747. if (INTEL_INFO(dev)->gen >= 4) {
  748. int reg = PIPECONF(cpu_transcoder);
  749. /* Wait for the Pipe State to go off */
  750. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  751. 100))
  752. WARN(1, "pipe_off wait timed out\n");
  753. } else {
  754. /* Wait for the display line to settle */
  755. if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
  756. WARN(1, "pipe_off wait timed out\n");
  757. }
  758. }
  759. /*
  760. * ibx_digital_port_connected - is the specified port connected?
  761. * @dev_priv: i915 private structure
  762. * @port: the port to test
  763. *
  764. * Returns true if @port is connected, false otherwise.
  765. */
  766. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  767. struct intel_digital_port *port)
  768. {
  769. u32 bit;
  770. if (HAS_PCH_IBX(dev_priv->dev)) {
  771. switch(port->port) {
  772. case PORT_B:
  773. bit = SDE_PORTB_HOTPLUG;
  774. break;
  775. case PORT_C:
  776. bit = SDE_PORTC_HOTPLUG;
  777. break;
  778. case PORT_D:
  779. bit = SDE_PORTD_HOTPLUG;
  780. break;
  781. default:
  782. return true;
  783. }
  784. } else {
  785. switch(port->port) {
  786. case PORT_B:
  787. bit = SDE_PORTB_HOTPLUG_CPT;
  788. break;
  789. case PORT_C:
  790. bit = SDE_PORTC_HOTPLUG_CPT;
  791. break;
  792. case PORT_D:
  793. bit = SDE_PORTD_HOTPLUG_CPT;
  794. break;
  795. default:
  796. return true;
  797. }
  798. }
  799. return I915_READ(SDEISR) & bit;
  800. }
  801. static const char *state_string(bool enabled)
  802. {
  803. return enabled ? "on" : "off";
  804. }
  805. /* Only for pre-ILK configs */
  806. void assert_pll(struct drm_i915_private *dev_priv,
  807. enum pipe pipe, bool state)
  808. {
  809. int reg;
  810. u32 val;
  811. bool cur_state;
  812. reg = DPLL(pipe);
  813. val = I915_READ(reg);
  814. cur_state = !!(val & DPLL_VCO_ENABLE);
  815. WARN(cur_state != state,
  816. "PLL state assertion failure (expected %s, current %s)\n",
  817. state_string(state), state_string(cur_state));
  818. }
  819. /* XXX: the dsi pll is shared between MIPI DSI ports */
  820. static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
  821. {
  822. u32 val;
  823. bool cur_state;
  824. mutex_lock(&dev_priv->dpio_lock);
  825. val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
  826. mutex_unlock(&dev_priv->dpio_lock);
  827. cur_state = val & DSI_PLL_VCO_EN;
  828. WARN(cur_state != state,
  829. "DSI PLL state assertion failure (expected %s, current %s)\n",
  830. state_string(state), state_string(cur_state));
  831. }
  832. #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
  833. #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
  834. struct intel_shared_dpll *
  835. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  836. {
  837. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  838. if (crtc->config.shared_dpll < 0)
  839. return NULL;
  840. return &dev_priv->shared_dplls[crtc->config.shared_dpll];
  841. }
  842. /* For ILK+ */
  843. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  844. struct intel_shared_dpll *pll,
  845. bool state)
  846. {
  847. bool cur_state;
  848. struct intel_dpll_hw_state hw_state;
  849. if (HAS_PCH_LPT(dev_priv->dev)) {
  850. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  851. return;
  852. }
  853. if (WARN (!pll,
  854. "asserting DPLL %s with no DPLL\n", state_string(state)))
  855. return;
  856. cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  857. WARN(cur_state != state,
  858. "%s assertion failure (expected %s, current %s)\n",
  859. pll->name, state_string(state), state_string(cur_state));
  860. }
  861. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  862. enum pipe pipe, bool state)
  863. {
  864. int reg;
  865. u32 val;
  866. bool cur_state;
  867. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  868. pipe);
  869. if (HAS_DDI(dev_priv->dev)) {
  870. /* DDI does not have a specific FDI_TX register */
  871. reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  872. val = I915_READ(reg);
  873. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  874. } else {
  875. reg = FDI_TX_CTL(pipe);
  876. val = I915_READ(reg);
  877. cur_state = !!(val & FDI_TX_ENABLE);
  878. }
  879. WARN(cur_state != state,
  880. "FDI TX state assertion failure (expected %s, current %s)\n",
  881. state_string(state), state_string(cur_state));
  882. }
  883. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  884. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  885. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  886. enum pipe pipe, bool state)
  887. {
  888. int reg;
  889. u32 val;
  890. bool cur_state;
  891. reg = FDI_RX_CTL(pipe);
  892. val = I915_READ(reg);
  893. cur_state = !!(val & FDI_RX_ENABLE);
  894. WARN(cur_state != state,
  895. "FDI RX state assertion failure (expected %s, current %s)\n",
  896. state_string(state), state_string(cur_state));
  897. }
  898. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  899. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  900. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  901. enum pipe pipe)
  902. {
  903. int reg;
  904. u32 val;
  905. /* ILK FDI PLL is always enabled */
  906. if (dev_priv->info->gen == 5)
  907. return;
  908. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  909. if (HAS_DDI(dev_priv->dev))
  910. return;
  911. reg = FDI_TX_CTL(pipe);
  912. val = I915_READ(reg);
  913. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  914. }
  915. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  916. enum pipe pipe, bool state)
  917. {
  918. int reg;
  919. u32 val;
  920. bool cur_state;
  921. reg = FDI_RX_CTL(pipe);
  922. val = I915_READ(reg);
  923. cur_state = !!(val & FDI_RX_PLL_ENABLE);
  924. WARN(cur_state != state,
  925. "FDI RX PLL assertion failure (expected %s, current %s)\n",
  926. state_string(state), state_string(cur_state));
  927. }
  928. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  929. enum pipe pipe)
  930. {
  931. int pp_reg, lvds_reg;
  932. u32 val;
  933. enum pipe panel_pipe = PIPE_A;
  934. bool locked = true;
  935. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  936. pp_reg = PCH_PP_CONTROL;
  937. lvds_reg = PCH_LVDS;
  938. } else {
  939. pp_reg = PP_CONTROL;
  940. lvds_reg = LVDS;
  941. }
  942. val = I915_READ(pp_reg);
  943. if (!(val & PANEL_POWER_ON) ||
  944. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  945. locked = false;
  946. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  947. panel_pipe = PIPE_B;
  948. WARN(panel_pipe == pipe && locked,
  949. "panel assertion failure, pipe %c regs locked\n",
  950. pipe_name(pipe));
  951. }
  952. static void assert_cursor(struct drm_i915_private *dev_priv,
  953. enum pipe pipe, bool state)
  954. {
  955. struct drm_device *dev = dev_priv->dev;
  956. bool cur_state;
  957. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  958. cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
  959. else if (IS_845G(dev) || IS_I865G(dev))
  960. cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
  961. else
  962. cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
  963. WARN(cur_state != state,
  964. "cursor on pipe %c assertion failure (expected %s, current %s)\n",
  965. pipe_name(pipe), state_string(state), state_string(cur_state));
  966. }
  967. #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
  968. #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
  969. void assert_pipe(struct drm_i915_private *dev_priv,
  970. enum pipe pipe, bool state)
  971. {
  972. int reg;
  973. u32 val;
  974. bool cur_state;
  975. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  976. pipe);
  977. /* if we need the pipe A quirk it must be always on */
  978. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  979. state = true;
  980. if (!intel_display_power_enabled(dev_priv->dev,
  981. POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  982. cur_state = false;
  983. } else {
  984. reg = PIPECONF(cpu_transcoder);
  985. val = I915_READ(reg);
  986. cur_state = !!(val & PIPECONF_ENABLE);
  987. }
  988. WARN(cur_state != state,
  989. "pipe %c assertion failure (expected %s, current %s)\n",
  990. pipe_name(pipe), state_string(state), state_string(cur_state));
  991. }
  992. static void assert_plane(struct drm_i915_private *dev_priv,
  993. enum plane plane, bool state)
  994. {
  995. int reg;
  996. u32 val;
  997. bool cur_state;
  998. reg = DSPCNTR(plane);
  999. val = I915_READ(reg);
  1000. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1001. WARN(cur_state != state,
  1002. "plane %c assertion failure (expected %s, current %s)\n",
  1003. plane_name(plane), state_string(state), state_string(cur_state));
  1004. }
  1005. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1006. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1007. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1008. enum pipe pipe)
  1009. {
  1010. struct drm_device *dev = dev_priv->dev;
  1011. int reg, i;
  1012. u32 val;
  1013. int cur_pipe;
  1014. /* Primary planes are fixed to pipes on gen4+ */
  1015. if (INTEL_INFO(dev)->gen >= 4) {
  1016. reg = DSPCNTR(pipe);
  1017. val = I915_READ(reg);
  1018. WARN((val & DISPLAY_PLANE_ENABLE),
  1019. "plane %c assertion failure, should be disabled but not\n",
  1020. plane_name(pipe));
  1021. return;
  1022. }
  1023. /* Need to check both planes against the pipe */
  1024. for_each_pipe(i) {
  1025. reg = DSPCNTR(i);
  1026. val = I915_READ(reg);
  1027. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1028. DISPPLANE_SEL_PIPE_SHIFT;
  1029. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1030. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1031. plane_name(i), pipe_name(pipe));
  1032. }
  1033. }
  1034. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1035. enum pipe pipe)
  1036. {
  1037. struct drm_device *dev = dev_priv->dev;
  1038. int reg, i;
  1039. u32 val;
  1040. if (IS_VALLEYVIEW(dev)) {
  1041. for (i = 0; i < dev_priv->num_plane; i++) {
  1042. reg = SPCNTR(pipe, i);
  1043. val = I915_READ(reg);
  1044. WARN((val & SP_ENABLE),
  1045. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1046. sprite_name(pipe, i), pipe_name(pipe));
  1047. }
  1048. } else if (INTEL_INFO(dev)->gen >= 7) {
  1049. reg = SPRCTL(pipe);
  1050. val = I915_READ(reg);
  1051. WARN((val & SPRITE_ENABLE),
  1052. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1053. plane_name(pipe), pipe_name(pipe));
  1054. } else if (INTEL_INFO(dev)->gen >= 5) {
  1055. reg = DVSCNTR(pipe);
  1056. val = I915_READ(reg);
  1057. WARN((val & DVS_ENABLE),
  1058. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1059. plane_name(pipe), pipe_name(pipe));
  1060. }
  1061. }
  1062. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1063. {
  1064. u32 val;
  1065. bool enabled;
  1066. if (HAS_PCH_LPT(dev_priv->dev)) {
  1067. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1068. return;
  1069. }
  1070. val = I915_READ(PCH_DREF_CONTROL);
  1071. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1072. DREF_SUPERSPREAD_SOURCE_MASK));
  1073. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1074. }
  1075. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1076. enum pipe pipe)
  1077. {
  1078. int reg;
  1079. u32 val;
  1080. bool enabled;
  1081. reg = PCH_TRANSCONF(pipe);
  1082. val = I915_READ(reg);
  1083. enabled = !!(val & TRANS_ENABLE);
  1084. WARN(enabled,
  1085. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1086. pipe_name(pipe));
  1087. }
  1088. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1089. enum pipe pipe, u32 port_sel, u32 val)
  1090. {
  1091. if ((val & DP_PORT_EN) == 0)
  1092. return false;
  1093. if (HAS_PCH_CPT(dev_priv->dev)) {
  1094. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1095. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1096. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1097. return false;
  1098. } else {
  1099. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1100. return false;
  1101. }
  1102. return true;
  1103. }
  1104. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1105. enum pipe pipe, u32 val)
  1106. {
  1107. if ((val & SDVO_ENABLE) == 0)
  1108. return false;
  1109. if (HAS_PCH_CPT(dev_priv->dev)) {
  1110. if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1111. return false;
  1112. } else {
  1113. if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1114. return false;
  1115. }
  1116. return true;
  1117. }
  1118. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1119. enum pipe pipe, u32 val)
  1120. {
  1121. if ((val & LVDS_PORT_EN) == 0)
  1122. return false;
  1123. if (HAS_PCH_CPT(dev_priv->dev)) {
  1124. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1125. return false;
  1126. } else {
  1127. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1128. return false;
  1129. }
  1130. return true;
  1131. }
  1132. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1133. enum pipe pipe, u32 val)
  1134. {
  1135. if ((val & ADPA_DAC_ENABLE) == 0)
  1136. return false;
  1137. if (HAS_PCH_CPT(dev_priv->dev)) {
  1138. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1139. return false;
  1140. } else {
  1141. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1142. return false;
  1143. }
  1144. return true;
  1145. }
  1146. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1147. enum pipe pipe, int reg, u32 port_sel)
  1148. {
  1149. u32 val = I915_READ(reg);
  1150. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1151. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1152. reg, pipe_name(pipe));
  1153. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1154. && (val & DP_PIPEB_SELECT),
  1155. "IBX PCH dp port still using transcoder B\n");
  1156. }
  1157. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1158. enum pipe pipe, int reg)
  1159. {
  1160. u32 val = I915_READ(reg);
  1161. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1162. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1163. reg, pipe_name(pipe));
  1164. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1165. && (val & SDVO_PIPE_B_SELECT),
  1166. "IBX PCH hdmi port still using transcoder B\n");
  1167. }
  1168. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1169. enum pipe pipe)
  1170. {
  1171. int reg;
  1172. u32 val;
  1173. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1174. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1175. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1176. reg = PCH_ADPA;
  1177. val = I915_READ(reg);
  1178. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1179. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1180. pipe_name(pipe));
  1181. reg = PCH_LVDS;
  1182. val = I915_READ(reg);
  1183. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1184. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1185. pipe_name(pipe));
  1186. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1187. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1188. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1189. }
  1190. static void intel_init_dpio(struct drm_device *dev)
  1191. {
  1192. struct drm_i915_private *dev_priv = dev->dev_private;
  1193. if (!IS_VALLEYVIEW(dev))
  1194. return;
  1195. /*
  1196. * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
  1197. * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
  1198. * a. GUnit 0x2110 bit[0] set to 1 (def 0)
  1199. * b. The other bits such as sfr settings / modesel may all be set
  1200. * to 0.
  1201. *
  1202. * This should only be done on init and resume from S3 with both
  1203. * PLLs disabled, or we risk losing DPIO and PLL synchronization.
  1204. */
  1205. I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
  1206. }
  1207. static void vlv_enable_pll(struct intel_crtc *crtc)
  1208. {
  1209. struct drm_device *dev = crtc->base.dev;
  1210. struct drm_i915_private *dev_priv = dev->dev_private;
  1211. int reg = DPLL(crtc->pipe);
  1212. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1213. assert_pipe_disabled(dev_priv, crtc->pipe);
  1214. /* No really, not for ILK+ */
  1215. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1216. /* PLL is protected by panel, make sure we can write it */
  1217. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1218. assert_panel_unlocked(dev_priv, crtc->pipe);
  1219. I915_WRITE(reg, dpll);
  1220. POSTING_READ(reg);
  1221. udelay(150);
  1222. if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1223. DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1224. I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
  1225. POSTING_READ(DPLL_MD(crtc->pipe));
  1226. /* We do this three times for luck */
  1227. I915_WRITE(reg, dpll);
  1228. POSTING_READ(reg);
  1229. udelay(150); /* wait for warmup */
  1230. I915_WRITE(reg, dpll);
  1231. POSTING_READ(reg);
  1232. udelay(150); /* wait for warmup */
  1233. I915_WRITE(reg, dpll);
  1234. POSTING_READ(reg);
  1235. udelay(150); /* wait for warmup */
  1236. }
  1237. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1238. {
  1239. struct drm_device *dev = crtc->base.dev;
  1240. struct drm_i915_private *dev_priv = dev->dev_private;
  1241. int reg = DPLL(crtc->pipe);
  1242. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1243. assert_pipe_disabled(dev_priv, crtc->pipe);
  1244. /* No really, not for ILK+ */
  1245. BUG_ON(dev_priv->info->gen >= 5);
  1246. /* PLL is protected by panel, make sure we can write it */
  1247. if (IS_MOBILE(dev) && !IS_I830(dev))
  1248. assert_panel_unlocked(dev_priv, crtc->pipe);
  1249. I915_WRITE(reg, dpll);
  1250. /* Wait for the clocks to stabilize. */
  1251. POSTING_READ(reg);
  1252. udelay(150);
  1253. if (INTEL_INFO(dev)->gen >= 4) {
  1254. I915_WRITE(DPLL_MD(crtc->pipe),
  1255. crtc->config.dpll_hw_state.dpll_md);
  1256. } else {
  1257. /* The pixel multiplier can only be updated once the
  1258. * DPLL is enabled and the clocks are stable.
  1259. *
  1260. * So write it again.
  1261. */
  1262. I915_WRITE(reg, dpll);
  1263. }
  1264. /* We do this three times for luck */
  1265. I915_WRITE(reg, dpll);
  1266. POSTING_READ(reg);
  1267. udelay(150); /* wait for warmup */
  1268. I915_WRITE(reg, dpll);
  1269. POSTING_READ(reg);
  1270. udelay(150); /* wait for warmup */
  1271. I915_WRITE(reg, dpll);
  1272. POSTING_READ(reg);
  1273. udelay(150); /* wait for warmup */
  1274. }
  1275. /**
  1276. * i9xx_disable_pll - disable a PLL
  1277. * @dev_priv: i915 private structure
  1278. * @pipe: pipe PLL to disable
  1279. *
  1280. * Disable the PLL for @pipe, making sure the pipe is off first.
  1281. *
  1282. * Note! This is for pre-ILK only.
  1283. */
  1284. static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1285. {
  1286. /* Don't disable pipe A or pipe A PLLs if needed */
  1287. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1288. return;
  1289. /* Make sure the pipe isn't still relying on us */
  1290. assert_pipe_disabled(dev_priv, pipe);
  1291. I915_WRITE(DPLL(pipe), 0);
  1292. POSTING_READ(DPLL(pipe));
  1293. }
  1294. static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1295. {
  1296. u32 val = 0;
  1297. /* Make sure the pipe isn't still relying on us */
  1298. assert_pipe_disabled(dev_priv, pipe);
  1299. /* Leave integrated clock source enabled */
  1300. if (pipe == PIPE_B)
  1301. val = DPLL_INTEGRATED_CRI_CLK_VLV;
  1302. I915_WRITE(DPLL(pipe), val);
  1303. POSTING_READ(DPLL(pipe));
  1304. }
  1305. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1306. {
  1307. u32 port_mask;
  1308. if (!port)
  1309. port_mask = DPLL_PORTB_READY_MASK;
  1310. else
  1311. port_mask = DPLL_PORTC_READY_MASK;
  1312. if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1313. WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1314. 'B' + port, I915_READ(DPLL(0)));
  1315. }
  1316. /**
  1317. * ironlake_enable_shared_dpll - enable PCH PLL
  1318. * @dev_priv: i915 private structure
  1319. * @pipe: pipe PLL to enable
  1320. *
  1321. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1322. * drives the transcoder clock.
  1323. */
  1324. static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
  1325. {
  1326. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1327. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1328. /* PCH PLLs only available on ILK, SNB and IVB */
  1329. BUG_ON(dev_priv->info->gen < 5);
  1330. if (WARN_ON(pll == NULL))
  1331. return;
  1332. if (WARN_ON(pll->refcount == 0))
  1333. return;
  1334. DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
  1335. pll->name, pll->active, pll->on,
  1336. crtc->base.base.id);
  1337. if (pll->active++) {
  1338. WARN_ON(!pll->on);
  1339. assert_shared_dpll_enabled(dev_priv, pll);
  1340. return;
  1341. }
  1342. WARN_ON(pll->on);
  1343. DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1344. pll->enable(dev_priv, pll);
  1345. pll->on = true;
  1346. }
  1347. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1348. {
  1349. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1350. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1351. /* PCH only available on ILK+ */
  1352. BUG_ON(dev_priv->info->gen < 5);
  1353. if (WARN_ON(pll == NULL))
  1354. return;
  1355. if (WARN_ON(pll->refcount == 0))
  1356. return;
  1357. DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1358. pll->name, pll->active, pll->on,
  1359. crtc->base.base.id);
  1360. if (WARN_ON(pll->active == 0)) {
  1361. assert_shared_dpll_disabled(dev_priv, pll);
  1362. return;
  1363. }
  1364. assert_shared_dpll_enabled(dev_priv, pll);
  1365. WARN_ON(!pll->on);
  1366. if (--pll->active)
  1367. return;
  1368. DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1369. pll->disable(dev_priv, pll);
  1370. pll->on = false;
  1371. }
  1372. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1373. enum pipe pipe)
  1374. {
  1375. struct drm_device *dev = dev_priv->dev;
  1376. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1377. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1378. uint32_t reg, val, pipeconf_val;
  1379. /* PCH only available on ILK+ */
  1380. BUG_ON(dev_priv->info->gen < 5);
  1381. /* Make sure PCH DPLL is enabled */
  1382. assert_shared_dpll_enabled(dev_priv,
  1383. intel_crtc_to_shared_dpll(intel_crtc));
  1384. /* FDI must be feeding us bits for PCH ports */
  1385. assert_fdi_tx_enabled(dev_priv, pipe);
  1386. assert_fdi_rx_enabled(dev_priv, pipe);
  1387. if (HAS_PCH_CPT(dev)) {
  1388. /* Workaround: Set the timing override bit before enabling the
  1389. * pch transcoder. */
  1390. reg = TRANS_CHICKEN2(pipe);
  1391. val = I915_READ(reg);
  1392. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1393. I915_WRITE(reg, val);
  1394. }
  1395. reg = PCH_TRANSCONF(pipe);
  1396. val = I915_READ(reg);
  1397. pipeconf_val = I915_READ(PIPECONF(pipe));
  1398. if (HAS_PCH_IBX(dev_priv->dev)) {
  1399. /*
  1400. * make the BPC in transcoder be consistent with
  1401. * that in pipeconf reg.
  1402. */
  1403. val &= ~PIPECONF_BPC_MASK;
  1404. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1405. }
  1406. val &= ~TRANS_INTERLACE_MASK;
  1407. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1408. if (HAS_PCH_IBX(dev_priv->dev) &&
  1409. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1410. val |= TRANS_LEGACY_INTERLACED_ILK;
  1411. else
  1412. val |= TRANS_INTERLACED;
  1413. else
  1414. val |= TRANS_PROGRESSIVE;
  1415. I915_WRITE(reg, val | TRANS_ENABLE);
  1416. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1417. DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1418. }
  1419. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1420. enum transcoder cpu_transcoder)
  1421. {
  1422. u32 val, pipeconf_val;
  1423. /* PCH only available on ILK+ */
  1424. BUG_ON(dev_priv->info->gen < 5);
  1425. /* FDI must be feeding us bits for PCH ports */
  1426. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1427. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1428. /* Workaround: set timing override bit. */
  1429. val = I915_READ(_TRANSA_CHICKEN2);
  1430. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1431. I915_WRITE(_TRANSA_CHICKEN2, val);
  1432. val = TRANS_ENABLE;
  1433. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1434. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1435. PIPECONF_INTERLACED_ILK)
  1436. val |= TRANS_INTERLACED;
  1437. else
  1438. val |= TRANS_PROGRESSIVE;
  1439. I915_WRITE(LPT_TRANSCONF, val);
  1440. if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1441. DRM_ERROR("Failed to enable PCH transcoder\n");
  1442. }
  1443. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1444. enum pipe pipe)
  1445. {
  1446. struct drm_device *dev = dev_priv->dev;
  1447. uint32_t reg, val;
  1448. /* FDI relies on the transcoder */
  1449. assert_fdi_tx_disabled(dev_priv, pipe);
  1450. assert_fdi_rx_disabled(dev_priv, pipe);
  1451. /* Ports must be off as well */
  1452. assert_pch_ports_disabled(dev_priv, pipe);
  1453. reg = PCH_TRANSCONF(pipe);
  1454. val = I915_READ(reg);
  1455. val &= ~TRANS_ENABLE;
  1456. I915_WRITE(reg, val);
  1457. /* wait for PCH transcoder off, transcoder state */
  1458. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1459. DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1460. if (!HAS_PCH_IBX(dev)) {
  1461. /* Workaround: Clear the timing override chicken bit again. */
  1462. reg = TRANS_CHICKEN2(pipe);
  1463. val = I915_READ(reg);
  1464. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1465. I915_WRITE(reg, val);
  1466. }
  1467. }
  1468. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1469. {
  1470. u32 val;
  1471. val = I915_READ(LPT_TRANSCONF);
  1472. val &= ~TRANS_ENABLE;
  1473. I915_WRITE(LPT_TRANSCONF, val);
  1474. /* wait for PCH transcoder off, transcoder state */
  1475. if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1476. DRM_ERROR("Failed to disable PCH transcoder\n");
  1477. /* Workaround: clear timing override bit. */
  1478. val = I915_READ(_TRANSA_CHICKEN2);
  1479. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1480. I915_WRITE(_TRANSA_CHICKEN2, val);
  1481. }
  1482. /**
  1483. * intel_enable_pipe - enable a pipe, asserting requirements
  1484. * @dev_priv: i915 private structure
  1485. * @pipe: pipe to enable
  1486. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1487. *
  1488. * Enable @pipe, making sure that various hardware specific requirements
  1489. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1490. *
  1491. * @pipe should be %PIPE_A or %PIPE_B.
  1492. *
  1493. * Will wait until the pipe is actually running (i.e. first vblank) before
  1494. * returning.
  1495. */
  1496. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1497. bool pch_port, bool dsi)
  1498. {
  1499. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1500. pipe);
  1501. enum pipe pch_transcoder;
  1502. int reg;
  1503. u32 val;
  1504. assert_planes_disabled(dev_priv, pipe);
  1505. assert_cursor_disabled(dev_priv, pipe);
  1506. assert_sprites_disabled(dev_priv, pipe);
  1507. if (HAS_PCH_LPT(dev_priv->dev))
  1508. pch_transcoder = TRANSCODER_A;
  1509. else
  1510. pch_transcoder = pipe;
  1511. /*
  1512. * A pipe without a PLL won't actually be able to drive bits from
  1513. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1514. * need the check.
  1515. */
  1516. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1517. if (dsi)
  1518. assert_dsi_pll_enabled(dev_priv);
  1519. else
  1520. assert_pll_enabled(dev_priv, pipe);
  1521. else {
  1522. if (pch_port) {
  1523. /* if driving the PCH, we need FDI enabled */
  1524. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1525. assert_fdi_tx_pll_enabled(dev_priv,
  1526. (enum pipe) cpu_transcoder);
  1527. }
  1528. /* FIXME: assert CPU port conditions for SNB+ */
  1529. }
  1530. reg = PIPECONF(cpu_transcoder);
  1531. val = I915_READ(reg);
  1532. if (val & PIPECONF_ENABLE)
  1533. return;
  1534. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1535. intel_wait_for_vblank(dev_priv->dev, pipe);
  1536. }
  1537. /**
  1538. * intel_disable_pipe - disable a pipe, asserting requirements
  1539. * @dev_priv: i915 private structure
  1540. * @pipe: pipe to disable
  1541. *
  1542. * Disable @pipe, making sure that various hardware specific requirements
  1543. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1544. *
  1545. * @pipe should be %PIPE_A or %PIPE_B.
  1546. *
  1547. * Will wait until the pipe has shut down before returning.
  1548. */
  1549. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1550. enum pipe pipe)
  1551. {
  1552. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1553. pipe);
  1554. int reg;
  1555. u32 val;
  1556. /*
  1557. * Make sure planes won't keep trying to pump pixels to us,
  1558. * or we might hang the display.
  1559. */
  1560. assert_planes_disabled(dev_priv, pipe);
  1561. assert_cursor_disabled(dev_priv, pipe);
  1562. assert_sprites_disabled(dev_priv, pipe);
  1563. /* Don't disable pipe A or pipe A PLLs if needed */
  1564. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1565. return;
  1566. reg = PIPECONF(cpu_transcoder);
  1567. val = I915_READ(reg);
  1568. if ((val & PIPECONF_ENABLE) == 0)
  1569. return;
  1570. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1571. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1572. }
  1573. /*
  1574. * Plane regs are double buffered, going from enabled->disabled needs a
  1575. * trigger in order to latch. The display address reg provides this.
  1576. */
  1577. void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
  1578. enum plane plane)
  1579. {
  1580. u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
  1581. I915_WRITE(reg, I915_READ(reg));
  1582. POSTING_READ(reg);
  1583. }
  1584. /**
  1585. * intel_enable_primary_plane - enable the primary plane on a given pipe
  1586. * @dev_priv: i915 private structure
  1587. * @plane: plane to enable
  1588. * @pipe: pipe being fed
  1589. *
  1590. * Enable @plane on @pipe, making sure that @pipe is running first.
  1591. */
  1592. static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
  1593. enum plane plane, enum pipe pipe)
  1594. {
  1595. struct intel_crtc *intel_crtc =
  1596. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  1597. int reg;
  1598. u32 val;
  1599. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1600. assert_pipe_enabled(dev_priv, pipe);
  1601. WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
  1602. intel_crtc->primary_enabled = true;
  1603. reg = DSPCNTR(plane);
  1604. val = I915_READ(reg);
  1605. if (val & DISPLAY_PLANE_ENABLE)
  1606. return;
  1607. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1608. intel_flush_primary_plane(dev_priv, plane);
  1609. intel_wait_for_vblank(dev_priv->dev, pipe);
  1610. }
  1611. /**
  1612. * intel_disable_primary_plane - disable the primary plane
  1613. * @dev_priv: i915 private structure
  1614. * @plane: plane to disable
  1615. * @pipe: pipe consuming the data
  1616. *
  1617. * Disable @plane; should be an independent operation.
  1618. */
  1619. static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
  1620. enum plane plane, enum pipe pipe)
  1621. {
  1622. struct intel_crtc *intel_crtc =
  1623. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  1624. int reg;
  1625. u32 val;
  1626. WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
  1627. intel_crtc->primary_enabled = false;
  1628. reg = DSPCNTR(plane);
  1629. val = I915_READ(reg);
  1630. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1631. return;
  1632. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1633. intel_flush_primary_plane(dev_priv, plane);
  1634. intel_wait_for_vblank(dev_priv->dev, pipe);
  1635. }
  1636. static bool need_vtd_wa(struct drm_device *dev)
  1637. {
  1638. #ifdef CONFIG_INTEL_IOMMU
  1639. if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1640. return true;
  1641. #endif
  1642. return false;
  1643. }
  1644. int
  1645. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1646. struct drm_i915_gem_object *obj,
  1647. struct intel_ring_buffer *pipelined)
  1648. {
  1649. struct drm_i915_private *dev_priv = dev->dev_private;
  1650. u32 alignment;
  1651. int ret;
  1652. switch (obj->tiling_mode) {
  1653. case I915_TILING_NONE:
  1654. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1655. alignment = 128 * 1024;
  1656. else if (INTEL_INFO(dev)->gen >= 4)
  1657. alignment = 4 * 1024;
  1658. else
  1659. alignment = 64 * 1024;
  1660. break;
  1661. case I915_TILING_X:
  1662. /* pin() will align the object as required by fence */
  1663. alignment = 0;
  1664. break;
  1665. case I915_TILING_Y:
  1666. /* Despite that we check this in framebuffer_init userspace can
  1667. * screw us over and change the tiling after the fact. Only
  1668. * pinned buffers can't change their tiling. */
  1669. DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1670. return -EINVAL;
  1671. default:
  1672. BUG();
  1673. }
  1674. /* Note that the w/a also requires 64 PTE of padding following the
  1675. * bo. We currently fill all unused PTE with the shadow page and so
  1676. * we should always have valid PTE following the scanout preventing
  1677. * the VT-d warning.
  1678. */
  1679. if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1680. alignment = 256 * 1024;
  1681. dev_priv->mm.interruptible = false;
  1682. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1683. if (ret)
  1684. goto err_interruptible;
  1685. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1686. * fence, whereas 965+ only requires a fence if using
  1687. * framebuffer compression. For simplicity, we always install
  1688. * a fence as the cost is not that onerous.
  1689. */
  1690. ret = i915_gem_object_get_fence(obj);
  1691. if (ret)
  1692. goto err_unpin;
  1693. i915_gem_object_pin_fence(obj);
  1694. dev_priv->mm.interruptible = true;
  1695. return 0;
  1696. err_unpin:
  1697. i915_gem_object_unpin_from_display_plane(obj);
  1698. err_interruptible:
  1699. dev_priv->mm.interruptible = true;
  1700. return ret;
  1701. }
  1702. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1703. {
  1704. i915_gem_object_unpin_fence(obj);
  1705. i915_gem_object_unpin_from_display_plane(obj);
  1706. }
  1707. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1708. * is assumed to be a power-of-two. */
  1709. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1710. unsigned int tiling_mode,
  1711. unsigned int cpp,
  1712. unsigned int pitch)
  1713. {
  1714. if (tiling_mode != I915_TILING_NONE) {
  1715. unsigned int tile_rows, tiles;
  1716. tile_rows = *y / 8;
  1717. *y %= 8;
  1718. tiles = *x / (512/cpp);
  1719. *x %= 512/cpp;
  1720. return tile_rows * pitch * 8 + tiles * 4096;
  1721. } else {
  1722. unsigned int offset;
  1723. offset = *y * pitch + *x * cpp;
  1724. *y = 0;
  1725. *x = (offset & 4095) / cpp;
  1726. return offset & -4096;
  1727. }
  1728. }
  1729. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1730. int x, int y)
  1731. {
  1732. struct drm_device *dev = crtc->dev;
  1733. struct drm_i915_private *dev_priv = dev->dev_private;
  1734. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1735. struct intel_framebuffer *intel_fb;
  1736. struct drm_i915_gem_object *obj;
  1737. int plane = intel_crtc->plane;
  1738. unsigned long linear_offset;
  1739. u32 dspcntr;
  1740. u32 reg;
  1741. switch (plane) {
  1742. case 0:
  1743. case 1:
  1744. break;
  1745. default:
  1746. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1747. return -EINVAL;
  1748. }
  1749. intel_fb = to_intel_framebuffer(fb);
  1750. obj = intel_fb->obj;
  1751. reg = DSPCNTR(plane);
  1752. dspcntr = I915_READ(reg);
  1753. /* Mask out pixel format bits in case we change it */
  1754. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1755. switch (fb->pixel_format) {
  1756. case DRM_FORMAT_C8:
  1757. dspcntr |= DISPPLANE_8BPP;
  1758. break;
  1759. case DRM_FORMAT_XRGB1555:
  1760. case DRM_FORMAT_ARGB1555:
  1761. dspcntr |= DISPPLANE_BGRX555;
  1762. break;
  1763. case DRM_FORMAT_RGB565:
  1764. dspcntr |= DISPPLANE_BGRX565;
  1765. break;
  1766. case DRM_FORMAT_XRGB8888:
  1767. case DRM_FORMAT_ARGB8888:
  1768. dspcntr |= DISPPLANE_BGRX888;
  1769. break;
  1770. case DRM_FORMAT_XBGR8888:
  1771. case DRM_FORMAT_ABGR8888:
  1772. dspcntr |= DISPPLANE_RGBX888;
  1773. break;
  1774. case DRM_FORMAT_XRGB2101010:
  1775. case DRM_FORMAT_ARGB2101010:
  1776. dspcntr |= DISPPLANE_BGRX101010;
  1777. break;
  1778. case DRM_FORMAT_XBGR2101010:
  1779. case DRM_FORMAT_ABGR2101010:
  1780. dspcntr |= DISPPLANE_RGBX101010;
  1781. break;
  1782. default:
  1783. BUG();
  1784. }
  1785. if (INTEL_INFO(dev)->gen >= 4) {
  1786. if (obj->tiling_mode != I915_TILING_NONE)
  1787. dspcntr |= DISPPLANE_TILED;
  1788. else
  1789. dspcntr &= ~DISPPLANE_TILED;
  1790. }
  1791. if (IS_G4X(dev))
  1792. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1793. I915_WRITE(reg, dspcntr);
  1794. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1795. if (INTEL_INFO(dev)->gen >= 4) {
  1796. intel_crtc->dspaddr_offset =
  1797. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1798. fb->bits_per_pixel / 8,
  1799. fb->pitches[0]);
  1800. linear_offset -= intel_crtc->dspaddr_offset;
  1801. } else {
  1802. intel_crtc->dspaddr_offset = linear_offset;
  1803. }
  1804. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1805. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1806. fb->pitches[0]);
  1807. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1808. if (INTEL_INFO(dev)->gen >= 4) {
  1809. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1810. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1811. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1812. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1813. } else
  1814. I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  1815. POSTING_READ(reg);
  1816. return 0;
  1817. }
  1818. static int ironlake_update_plane(struct drm_crtc *crtc,
  1819. struct drm_framebuffer *fb, int x, int y)
  1820. {
  1821. struct drm_device *dev = crtc->dev;
  1822. struct drm_i915_private *dev_priv = dev->dev_private;
  1823. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1824. struct intel_framebuffer *intel_fb;
  1825. struct drm_i915_gem_object *obj;
  1826. int plane = intel_crtc->plane;
  1827. unsigned long linear_offset;
  1828. u32 dspcntr;
  1829. u32 reg;
  1830. switch (plane) {
  1831. case 0:
  1832. case 1:
  1833. case 2:
  1834. break;
  1835. default:
  1836. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1837. return -EINVAL;
  1838. }
  1839. intel_fb = to_intel_framebuffer(fb);
  1840. obj = intel_fb->obj;
  1841. reg = DSPCNTR(plane);
  1842. dspcntr = I915_READ(reg);
  1843. /* Mask out pixel format bits in case we change it */
  1844. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1845. switch (fb->pixel_format) {
  1846. case DRM_FORMAT_C8:
  1847. dspcntr |= DISPPLANE_8BPP;
  1848. break;
  1849. case DRM_FORMAT_RGB565:
  1850. dspcntr |= DISPPLANE_BGRX565;
  1851. break;
  1852. case DRM_FORMAT_XRGB8888:
  1853. case DRM_FORMAT_ARGB8888:
  1854. dspcntr |= DISPPLANE_BGRX888;
  1855. break;
  1856. case DRM_FORMAT_XBGR8888:
  1857. case DRM_FORMAT_ABGR8888:
  1858. dspcntr |= DISPPLANE_RGBX888;
  1859. break;
  1860. case DRM_FORMAT_XRGB2101010:
  1861. case DRM_FORMAT_ARGB2101010:
  1862. dspcntr |= DISPPLANE_BGRX101010;
  1863. break;
  1864. case DRM_FORMAT_XBGR2101010:
  1865. case DRM_FORMAT_ABGR2101010:
  1866. dspcntr |= DISPPLANE_RGBX101010;
  1867. break;
  1868. default:
  1869. BUG();
  1870. }
  1871. if (obj->tiling_mode != I915_TILING_NONE)
  1872. dspcntr |= DISPPLANE_TILED;
  1873. else
  1874. dspcntr &= ~DISPPLANE_TILED;
  1875. if (IS_HASWELL(dev))
  1876. dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
  1877. else
  1878. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1879. I915_WRITE(reg, dspcntr);
  1880. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1881. intel_crtc->dspaddr_offset =
  1882. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1883. fb->bits_per_pixel / 8,
  1884. fb->pitches[0]);
  1885. linear_offset -= intel_crtc->dspaddr_offset;
  1886. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1887. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1888. fb->pitches[0]);
  1889. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1890. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1891. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1892. if (IS_HASWELL(dev)) {
  1893. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  1894. } else {
  1895. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1896. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1897. }
  1898. POSTING_READ(reg);
  1899. return 0;
  1900. }
  1901. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1902. static int
  1903. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1904. int x, int y, enum mode_set_atomic state)
  1905. {
  1906. struct drm_device *dev = crtc->dev;
  1907. struct drm_i915_private *dev_priv = dev->dev_private;
  1908. if (dev_priv->display.disable_fbc)
  1909. dev_priv->display.disable_fbc(dev);
  1910. intel_increase_pllclock(crtc);
  1911. return dev_priv->display.update_plane(crtc, fb, x, y);
  1912. }
  1913. void intel_display_handle_reset(struct drm_device *dev)
  1914. {
  1915. struct drm_i915_private *dev_priv = dev->dev_private;
  1916. struct drm_crtc *crtc;
  1917. /*
  1918. * Flips in the rings have been nuked by the reset,
  1919. * so complete all pending flips so that user space
  1920. * will get its events and not get stuck.
  1921. *
  1922. * Also update the base address of all primary
  1923. * planes to the the last fb to make sure we're
  1924. * showing the correct fb after a reset.
  1925. *
  1926. * Need to make two loops over the crtcs so that we
  1927. * don't try to grab a crtc mutex before the
  1928. * pending_flip_queue really got woken up.
  1929. */
  1930. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1931. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1932. enum plane plane = intel_crtc->plane;
  1933. intel_prepare_page_flip(dev, plane);
  1934. intel_finish_page_flip_plane(dev, plane);
  1935. }
  1936. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1937. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1938. mutex_lock(&crtc->mutex);
  1939. if (intel_crtc->active)
  1940. dev_priv->display.update_plane(crtc, crtc->fb,
  1941. crtc->x, crtc->y);
  1942. mutex_unlock(&crtc->mutex);
  1943. }
  1944. }
  1945. static int
  1946. intel_finish_fb(struct drm_framebuffer *old_fb)
  1947. {
  1948. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1949. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1950. bool was_interruptible = dev_priv->mm.interruptible;
  1951. int ret;
  1952. /* Big Hammer, we also need to ensure that any pending
  1953. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1954. * current scanout is retired before unpinning the old
  1955. * framebuffer.
  1956. *
  1957. * This should only fail upon a hung GPU, in which case we
  1958. * can safely continue.
  1959. */
  1960. dev_priv->mm.interruptible = false;
  1961. ret = i915_gem_object_finish_gpu(obj);
  1962. dev_priv->mm.interruptible = was_interruptible;
  1963. return ret;
  1964. }
  1965. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  1966. {
  1967. struct drm_device *dev = crtc->dev;
  1968. struct drm_i915_master_private *master_priv;
  1969. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1970. if (!dev->primary->master)
  1971. return;
  1972. master_priv = dev->primary->master->driver_priv;
  1973. if (!master_priv->sarea_priv)
  1974. return;
  1975. switch (intel_crtc->pipe) {
  1976. case 0:
  1977. master_priv->sarea_priv->pipeA_x = x;
  1978. master_priv->sarea_priv->pipeA_y = y;
  1979. break;
  1980. case 1:
  1981. master_priv->sarea_priv->pipeB_x = x;
  1982. master_priv->sarea_priv->pipeB_y = y;
  1983. break;
  1984. default:
  1985. break;
  1986. }
  1987. }
  1988. static int
  1989. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1990. struct drm_framebuffer *fb)
  1991. {
  1992. struct drm_device *dev = crtc->dev;
  1993. struct drm_i915_private *dev_priv = dev->dev_private;
  1994. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1995. struct drm_framebuffer *old_fb;
  1996. int ret;
  1997. /* no fb bound */
  1998. if (!fb) {
  1999. DRM_ERROR("No FB bound\n");
  2000. return 0;
  2001. }
  2002. if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  2003. DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  2004. plane_name(intel_crtc->plane),
  2005. INTEL_INFO(dev)->num_pipes);
  2006. return -EINVAL;
  2007. }
  2008. mutex_lock(&dev->struct_mutex);
  2009. ret = intel_pin_and_fence_fb_obj(dev,
  2010. to_intel_framebuffer(fb)->obj,
  2011. NULL);
  2012. if (ret != 0) {
  2013. mutex_unlock(&dev->struct_mutex);
  2014. DRM_ERROR("pin & fence failed\n");
  2015. return ret;
  2016. }
  2017. /*
  2018. * Update pipe size and adjust fitter if needed: the reason for this is
  2019. * that in compute_mode_changes we check the native mode (not the pfit
  2020. * mode) to see if we can flip rather than do a full mode set. In the
  2021. * fastboot case, we'll flip, but if we don't update the pipesrc and
  2022. * pfit state, we'll end up with a big fb scanned out into the wrong
  2023. * sized surface.
  2024. *
  2025. * To fix this properly, we need to hoist the checks up into
  2026. * compute_mode_changes (or above), check the actual pfit state and
  2027. * whether the platform allows pfit disable with pipe active, and only
  2028. * then update the pipesrc and pfit state, even on the flip path.
  2029. */
  2030. if (i915_fastboot) {
  2031. const struct drm_display_mode *adjusted_mode =
  2032. &intel_crtc->config.adjusted_mode;
  2033. I915_WRITE(PIPESRC(intel_crtc->pipe),
  2034. ((adjusted_mode->crtc_hdisplay - 1) << 16) |
  2035. (adjusted_mode->crtc_vdisplay - 1));
  2036. if (!intel_crtc->config.pch_pfit.enabled &&
  2037. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2038. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2039. I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
  2040. I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
  2041. I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
  2042. }
  2043. }
  2044. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2045. if (ret) {
  2046. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2047. mutex_unlock(&dev->struct_mutex);
  2048. DRM_ERROR("failed to update base address\n");
  2049. return ret;
  2050. }
  2051. old_fb = crtc->fb;
  2052. crtc->fb = fb;
  2053. crtc->x = x;
  2054. crtc->y = y;
  2055. if (old_fb) {
  2056. if (intel_crtc->active && old_fb != fb)
  2057. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2058. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2059. }
  2060. intel_update_fbc(dev);
  2061. intel_edp_psr_update(dev);
  2062. mutex_unlock(&dev->struct_mutex);
  2063. intel_crtc_update_sarea_pos(crtc, x, y);
  2064. return 0;
  2065. }
  2066. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2067. {
  2068. struct drm_device *dev = crtc->dev;
  2069. struct drm_i915_private *dev_priv = dev->dev_private;
  2070. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2071. int pipe = intel_crtc->pipe;
  2072. u32 reg, temp;
  2073. /* enable normal train */
  2074. reg = FDI_TX_CTL(pipe);
  2075. temp = I915_READ(reg);
  2076. if (IS_IVYBRIDGE(dev)) {
  2077. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2078. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2079. } else {
  2080. temp &= ~FDI_LINK_TRAIN_NONE;
  2081. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2082. }
  2083. I915_WRITE(reg, temp);
  2084. reg = FDI_RX_CTL(pipe);
  2085. temp = I915_READ(reg);
  2086. if (HAS_PCH_CPT(dev)) {
  2087. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2088. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2089. } else {
  2090. temp &= ~FDI_LINK_TRAIN_NONE;
  2091. temp |= FDI_LINK_TRAIN_NONE;
  2092. }
  2093. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2094. /* wait one idle pattern time */
  2095. POSTING_READ(reg);
  2096. udelay(1000);
  2097. /* IVB wants error correction enabled */
  2098. if (IS_IVYBRIDGE(dev))
  2099. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2100. FDI_FE_ERRC_ENABLE);
  2101. }
  2102. static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
  2103. {
  2104. return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
  2105. }
  2106. static void ivb_modeset_global_resources(struct drm_device *dev)
  2107. {
  2108. struct drm_i915_private *dev_priv = dev->dev_private;
  2109. struct intel_crtc *pipe_B_crtc =
  2110. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2111. struct intel_crtc *pipe_C_crtc =
  2112. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2113. uint32_t temp;
  2114. /*
  2115. * When everything is off disable fdi C so that we could enable fdi B
  2116. * with all lanes. Note that we don't care about enabled pipes without
  2117. * an enabled pch encoder.
  2118. */
  2119. if (!pipe_has_enabled_pch(pipe_B_crtc) &&
  2120. !pipe_has_enabled_pch(pipe_C_crtc)) {
  2121. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2122. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2123. temp = I915_READ(SOUTH_CHICKEN1);
  2124. temp &= ~FDI_BC_BIFURCATION_SELECT;
  2125. DRM_DEBUG_KMS("disabling fdi C rx\n");
  2126. I915_WRITE(SOUTH_CHICKEN1, temp);
  2127. }
  2128. }
  2129. /* The FDI link training functions for ILK/Ibexpeak. */
  2130. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2131. {
  2132. struct drm_device *dev = crtc->dev;
  2133. struct drm_i915_private *dev_priv = dev->dev_private;
  2134. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2135. int pipe = intel_crtc->pipe;
  2136. int plane = intel_crtc->plane;
  2137. u32 reg, temp, tries;
  2138. /* FDI needs bits from pipe & plane first */
  2139. assert_pipe_enabled(dev_priv, pipe);
  2140. assert_plane_enabled(dev_priv, plane);
  2141. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2142. for train result */
  2143. reg = FDI_RX_IMR(pipe);
  2144. temp = I915_READ(reg);
  2145. temp &= ~FDI_RX_SYMBOL_LOCK;
  2146. temp &= ~FDI_RX_BIT_LOCK;
  2147. I915_WRITE(reg, temp);
  2148. I915_READ(reg);
  2149. udelay(150);
  2150. /* enable CPU FDI TX and PCH FDI RX */
  2151. reg = FDI_TX_CTL(pipe);
  2152. temp = I915_READ(reg);
  2153. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2154. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2155. temp &= ~FDI_LINK_TRAIN_NONE;
  2156. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2157. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2158. reg = FDI_RX_CTL(pipe);
  2159. temp = I915_READ(reg);
  2160. temp &= ~FDI_LINK_TRAIN_NONE;
  2161. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2162. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2163. POSTING_READ(reg);
  2164. udelay(150);
  2165. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2166. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2167. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2168. FDI_RX_PHASE_SYNC_POINTER_EN);
  2169. reg = FDI_RX_IIR(pipe);
  2170. for (tries = 0; tries < 5; tries++) {
  2171. temp = I915_READ(reg);
  2172. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2173. if ((temp & FDI_RX_BIT_LOCK)) {
  2174. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2175. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2176. break;
  2177. }
  2178. }
  2179. if (tries == 5)
  2180. DRM_ERROR("FDI train 1 fail!\n");
  2181. /* Train 2 */
  2182. reg = FDI_TX_CTL(pipe);
  2183. temp = I915_READ(reg);
  2184. temp &= ~FDI_LINK_TRAIN_NONE;
  2185. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2186. I915_WRITE(reg, temp);
  2187. reg = FDI_RX_CTL(pipe);
  2188. temp = I915_READ(reg);
  2189. temp &= ~FDI_LINK_TRAIN_NONE;
  2190. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2191. I915_WRITE(reg, temp);
  2192. POSTING_READ(reg);
  2193. udelay(150);
  2194. reg = FDI_RX_IIR(pipe);
  2195. for (tries = 0; tries < 5; tries++) {
  2196. temp = I915_READ(reg);
  2197. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2198. if (temp & FDI_RX_SYMBOL_LOCK) {
  2199. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2200. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2201. break;
  2202. }
  2203. }
  2204. if (tries == 5)
  2205. DRM_ERROR("FDI train 2 fail!\n");
  2206. DRM_DEBUG_KMS("FDI train done\n");
  2207. }
  2208. static const int snb_b_fdi_train_param[] = {
  2209. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2210. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2211. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2212. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2213. };
  2214. /* The FDI link training functions for SNB/Cougarpoint. */
  2215. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2216. {
  2217. struct drm_device *dev = crtc->dev;
  2218. struct drm_i915_private *dev_priv = dev->dev_private;
  2219. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2220. int pipe = intel_crtc->pipe;
  2221. u32 reg, temp, i, retry;
  2222. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2223. for train result */
  2224. reg = FDI_RX_IMR(pipe);
  2225. temp = I915_READ(reg);
  2226. temp &= ~FDI_RX_SYMBOL_LOCK;
  2227. temp &= ~FDI_RX_BIT_LOCK;
  2228. I915_WRITE(reg, temp);
  2229. POSTING_READ(reg);
  2230. udelay(150);
  2231. /* enable CPU FDI TX and PCH FDI RX */
  2232. reg = FDI_TX_CTL(pipe);
  2233. temp = I915_READ(reg);
  2234. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2235. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2236. temp &= ~FDI_LINK_TRAIN_NONE;
  2237. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2238. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2239. /* SNB-B */
  2240. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2241. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2242. I915_WRITE(FDI_RX_MISC(pipe),
  2243. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2244. reg = FDI_RX_CTL(pipe);
  2245. temp = I915_READ(reg);
  2246. if (HAS_PCH_CPT(dev)) {
  2247. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2248. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2249. } else {
  2250. temp &= ~FDI_LINK_TRAIN_NONE;
  2251. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2252. }
  2253. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2254. POSTING_READ(reg);
  2255. udelay(150);
  2256. for (i = 0; i < 4; i++) {
  2257. reg = FDI_TX_CTL(pipe);
  2258. temp = I915_READ(reg);
  2259. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2260. temp |= snb_b_fdi_train_param[i];
  2261. I915_WRITE(reg, temp);
  2262. POSTING_READ(reg);
  2263. udelay(500);
  2264. for (retry = 0; retry < 5; retry++) {
  2265. reg = FDI_RX_IIR(pipe);
  2266. temp = I915_READ(reg);
  2267. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2268. if (temp & FDI_RX_BIT_LOCK) {
  2269. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2270. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2271. break;
  2272. }
  2273. udelay(50);
  2274. }
  2275. if (retry < 5)
  2276. break;
  2277. }
  2278. if (i == 4)
  2279. DRM_ERROR("FDI train 1 fail!\n");
  2280. /* Train 2 */
  2281. reg = FDI_TX_CTL(pipe);
  2282. temp = I915_READ(reg);
  2283. temp &= ~FDI_LINK_TRAIN_NONE;
  2284. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2285. if (IS_GEN6(dev)) {
  2286. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2287. /* SNB-B */
  2288. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2289. }
  2290. I915_WRITE(reg, temp);
  2291. reg = FDI_RX_CTL(pipe);
  2292. temp = I915_READ(reg);
  2293. if (HAS_PCH_CPT(dev)) {
  2294. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2295. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2296. } else {
  2297. temp &= ~FDI_LINK_TRAIN_NONE;
  2298. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2299. }
  2300. I915_WRITE(reg, temp);
  2301. POSTING_READ(reg);
  2302. udelay(150);
  2303. for (i = 0; i < 4; i++) {
  2304. reg = FDI_TX_CTL(pipe);
  2305. temp = I915_READ(reg);
  2306. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2307. temp |= snb_b_fdi_train_param[i];
  2308. I915_WRITE(reg, temp);
  2309. POSTING_READ(reg);
  2310. udelay(500);
  2311. for (retry = 0; retry < 5; retry++) {
  2312. reg = FDI_RX_IIR(pipe);
  2313. temp = I915_READ(reg);
  2314. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2315. if (temp & FDI_RX_SYMBOL_LOCK) {
  2316. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2317. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2318. break;
  2319. }
  2320. udelay(50);
  2321. }
  2322. if (retry < 5)
  2323. break;
  2324. }
  2325. if (i == 4)
  2326. DRM_ERROR("FDI train 2 fail!\n");
  2327. DRM_DEBUG_KMS("FDI train done.\n");
  2328. }
  2329. /* Manual link training for Ivy Bridge A0 parts */
  2330. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2331. {
  2332. struct drm_device *dev = crtc->dev;
  2333. struct drm_i915_private *dev_priv = dev->dev_private;
  2334. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2335. int pipe = intel_crtc->pipe;
  2336. u32 reg, temp, i, j;
  2337. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2338. for train result */
  2339. reg = FDI_RX_IMR(pipe);
  2340. temp = I915_READ(reg);
  2341. temp &= ~FDI_RX_SYMBOL_LOCK;
  2342. temp &= ~FDI_RX_BIT_LOCK;
  2343. I915_WRITE(reg, temp);
  2344. POSTING_READ(reg);
  2345. udelay(150);
  2346. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2347. I915_READ(FDI_RX_IIR(pipe)));
  2348. /* Try each vswing and preemphasis setting twice before moving on */
  2349. for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  2350. /* disable first in case we need to retry */
  2351. reg = FDI_TX_CTL(pipe);
  2352. temp = I915_READ(reg);
  2353. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2354. temp &= ~FDI_TX_ENABLE;
  2355. I915_WRITE(reg, temp);
  2356. reg = FDI_RX_CTL(pipe);
  2357. temp = I915_READ(reg);
  2358. temp &= ~FDI_LINK_TRAIN_AUTO;
  2359. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2360. temp &= ~FDI_RX_ENABLE;
  2361. I915_WRITE(reg, temp);
  2362. /* enable CPU FDI TX and PCH FDI RX */
  2363. reg = FDI_TX_CTL(pipe);
  2364. temp = I915_READ(reg);
  2365. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2366. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2367. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2368. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2369. temp |= snb_b_fdi_train_param[j/2];
  2370. temp |= FDI_COMPOSITE_SYNC;
  2371. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2372. I915_WRITE(FDI_RX_MISC(pipe),
  2373. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2374. reg = FDI_RX_CTL(pipe);
  2375. temp = I915_READ(reg);
  2376. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2377. temp |= FDI_COMPOSITE_SYNC;
  2378. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2379. POSTING_READ(reg);
  2380. udelay(1); /* should be 0.5us */
  2381. for (i = 0; i < 4; i++) {
  2382. reg = FDI_RX_IIR(pipe);
  2383. temp = I915_READ(reg);
  2384. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2385. if (temp & FDI_RX_BIT_LOCK ||
  2386. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2387. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2388. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
  2389. i);
  2390. break;
  2391. }
  2392. udelay(1); /* should be 0.5us */
  2393. }
  2394. if (i == 4) {
  2395. DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
  2396. continue;
  2397. }
  2398. /* Train 2 */
  2399. reg = FDI_TX_CTL(pipe);
  2400. temp = I915_READ(reg);
  2401. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2402. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2403. I915_WRITE(reg, temp);
  2404. reg = FDI_RX_CTL(pipe);
  2405. temp = I915_READ(reg);
  2406. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2407. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2408. I915_WRITE(reg, temp);
  2409. POSTING_READ(reg);
  2410. udelay(2); /* should be 1.5us */
  2411. for (i = 0; i < 4; i++) {
  2412. reg = FDI_RX_IIR(pipe);
  2413. temp = I915_READ(reg);
  2414. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2415. if (temp & FDI_RX_SYMBOL_LOCK ||
  2416. (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
  2417. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2418. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
  2419. i);
  2420. goto train_done;
  2421. }
  2422. udelay(2); /* should be 1.5us */
  2423. }
  2424. if (i == 4)
  2425. DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
  2426. }
  2427. train_done:
  2428. DRM_DEBUG_KMS("FDI train done.\n");
  2429. }
  2430. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2431. {
  2432. struct drm_device *dev = intel_crtc->base.dev;
  2433. struct drm_i915_private *dev_priv = dev->dev_private;
  2434. int pipe = intel_crtc->pipe;
  2435. u32 reg, temp;
  2436. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2437. reg = FDI_RX_CTL(pipe);
  2438. temp = I915_READ(reg);
  2439. temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  2440. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2441. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2442. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2443. POSTING_READ(reg);
  2444. udelay(200);
  2445. /* Switch from Rawclk to PCDclk */
  2446. temp = I915_READ(reg);
  2447. I915_WRITE(reg, temp | FDI_PCDCLK);
  2448. POSTING_READ(reg);
  2449. udelay(200);
  2450. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2451. reg = FDI_TX_CTL(pipe);
  2452. temp = I915_READ(reg);
  2453. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2454. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2455. POSTING_READ(reg);
  2456. udelay(100);
  2457. }
  2458. }
  2459. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2460. {
  2461. struct drm_device *dev = intel_crtc->base.dev;
  2462. struct drm_i915_private *dev_priv = dev->dev_private;
  2463. int pipe = intel_crtc->pipe;
  2464. u32 reg, temp;
  2465. /* Switch from PCDclk to Rawclk */
  2466. reg = FDI_RX_CTL(pipe);
  2467. temp = I915_READ(reg);
  2468. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2469. /* Disable CPU FDI TX PLL */
  2470. reg = FDI_TX_CTL(pipe);
  2471. temp = I915_READ(reg);
  2472. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2473. POSTING_READ(reg);
  2474. udelay(100);
  2475. reg = FDI_RX_CTL(pipe);
  2476. temp = I915_READ(reg);
  2477. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2478. /* Wait for the clocks to turn off. */
  2479. POSTING_READ(reg);
  2480. udelay(100);
  2481. }
  2482. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2483. {
  2484. struct drm_device *dev = crtc->dev;
  2485. struct drm_i915_private *dev_priv = dev->dev_private;
  2486. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2487. int pipe = intel_crtc->pipe;
  2488. u32 reg, temp;
  2489. /* disable CPU FDI tx and PCH FDI rx */
  2490. reg = FDI_TX_CTL(pipe);
  2491. temp = I915_READ(reg);
  2492. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2493. POSTING_READ(reg);
  2494. reg = FDI_RX_CTL(pipe);
  2495. temp = I915_READ(reg);
  2496. temp &= ~(0x7 << 16);
  2497. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2498. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2499. POSTING_READ(reg);
  2500. udelay(100);
  2501. /* Ironlake workaround, disable clock pointer after downing FDI */
  2502. if (HAS_PCH_IBX(dev)) {
  2503. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2504. }
  2505. /* still set train pattern 1 */
  2506. reg = FDI_TX_CTL(pipe);
  2507. temp = I915_READ(reg);
  2508. temp &= ~FDI_LINK_TRAIN_NONE;
  2509. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2510. I915_WRITE(reg, temp);
  2511. reg = FDI_RX_CTL(pipe);
  2512. temp = I915_READ(reg);
  2513. if (HAS_PCH_CPT(dev)) {
  2514. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2515. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2516. } else {
  2517. temp &= ~FDI_LINK_TRAIN_NONE;
  2518. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2519. }
  2520. /* BPC in FDI rx is consistent with that in PIPECONF */
  2521. temp &= ~(0x07 << 16);
  2522. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2523. I915_WRITE(reg, temp);
  2524. POSTING_READ(reg);
  2525. udelay(100);
  2526. }
  2527. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2528. {
  2529. struct drm_device *dev = crtc->dev;
  2530. struct drm_i915_private *dev_priv = dev->dev_private;
  2531. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2532. unsigned long flags;
  2533. bool pending;
  2534. if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  2535. intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  2536. return false;
  2537. spin_lock_irqsave(&dev->event_lock, flags);
  2538. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2539. spin_unlock_irqrestore(&dev->event_lock, flags);
  2540. return pending;
  2541. }
  2542. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2543. {
  2544. struct drm_device *dev = crtc->dev;
  2545. struct drm_i915_private *dev_priv = dev->dev_private;
  2546. if (crtc->fb == NULL)
  2547. return;
  2548. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2549. wait_event(dev_priv->pending_flip_queue,
  2550. !intel_crtc_has_pending_flip(crtc));
  2551. mutex_lock(&dev->struct_mutex);
  2552. intel_finish_fb(crtc->fb);
  2553. mutex_unlock(&dev->struct_mutex);
  2554. }
  2555. /* Program iCLKIP clock to the desired frequency */
  2556. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2557. {
  2558. struct drm_device *dev = crtc->dev;
  2559. struct drm_i915_private *dev_priv = dev->dev_private;
  2560. int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
  2561. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2562. u32 temp;
  2563. mutex_lock(&dev_priv->dpio_lock);
  2564. /* It is necessary to ungate the pixclk gate prior to programming
  2565. * the divisors, and gate it back when it is done.
  2566. */
  2567. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2568. /* Disable SSCCTL */
  2569. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2570. intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2571. SBI_SSCCTL_DISABLE,
  2572. SBI_ICLK);
  2573. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2574. if (clock == 20000) {
  2575. auxdiv = 1;
  2576. divsel = 0x41;
  2577. phaseinc = 0x20;
  2578. } else {
  2579. /* The iCLK virtual clock root frequency is in MHz,
  2580. * but the adjusted_mode->crtc_clock in in KHz. To get the
  2581. * divisors, it is necessary to divide one by another, so we
  2582. * convert the virtual clock precision to KHz here for higher
  2583. * precision.
  2584. */
  2585. u32 iclk_virtual_root_freq = 172800 * 1000;
  2586. u32 iclk_pi_range = 64;
  2587. u32 desired_divisor, msb_divisor_value, pi_value;
  2588. desired_divisor = (iclk_virtual_root_freq / clock);
  2589. msb_divisor_value = desired_divisor / iclk_pi_range;
  2590. pi_value = desired_divisor % iclk_pi_range;
  2591. auxdiv = 0;
  2592. divsel = msb_divisor_value - 2;
  2593. phaseinc = pi_value;
  2594. }
  2595. /* This should not happen with any sane values */
  2596. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2597. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2598. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2599. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2600. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2601. clock,
  2602. auxdiv,
  2603. divsel,
  2604. phasedir,
  2605. phaseinc);
  2606. /* Program SSCDIVINTPHASE6 */
  2607. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2608. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2609. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2610. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2611. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2612. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2613. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2614. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2615. /* Program SSCAUXDIV */
  2616. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2617. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2618. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2619. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2620. /* Enable modulator and associated divider */
  2621. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2622. temp &= ~SBI_SSCCTL_DISABLE;
  2623. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2624. /* Wait for initialization time */
  2625. udelay(24);
  2626. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2627. mutex_unlock(&dev_priv->dpio_lock);
  2628. }
  2629. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  2630. enum pipe pch_transcoder)
  2631. {
  2632. struct drm_device *dev = crtc->base.dev;
  2633. struct drm_i915_private *dev_priv = dev->dev_private;
  2634. enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
  2635. I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  2636. I915_READ(HTOTAL(cpu_transcoder)));
  2637. I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  2638. I915_READ(HBLANK(cpu_transcoder)));
  2639. I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  2640. I915_READ(HSYNC(cpu_transcoder)));
  2641. I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  2642. I915_READ(VTOTAL(cpu_transcoder)));
  2643. I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  2644. I915_READ(VBLANK(cpu_transcoder)));
  2645. I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  2646. I915_READ(VSYNC(cpu_transcoder)));
  2647. I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  2648. I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2649. }
  2650. /*
  2651. * Enable PCH resources required for PCH ports:
  2652. * - PCH PLLs
  2653. * - FDI training & RX/TX
  2654. * - update transcoder timings
  2655. * - DP transcoding bits
  2656. * - transcoder
  2657. */
  2658. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2659. {
  2660. struct drm_device *dev = crtc->dev;
  2661. struct drm_i915_private *dev_priv = dev->dev_private;
  2662. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2663. int pipe = intel_crtc->pipe;
  2664. u32 reg, temp;
  2665. assert_pch_transcoder_disabled(dev_priv, pipe);
  2666. /* Write the TU size bits before fdi link training, so that error
  2667. * detection works. */
  2668. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2669. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2670. /* For PCH output, training FDI link */
  2671. dev_priv->display.fdi_link_train(crtc);
  2672. /* We need to program the right clock selection before writing the pixel
  2673. * mutliplier into the DPLL. */
  2674. if (HAS_PCH_CPT(dev)) {
  2675. u32 sel;
  2676. temp = I915_READ(PCH_DPLL_SEL);
  2677. temp |= TRANS_DPLL_ENABLE(pipe);
  2678. sel = TRANS_DPLLB_SEL(pipe);
  2679. if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
  2680. temp |= sel;
  2681. else
  2682. temp &= ~sel;
  2683. I915_WRITE(PCH_DPLL_SEL, temp);
  2684. }
  2685. /* XXX: pch pll's can be enabled any time before we enable the PCH
  2686. * transcoder, and we actually should do this to not upset any PCH
  2687. * transcoder that already use the clock when we share it.
  2688. *
  2689. * Note that enable_shared_dpll tries to do the right thing, but
  2690. * get_shared_dpll unconditionally resets the pll - we need that to have
  2691. * the right LVDS enable sequence. */
  2692. ironlake_enable_shared_dpll(intel_crtc);
  2693. /* set transcoder timing, panel must allow it */
  2694. assert_panel_unlocked(dev_priv, pipe);
  2695. ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  2696. intel_fdi_normal_train(crtc);
  2697. /* For PCH DP, enable TRANS_DP_CTL */
  2698. if (HAS_PCH_CPT(dev) &&
  2699. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2700. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2701. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  2702. reg = TRANS_DP_CTL(pipe);
  2703. temp = I915_READ(reg);
  2704. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2705. TRANS_DP_SYNC_MASK |
  2706. TRANS_DP_BPC_MASK);
  2707. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2708. TRANS_DP_ENH_FRAMING);
  2709. temp |= bpc << 9; /* same format but at 11:9 */
  2710. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2711. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2712. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2713. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2714. switch (intel_trans_dp_port_sel(crtc)) {
  2715. case PCH_DP_B:
  2716. temp |= TRANS_DP_PORT_SEL_B;
  2717. break;
  2718. case PCH_DP_C:
  2719. temp |= TRANS_DP_PORT_SEL_C;
  2720. break;
  2721. case PCH_DP_D:
  2722. temp |= TRANS_DP_PORT_SEL_D;
  2723. break;
  2724. default:
  2725. BUG();
  2726. }
  2727. I915_WRITE(reg, temp);
  2728. }
  2729. ironlake_enable_pch_transcoder(dev_priv, pipe);
  2730. }
  2731. static void lpt_pch_enable(struct drm_crtc *crtc)
  2732. {
  2733. struct drm_device *dev = crtc->dev;
  2734. struct drm_i915_private *dev_priv = dev->dev_private;
  2735. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2736. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  2737. assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  2738. lpt_program_iclkip(crtc);
  2739. /* Set transcoder timing. */
  2740. ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  2741. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  2742. }
  2743. static void intel_put_shared_dpll(struct intel_crtc *crtc)
  2744. {
  2745. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2746. if (pll == NULL)
  2747. return;
  2748. if (pll->refcount == 0) {
  2749. WARN(1, "bad %s refcount\n", pll->name);
  2750. return;
  2751. }
  2752. if (--pll->refcount == 0) {
  2753. WARN_ON(pll->on);
  2754. WARN_ON(pll->active);
  2755. }
  2756. crtc->config.shared_dpll = DPLL_ID_PRIVATE;
  2757. }
  2758. static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
  2759. {
  2760. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2761. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2762. enum intel_dpll_id i;
  2763. if (pll) {
  2764. DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
  2765. crtc->base.base.id, pll->name);
  2766. intel_put_shared_dpll(crtc);
  2767. }
  2768. if (HAS_PCH_IBX(dev_priv->dev)) {
  2769. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2770. i = (enum intel_dpll_id) crtc->pipe;
  2771. pll = &dev_priv->shared_dplls[i];
  2772. DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  2773. crtc->base.base.id, pll->name);
  2774. goto found;
  2775. }
  2776. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2777. pll = &dev_priv->shared_dplls[i];
  2778. /* Only want to check enabled timings first */
  2779. if (pll->refcount == 0)
  2780. continue;
  2781. if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
  2782. sizeof(pll->hw_state)) == 0) {
  2783. DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
  2784. crtc->base.base.id,
  2785. pll->name, pll->refcount, pll->active);
  2786. goto found;
  2787. }
  2788. }
  2789. /* Ok no matching timings, maybe there's a free one? */
  2790. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2791. pll = &dev_priv->shared_dplls[i];
  2792. if (pll->refcount == 0) {
  2793. DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  2794. crtc->base.base.id, pll->name);
  2795. goto found;
  2796. }
  2797. }
  2798. return NULL;
  2799. found:
  2800. crtc->config.shared_dpll = i;
  2801. DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
  2802. pipe_name(crtc->pipe));
  2803. if (pll->active == 0) {
  2804. memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
  2805. sizeof(pll->hw_state));
  2806. DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
  2807. WARN_ON(pll->on);
  2808. assert_shared_dpll_disabled(dev_priv, pll);
  2809. pll->mode_set(dev_priv, pll);
  2810. }
  2811. pll->refcount++;
  2812. return pll;
  2813. }
  2814. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  2815. {
  2816. struct drm_i915_private *dev_priv = dev->dev_private;
  2817. int dslreg = PIPEDSL(pipe);
  2818. u32 temp;
  2819. temp = I915_READ(dslreg);
  2820. udelay(500);
  2821. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2822. if (wait_for(I915_READ(dslreg) != temp, 5))
  2823. DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  2824. }
  2825. }
  2826. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  2827. {
  2828. struct drm_device *dev = crtc->base.dev;
  2829. struct drm_i915_private *dev_priv = dev->dev_private;
  2830. int pipe = crtc->pipe;
  2831. if (crtc->config.pch_pfit.enabled) {
  2832. /* Force use of hard-coded filter coefficients
  2833. * as some pre-programmed values are broken,
  2834. * e.g. x201.
  2835. */
  2836. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  2837. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2838. PF_PIPE_SEL_IVB(pipe));
  2839. else
  2840. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2841. I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
  2842. I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
  2843. }
  2844. }
  2845. static void intel_enable_planes(struct drm_crtc *crtc)
  2846. {
  2847. struct drm_device *dev = crtc->dev;
  2848. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2849. struct intel_plane *intel_plane;
  2850. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2851. if (intel_plane->pipe == pipe)
  2852. intel_plane_restore(&intel_plane->base);
  2853. }
  2854. static void intel_disable_planes(struct drm_crtc *crtc)
  2855. {
  2856. struct drm_device *dev = crtc->dev;
  2857. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2858. struct intel_plane *intel_plane;
  2859. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2860. if (intel_plane->pipe == pipe)
  2861. intel_plane_disable(&intel_plane->base);
  2862. }
  2863. void hsw_enable_ips(struct intel_crtc *crtc)
  2864. {
  2865. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2866. if (!crtc->config.ips_enabled)
  2867. return;
  2868. /* We can only enable IPS after we enable a plane and wait for a vblank.
  2869. * We guarantee that the plane is enabled by calling intel_enable_ips
  2870. * only after intel_enable_plane. And intel_enable_plane already waits
  2871. * for a vblank, so all we need to do here is to enable the IPS bit. */
  2872. assert_plane_enabled(dev_priv, crtc->plane);
  2873. I915_WRITE(IPS_CTL, IPS_ENABLE);
  2874. /* The bit only becomes 1 in the next vblank, so this wait here is
  2875. * essentially intel_wait_for_vblank. If we don't have this and don't
  2876. * wait for vblanks until the end of crtc_enable, then the HW state
  2877. * readout code will complain that the expected IPS_CTL value is not the
  2878. * one we read. */
  2879. if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
  2880. DRM_ERROR("Timed out waiting for IPS enable\n");
  2881. }
  2882. void hsw_disable_ips(struct intel_crtc *crtc)
  2883. {
  2884. struct drm_device *dev = crtc->base.dev;
  2885. struct drm_i915_private *dev_priv = dev->dev_private;
  2886. if (!crtc->config.ips_enabled)
  2887. return;
  2888. assert_plane_enabled(dev_priv, crtc->plane);
  2889. I915_WRITE(IPS_CTL, 0);
  2890. POSTING_READ(IPS_CTL);
  2891. /* We need to wait for a vblank before we can disable the plane. */
  2892. intel_wait_for_vblank(dev, crtc->pipe);
  2893. }
  2894. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  2895. static void intel_crtc_load_lut(struct drm_crtc *crtc)
  2896. {
  2897. struct drm_device *dev = crtc->dev;
  2898. struct drm_i915_private *dev_priv = dev->dev_private;
  2899. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2900. enum pipe pipe = intel_crtc->pipe;
  2901. int palreg = PALETTE(pipe);
  2902. int i;
  2903. bool reenable_ips = false;
  2904. /* The clocks have to be on to load the palette. */
  2905. if (!crtc->enabled || !intel_crtc->active)
  2906. return;
  2907. if (!HAS_PCH_SPLIT(dev_priv->dev)) {
  2908. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  2909. assert_dsi_pll_enabled(dev_priv);
  2910. else
  2911. assert_pll_enabled(dev_priv, pipe);
  2912. }
  2913. /* use legacy palette for Ironlake */
  2914. if (HAS_PCH_SPLIT(dev))
  2915. palreg = LGC_PALETTE(pipe);
  2916. /* Workaround : Do not read or write the pipe palette/gamma data while
  2917. * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
  2918. */
  2919. if (intel_crtc->config.ips_enabled &&
  2920. ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
  2921. GAMMA_MODE_MODE_SPLIT)) {
  2922. hsw_disable_ips(intel_crtc);
  2923. reenable_ips = true;
  2924. }
  2925. for (i = 0; i < 256; i++) {
  2926. I915_WRITE(palreg + 4 * i,
  2927. (intel_crtc->lut_r[i] << 16) |
  2928. (intel_crtc->lut_g[i] << 8) |
  2929. intel_crtc->lut_b[i]);
  2930. }
  2931. if (reenable_ips)
  2932. hsw_enable_ips(intel_crtc);
  2933. }
  2934. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2935. {
  2936. struct drm_device *dev = crtc->dev;
  2937. struct drm_i915_private *dev_priv = dev->dev_private;
  2938. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2939. struct intel_encoder *encoder;
  2940. int pipe = intel_crtc->pipe;
  2941. int plane = intel_crtc->plane;
  2942. WARN_ON(!crtc->enabled);
  2943. if (intel_crtc->active)
  2944. return;
  2945. intel_crtc->active = true;
  2946. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2947. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  2948. for_each_encoder_on_crtc(dev, crtc, encoder)
  2949. if (encoder->pre_enable)
  2950. encoder->pre_enable(encoder);
  2951. if (intel_crtc->config.has_pch_encoder) {
  2952. /* Note: FDI PLL enabling _must_ be done before we enable the
  2953. * cpu pipes, hence this is separate from all the other fdi/pch
  2954. * enabling. */
  2955. ironlake_fdi_pll_enable(intel_crtc);
  2956. } else {
  2957. assert_fdi_tx_disabled(dev_priv, pipe);
  2958. assert_fdi_rx_disabled(dev_priv, pipe);
  2959. }
  2960. ironlake_pfit_enable(intel_crtc);
  2961. /*
  2962. * On ILK+ LUT must be loaded before the pipe is running but with
  2963. * clocks enabled
  2964. */
  2965. intel_crtc_load_lut(crtc);
  2966. intel_update_watermarks(crtc);
  2967. intel_enable_pipe(dev_priv, pipe,
  2968. intel_crtc->config.has_pch_encoder, false);
  2969. intel_enable_primary_plane(dev_priv, plane, pipe);
  2970. intel_enable_planes(crtc);
  2971. intel_crtc_update_cursor(crtc, true);
  2972. if (intel_crtc->config.has_pch_encoder)
  2973. ironlake_pch_enable(crtc);
  2974. mutex_lock(&dev->struct_mutex);
  2975. intel_update_fbc(dev);
  2976. mutex_unlock(&dev->struct_mutex);
  2977. for_each_encoder_on_crtc(dev, crtc, encoder)
  2978. encoder->enable(encoder);
  2979. if (HAS_PCH_CPT(dev))
  2980. cpt_verify_modeset(dev, intel_crtc->pipe);
  2981. /*
  2982. * There seems to be a race in PCH platform hw (at least on some
  2983. * outputs) where an enabled pipe still completes any pageflip right
  2984. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2985. * as the first vblank happend, everything works as expected. Hence just
  2986. * wait for one vblank before returning to avoid strange things
  2987. * happening.
  2988. */
  2989. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2990. }
  2991. /* IPS only exists on ULT machines and is tied to pipe A. */
  2992. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  2993. {
  2994. return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  2995. }
  2996. static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
  2997. {
  2998. struct drm_device *dev = crtc->dev;
  2999. struct drm_i915_private *dev_priv = dev->dev_private;
  3000. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3001. int pipe = intel_crtc->pipe;
  3002. int plane = intel_crtc->plane;
  3003. intel_enable_primary_plane(dev_priv, plane, pipe);
  3004. intel_enable_planes(crtc);
  3005. intel_crtc_update_cursor(crtc, true);
  3006. hsw_enable_ips(intel_crtc);
  3007. mutex_lock(&dev->struct_mutex);
  3008. intel_update_fbc(dev);
  3009. mutex_unlock(&dev->struct_mutex);
  3010. }
  3011. static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
  3012. {
  3013. struct drm_device *dev = crtc->dev;
  3014. struct drm_i915_private *dev_priv = dev->dev_private;
  3015. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3016. int pipe = intel_crtc->pipe;
  3017. int plane = intel_crtc->plane;
  3018. intel_crtc_wait_for_pending_flips(crtc);
  3019. drm_vblank_off(dev, pipe);
  3020. /* FBC must be disabled before disabling the plane on HSW. */
  3021. if (dev_priv->fbc.plane == plane)
  3022. intel_disable_fbc(dev);
  3023. hsw_disable_ips(intel_crtc);
  3024. intel_crtc_update_cursor(crtc, false);
  3025. intel_disable_planes(crtc);
  3026. intel_disable_primary_plane(dev_priv, plane, pipe);
  3027. }
  3028. /*
  3029. * This implements the workaround described in the "notes" section of the mode
  3030. * set sequence documentation. When going from no pipes or single pipe to
  3031. * multiple pipes, and planes are enabled after the pipe, we need to wait at
  3032. * least 2 vblanks on the first pipe before enabling planes on the second pipe.
  3033. */
  3034. static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
  3035. {
  3036. struct drm_device *dev = crtc->base.dev;
  3037. struct intel_crtc *crtc_it, *other_active_crtc = NULL;
  3038. /* We want to get the other_active_crtc only if there's only 1 other
  3039. * active crtc. */
  3040. list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
  3041. if (!crtc_it->active || crtc_it == crtc)
  3042. continue;
  3043. if (other_active_crtc)
  3044. return;
  3045. other_active_crtc = crtc_it;
  3046. }
  3047. if (!other_active_crtc)
  3048. return;
  3049. intel_wait_for_vblank(dev, other_active_crtc->pipe);
  3050. intel_wait_for_vblank(dev, other_active_crtc->pipe);
  3051. }
  3052. static void haswell_crtc_enable(struct drm_crtc *crtc)
  3053. {
  3054. struct drm_device *dev = crtc->dev;
  3055. struct drm_i915_private *dev_priv = dev->dev_private;
  3056. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3057. struct intel_encoder *encoder;
  3058. int pipe = intel_crtc->pipe;
  3059. WARN_ON(!crtc->enabled);
  3060. if (intel_crtc->active)
  3061. return;
  3062. intel_crtc->active = true;
  3063. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  3064. if (intel_crtc->config.has_pch_encoder)
  3065. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3066. if (intel_crtc->config.has_pch_encoder)
  3067. dev_priv->display.fdi_link_train(crtc);
  3068. for_each_encoder_on_crtc(dev, crtc, encoder)
  3069. if (encoder->pre_enable)
  3070. encoder->pre_enable(encoder);
  3071. intel_ddi_enable_pipe_clock(intel_crtc);
  3072. ironlake_pfit_enable(intel_crtc);
  3073. /*
  3074. * On ILK+ LUT must be loaded before the pipe is running but with
  3075. * clocks enabled
  3076. */
  3077. intel_crtc_load_lut(crtc);
  3078. intel_ddi_set_pipe_settings(crtc);
  3079. intel_ddi_enable_transcoder_func(crtc);
  3080. intel_update_watermarks(crtc);
  3081. intel_enable_pipe(dev_priv, pipe,
  3082. intel_crtc->config.has_pch_encoder, false);
  3083. if (intel_crtc->config.has_pch_encoder)
  3084. lpt_pch_enable(crtc);
  3085. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3086. encoder->enable(encoder);
  3087. intel_opregion_notify_encoder(encoder, true);
  3088. }
  3089. /* If we change the relative order between pipe/planes enabling, we need
  3090. * to change the workaround. */
  3091. haswell_mode_set_planes_workaround(intel_crtc);
  3092. haswell_crtc_enable_planes(crtc);
  3093. /*
  3094. * There seems to be a race in PCH platform hw (at least on some
  3095. * outputs) where an enabled pipe still completes any pageflip right
  3096. * away (as if the pipe is off) instead of waiting for vblank. As soon
  3097. * as the first vblank happend, everything works as expected. Hence just
  3098. * wait for one vblank before returning to avoid strange things
  3099. * happening.
  3100. */
  3101. intel_wait_for_vblank(dev, intel_crtc->pipe);
  3102. }
  3103. static void ironlake_pfit_disable(struct intel_crtc *crtc)
  3104. {
  3105. struct drm_device *dev = crtc->base.dev;
  3106. struct drm_i915_private *dev_priv = dev->dev_private;
  3107. int pipe = crtc->pipe;
  3108. /* To avoid upsetting the power well on haswell only disable the pfit if
  3109. * it's in use. The hw state code will make sure we get this right. */
  3110. if (crtc->config.pch_pfit.enabled) {
  3111. I915_WRITE(PF_CTL(pipe), 0);
  3112. I915_WRITE(PF_WIN_POS(pipe), 0);
  3113. I915_WRITE(PF_WIN_SZ(pipe), 0);
  3114. }
  3115. }
  3116. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  3117. {
  3118. struct drm_device *dev = crtc->dev;
  3119. struct drm_i915_private *dev_priv = dev->dev_private;
  3120. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3121. struct intel_encoder *encoder;
  3122. int pipe = intel_crtc->pipe;
  3123. int plane = intel_crtc->plane;
  3124. u32 reg, temp;
  3125. if (!intel_crtc->active)
  3126. return;
  3127. for_each_encoder_on_crtc(dev, crtc, encoder)
  3128. encoder->disable(encoder);
  3129. intel_crtc_wait_for_pending_flips(crtc);
  3130. drm_vblank_off(dev, pipe);
  3131. if (dev_priv->fbc.plane == plane)
  3132. intel_disable_fbc(dev);
  3133. intel_crtc_update_cursor(crtc, false);
  3134. intel_disable_planes(crtc);
  3135. intel_disable_primary_plane(dev_priv, plane, pipe);
  3136. if (intel_crtc->config.has_pch_encoder)
  3137. intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
  3138. intel_disable_pipe(dev_priv, pipe);
  3139. ironlake_pfit_disable(intel_crtc);
  3140. for_each_encoder_on_crtc(dev, crtc, encoder)
  3141. if (encoder->post_disable)
  3142. encoder->post_disable(encoder);
  3143. if (intel_crtc->config.has_pch_encoder) {
  3144. ironlake_fdi_disable(crtc);
  3145. ironlake_disable_pch_transcoder(dev_priv, pipe);
  3146. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  3147. if (HAS_PCH_CPT(dev)) {
  3148. /* disable TRANS_DP_CTL */
  3149. reg = TRANS_DP_CTL(pipe);
  3150. temp = I915_READ(reg);
  3151. temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  3152. TRANS_DP_PORT_SEL_MASK);
  3153. temp |= TRANS_DP_PORT_SEL_NONE;
  3154. I915_WRITE(reg, temp);
  3155. /* disable DPLL_SEL */
  3156. temp = I915_READ(PCH_DPLL_SEL);
  3157. temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  3158. I915_WRITE(PCH_DPLL_SEL, temp);
  3159. }
  3160. /* disable PCH DPLL */
  3161. intel_disable_shared_dpll(intel_crtc);
  3162. ironlake_fdi_pll_disable(intel_crtc);
  3163. }
  3164. intel_crtc->active = false;
  3165. intel_update_watermarks(crtc);
  3166. mutex_lock(&dev->struct_mutex);
  3167. intel_update_fbc(dev);
  3168. mutex_unlock(&dev->struct_mutex);
  3169. }
  3170. static void haswell_crtc_disable(struct drm_crtc *crtc)
  3171. {
  3172. struct drm_device *dev = crtc->dev;
  3173. struct drm_i915_private *dev_priv = dev->dev_private;
  3174. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3175. struct intel_encoder *encoder;
  3176. int pipe = intel_crtc->pipe;
  3177. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3178. if (!intel_crtc->active)
  3179. return;
  3180. haswell_crtc_disable_planes(crtc);
  3181. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3182. intel_opregion_notify_encoder(encoder, false);
  3183. encoder->disable(encoder);
  3184. }
  3185. if (intel_crtc->config.has_pch_encoder)
  3186. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
  3187. intel_disable_pipe(dev_priv, pipe);
  3188. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3189. ironlake_pfit_disable(intel_crtc);
  3190. intel_ddi_disable_pipe_clock(intel_crtc);
  3191. for_each_encoder_on_crtc(dev, crtc, encoder)
  3192. if (encoder->post_disable)
  3193. encoder->post_disable(encoder);
  3194. if (intel_crtc->config.has_pch_encoder) {
  3195. lpt_disable_pch_transcoder(dev_priv);
  3196. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3197. intel_ddi_fdi_disable(crtc);
  3198. }
  3199. intel_crtc->active = false;
  3200. intel_update_watermarks(crtc);
  3201. mutex_lock(&dev->struct_mutex);
  3202. intel_update_fbc(dev);
  3203. mutex_unlock(&dev->struct_mutex);
  3204. }
  3205. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3206. {
  3207. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3208. intel_put_shared_dpll(intel_crtc);
  3209. }
  3210. static void haswell_crtc_off(struct drm_crtc *crtc)
  3211. {
  3212. intel_ddi_put_crtc_pll(crtc);
  3213. }
  3214. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3215. {
  3216. if (!enable && intel_crtc->overlay) {
  3217. struct drm_device *dev = intel_crtc->base.dev;
  3218. struct drm_i915_private *dev_priv = dev->dev_private;
  3219. mutex_lock(&dev->struct_mutex);
  3220. dev_priv->mm.interruptible = false;
  3221. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3222. dev_priv->mm.interruptible = true;
  3223. mutex_unlock(&dev->struct_mutex);
  3224. }
  3225. /* Let userspace switch the overlay on again. In most cases userspace
  3226. * has to recompute where to put it anyway.
  3227. */
  3228. }
  3229. /**
  3230. * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
  3231. * cursor plane briefly if not already running after enabling the display
  3232. * plane.
  3233. * This workaround avoids occasional blank screens when self refresh is
  3234. * enabled.
  3235. */
  3236. static void
  3237. g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
  3238. {
  3239. u32 cntl = I915_READ(CURCNTR(pipe));
  3240. if ((cntl & CURSOR_MODE) == 0) {
  3241. u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
  3242. I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
  3243. I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
  3244. intel_wait_for_vblank(dev_priv->dev, pipe);
  3245. I915_WRITE(CURCNTR(pipe), cntl);
  3246. I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
  3247. I915_WRITE(FW_BLC_SELF, fw_bcl_self);
  3248. }
  3249. }
  3250. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  3251. {
  3252. struct drm_device *dev = crtc->base.dev;
  3253. struct drm_i915_private *dev_priv = dev->dev_private;
  3254. struct intel_crtc_config *pipe_config = &crtc->config;
  3255. if (!crtc->config.gmch_pfit.control)
  3256. return;
  3257. /*
  3258. * The panel fitter should only be adjusted whilst the pipe is disabled,
  3259. * according to register description and PRM.
  3260. */
  3261. WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  3262. assert_pipe_disabled(dev_priv, crtc->pipe);
  3263. I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  3264. I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  3265. /* Border color in case we don't scale up to the full screen. Black by
  3266. * default, change to something else for debugging. */
  3267. I915_WRITE(BCLRPAT(crtc->pipe), 0);
  3268. }
  3269. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  3270. {
  3271. struct drm_device *dev = crtc->dev;
  3272. struct drm_i915_private *dev_priv = dev->dev_private;
  3273. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3274. struct intel_encoder *encoder;
  3275. int pipe = intel_crtc->pipe;
  3276. int plane = intel_crtc->plane;
  3277. bool is_dsi;
  3278. WARN_ON(!crtc->enabled);
  3279. if (intel_crtc->active)
  3280. return;
  3281. intel_crtc->active = true;
  3282. for_each_encoder_on_crtc(dev, crtc, encoder)
  3283. if (encoder->pre_pll_enable)
  3284. encoder->pre_pll_enable(encoder);
  3285. is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
  3286. if (!is_dsi)
  3287. vlv_enable_pll(intel_crtc);
  3288. for_each_encoder_on_crtc(dev, crtc, encoder)
  3289. if (encoder->pre_enable)
  3290. encoder->pre_enable(encoder);
  3291. i9xx_pfit_enable(intel_crtc);
  3292. intel_crtc_load_lut(crtc);
  3293. intel_update_watermarks(crtc);
  3294. intel_enable_pipe(dev_priv, pipe, false, is_dsi);
  3295. intel_enable_primary_plane(dev_priv, plane, pipe);
  3296. intel_enable_planes(crtc);
  3297. intel_crtc_update_cursor(crtc, true);
  3298. intel_update_fbc(dev);
  3299. for_each_encoder_on_crtc(dev, crtc, encoder)
  3300. encoder->enable(encoder);
  3301. }
  3302. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3303. {
  3304. struct drm_device *dev = crtc->dev;
  3305. struct drm_i915_private *dev_priv = dev->dev_private;
  3306. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3307. struct intel_encoder *encoder;
  3308. int pipe = intel_crtc->pipe;
  3309. int plane = intel_crtc->plane;
  3310. WARN_ON(!crtc->enabled);
  3311. if (intel_crtc->active)
  3312. return;
  3313. intel_crtc->active = true;
  3314. for_each_encoder_on_crtc(dev, crtc, encoder)
  3315. if (encoder->pre_enable)
  3316. encoder->pre_enable(encoder);
  3317. i9xx_enable_pll(intel_crtc);
  3318. i9xx_pfit_enable(intel_crtc);
  3319. intel_crtc_load_lut(crtc);
  3320. intel_update_watermarks(crtc);
  3321. intel_enable_pipe(dev_priv, pipe, false, false);
  3322. intel_enable_primary_plane(dev_priv, plane, pipe);
  3323. intel_enable_planes(crtc);
  3324. /* The fixup needs to happen before cursor is enabled */
  3325. if (IS_G4X(dev))
  3326. g4x_fixup_plane(dev_priv, pipe);
  3327. intel_crtc_update_cursor(crtc, true);
  3328. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3329. intel_crtc_dpms_overlay(intel_crtc, true);
  3330. intel_update_fbc(dev);
  3331. for_each_encoder_on_crtc(dev, crtc, encoder)
  3332. encoder->enable(encoder);
  3333. }
  3334. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  3335. {
  3336. struct drm_device *dev = crtc->base.dev;
  3337. struct drm_i915_private *dev_priv = dev->dev_private;
  3338. if (!crtc->config.gmch_pfit.control)
  3339. return;
  3340. assert_pipe_disabled(dev_priv, crtc->pipe);
  3341. DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  3342. I915_READ(PFIT_CONTROL));
  3343. I915_WRITE(PFIT_CONTROL, 0);
  3344. }
  3345. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3346. {
  3347. struct drm_device *dev = crtc->dev;
  3348. struct drm_i915_private *dev_priv = dev->dev_private;
  3349. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3350. struct intel_encoder *encoder;
  3351. int pipe = intel_crtc->pipe;
  3352. int plane = intel_crtc->plane;
  3353. if (!intel_crtc->active)
  3354. return;
  3355. for_each_encoder_on_crtc(dev, crtc, encoder)
  3356. encoder->disable(encoder);
  3357. /* Give the overlay scaler a chance to disable if it's on this pipe */
  3358. intel_crtc_wait_for_pending_flips(crtc);
  3359. drm_vblank_off(dev, pipe);
  3360. if (dev_priv->fbc.plane == plane)
  3361. intel_disable_fbc(dev);
  3362. intel_crtc_dpms_overlay(intel_crtc, false);
  3363. intel_crtc_update_cursor(crtc, false);
  3364. intel_disable_planes(crtc);
  3365. intel_disable_primary_plane(dev_priv, plane, pipe);
  3366. intel_disable_pipe(dev_priv, pipe);
  3367. i9xx_pfit_disable(intel_crtc);
  3368. for_each_encoder_on_crtc(dev, crtc, encoder)
  3369. if (encoder->post_disable)
  3370. encoder->post_disable(encoder);
  3371. if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  3372. vlv_disable_pll(dev_priv, pipe);
  3373. else if (!IS_VALLEYVIEW(dev))
  3374. i9xx_disable_pll(dev_priv, pipe);
  3375. intel_crtc->active = false;
  3376. intel_update_watermarks(crtc);
  3377. intel_update_fbc(dev);
  3378. }
  3379. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3380. {
  3381. }
  3382. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3383. bool enabled)
  3384. {
  3385. struct drm_device *dev = crtc->dev;
  3386. struct drm_i915_master_private *master_priv;
  3387. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3388. int pipe = intel_crtc->pipe;
  3389. if (!dev->primary->master)
  3390. return;
  3391. master_priv = dev->primary->master->driver_priv;
  3392. if (!master_priv->sarea_priv)
  3393. return;
  3394. switch (pipe) {
  3395. case 0:
  3396. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3397. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3398. break;
  3399. case 1:
  3400. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3401. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3402. break;
  3403. default:
  3404. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3405. break;
  3406. }
  3407. }
  3408. /**
  3409. * Sets the power management mode of the pipe and plane.
  3410. */
  3411. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3412. {
  3413. struct drm_device *dev = crtc->dev;
  3414. struct drm_i915_private *dev_priv = dev->dev_private;
  3415. struct intel_encoder *intel_encoder;
  3416. bool enable = false;
  3417. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3418. enable |= intel_encoder->connectors_active;
  3419. if (enable)
  3420. dev_priv->display.crtc_enable(crtc);
  3421. else
  3422. dev_priv->display.crtc_disable(crtc);
  3423. intel_crtc_update_sarea(crtc, enable);
  3424. }
  3425. static void intel_crtc_disable(struct drm_crtc *crtc)
  3426. {
  3427. struct drm_device *dev = crtc->dev;
  3428. struct drm_connector *connector;
  3429. struct drm_i915_private *dev_priv = dev->dev_private;
  3430. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3431. /* crtc should still be enabled when we disable it. */
  3432. WARN_ON(!crtc->enabled);
  3433. dev_priv->display.crtc_disable(crtc);
  3434. intel_crtc->eld_vld = false;
  3435. intel_crtc_update_sarea(crtc, false);
  3436. dev_priv->display.off(crtc);
  3437. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3438. assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
  3439. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3440. if (crtc->fb) {
  3441. mutex_lock(&dev->struct_mutex);
  3442. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3443. mutex_unlock(&dev->struct_mutex);
  3444. crtc->fb = NULL;
  3445. }
  3446. /* Update computed state. */
  3447. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3448. if (!connector->encoder || !connector->encoder->crtc)
  3449. continue;
  3450. if (connector->encoder->crtc != crtc)
  3451. continue;
  3452. connector->dpms = DRM_MODE_DPMS_OFF;
  3453. to_intel_encoder(connector->encoder)->connectors_active = false;
  3454. }
  3455. }
  3456. void intel_encoder_destroy(struct drm_encoder *encoder)
  3457. {
  3458. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3459. drm_encoder_cleanup(encoder);
  3460. kfree(intel_encoder);
  3461. }
  3462. /* Simple dpms helper for encoders with just one connector, no cloning and only
  3463. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3464. * state of the entire output pipe. */
  3465. static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3466. {
  3467. if (mode == DRM_MODE_DPMS_ON) {
  3468. encoder->connectors_active = true;
  3469. intel_crtc_update_dpms(encoder->base.crtc);
  3470. } else {
  3471. encoder->connectors_active = false;
  3472. intel_crtc_update_dpms(encoder->base.crtc);
  3473. }
  3474. }
  3475. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3476. * internal consistency). */
  3477. static void intel_connector_check_state(struct intel_connector *connector)
  3478. {
  3479. if (connector->get_hw_state(connector)) {
  3480. struct intel_encoder *encoder = connector->encoder;
  3481. struct drm_crtc *crtc;
  3482. bool encoder_enabled;
  3483. enum pipe pipe;
  3484. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3485. connector->base.base.id,
  3486. drm_get_connector_name(&connector->base));
  3487. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3488. "wrong connector dpms state\n");
  3489. WARN(connector->base.encoder != &encoder->base,
  3490. "active connector not linked to encoder\n");
  3491. WARN(!encoder->connectors_active,
  3492. "encoder->connectors_active not set\n");
  3493. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3494. WARN(!encoder_enabled, "encoder not enabled\n");
  3495. if (WARN_ON(!encoder->base.crtc))
  3496. return;
  3497. crtc = encoder->base.crtc;
  3498. WARN(!crtc->enabled, "crtc not enabled\n");
  3499. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3500. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3501. "encoder active on the wrong pipe\n");
  3502. }
  3503. }
  3504. /* Even simpler default implementation, if there's really no special case to
  3505. * consider. */
  3506. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3507. {
  3508. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3509. /* All the simple cases only support two dpms states. */
  3510. if (mode != DRM_MODE_DPMS_ON)
  3511. mode = DRM_MODE_DPMS_OFF;
  3512. if (mode == connector->dpms)
  3513. return;
  3514. connector->dpms = mode;
  3515. /* Only need to change hw state when actually enabled */
  3516. if (encoder->base.crtc)
  3517. intel_encoder_dpms(encoder, mode);
  3518. else
  3519. WARN_ON(encoder->connectors_active != false);
  3520. intel_modeset_check_state(connector->dev);
  3521. }
  3522. /* Simple connector->get_hw_state implementation for encoders that support only
  3523. * one connector and no cloning and hence the encoder state determines the state
  3524. * of the connector. */
  3525. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3526. {
  3527. enum pipe pipe = 0;
  3528. struct intel_encoder *encoder = connector->encoder;
  3529. return encoder->get_hw_state(encoder, &pipe);
  3530. }
  3531. static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  3532. struct intel_crtc_config *pipe_config)
  3533. {
  3534. struct drm_i915_private *dev_priv = dev->dev_private;
  3535. struct intel_crtc *pipe_B_crtc =
  3536. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  3537. DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  3538. pipe_name(pipe), pipe_config->fdi_lanes);
  3539. if (pipe_config->fdi_lanes > 4) {
  3540. DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  3541. pipe_name(pipe), pipe_config->fdi_lanes);
  3542. return false;
  3543. }
  3544. if (IS_HASWELL(dev)) {
  3545. if (pipe_config->fdi_lanes > 2) {
  3546. DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  3547. pipe_config->fdi_lanes);
  3548. return false;
  3549. } else {
  3550. return true;
  3551. }
  3552. }
  3553. if (INTEL_INFO(dev)->num_pipes == 2)
  3554. return true;
  3555. /* Ivybridge 3 pipe is really complicated */
  3556. switch (pipe) {
  3557. case PIPE_A:
  3558. return true;
  3559. case PIPE_B:
  3560. if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  3561. pipe_config->fdi_lanes > 2) {
  3562. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3563. pipe_name(pipe), pipe_config->fdi_lanes);
  3564. return false;
  3565. }
  3566. return true;
  3567. case PIPE_C:
  3568. if (!pipe_has_enabled_pch(pipe_B_crtc) ||
  3569. pipe_B_crtc->config.fdi_lanes <= 2) {
  3570. if (pipe_config->fdi_lanes > 2) {
  3571. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3572. pipe_name(pipe), pipe_config->fdi_lanes);
  3573. return false;
  3574. }
  3575. } else {
  3576. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  3577. return false;
  3578. }
  3579. return true;
  3580. default:
  3581. BUG();
  3582. }
  3583. }
  3584. #define RETRY 1
  3585. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  3586. struct intel_crtc_config *pipe_config)
  3587. {
  3588. struct drm_device *dev = intel_crtc->base.dev;
  3589. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3590. int lane, link_bw, fdi_dotclock;
  3591. bool setup_ok, needs_recompute = false;
  3592. retry:
  3593. /* FDI is a binary signal running at ~2.7GHz, encoding
  3594. * each output octet as 10 bits. The actual frequency
  3595. * is stored as a divider into a 100MHz clock, and the
  3596. * mode pixel clock is stored in units of 1KHz.
  3597. * Hence the bw of each lane in terms of the mode signal
  3598. * is:
  3599. */
  3600. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  3601. fdi_dotclock = adjusted_mode->crtc_clock;
  3602. lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  3603. pipe_config->pipe_bpp);
  3604. pipe_config->fdi_lanes = lane;
  3605. intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  3606. link_bw, &pipe_config->fdi_m_n);
  3607. setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
  3608. intel_crtc->pipe, pipe_config);
  3609. if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
  3610. pipe_config->pipe_bpp -= 2*3;
  3611. DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  3612. pipe_config->pipe_bpp);
  3613. needs_recompute = true;
  3614. pipe_config->bw_constrained = true;
  3615. goto retry;
  3616. }
  3617. if (needs_recompute)
  3618. return RETRY;
  3619. return setup_ok ? 0 : -EINVAL;
  3620. }
  3621. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  3622. struct intel_crtc_config *pipe_config)
  3623. {
  3624. pipe_config->ips_enabled = i915_enable_ips &&
  3625. hsw_crtc_supports_ips(crtc) &&
  3626. pipe_config->pipe_bpp <= 24;
  3627. }
  3628. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  3629. struct intel_crtc_config *pipe_config)
  3630. {
  3631. struct drm_device *dev = crtc->base.dev;
  3632. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3633. /* FIXME should check pixel clock limits on all platforms */
  3634. if (INTEL_INFO(dev)->gen < 4) {
  3635. struct drm_i915_private *dev_priv = dev->dev_private;
  3636. int clock_limit =
  3637. dev_priv->display.get_display_clock_speed(dev);
  3638. /*
  3639. * Enable pixel doubling when the dot clock
  3640. * is > 90% of the (display) core speed.
  3641. *
  3642. * GDG double wide on either pipe,
  3643. * otherwise pipe A only.
  3644. */
  3645. if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
  3646. adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
  3647. clock_limit *= 2;
  3648. pipe_config->double_wide = true;
  3649. }
  3650. if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
  3651. return -EINVAL;
  3652. }
  3653. /*
  3654. * Pipe horizontal size must be even in:
  3655. * - DVO ganged mode
  3656. * - LVDS dual channel mode
  3657. * - Double wide pipe
  3658. */
  3659. if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3660. intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
  3661. pipe_config->pipe_src_w &= ~1;
  3662. /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  3663. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  3664. */
  3665. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3666. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3667. return -EINVAL;
  3668. if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
  3669. pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
  3670. } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
  3671. /* only a 8bpc pipe, with 6bpc dither through the panel fitter
  3672. * for lvds. */
  3673. pipe_config->pipe_bpp = 8*3;
  3674. }
  3675. if (HAS_IPS(dev))
  3676. hsw_compute_ips_config(crtc, pipe_config);
  3677. /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
  3678. * clock survives for now. */
  3679. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  3680. pipe_config->shared_dpll = crtc->config.shared_dpll;
  3681. if (pipe_config->has_pch_encoder)
  3682. return ironlake_fdi_compute_config(crtc, pipe_config);
  3683. return 0;
  3684. }
  3685. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3686. {
  3687. return 400000; /* FIXME */
  3688. }
  3689. static int i945_get_display_clock_speed(struct drm_device *dev)
  3690. {
  3691. return 400000;
  3692. }
  3693. static int i915_get_display_clock_speed(struct drm_device *dev)
  3694. {
  3695. return 333000;
  3696. }
  3697. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3698. {
  3699. return 200000;
  3700. }
  3701. static int pnv_get_display_clock_speed(struct drm_device *dev)
  3702. {
  3703. u16 gcfgc = 0;
  3704. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3705. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3706. case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  3707. return 267000;
  3708. case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  3709. return 333000;
  3710. case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  3711. return 444000;
  3712. case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  3713. return 200000;
  3714. default:
  3715. DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  3716. case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  3717. return 133000;
  3718. case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  3719. return 167000;
  3720. }
  3721. }
  3722. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3723. {
  3724. u16 gcfgc = 0;
  3725. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3726. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3727. return 133000;
  3728. else {
  3729. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3730. case GC_DISPLAY_CLOCK_333_MHZ:
  3731. return 333000;
  3732. default:
  3733. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3734. return 190000;
  3735. }
  3736. }
  3737. }
  3738. static int i865_get_display_clock_speed(struct drm_device *dev)
  3739. {
  3740. return 266000;
  3741. }
  3742. static int i855_get_display_clock_speed(struct drm_device *dev)
  3743. {
  3744. u16 hpllcc = 0;
  3745. /* Assume that the hardware is in the high speed state. This
  3746. * should be the default.
  3747. */
  3748. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3749. case GC_CLOCK_133_200:
  3750. case GC_CLOCK_100_200:
  3751. return 200000;
  3752. case GC_CLOCK_166_250:
  3753. return 250000;
  3754. case GC_CLOCK_100_133:
  3755. return 133000;
  3756. }
  3757. /* Shouldn't happen */
  3758. return 0;
  3759. }
  3760. static int i830_get_display_clock_speed(struct drm_device *dev)
  3761. {
  3762. return 133000;
  3763. }
  3764. static void
  3765. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  3766. {
  3767. while (*num > DATA_LINK_M_N_MASK ||
  3768. *den > DATA_LINK_M_N_MASK) {
  3769. *num >>= 1;
  3770. *den >>= 1;
  3771. }
  3772. }
  3773. static void compute_m_n(unsigned int m, unsigned int n,
  3774. uint32_t *ret_m, uint32_t *ret_n)
  3775. {
  3776. *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  3777. *ret_m = div_u64((uint64_t) m * *ret_n, n);
  3778. intel_reduce_m_n_ratio(ret_m, ret_n);
  3779. }
  3780. void
  3781. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  3782. int pixel_clock, int link_clock,
  3783. struct intel_link_m_n *m_n)
  3784. {
  3785. m_n->tu = 64;
  3786. compute_m_n(bits_per_pixel * pixel_clock,
  3787. link_clock * nlanes * 8,
  3788. &m_n->gmch_m, &m_n->gmch_n);
  3789. compute_m_n(pixel_clock, link_clock,
  3790. &m_n->link_m, &m_n->link_n);
  3791. }
  3792. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3793. {
  3794. if (i915_panel_use_ssc >= 0)
  3795. return i915_panel_use_ssc != 0;
  3796. return dev_priv->vbt.lvds_use_ssc
  3797. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3798. }
  3799. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3800. {
  3801. struct drm_device *dev = crtc->dev;
  3802. struct drm_i915_private *dev_priv = dev->dev_private;
  3803. int refclk;
  3804. if (IS_VALLEYVIEW(dev)) {
  3805. refclk = 100000;
  3806. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3807. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3808. refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
  3809. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3810. refclk / 1000);
  3811. } else if (!IS_GEN2(dev)) {
  3812. refclk = 96000;
  3813. } else {
  3814. refclk = 48000;
  3815. }
  3816. return refclk;
  3817. }
  3818. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  3819. {
  3820. return (1 << dpll->n) << 16 | dpll->m2;
  3821. }
  3822. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  3823. {
  3824. return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  3825. }
  3826. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  3827. intel_clock_t *reduced_clock)
  3828. {
  3829. struct drm_device *dev = crtc->base.dev;
  3830. struct drm_i915_private *dev_priv = dev->dev_private;
  3831. int pipe = crtc->pipe;
  3832. u32 fp, fp2 = 0;
  3833. if (IS_PINEVIEW(dev)) {
  3834. fp = pnv_dpll_compute_fp(&crtc->config.dpll);
  3835. if (reduced_clock)
  3836. fp2 = pnv_dpll_compute_fp(reduced_clock);
  3837. } else {
  3838. fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
  3839. if (reduced_clock)
  3840. fp2 = i9xx_dpll_compute_fp(reduced_clock);
  3841. }
  3842. I915_WRITE(FP0(pipe), fp);
  3843. crtc->config.dpll_hw_state.fp0 = fp;
  3844. crtc->lowfreq_avail = false;
  3845. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3846. reduced_clock && i915_powersave) {
  3847. I915_WRITE(FP1(pipe), fp2);
  3848. crtc->config.dpll_hw_state.fp1 = fp2;
  3849. crtc->lowfreq_avail = true;
  3850. } else {
  3851. I915_WRITE(FP1(pipe), fp);
  3852. crtc->config.dpll_hw_state.fp1 = fp;
  3853. }
  3854. }
  3855. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
  3856. pipe)
  3857. {
  3858. u32 reg_val;
  3859. /*
  3860. * PLLB opamp always calibrates to max value of 0x3f, force enable it
  3861. * and set it to a reasonable value instead.
  3862. */
  3863. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
  3864. reg_val &= 0xffffff00;
  3865. reg_val |= 0x00000030;
  3866. vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
  3867. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
  3868. reg_val &= 0x8cffffff;
  3869. reg_val = 0x8c000000;
  3870. vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
  3871. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
  3872. reg_val &= 0xffffff00;
  3873. vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
  3874. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
  3875. reg_val &= 0x00ffffff;
  3876. reg_val |= 0xb0000000;
  3877. vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
  3878. }
  3879. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  3880. struct intel_link_m_n *m_n)
  3881. {
  3882. struct drm_device *dev = crtc->base.dev;
  3883. struct drm_i915_private *dev_priv = dev->dev_private;
  3884. int pipe = crtc->pipe;
  3885. I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3886. I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  3887. I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  3888. I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  3889. }
  3890. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  3891. struct intel_link_m_n *m_n)
  3892. {
  3893. struct drm_device *dev = crtc->base.dev;
  3894. struct drm_i915_private *dev_priv = dev->dev_private;
  3895. int pipe = crtc->pipe;
  3896. enum transcoder transcoder = crtc->config.cpu_transcoder;
  3897. if (INTEL_INFO(dev)->gen >= 5) {
  3898. I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3899. I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  3900. I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  3901. I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  3902. } else {
  3903. I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3904. I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  3905. I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  3906. I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  3907. }
  3908. }
  3909. static void intel_dp_set_m_n(struct intel_crtc *crtc)
  3910. {
  3911. if (crtc->config.has_pch_encoder)
  3912. intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3913. else
  3914. intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3915. }
  3916. static void vlv_update_pll(struct intel_crtc *crtc)
  3917. {
  3918. struct drm_device *dev = crtc->base.dev;
  3919. struct drm_i915_private *dev_priv = dev->dev_private;
  3920. int pipe = crtc->pipe;
  3921. u32 dpll, mdiv;
  3922. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3923. u32 coreclk, reg_val, dpll_md;
  3924. mutex_lock(&dev_priv->dpio_lock);
  3925. bestn = crtc->config.dpll.n;
  3926. bestm1 = crtc->config.dpll.m1;
  3927. bestm2 = crtc->config.dpll.m2;
  3928. bestp1 = crtc->config.dpll.p1;
  3929. bestp2 = crtc->config.dpll.p2;
  3930. /* See eDP HDMI DPIO driver vbios notes doc */
  3931. /* PLL B needs special handling */
  3932. if (pipe)
  3933. vlv_pllb_recal_opamp(dev_priv, pipe);
  3934. /* Set up Tx target for periodic Rcomp update */
  3935. vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
  3936. /* Disable target IRef on PLL */
  3937. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
  3938. reg_val &= 0x00ffffff;
  3939. vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
  3940. /* Disable fast lock */
  3941. vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
  3942. /* Set idtafcrecal before PLL is enabled */
  3943. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3944. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3945. mdiv |= ((bestn << DPIO_N_SHIFT));
  3946. mdiv |= (1 << DPIO_K_SHIFT);
  3947. /*
  3948. * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  3949. * but we don't support that).
  3950. * Note: don't use the DAC post divider as it seems unstable.
  3951. */
  3952. mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  3953. vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
  3954. mdiv |= DPIO_ENABLE_CALIBRATION;
  3955. vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
  3956. /* Set HBR and RBR LPF coefficients */
  3957. if (crtc->config.port_clock == 162000 ||
  3958. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
  3959. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
  3960. vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
  3961. 0x009f0003);
  3962. else
  3963. vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
  3964. 0x00d0000f);
  3965. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  3966. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
  3967. /* Use SSC source */
  3968. if (!pipe)
  3969. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3970. 0x0df40000);
  3971. else
  3972. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3973. 0x0df70000);
  3974. } else { /* HDMI or VGA */
  3975. /* Use bend source */
  3976. if (!pipe)
  3977. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3978. 0x0df70000);
  3979. else
  3980. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3981. 0x0df40000);
  3982. }
  3983. coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
  3984. coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  3985. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
  3986. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
  3987. coreclk |= 0x01000000;
  3988. vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
  3989. vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
  3990. /* Enable DPIO clock input */
  3991. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3992. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3993. /* We should never disable this, set it here for state tracking */
  3994. if (pipe == PIPE_B)
  3995. dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  3996. dpll |= DPLL_VCO_ENABLE;
  3997. crtc->config.dpll_hw_state.dpll = dpll;
  3998. dpll_md = (crtc->config.pixel_multiplier - 1)
  3999. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4000. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  4001. if (crtc->config.has_dp_encoder)
  4002. intel_dp_set_m_n(crtc);
  4003. mutex_unlock(&dev_priv->dpio_lock);
  4004. }
  4005. static void i9xx_update_pll(struct intel_crtc *crtc,
  4006. intel_clock_t *reduced_clock,
  4007. int num_connectors)
  4008. {
  4009. struct drm_device *dev = crtc->base.dev;
  4010. struct drm_i915_private *dev_priv = dev->dev_private;
  4011. u32 dpll;
  4012. bool is_sdvo;
  4013. struct dpll *clock = &crtc->config.dpll;
  4014. i9xx_update_pll_dividers(crtc, reduced_clock);
  4015. is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
  4016. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  4017. dpll = DPLL_VGA_MODE_DIS;
  4018. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
  4019. dpll |= DPLLB_MODE_LVDS;
  4020. else
  4021. dpll |= DPLLB_MODE_DAC_SERIAL;
  4022. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  4023. dpll |= (crtc->config.pixel_multiplier - 1)
  4024. << SDVO_MULTIPLIER_SHIFT_HIRES;
  4025. }
  4026. if (is_sdvo)
  4027. dpll |= DPLL_SDVO_HIGH_SPEED;
  4028. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  4029. dpll |= DPLL_SDVO_HIGH_SPEED;
  4030. /* compute bitmask from p1 value */
  4031. if (IS_PINEVIEW(dev))
  4032. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  4033. else {
  4034. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4035. if (IS_G4X(dev) && reduced_clock)
  4036. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4037. }
  4038. switch (clock->p2) {
  4039. case 5:
  4040. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4041. break;
  4042. case 7:
  4043. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4044. break;
  4045. case 10:
  4046. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4047. break;
  4048. case 14:
  4049. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4050. break;
  4051. }
  4052. if (INTEL_INFO(dev)->gen >= 4)
  4053. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  4054. if (crtc->config.sdvo_tv_clock)
  4055. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4056. else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  4057. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4058. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4059. else
  4060. dpll |= PLL_REF_INPUT_DREFCLK;
  4061. dpll |= DPLL_VCO_ENABLE;
  4062. crtc->config.dpll_hw_state.dpll = dpll;
  4063. if (INTEL_INFO(dev)->gen >= 4) {
  4064. u32 dpll_md = (crtc->config.pixel_multiplier - 1)
  4065. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4066. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  4067. }
  4068. if (crtc->config.has_dp_encoder)
  4069. intel_dp_set_m_n(crtc);
  4070. }
  4071. static void i8xx_update_pll(struct intel_crtc *crtc,
  4072. intel_clock_t *reduced_clock,
  4073. int num_connectors)
  4074. {
  4075. struct drm_device *dev = crtc->base.dev;
  4076. struct drm_i915_private *dev_priv = dev->dev_private;
  4077. u32 dpll;
  4078. struct dpll *clock = &crtc->config.dpll;
  4079. i9xx_update_pll_dividers(crtc, reduced_clock);
  4080. dpll = DPLL_VGA_MODE_DIS;
  4081. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
  4082. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4083. } else {
  4084. if (clock->p1 == 2)
  4085. dpll |= PLL_P1_DIVIDE_BY_TWO;
  4086. else
  4087. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4088. if (clock->p2 == 4)
  4089. dpll |= PLL_P2_DIVIDE_BY_4;
  4090. }
  4091. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
  4092. dpll |= DPLL_DVO_2X_MODE;
  4093. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  4094. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4095. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4096. else
  4097. dpll |= PLL_REF_INPUT_DREFCLK;
  4098. dpll |= DPLL_VCO_ENABLE;
  4099. crtc->config.dpll_hw_state.dpll = dpll;
  4100. }
  4101. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  4102. {
  4103. struct drm_device *dev = intel_crtc->base.dev;
  4104. struct drm_i915_private *dev_priv = dev->dev_private;
  4105. enum pipe pipe = intel_crtc->pipe;
  4106. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4107. struct drm_display_mode *adjusted_mode =
  4108. &intel_crtc->config.adjusted_mode;
  4109. uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
  4110. /* We need to be careful not to changed the adjusted mode, for otherwise
  4111. * the hw state checker will get angry at the mismatch. */
  4112. crtc_vtotal = adjusted_mode->crtc_vtotal;
  4113. crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  4114. if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4115. /* the chip adds 2 halflines automatically */
  4116. crtc_vtotal -= 1;
  4117. crtc_vblank_end -= 1;
  4118. vsyncshift = adjusted_mode->crtc_hsync_start
  4119. - adjusted_mode->crtc_htotal / 2;
  4120. } else {
  4121. vsyncshift = 0;
  4122. }
  4123. if (INTEL_INFO(dev)->gen > 3)
  4124. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  4125. I915_WRITE(HTOTAL(cpu_transcoder),
  4126. (adjusted_mode->crtc_hdisplay - 1) |
  4127. ((adjusted_mode->crtc_htotal - 1) << 16));
  4128. I915_WRITE(HBLANK(cpu_transcoder),
  4129. (adjusted_mode->crtc_hblank_start - 1) |
  4130. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4131. I915_WRITE(HSYNC(cpu_transcoder),
  4132. (adjusted_mode->crtc_hsync_start - 1) |
  4133. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4134. I915_WRITE(VTOTAL(cpu_transcoder),
  4135. (adjusted_mode->crtc_vdisplay - 1) |
  4136. ((crtc_vtotal - 1) << 16));
  4137. I915_WRITE(VBLANK(cpu_transcoder),
  4138. (adjusted_mode->crtc_vblank_start - 1) |
  4139. ((crtc_vblank_end - 1) << 16));
  4140. I915_WRITE(VSYNC(cpu_transcoder),
  4141. (adjusted_mode->crtc_vsync_start - 1) |
  4142. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4143. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  4144. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  4145. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  4146. * bits. */
  4147. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  4148. (pipe == PIPE_B || pipe == PIPE_C))
  4149. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  4150. /* pipesrc controls the size that is scaled from, which should
  4151. * always be the user's requested size.
  4152. */
  4153. I915_WRITE(PIPESRC(pipe),
  4154. ((intel_crtc->config.pipe_src_w - 1) << 16) |
  4155. (intel_crtc->config.pipe_src_h - 1));
  4156. }
  4157. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  4158. struct intel_crtc_config *pipe_config)
  4159. {
  4160. struct drm_device *dev = crtc->base.dev;
  4161. struct drm_i915_private *dev_priv = dev->dev_private;
  4162. enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  4163. uint32_t tmp;
  4164. tmp = I915_READ(HTOTAL(cpu_transcoder));
  4165. pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  4166. pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  4167. tmp = I915_READ(HBLANK(cpu_transcoder));
  4168. pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  4169. pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  4170. tmp = I915_READ(HSYNC(cpu_transcoder));
  4171. pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  4172. pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  4173. tmp = I915_READ(VTOTAL(cpu_transcoder));
  4174. pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  4175. pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  4176. tmp = I915_READ(VBLANK(cpu_transcoder));
  4177. pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  4178. pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  4179. tmp = I915_READ(VSYNC(cpu_transcoder));
  4180. pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  4181. pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  4182. if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  4183. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  4184. pipe_config->adjusted_mode.crtc_vtotal += 1;
  4185. pipe_config->adjusted_mode.crtc_vblank_end += 1;
  4186. }
  4187. tmp = I915_READ(PIPESRC(crtc->pipe));
  4188. pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
  4189. pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
  4190. pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
  4191. pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
  4192. }
  4193. static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
  4194. struct intel_crtc_config *pipe_config)
  4195. {
  4196. struct drm_crtc *crtc = &intel_crtc->base;
  4197. crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
  4198. crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
  4199. crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
  4200. crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
  4201. crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
  4202. crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
  4203. crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
  4204. crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
  4205. crtc->mode.flags = pipe_config->adjusted_mode.flags;
  4206. crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
  4207. crtc->mode.flags |= pipe_config->adjusted_mode.flags;
  4208. }
  4209. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  4210. {
  4211. struct drm_device *dev = intel_crtc->base.dev;
  4212. struct drm_i915_private *dev_priv = dev->dev_private;
  4213. uint32_t pipeconf;
  4214. pipeconf = 0;
  4215. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  4216. I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
  4217. pipeconf |= PIPECONF_ENABLE;
  4218. if (intel_crtc->config.double_wide)
  4219. pipeconf |= PIPECONF_DOUBLE_WIDE;
  4220. /* only g4x and later have fancy bpc/dither controls */
  4221. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4222. /* Bspec claims that we can't use dithering for 30bpp pipes. */
  4223. if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
  4224. pipeconf |= PIPECONF_DITHER_EN |
  4225. PIPECONF_DITHER_TYPE_SP;
  4226. switch (intel_crtc->config.pipe_bpp) {
  4227. case 18:
  4228. pipeconf |= PIPECONF_6BPC;
  4229. break;
  4230. case 24:
  4231. pipeconf |= PIPECONF_8BPC;
  4232. break;
  4233. case 30:
  4234. pipeconf |= PIPECONF_10BPC;
  4235. break;
  4236. default:
  4237. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4238. BUG();
  4239. }
  4240. }
  4241. if (HAS_PIPE_CXSR(dev)) {
  4242. if (intel_crtc->lowfreq_avail) {
  4243. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4244. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4245. } else {
  4246. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4247. }
  4248. }
  4249. if (!IS_GEN2(dev) &&
  4250. intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4251. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4252. else
  4253. pipeconf |= PIPECONF_PROGRESSIVE;
  4254. if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
  4255. pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  4256. I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  4257. POSTING_READ(PIPECONF(intel_crtc->pipe));
  4258. }
  4259. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4260. int x, int y,
  4261. struct drm_framebuffer *fb)
  4262. {
  4263. struct drm_device *dev = crtc->dev;
  4264. struct drm_i915_private *dev_priv = dev->dev_private;
  4265. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4266. int pipe = intel_crtc->pipe;
  4267. int plane = intel_crtc->plane;
  4268. int refclk, num_connectors = 0;
  4269. intel_clock_t clock, reduced_clock;
  4270. u32 dspcntr;
  4271. bool ok, has_reduced_clock = false;
  4272. bool is_lvds = false, is_dsi = false;
  4273. struct intel_encoder *encoder;
  4274. const intel_limit_t *limit;
  4275. int ret;
  4276. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4277. switch (encoder->type) {
  4278. case INTEL_OUTPUT_LVDS:
  4279. is_lvds = true;
  4280. break;
  4281. case INTEL_OUTPUT_DSI:
  4282. is_dsi = true;
  4283. break;
  4284. }
  4285. num_connectors++;
  4286. }
  4287. if (is_dsi)
  4288. goto skip_dpll;
  4289. if (!intel_crtc->config.clock_set) {
  4290. refclk = i9xx_get_refclk(crtc, num_connectors);
  4291. /*
  4292. * Returns a set of divisors for the desired target clock with
  4293. * the given refclk, or FALSE. The returned values represent
  4294. * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
  4295. * 2) / p1 / p2.
  4296. */
  4297. limit = intel_limit(crtc, refclk);
  4298. ok = dev_priv->display.find_dpll(limit, crtc,
  4299. intel_crtc->config.port_clock,
  4300. refclk, NULL, &clock);
  4301. if (!ok) {
  4302. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4303. return -EINVAL;
  4304. }
  4305. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4306. /*
  4307. * Ensure we match the reduced clock's P to the target
  4308. * clock. If the clocks don't match, we can't switch
  4309. * the display clock by using the FP0/FP1. In such case
  4310. * we will disable the LVDS downclock feature.
  4311. */
  4312. has_reduced_clock =
  4313. dev_priv->display.find_dpll(limit, crtc,
  4314. dev_priv->lvds_downclock,
  4315. refclk, &clock,
  4316. &reduced_clock);
  4317. }
  4318. /* Compat-code for transition, will disappear. */
  4319. intel_crtc->config.dpll.n = clock.n;
  4320. intel_crtc->config.dpll.m1 = clock.m1;
  4321. intel_crtc->config.dpll.m2 = clock.m2;
  4322. intel_crtc->config.dpll.p1 = clock.p1;
  4323. intel_crtc->config.dpll.p2 = clock.p2;
  4324. }
  4325. if (IS_GEN2(dev)) {
  4326. i8xx_update_pll(intel_crtc,
  4327. has_reduced_clock ? &reduced_clock : NULL,
  4328. num_connectors);
  4329. } else if (IS_VALLEYVIEW(dev)) {
  4330. vlv_update_pll(intel_crtc);
  4331. } else {
  4332. i9xx_update_pll(intel_crtc,
  4333. has_reduced_clock ? &reduced_clock : NULL,
  4334. num_connectors);
  4335. }
  4336. skip_dpll:
  4337. /* Set up the display plane register */
  4338. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4339. if (!IS_VALLEYVIEW(dev)) {
  4340. if (pipe == 0)
  4341. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4342. else
  4343. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4344. }
  4345. intel_set_pipe_timings(intel_crtc);
  4346. /* pipesrc and dspsize control the size that is scaled from,
  4347. * which should always be the user's requested size.
  4348. */
  4349. I915_WRITE(DSPSIZE(plane),
  4350. ((intel_crtc->config.pipe_src_h - 1) << 16) |
  4351. (intel_crtc->config.pipe_src_w - 1));
  4352. I915_WRITE(DSPPOS(plane), 0);
  4353. i9xx_set_pipeconf(intel_crtc);
  4354. I915_WRITE(DSPCNTR(plane), dspcntr);
  4355. POSTING_READ(DSPCNTR(plane));
  4356. ret = intel_pipe_set_base(crtc, x, y, fb);
  4357. return ret;
  4358. }
  4359. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  4360. struct intel_crtc_config *pipe_config)
  4361. {
  4362. struct drm_device *dev = crtc->base.dev;
  4363. struct drm_i915_private *dev_priv = dev->dev_private;
  4364. uint32_t tmp;
  4365. tmp = I915_READ(PFIT_CONTROL);
  4366. if (!(tmp & PFIT_ENABLE))
  4367. return;
  4368. /* Check whether the pfit is attached to our pipe. */
  4369. if (INTEL_INFO(dev)->gen < 4) {
  4370. if (crtc->pipe != PIPE_B)
  4371. return;
  4372. } else {
  4373. if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  4374. return;
  4375. }
  4376. pipe_config->gmch_pfit.control = tmp;
  4377. pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  4378. if (INTEL_INFO(dev)->gen < 5)
  4379. pipe_config->gmch_pfit.lvds_border_bits =
  4380. I915_READ(LVDS) & LVDS_BORDER_ENABLE;
  4381. }
  4382. static void vlv_crtc_clock_get(struct intel_crtc *crtc,
  4383. struct intel_crtc_config *pipe_config)
  4384. {
  4385. struct drm_device *dev = crtc->base.dev;
  4386. struct drm_i915_private *dev_priv = dev->dev_private;
  4387. int pipe = pipe_config->cpu_transcoder;
  4388. intel_clock_t clock;
  4389. u32 mdiv;
  4390. int refclk = 100000;
  4391. mutex_lock(&dev_priv->dpio_lock);
  4392. mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
  4393. mutex_unlock(&dev_priv->dpio_lock);
  4394. clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
  4395. clock.m2 = mdiv & DPIO_M2DIV_MASK;
  4396. clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
  4397. clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
  4398. clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
  4399. vlv_clock(refclk, &clock);
  4400. /* clock.dot is the fast clock */
  4401. pipe_config->port_clock = clock.dot / 5;
  4402. }
  4403. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  4404. struct intel_crtc_config *pipe_config)
  4405. {
  4406. struct drm_device *dev = crtc->base.dev;
  4407. struct drm_i915_private *dev_priv = dev->dev_private;
  4408. uint32_t tmp;
  4409. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  4410. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  4411. tmp = I915_READ(PIPECONF(crtc->pipe));
  4412. if (!(tmp & PIPECONF_ENABLE))
  4413. return false;
  4414. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4415. switch (tmp & PIPECONF_BPC_MASK) {
  4416. case PIPECONF_6BPC:
  4417. pipe_config->pipe_bpp = 18;
  4418. break;
  4419. case PIPECONF_8BPC:
  4420. pipe_config->pipe_bpp = 24;
  4421. break;
  4422. case PIPECONF_10BPC:
  4423. pipe_config->pipe_bpp = 30;
  4424. break;
  4425. default:
  4426. break;
  4427. }
  4428. }
  4429. if (INTEL_INFO(dev)->gen < 4)
  4430. pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
  4431. intel_get_pipe_timings(crtc, pipe_config);
  4432. i9xx_get_pfit_config(crtc, pipe_config);
  4433. if (INTEL_INFO(dev)->gen >= 4) {
  4434. tmp = I915_READ(DPLL_MD(crtc->pipe));
  4435. pipe_config->pixel_multiplier =
  4436. ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  4437. >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  4438. pipe_config->dpll_hw_state.dpll_md = tmp;
  4439. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  4440. tmp = I915_READ(DPLL(crtc->pipe));
  4441. pipe_config->pixel_multiplier =
  4442. ((tmp & SDVO_MULTIPLIER_MASK)
  4443. >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  4444. } else {
  4445. /* Note that on i915G/GM the pixel multiplier is in the sdvo
  4446. * port and will be fixed up in the encoder->get_config
  4447. * function. */
  4448. pipe_config->pixel_multiplier = 1;
  4449. }
  4450. pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  4451. if (!IS_VALLEYVIEW(dev)) {
  4452. pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  4453. pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  4454. } else {
  4455. /* Mask out read-only status bits. */
  4456. pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  4457. DPLL_PORTC_READY_MASK |
  4458. DPLL_PORTB_READY_MASK);
  4459. }
  4460. if (IS_VALLEYVIEW(dev))
  4461. vlv_crtc_clock_get(crtc, pipe_config);
  4462. else
  4463. i9xx_crtc_clock_get(crtc, pipe_config);
  4464. return true;
  4465. }
  4466. static void ironlake_init_pch_refclk(struct drm_device *dev)
  4467. {
  4468. struct drm_i915_private *dev_priv = dev->dev_private;
  4469. struct drm_mode_config *mode_config = &dev->mode_config;
  4470. struct intel_encoder *encoder;
  4471. u32 val, final;
  4472. bool has_lvds = false;
  4473. bool has_cpu_edp = false;
  4474. bool has_panel = false;
  4475. bool has_ck505 = false;
  4476. bool can_ssc = false;
  4477. /* We need to take the global config into account */
  4478. list_for_each_entry(encoder, &mode_config->encoder_list,
  4479. base.head) {
  4480. switch (encoder->type) {
  4481. case INTEL_OUTPUT_LVDS:
  4482. has_panel = true;
  4483. has_lvds = true;
  4484. break;
  4485. case INTEL_OUTPUT_EDP:
  4486. has_panel = true;
  4487. if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  4488. has_cpu_edp = true;
  4489. break;
  4490. }
  4491. }
  4492. if (HAS_PCH_IBX(dev)) {
  4493. has_ck505 = dev_priv->vbt.display_clock_mode;
  4494. can_ssc = has_ck505;
  4495. } else {
  4496. has_ck505 = false;
  4497. can_ssc = true;
  4498. }
  4499. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  4500. has_panel, has_lvds, has_ck505);
  4501. /* Ironlake: try to setup display ref clock before DPLL
  4502. * enabling. This is only under driver's control after
  4503. * PCH B stepping, previous chipset stepping should be
  4504. * ignoring this setting.
  4505. */
  4506. val = I915_READ(PCH_DREF_CONTROL);
  4507. /* As we must carefully and slowly disable/enable each source in turn,
  4508. * compute the final state we want first and check if we need to
  4509. * make any changes at all.
  4510. */
  4511. final = val;
  4512. final &= ~DREF_NONSPREAD_SOURCE_MASK;
  4513. if (has_ck505)
  4514. final |= DREF_NONSPREAD_CK505_ENABLE;
  4515. else
  4516. final |= DREF_NONSPREAD_SOURCE_ENABLE;
  4517. final &= ~DREF_SSC_SOURCE_MASK;
  4518. final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4519. final &= ~DREF_SSC1_ENABLE;
  4520. if (has_panel) {
  4521. final |= DREF_SSC_SOURCE_ENABLE;
  4522. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4523. final |= DREF_SSC1_ENABLE;
  4524. if (has_cpu_edp) {
  4525. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4526. final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4527. else
  4528. final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4529. } else
  4530. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4531. } else {
  4532. final |= DREF_SSC_SOURCE_DISABLE;
  4533. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4534. }
  4535. if (final == val)
  4536. return;
  4537. /* Always enable nonspread source */
  4538. val &= ~DREF_NONSPREAD_SOURCE_MASK;
  4539. if (has_ck505)
  4540. val |= DREF_NONSPREAD_CK505_ENABLE;
  4541. else
  4542. val |= DREF_NONSPREAD_SOURCE_ENABLE;
  4543. if (has_panel) {
  4544. val &= ~DREF_SSC_SOURCE_MASK;
  4545. val |= DREF_SSC_SOURCE_ENABLE;
  4546. /* SSC must be turned on before enabling the CPU output */
  4547. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4548. DRM_DEBUG_KMS("Using SSC on panel\n");
  4549. val |= DREF_SSC1_ENABLE;
  4550. } else
  4551. val &= ~DREF_SSC1_ENABLE;
  4552. /* Get SSC going before enabling the outputs */
  4553. I915_WRITE(PCH_DREF_CONTROL, val);
  4554. POSTING_READ(PCH_DREF_CONTROL);
  4555. udelay(200);
  4556. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4557. /* Enable CPU source on CPU attached eDP */
  4558. if (has_cpu_edp) {
  4559. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4560. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4561. val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4562. }
  4563. else
  4564. val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4565. } else
  4566. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4567. I915_WRITE(PCH_DREF_CONTROL, val);
  4568. POSTING_READ(PCH_DREF_CONTROL);
  4569. udelay(200);
  4570. } else {
  4571. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4572. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4573. /* Turn off CPU output */
  4574. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4575. I915_WRITE(PCH_DREF_CONTROL, val);
  4576. POSTING_READ(PCH_DREF_CONTROL);
  4577. udelay(200);
  4578. /* Turn off the SSC source */
  4579. val &= ~DREF_SSC_SOURCE_MASK;
  4580. val |= DREF_SSC_SOURCE_DISABLE;
  4581. /* Turn off SSC1 */
  4582. val &= ~DREF_SSC1_ENABLE;
  4583. I915_WRITE(PCH_DREF_CONTROL, val);
  4584. POSTING_READ(PCH_DREF_CONTROL);
  4585. udelay(200);
  4586. }
  4587. BUG_ON(val != final);
  4588. }
  4589. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  4590. {
  4591. uint32_t tmp;
  4592. tmp = I915_READ(SOUTH_CHICKEN2);
  4593. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  4594. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4595. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  4596. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  4597. DRM_ERROR("FDI mPHY reset assert timeout\n");
  4598. tmp = I915_READ(SOUTH_CHICKEN2);
  4599. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  4600. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4601. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  4602. FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  4603. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  4604. }
  4605. /* WaMPhyProgramming:hsw */
  4606. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  4607. {
  4608. uint32_t tmp;
  4609. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  4610. tmp &= ~(0xFF << 24);
  4611. tmp |= (0x12 << 24);
  4612. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  4613. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  4614. tmp |= (1 << 11);
  4615. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  4616. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  4617. tmp |= (1 << 11);
  4618. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  4619. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  4620. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4621. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  4622. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  4623. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4624. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  4625. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  4626. tmp &= ~(7 << 13);
  4627. tmp |= (5 << 13);
  4628. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  4629. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  4630. tmp &= ~(7 << 13);
  4631. tmp |= (5 << 13);
  4632. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  4633. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  4634. tmp &= ~0xFF;
  4635. tmp |= 0x1C;
  4636. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  4637. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  4638. tmp &= ~0xFF;
  4639. tmp |= 0x1C;
  4640. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  4641. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  4642. tmp &= ~(0xFF << 16);
  4643. tmp |= (0x1C << 16);
  4644. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  4645. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  4646. tmp &= ~(0xFF << 16);
  4647. tmp |= (0x1C << 16);
  4648. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  4649. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  4650. tmp |= (1 << 27);
  4651. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  4652. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  4653. tmp |= (1 << 27);
  4654. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  4655. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  4656. tmp &= ~(0xF << 28);
  4657. tmp |= (4 << 28);
  4658. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  4659. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  4660. tmp &= ~(0xF << 28);
  4661. tmp |= (4 << 28);
  4662. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  4663. }
  4664. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  4665. * Programming" based on the parameters passed:
  4666. * - Sequence to enable CLKOUT_DP
  4667. * - Sequence to enable CLKOUT_DP without spread
  4668. * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  4669. */
  4670. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  4671. bool with_fdi)
  4672. {
  4673. struct drm_i915_private *dev_priv = dev->dev_private;
  4674. uint32_t reg, tmp;
  4675. if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  4676. with_spread = true;
  4677. if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
  4678. with_fdi, "LP PCH doesn't have FDI\n"))
  4679. with_fdi = false;
  4680. mutex_lock(&dev_priv->dpio_lock);
  4681. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4682. tmp &= ~SBI_SSCCTL_DISABLE;
  4683. tmp |= SBI_SSCCTL_PATHALT;
  4684. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4685. udelay(24);
  4686. if (with_spread) {
  4687. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4688. tmp &= ~SBI_SSCCTL_PATHALT;
  4689. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4690. if (with_fdi) {
  4691. lpt_reset_fdi_mphy(dev_priv);
  4692. lpt_program_fdi_mphy(dev_priv);
  4693. }
  4694. }
  4695. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4696. SBI_GEN0 : SBI_DBUFF0;
  4697. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4698. tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4699. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4700. mutex_unlock(&dev_priv->dpio_lock);
  4701. }
  4702. /* Sequence to disable CLKOUT_DP */
  4703. static void lpt_disable_clkout_dp(struct drm_device *dev)
  4704. {
  4705. struct drm_i915_private *dev_priv = dev->dev_private;
  4706. uint32_t reg, tmp;
  4707. mutex_lock(&dev_priv->dpio_lock);
  4708. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4709. SBI_GEN0 : SBI_DBUFF0;
  4710. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4711. tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4712. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4713. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4714. if (!(tmp & SBI_SSCCTL_DISABLE)) {
  4715. if (!(tmp & SBI_SSCCTL_PATHALT)) {
  4716. tmp |= SBI_SSCCTL_PATHALT;
  4717. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4718. udelay(32);
  4719. }
  4720. tmp |= SBI_SSCCTL_DISABLE;
  4721. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4722. }
  4723. mutex_unlock(&dev_priv->dpio_lock);
  4724. }
  4725. static void lpt_init_pch_refclk(struct drm_device *dev)
  4726. {
  4727. struct drm_mode_config *mode_config = &dev->mode_config;
  4728. struct intel_encoder *encoder;
  4729. bool has_vga = false;
  4730. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4731. switch (encoder->type) {
  4732. case INTEL_OUTPUT_ANALOG:
  4733. has_vga = true;
  4734. break;
  4735. }
  4736. }
  4737. if (has_vga)
  4738. lpt_enable_clkout_dp(dev, true, true);
  4739. else
  4740. lpt_disable_clkout_dp(dev);
  4741. }
  4742. /*
  4743. * Initialize reference clocks when the driver loads
  4744. */
  4745. void intel_init_pch_refclk(struct drm_device *dev)
  4746. {
  4747. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4748. ironlake_init_pch_refclk(dev);
  4749. else if (HAS_PCH_LPT(dev))
  4750. lpt_init_pch_refclk(dev);
  4751. }
  4752. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4753. {
  4754. struct drm_device *dev = crtc->dev;
  4755. struct drm_i915_private *dev_priv = dev->dev_private;
  4756. struct intel_encoder *encoder;
  4757. int num_connectors = 0;
  4758. bool is_lvds = false;
  4759. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4760. switch (encoder->type) {
  4761. case INTEL_OUTPUT_LVDS:
  4762. is_lvds = true;
  4763. break;
  4764. }
  4765. num_connectors++;
  4766. }
  4767. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4768. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4769. dev_priv->vbt.lvds_ssc_freq);
  4770. return dev_priv->vbt.lvds_ssc_freq * 1000;
  4771. }
  4772. return 120000;
  4773. }
  4774. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  4775. {
  4776. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4777. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4778. int pipe = intel_crtc->pipe;
  4779. uint32_t val;
  4780. val = 0;
  4781. switch (intel_crtc->config.pipe_bpp) {
  4782. case 18:
  4783. val |= PIPECONF_6BPC;
  4784. break;
  4785. case 24:
  4786. val |= PIPECONF_8BPC;
  4787. break;
  4788. case 30:
  4789. val |= PIPECONF_10BPC;
  4790. break;
  4791. case 36:
  4792. val |= PIPECONF_12BPC;
  4793. break;
  4794. default:
  4795. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4796. BUG();
  4797. }
  4798. if (intel_crtc->config.dither)
  4799. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4800. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4801. val |= PIPECONF_INTERLACED_ILK;
  4802. else
  4803. val |= PIPECONF_PROGRESSIVE;
  4804. if (intel_crtc->config.limited_color_range)
  4805. val |= PIPECONF_COLOR_RANGE_SELECT;
  4806. I915_WRITE(PIPECONF(pipe), val);
  4807. POSTING_READ(PIPECONF(pipe));
  4808. }
  4809. /*
  4810. * Set up the pipe CSC unit.
  4811. *
  4812. * Currently only full range RGB to limited range RGB conversion
  4813. * is supported, but eventually this should handle various
  4814. * RGB<->YCbCr scenarios as well.
  4815. */
  4816. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  4817. {
  4818. struct drm_device *dev = crtc->dev;
  4819. struct drm_i915_private *dev_priv = dev->dev_private;
  4820. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4821. int pipe = intel_crtc->pipe;
  4822. uint16_t coeff = 0x7800; /* 1.0 */
  4823. /*
  4824. * TODO: Check what kind of values actually come out of the pipe
  4825. * with these coeff/postoff values and adjust to get the best
  4826. * accuracy. Perhaps we even need to take the bpc value into
  4827. * consideration.
  4828. */
  4829. if (intel_crtc->config.limited_color_range)
  4830. coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  4831. /*
  4832. * GY/GU and RY/RU should be the other way around according
  4833. * to BSpec, but reality doesn't agree. Just set them up in
  4834. * a way that results in the correct picture.
  4835. */
  4836. I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  4837. I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  4838. I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  4839. I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  4840. I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  4841. I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  4842. I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  4843. I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  4844. I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  4845. if (INTEL_INFO(dev)->gen > 6) {
  4846. uint16_t postoff = 0;
  4847. if (intel_crtc->config.limited_color_range)
  4848. postoff = (16 * (1 << 13) / 255) & 0x1fff;
  4849. I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  4850. I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  4851. I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  4852. I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  4853. } else {
  4854. uint32_t mode = CSC_MODE_YUV_TO_RGB;
  4855. if (intel_crtc->config.limited_color_range)
  4856. mode |= CSC_BLACK_SCREEN_OFFSET;
  4857. I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  4858. }
  4859. }
  4860. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  4861. {
  4862. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4863. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4864. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4865. uint32_t val;
  4866. val = 0;
  4867. if (intel_crtc->config.dither)
  4868. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4869. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4870. val |= PIPECONF_INTERLACED_ILK;
  4871. else
  4872. val |= PIPECONF_PROGRESSIVE;
  4873. I915_WRITE(PIPECONF(cpu_transcoder), val);
  4874. POSTING_READ(PIPECONF(cpu_transcoder));
  4875. I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
  4876. POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
  4877. }
  4878. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  4879. intel_clock_t *clock,
  4880. bool *has_reduced_clock,
  4881. intel_clock_t *reduced_clock)
  4882. {
  4883. struct drm_device *dev = crtc->dev;
  4884. struct drm_i915_private *dev_priv = dev->dev_private;
  4885. struct intel_encoder *intel_encoder;
  4886. int refclk;
  4887. const intel_limit_t *limit;
  4888. bool ret, is_lvds = false;
  4889. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4890. switch (intel_encoder->type) {
  4891. case INTEL_OUTPUT_LVDS:
  4892. is_lvds = true;
  4893. break;
  4894. }
  4895. }
  4896. refclk = ironlake_get_refclk(crtc);
  4897. /*
  4898. * Returns a set of divisors for the desired target clock with the given
  4899. * refclk, or FALSE. The returned values represent the clock equation:
  4900. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4901. */
  4902. limit = intel_limit(crtc, refclk);
  4903. ret = dev_priv->display.find_dpll(limit, crtc,
  4904. to_intel_crtc(crtc)->config.port_clock,
  4905. refclk, NULL, clock);
  4906. if (!ret)
  4907. return false;
  4908. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4909. /*
  4910. * Ensure we match the reduced clock's P to the target clock.
  4911. * If the clocks don't match, we can't switch the display clock
  4912. * by using the FP0/FP1. In such case we will disable the LVDS
  4913. * downclock feature.
  4914. */
  4915. *has_reduced_clock =
  4916. dev_priv->display.find_dpll(limit, crtc,
  4917. dev_priv->lvds_downclock,
  4918. refclk, clock,
  4919. reduced_clock);
  4920. }
  4921. return true;
  4922. }
  4923. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  4924. {
  4925. struct drm_i915_private *dev_priv = dev->dev_private;
  4926. uint32_t temp;
  4927. temp = I915_READ(SOUTH_CHICKEN1);
  4928. if (temp & FDI_BC_BIFURCATION_SELECT)
  4929. return;
  4930. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4931. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4932. temp |= FDI_BC_BIFURCATION_SELECT;
  4933. DRM_DEBUG_KMS("enabling fdi C rx\n");
  4934. I915_WRITE(SOUTH_CHICKEN1, temp);
  4935. POSTING_READ(SOUTH_CHICKEN1);
  4936. }
  4937. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  4938. {
  4939. struct drm_device *dev = intel_crtc->base.dev;
  4940. struct drm_i915_private *dev_priv = dev->dev_private;
  4941. switch (intel_crtc->pipe) {
  4942. case PIPE_A:
  4943. break;
  4944. case PIPE_B:
  4945. if (intel_crtc->config.fdi_lanes > 2)
  4946. WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  4947. else
  4948. cpt_enable_fdi_bc_bifurcation(dev);
  4949. break;
  4950. case PIPE_C:
  4951. cpt_enable_fdi_bc_bifurcation(dev);
  4952. break;
  4953. default:
  4954. BUG();
  4955. }
  4956. }
  4957. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  4958. {
  4959. /*
  4960. * Account for spread spectrum to avoid
  4961. * oversubscribing the link. Max center spread
  4962. * is 2.5%; use 5% for safety's sake.
  4963. */
  4964. u32 bps = target_clock * bpp * 21 / 20;
  4965. return bps / (link_bw * 8) + 1;
  4966. }
  4967. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  4968. {
  4969. return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  4970. }
  4971. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  4972. u32 *fp,
  4973. intel_clock_t *reduced_clock, u32 *fp2)
  4974. {
  4975. struct drm_crtc *crtc = &intel_crtc->base;
  4976. struct drm_device *dev = crtc->dev;
  4977. struct drm_i915_private *dev_priv = dev->dev_private;
  4978. struct intel_encoder *intel_encoder;
  4979. uint32_t dpll;
  4980. int factor, num_connectors = 0;
  4981. bool is_lvds = false, is_sdvo = false;
  4982. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4983. switch (intel_encoder->type) {
  4984. case INTEL_OUTPUT_LVDS:
  4985. is_lvds = true;
  4986. break;
  4987. case INTEL_OUTPUT_SDVO:
  4988. case INTEL_OUTPUT_HDMI:
  4989. is_sdvo = true;
  4990. break;
  4991. }
  4992. num_connectors++;
  4993. }
  4994. /* Enable autotuning of the PLL clock (if permissible) */
  4995. factor = 21;
  4996. if (is_lvds) {
  4997. if ((intel_panel_use_ssc(dev_priv) &&
  4998. dev_priv->vbt.lvds_ssc_freq == 100) ||
  4999. (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  5000. factor = 25;
  5001. } else if (intel_crtc->config.sdvo_tv_clock)
  5002. factor = 20;
  5003. if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
  5004. *fp |= FP_CB_TUNE;
  5005. if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  5006. *fp2 |= FP_CB_TUNE;
  5007. dpll = 0;
  5008. if (is_lvds)
  5009. dpll |= DPLLB_MODE_LVDS;
  5010. else
  5011. dpll |= DPLLB_MODE_DAC_SERIAL;
  5012. dpll |= (intel_crtc->config.pixel_multiplier - 1)
  5013. << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  5014. if (is_sdvo)
  5015. dpll |= DPLL_SDVO_HIGH_SPEED;
  5016. if (intel_crtc->config.has_dp_encoder)
  5017. dpll |= DPLL_SDVO_HIGH_SPEED;
  5018. /* compute bitmask from p1 value */
  5019. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  5020. /* also FPA1 */
  5021. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  5022. switch (intel_crtc->config.dpll.p2) {
  5023. case 5:
  5024. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  5025. break;
  5026. case 7:
  5027. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  5028. break;
  5029. case 10:
  5030. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  5031. break;
  5032. case 14:
  5033. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  5034. break;
  5035. }
  5036. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  5037. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  5038. else
  5039. dpll |= PLL_REF_INPUT_DREFCLK;
  5040. return dpll | DPLL_VCO_ENABLE;
  5041. }
  5042. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  5043. int x, int y,
  5044. struct drm_framebuffer *fb)
  5045. {
  5046. struct drm_device *dev = crtc->dev;
  5047. struct drm_i915_private *dev_priv = dev->dev_private;
  5048. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5049. int pipe = intel_crtc->pipe;
  5050. int plane = intel_crtc->plane;
  5051. int num_connectors = 0;
  5052. intel_clock_t clock, reduced_clock;
  5053. u32 dpll = 0, fp = 0, fp2 = 0;
  5054. bool ok, has_reduced_clock = false;
  5055. bool is_lvds = false;
  5056. struct intel_encoder *encoder;
  5057. struct intel_shared_dpll *pll;
  5058. int ret;
  5059. for_each_encoder_on_crtc(dev, crtc, encoder) {
  5060. switch (encoder->type) {
  5061. case INTEL_OUTPUT_LVDS:
  5062. is_lvds = true;
  5063. break;
  5064. }
  5065. num_connectors++;
  5066. }
  5067. WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  5068. "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  5069. ok = ironlake_compute_clocks(crtc, &clock,
  5070. &has_reduced_clock, &reduced_clock);
  5071. if (!ok && !intel_crtc->config.clock_set) {
  5072. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  5073. return -EINVAL;
  5074. }
  5075. /* Compat-code for transition, will disappear. */
  5076. if (!intel_crtc->config.clock_set) {
  5077. intel_crtc->config.dpll.n = clock.n;
  5078. intel_crtc->config.dpll.m1 = clock.m1;
  5079. intel_crtc->config.dpll.m2 = clock.m2;
  5080. intel_crtc->config.dpll.p1 = clock.p1;
  5081. intel_crtc->config.dpll.p2 = clock.p2;
  5082. }
  5083. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  5084. if (intel_crtc->config.has_pch_encoder) {
  5085. fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
  5086. if (has_reduced_clock)
  5087. fp2 = i9xx_dpll_compute_fp(&reduced_clock);
  5088. dpll = ironlake_compute_dpll(intel_crtc,
  5089. &fp, &reduced_clock,
  5090. has_reduced_clock ? &fp2 : NULL);
  5091. intel_crtc->config.dpll_hw_state.dpll = dpll;
  5092. intel_crtc->config.dpll_hw_state.fp0 = fp;
  5093. if (has_reduced_clock)
  5094. intel_crtc->config.dpll_hw_state.fp1 = fp2;
  5095. else
  5096. intel_crtc->config.dpll_hw_state.fp1 = fp;
  5097. pll = intel_get_shared_dpll(intel_crtc);
  5098. if (pll == NULL) {
  5099. DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  5100. pipe_name(pipe));
  5101. return -EINVAL;
  5102. }
  5103. } else
  5104. intel_put_shared_dpll(intel_crtc);
  5105. if (intel_crtc->config.has_dp_encoder)
  5106. intel_dp_set_m_n(intel_crtc);
  5107. if (is_lvds && has_reduced_clock && i915_powersave)
  5108. intel_crtc->lowfreq_avail = true;
  5109. else
  5110. intel_crtc->lowfreq_avail = false;
  5111. if (intel_crtc->config.has_pch_encoder) {
  5112. pll = intel_crtc_to_shared_dpll(intel_crtc);
  5113. }
  5114. intel_set_pipe_timings(intel_crtc);
  5115. if (intel_crtc->config.has_pch_encoder) {
  5116. intel_cpu_transcoder_set_m_n(intel_crtc,
  5117. &intel_crtc->config.fdi_m_n);
  5118. }
  5119. if (IS_IVYBRIDGE(dev))
  5120. ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  5121. ironlake_set_pipeconf(crtc);
  5122. /* Set up the display plane register */
  5123. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  5124. POSTING_READ(DSPCNTR(plane));
  5125. ret = intel_pipe_set_base(crtc, x, y, fb);
  5126. return ret;
  5127. }
  5128. static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
  5129. struct intel_link_m_n *m_n)
  5130. {
  5131. struct drm_device *dev = crtc->base.dev;
  5132. struct drm_i915_private *dev_priv = dev->dev_private;
  5133. enum pipe pipe = crtc->pipe;
  5134. m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
  5135. m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
  5136. m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
  5137. & ~TU_SIZE_MASK;
  5138. m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
  5139. m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
  5140. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5141. }
  5142. static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
  5143. enum transcoder transcoder,
  5144. struct intel_link_m_n *m_n)
  5145. {
  5146. struct drm_device *dev = crtc->base.dev;
  5147. struct drm_i915_private *dev_priv = dev->dev_private;
  5148. enum pipe pipe = crtc->pipe;
  5149. if (INTEL_INFO(dev)->gen >= 5) {
  5150. m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
  5151. m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
  5152. m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  5153. & ~TU_SIZE_MASK;
  5154. m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  5155. m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  5156. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5157. } else {
  5158. m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
  5159. m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
  5160. m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
  5161. & ~TU_SIZE_MASK;
  5162. m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
  5163. m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
  5164. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5165. }
  5166. }
  5167. void intel_dp_get_m_n(struct intel_crtc *crtc,
  5168. struct intel_crtc_config *pipe_config)
  5169. {
  5170. if (crtc->config.has_pch_encoder)
  5171. intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
  5172. else
  5173. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  5174. &pipe_config->dp_m_n);
  5175. }
  5176. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  5177. struct intel_crtc_config *pipe_config)
  5178. {
  5179. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  5180. &pipe_config->fdi_m_n);
  5181. }
  5182. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  5183. struct intel_crtc_config *pipe_config)
  5184. {
  5185. struct drm_device *dev = crtc->base.dev;
  5186. struct drm_i915_private *dev_priv = dev->dev_private;
  5187. uint32_t tmp;
  5188. tmp = I915_READ(PF_CTL(crtc->pipe));
  5189. if (tmp & PF_ENABLE) {
  5190. pipe_config->pch_pfit.enabled = true;
  5191. pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  5192. pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  5193. /* We currently do not free assignements of panel fitters on
  5194. * ivb/hsw (since we don't use the higher upscaling modes which
  5195. * differentiates them) so just WARN about this case for now. */
  5196. if (IS_GEN7(dev)) {
  5197. WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  5198. PF_PIPE_SEL_IVB(crtc->pipe));
  5199. }
  5200. }
  5201. }
  5202. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  5203. struct intel_crtc_config *pipe_config)
  5204. {
  5205. struct drm_device *dev = crtc->base.dev;
  5206. struct drm_i915_private *dev_priv = dev->dev_private;
  5207. uint32_t tmp;
  5208. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5209. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5210. tmp = I915_READ(PIPECONF(crtc->pipe));
  5211. if (!(tmp & PIPECONF_ENABLE))
  5212. return false;
  5213. switch (tmp & PIPECONF_BPC_MASK) {
  5214. case PIPECONF_6BPC:
  5215. pipe_config->pipe_bpp = 18;
  5216. break;
  5217. case PIPECONF_8BPC:
  5218. pipe_config->pipe_bpp = 24;
  5219. break;
  5220. case PIPECONF_10BPC:
  5221. pipe_config->pipe_bpp = 30;
  5222. break;
  5223. case PIPECONF_12BPC:
  5224. pipe_config->pipe_bpp = 36;
  5225. break;
  5226. default:
  5227. break;
  5228. }
  5229. if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  5230. struct intel_shared_dpll *pll;
  5231. pipe_config->has_pch_encoder = true;
  5232. tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  5233. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5234. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5235. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5236. if (HAS_PCH_IBX(dev_priv->dev)) {
  5237. pipe_config->shared_dpll =
  5238. (enum intel_dpll_id) crtc->pipe;
  5239. } else {
  5240. tmp = I915_READ(PCH_DPLL_SEL);
  5241. if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  5242. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
  5243. else
  5244. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
  5245. }
  5246. pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  5247. WARN_ON(!pll->get_hw_state(dev_priv, pll,
  5248. &pipe_config->dpll_hw_state));
  5249. tmp = pipe_config->dpll_hw_state.dpll;
  5250. pipe_config->pixel_multiplier =
  5251. ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  5252. >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  5253. ironlake_pch_clock_get(crtc, pipe_config);
  5254. } else {
  5255. pipe_config->pixel_multiplier = 1;
  5256. }
  5257. intel_get_pipe_timings(crtc, pipe_config);
  5258. ironlake_get_pfit_config(crtc, pipe_config);
  5259. return true;
  5260. }
  5261. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  5262. {
  5263. struct drm_device *dev = dev_priv->dev;
  5264. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  5265. struct intel_crtc *crtc;
  5266. unsigned long irqflags;
  5267. uint32_t val;
  5268. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5269. WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
  5270. pipe_name(crtc->pipe));
  5271. WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  5272. WARN(plls->spll_refcount, "SPLL enabled\n");
  5273. WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
  5274. WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
  5275. WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  5276. WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  5277. "CPU PWM1 enabled\n");
  5278. WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  5279. "CPU PWM2 enabled\n");
  5280. WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  5281. "PCH PWM1 enabled\n");
  5282. WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  5283. "Utility pin enabled\n");
  5284. WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  5285. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  5286. val = I915_READ(DEIMR);
  5287. WARN((val & ~DE_PCH_EVENT_IVB) != val,
  5288. "Unexpected DEIMR bits enabled: 0x%x\n", val);
  5289. val = I915_READ(SDEIMR);
  5290. WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
  5291. "Unexpected SDEIMR bits enabled: 0x%x\n", val);
  5292. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  5293. }
  5294. /*
  5295. * This function implements pieces of two sequences from BSpec:
  5296. * - Sequence for display software to disable LCPLL
  5297. * - Sequence for display software to allow package C8+
  5298. * The steps implemented here are just the steps that actually touch the LCPLL
  5299. * register. Callers should take care of disabling all the display engine
  5300. * functions, doing the mode unset, fixing interrupts, etc.
  5301. */
  5302. static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  5303. bool switch_to_fclk, bool allow_power_down)
  5304. {
  5305. uint32_t val;
  5306. assert_can_disable_lcpll(dev_priv);
  5307. val = I915_READ(LCPLL_CTL);
  5308. if (switch_to_fclk) {
  5309. val |= LCPLL_CD_SOURCE_FCLK;
  5310. I915_WRITE(LCPLL_CTL, val);
  5311. if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  5312. LCPLL_CD_SOURCE_FCLK_DONE, 1))
  5313. DRM_ERROR("Switching to FCLK failed\n");
  5314. val = I915_READ(LCPLL_CTL);
  5315. }
  5316. val |= LCPLL_PLL_DISABLE;
  5317. I915_WRITE(LCPLL_CTL, val);
  5318. POSTING_READ(LCPLL_CTL);
  5319. if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  5320. DRM_ERROR("LCPLL still locked\n");
  5321. val = I915_READ(D_COMP);
  5322. val |= D_COMP_COMP_DISABLE;
  5323. mutex_lock(&dev_priv->rps.hw_lock);
  5324. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
  5325. DRM_ERROR("Failed to disable D_COMP\n");
  5326. mutex_unlock(&dev_priv->rps.hw_lock);
  5327. POSTING_READ(D_COMP);
  5328. ndelay(100);
  5329. if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
  5330. DRM_ERROR("D_COMP RCOMP still in progress\n");
  5331. if (allow_power_down) {
  5332. val = I915_READ(LCPLL_CTL);
  5333. val |= LCPLL_POWER_DOWN_ALLOW;
  5334. I915_WRITE(LCPLL_CTL, val);
  5335. POSTING_READ(LCPLL_CTL);
  5336. }
  5337. }
  5338. /*
  5339. * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  5340. * source.
  5341. */
  5342. static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  5343. {
  5344. uint32_t val;
  5345. val = I915_READ(LCPLL_CTL);
  5346. if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  5347. LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  5348. return;
  5349. /* Make sure we're not on PC8 state before disabling PC8, otherwise
  5350. * we'll hang the machine! */
  5351. dev_priv->uncore.funcs.force_wake_get(dev_priv);
  5352. if (val & LCPLL_POWER_DOWN_ALLOW) {
  5353. val &= ~LCPLL_POWER_DOWN_ALLOW;
  5354. I915_WRITE(LCPLL_CTL, val);
  5355. POSTING_READ(LCPLL_CTL);
  5356. }
  5357. val = I915_READ(D_COMP);
  5358. val |= D_COMP_COMP_FORCE;
  5359. val &= ~D_COMP_COMP_DISABLE;
  5360. mutex_lock(&dev_priv->rps.hw_lock);
  5361. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
  5362. DRM_ERROR("Failed to enable D_COMP\n");
  5363. mutex_unlock(&dev_priv->rps.hw_lock);
  5364. POSTING_READ(D_COMP);
  5365. val = I915_READ(LCPLL_CTL);
  5366. val &= ~LCPLL_PLL_DISABLE;
  5367. I915_WRITE(LCPLL_CTL, val);
  5368. if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  5369. DRM_ERROR("LCPLL not locked yet\n");
  5370. if (val & LCPLL_CD_SOURCE_FCLK) {
  5371. val = I915_READ(LCPLL_CTL);
  5372. val &= ~LCPLL_CD_SOURCE_FCLK;
  5373. I915_WRITE(LCPLL_CTL, val);
  5374. if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  5375. LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  5376. DRM_ERROR("Switching back to LCPLL failed\n");
  5377. }
  5378. dev_priv->uncore.funcs.force_wake_put(dev_priv);
  5379. }
  5380. void hsw_enable_pc8_work(struct work_struct *__work)
  5381. {
  5382. struct drm_i915_private *dev_priv =
  5383. container_of(to_delayed_work(__work), struct drm_i915_private,
  5384. pc8.enable_work);
  5385. struct drm_device *dev = dev_priv->dev;
  5386. uint32_t val;
  5387. if (dev_priv->pc8.enabled)
  5388. return;
  5389. DRM_DEBUG_KMS("Enabling package C8+\n");
  5390. dev_priv->pc8.enabled = true;
  5391. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  5392. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  5393. val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  5394. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  5395. }
  5396. lpt_disable_clkout_dp(dev);
  5397. hsw_pc8_disable_interrupts(dev);
  5398. hsw_disable_lcpll(dev_priv, true, true);
  5399. }
  5400. static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  5401. {
  5402. WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  5403. WARN(dev_priv->pc8.disable_count < 1,
  5404. "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  5405. dev_priv->pc8.disable_count--;
  5406. if (dev_priv->pc8.disable_count != 0)
  5407. return;
  5408. schedule_delayed_work(&dev_priv->pc8.enable_work,
  5409. msecs_to_jiffies(i915_pc8_timeout));
  5410. }
  5411. static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  5412. {
  5413. struct drm_device *dev = dev_priv->dev;
  5414. uint32_t val;
  5415. WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  5416. WARN(dev_priv->pc8.disable_count < 0,
  5417. "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  5418. dev_priv->pc8.disable_count++;
  5419. if (dev_priv->pc8.disable_count != 1)
  5420. return;
  5421. cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
  5422. if (!dev_priv->pc8.enabled)
  5423. return;
  5424. DRM_DEBUG_KMS("Disabling package C8+\n");
  5425. hsw_restore_lcpll(dev_priv);
  5426. hsw_pc8_restore_interrupts(dev);
  5427. lpt_init_pch_refclk(dev);
  5428. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  5429. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  5430. val |= PCH_LP_PARTITION_LEVEL_DISABLE;
  5431. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  5432. }
  5433. intel_prepare_ddi(dev);
  5434. i915_gem_init_swizzling(dev);
  5435. mutex_lock(&dev_priv->rps.hw_lock);
  5436. gen6_update_ring_freq(dev);
  5437. mutex_unlock(&dev_priv->rps.hw_lock);
  5438. dev_priv->pc8.enabled = false;
  5439. }
  5440. void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  5441. {
  5442. mutex_lock(&dev_priv->pc8.lock);
  5443. __hsw_enable_package_c8(dev_priv);
  5444. mutex_unlock(&dev_priv->pc8.lock);
  5445. }
  5446. void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  5447. {
  5448. mutex_lock(&dev_priv->pc8.lock);
  5449. __hsw_disable_package_c8(dev_priv);
  5450. mutex_unlock(&dev_priv->pc8.lock);
  5451. }
  5452. static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
  5453. {
  5454. struct drm_device *dev = dev_priv->dev;
  5455. struct intel_crtc *crtc;
  5456. uint32_t val;
  5457. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5458. if (crtc->base.enabled)
  5459. return false;
  5460. /* This case is still possible since we have the i915.disable_power_well
  5461. * parameter and also the KVMr or something else might be requesting the
  5462. * power well. */
  5463. val = I915_READ(HSW_PWR_WELL_DRIVER);
  5464. if (val != 0) {
  5465. DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
  5466. return false;
  5467. }
  5468. return true;
  5469. }
  5470. /* Since we're called from modeset_global_resources there's no way to
  5471. * symmetrically increase and decrease the refcount, so we use
  5472. * dev_priv->pc8.requirements_met to track whether we already have the refcount
  5473. * or not.
  5474. */
  5475. static void hsw_update_package_c8(struct drm_device *dev)
  5476. {
  5477. struct drm_i915_private *dev_priv = dev->dev_private;
  5478. bool allow;
  5479. if (!i915_enable_pc8)
  5480. return;
  5481. mutex_lock(&dev_priv->pc8.lock);
  5482. allow = hsw_can_enable_package_c8(dev_priv);
  5483. if (allow == dev_priv->pc8.requirements_met)
  5484. goto done;
  5485. dev_priv->pc8.requirements_met = allow;
  5486. if (allow)
  5487. __hsw_enable_package_c8(dev_priv);
  5488. else
  5489. __hsw_disable_package_c8(dev_priv);
  5490. done:
  5491. mutex_unlock(&dev_priv->pc8.lock);
  5492. }
  5493. static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
  5494. {
  5495. if (!dev_priv->pc8.gpu_idle) {
  5496. dev_priv->pc8.gpu_idle = true;
  5497. hsw_enable_package_c8(dev_priv);
  5498. }
  5499. }
  5500. static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
  5501. {
  5502. if (dev_priv->pc8.gpu_idle) {
  5503. dev_priv->pc8.gpu_idle = false;
  5504. hsw_disable_package_c8(dev_priv);
  5505. }
  5506. }
  5507. static void haswell_modeset_global_resources(struct drm_device *dev)
  5508. {
  5509. bool enable = false;
  5510. struct intel_crtc *crtc;
  5511. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  5512. if (!crtc->base.enabled)
  5513. continue;
  5514. if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
  5515. crtc->config.cpu_transcoder != TRANSCODER_EDP)
  5516. enable = true;
  5517. }
  5518. intel_set_power_well(dev, enable);
  5519. hsw_update_package_c8(dev);
  5520. }
  5521. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  5522. int x, int y,
  5523. struct drm_framebuffer *fb)
  5524. {
  5525. struct drm_device *dev = crtc->dev;
  5526. struct drm_i915_private *dev_priv = dev->dev_private;
  5527. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5528. int plane = intel_crtc->plane;
  5529. int ret;
  5530. if (!intel_ddi_pll_mode_set(crtc))
  5531. return -EINVAL;
  5532. if (intel_crtc->config.has_dp_encoder)
  5533. intel_dp_set_m_n(intel_crtc);
  5534. intel_crtc->lowfreq_avail = false;
  5535. intel_set_pipe_timings(intel_crtc);
  5536. if (intel_crtc->config.has_pch_encoder) {
  5537. intel_cpu_transcoder_set_m_n(intel_crtc,
  5538. &intel_crtc->config.fdi_m_n);
  5539. }
  5540. haswell_set_pipeconf(crtc);
  5541. intel_set_pipe_csc(crtc);
  5542. /* Set up the display plane register */
  5543. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
  5544. POSTING_READ(DSPCNTR(plane));
  5545. ret = intel_pipe_set_base(crtc, x, y, fb);
  5546. return ret;
  5547. }
  5548. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  5549. struct intel_crtc_config *pipe_config)
  5550. {
  5551. struct drm_device *dev = crtc->base.dev;
  5552. struct drm_i915_private *dev_priv = dev->dev_private;
  5553. enum intel_display_power_domain pfit_domain;
  5554. uint32_t tmp;
  5555. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5556. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5557. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  5558. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  5559. enum pipe trans_edp_pipe;
  5560. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  5561. default:
  5562. WARN(1, "unknown pipe linked to edp transcoder\n");
  5563. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  5564. case TRANS_DDI_EDP_INPUT_A_ON:
  5565. trans_edp_pipe = PIPE_A;
  5566. break;
  5567. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  5568. trans_edp_pipe = PIPE_B;
  5569. break;
  5570. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  5571. trans_edp_pipe = PIPE_C;
  5572. break;
  5573. }
  5574. if (trans_edp_pipe == crtc->pipe)
  5575. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  5576. }
  5577. if (!intel_display_power_enabled(dev,
  5578. POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
  5579. return false;
  5580. tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  5581. if (!(tmp & PIPECONF_ENABLE))
  5582. return false;
  5583. /*
  5584. * Haswell has only FDI/PCH transcoder A. It is which is connected to
  5585. * DDI E. So just check whether this pipe is wired to DDI E and whether
  5586. * the PCH transcoder is on.
  5587. */
  5588. tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  5589. if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
  5590. I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  5591. pipe_config->has_pch_encoder = true;
  5592. tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  5593. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5594. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5595. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5596. }
  5597. intel_get_pipe_timings(crtc, pipe_config);
  5598. pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  5599. if (intel_display_power_enabled(dev, pfit_domain))
  5600. ironlake_get_pfit_config(crtc, pipe_config);
  5601. pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  5602. (I915_READ(IPS_CTL) & IPS_ENABLE);
  5603. pipe_config->pixel_multiplier = 1;
  5604. return true;
  5605. }
  5606. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  5607. int x, int y,
  5608. struct drm_framebuffer *fb)
  5609. {
  5610. struct drm_device *dev = crtc->dev;
  5611. struct drm_i915_private *dev_priv = dev->dev_private;
  5612. struct intel_encoder *encoder;
  5613. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5614. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  5615. int pipe = intel_crtc->pipe;
  5616. int ret;
  5617. drm_vblank_pre_modeset(dev, pipe);
  5618. ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
  5619. drm_vblank_post_modeset(dev, pipe);
  5620. if (ret != 0)
  5621. return ret;
  5622. for_each_encoder_on_crtc(dev, crtc, encoder) {
  5623. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  5624. encoder->base.base.id,
  5625. drm_get_encoder_name(&encoder->base),
  5626. mode->base.id, mode->name);
  5627. encoder->mode_set(encoder);
  5628. }
  5629. return 0;
  5630. }
  5631. static bool intel_eld_uptodate(struct drm_connector *connector,
  5632. int reg_eldv, uint32_t bits_eldv,
  5633. int reg_elda, uint32_t bits_elda,
  5634. int reg_edid)
  5635. {
  5636. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5637. uint8_t *eld = connector->eld;
  5638. uint32_t i;
  5639. i = I915_READ(reg_eldv);
  5640. i &= bits_eldv;
  5641. if (!eld[0])
  5642. return !i;
  5643. if (!i)
  5644. return false;
  5645. i = I915_READ(reg_elda);
  5646. i &= ~bits_elda;
  5647. I915_WRITE(reg_elda, i);
  5648. for (i = 0; i < eld[2]; i++)
  5649. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  5650. return false;
  5651. return true;
  5652. }
  5653. static void g4x_write_eld(struct drm_connector *connector,
  5654. struct drm_crtc *crtc)
  5655. {
  5656. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5657. uint8_t *eld = connector->eld;
  5658. uint32_t eldv;
  5659. uint32_t len;
  5660. uint32_t i;
  5661. i = I915_READ(G4X_AUD_VID_DID);
  5662. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  5663. eldv = G4X_ELDV_DEVCL_DEVBLC;
  5664. else
  5665. eldv = G4X_ELDV_DEVCTG;
  5666. if (intel_eld_uptodate(connector,
  5667. G4X_AUD_CNTL_ST, eldv,
  5668. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  5669. G4X_HDMIW_HDMIEDID))
  5670. return;
  5671. i = I915_READ(G4X_AUD_CNTL_ST);
  5672. i &= ~(eldv | G4X_ELD_ADDR);
  5673. len = (i >> 9) & 0x1f; /* ELD buffer size */
  5674. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5675. if (!eld[0])
  5676. return;
  5677. len = min_t(uint8_t, eld[2], len);
  5678. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5679. for (i = 0; i < len; i++)
  5680. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  5681. i = I915_READ(G4X_AUD_CNTL_ST);
  5682. i |= eldv;
  5683. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5684. }
  5685. static void haswell_write_eld(struct drm_connector *connector,
  5686. struct drm_crtc *crtc)
  5687. {
  5688. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5689. uint8_t *eld = connector->eld;
  5690. struct drm_device *dev = crtc->dev;
  5691. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5692. uint32_t eldv;
  5693. uint32_t i;
  5694. int len;
  5695. int pipe = to_intel_crtc(crtc)->pipe;
  5696. int tmp;
  5697. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  5698. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  5699. int aud_config = HSW_AUD_CFG(pipe);
  5700. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  5701. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  5702. /* Audio output enable */
  5703. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  5704. tmp = I915_READ(aud_cntrl_st2);
  5705. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  5706. I915_WRITE(aud_cntrl_st2, tmp);
  5707. /* Wait for 1 vertical blank */
  5708. intel_wait_for_vblank(dev, pipe);
  5709. /* Set ELD valid state */
  5710. tmp = I915_READ(aud_cntrl_st2);
  5711. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
  5712. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  5713. I915_WRITE(aud_cntrl_st2, tmp);
  5714. tmp = I915_READ(aud_cntrl_st2);
  5715. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
  5716. /* Enable HDMI mode */
  5717. tmp = I915_READ(aud_config);
  5718. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
  5719. /* clear N_programing_enable and N_value_index */
  5720. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  5721. I915_WRITE(aud_config, tmp);
  5722. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5723. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  5724. intel_crtc->eld_vld = true;
  5725. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5726. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5727. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5728. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5729. } else
  5730. I915_WRITE(aud_config, 0);
  5731. if (intel_eld_uptodate(connector,
  5732. aud_cntrl_st2, eldv,
  5733. aud_cntl_st, IBX_ELD_ADDRESS,
  5734. hdmiw_hdmiedid))
  5735. return;
  5736. i = I915_READ(aud_cntrl_st2);
  5737. i &= ~eldv;
  5738. I915_WRITE(aud_cntrl_st2, i);
  5739. if (!eld[0])
  5740. return;
  5741. i = I915_READ(aud_cntl_st);
  5742. i &= ~IBX_ELD_ADDRESS;
  5743. I915_WRITE(aud_cntl_st, i);
  5744. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5745. DRM_DEBUG_DRIVER("port num:%d\n", i);
  5746. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5747. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5748. for (i = 0; i < len; i++)
  5749. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5750. i = I915_READ(aud_cntrl_st2);
  5751. i |= eldv;
  5752. I915_WRITE(aud_cntrl_st2, i);
  5753. }
  5754. static void ironlake_write_eld(struct drm_connector *connector,
  5755. struct drm_crtc *crtc)
  5756. {
  5757. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5758. uint8_t *eld = connector->eld;
  5759. uint32_t eldv;
  5760. uint32_t i;
  5761. int len;
  5762. int hdmiw_hdmiedid;
  5763. int aud_config;
  5764. int aud_cntl_st;
  5765. int aud_cntrl_st2;
  5766. int pipe = to_intel_crtc(crtc)->pipe;
  5767. if (HAS_PCH_IBX(connector->dev)) {
  5768. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  5769. aud_config = IBX_AUD_CFG(pipe);
  5770. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  5771. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5772. } else {
  5773. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  5774. aud_config = CPT_AUD_CFG(pipe);
  5775. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  5776. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5777. }
  5778. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5779. i = I915_READ(aud_cntl_st);
  5780. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5781. if (!i) {
  5782. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5783. /* operate blindly on all ports */
  5784. eldv = IBX_ELD_VALIDB;
  5785. eldv |= IBX_ELD_VALIDB << 4;
  5786. eldv |= IBX_ELD_VALIDB << 8;
  5787. } else {
  5788. DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
  5789. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5790. }
  5791. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5792. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5793. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5794. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5795. } else
  5796. I915_WRITE(aud_config, 0);
  5797. if (intel_eld_uptodate(connector,
  5798. aud_cntrl_st2, eldv,
  5799. aud_cntl_st, IBX_ELD_ADDRESS,
  5800. hdmiw_hdmiedid))
  5801. return;
  5802. i = I915_READ(aud_cntrl_st2);
  5803. i &= ~eldv;
  5804. I915_WRITE(aud_cntrl_st2, i);
  5805. if (!eld[0])
  5806. return;
  5807. i = I915_READ(aud_cntl_st);
  5808. i &= ~IBX_ELD_ADDRESS;
  5809. I915_WRITE(aud_cntl_st, i);
  5810. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5811. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5812. for (i = 0; i < len; i++)
  5813. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5814. i = I915_READ(aud_cntrl_st2);
  5815. i |= eldv;
  5816. I915_WRITE(aud_cntrl_st2, i);
  5817. }
  5818. void intel_write_eld(struct drm_encoder *encoder,
  5819. struct drm_display_mode *mode)
  5820. {
  5821. struct drm_crtc *crtc = encoder->crtc;
  5822. struct drm_connector *connector;
  5823. struct drm_device *dev = encoder->dev;
  5824. struct drm_i915_private *dev_priv = dev->dev_private;
  5825. connector = drm_select_eld(encoder, mode);
  5826. if (!connector)
  5827. return;
  5828. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5829. connector->base.id,
  5830. drm_get_connector_name(connector),
  5831. connector->encoder->base.id,
  5832. drm_get_encoder_name(connector->encoder));
  5833. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5834. if (dev_priv->display.write_eld)
  5835. dev_priv->display.write_eld(connector, crtc);
  5836. }
  5837. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5838. {
  5839. struct drm_device *dev = crtc->dev;
  5840. struct drm_i915_private *dev_priv = dev->dev_private;
  5841. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5842. bool visible = base != 0;
  5843. u32 cntl;
  5844. if (intel_crtc->cursor_visible == visible)
  5845. return;
  5846. cntl = I915_READ(_CURACNTR);
  5847. if (visible) {
  5848. /* On these chipsets we can only modify the base whilst
  5849. * the cursor is disabled.
  5850. */
  5851. I915_WRITE(_CURABASE, base);
  5852. cntl &= ~(CURSOR_FORMAT_MASK);
  5853. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5854. cntl |= CURSOR_ENABLE |
  5855. CURSOR_GAMMA_ENABLE |
  5856. CURSOR_FORMAT_ARGB;
  5857. } else
  5858. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5859. I915_WRITE(_CURACNTR, cntl);
  5860. intel_crtc->cursor_visible = visible;
  5861. }
  5862. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5863. {
  5864. struct drm_device *dev = crtc->dev;
  5865. struct drm_i915_private *dev_priv = dev->dev_private;
  5866. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5867. int pipe = intel_crtc->pipe;
  5868. bool visible = base != 0;
  5869. if (intel_crtc->cursor_visible != visible) {
  5870. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5871. if (base) {
  5872. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5873. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5874. cntl |= pipe << 28; /* Connect to correct pipe */
  5875. } else {
  5876. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5877. cntl |= CURSOR_MODE_DISABLE;
  5878. }
  5879. I915_WRITE(CURCNTR(pipe), cntl);
  5880. intel_crtc->cursor_visible = visible;
  5881. }
  5882. /* and commit changes on next vblank */
  5883. I915_WRITE(CURBASE(pipe), base);
  5884. }
  5885. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5886. {
  5887. struct drm_device *dev = crtc->dev;
  5888. struct drm_i915_private *dev_priv = dev->dev_private;
  5889. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5890. int pipe = intel_crtc->pipe;
  5891. bool visible = base != 0;
  5892. if (intel_crtc->cursor_visible != visible) {
  5893. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5894. if (base) {
  5895. cntl &= ~CURSOR_MODE;
  5896. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5897. } else {
  5898. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5899. cntl |= CURSOR_MODE_DISABLE;
  5900. }
  5901. if (IS_HASWELL(dev)) {
  5902. cntl |= CURSOR_PIPE_CSC_ENABLE;
  5903. cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
  5904. }
  5905. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5906. intel_crtc->cursor_visible = visible;
  5907. }
  5908. /* and commit changes on next vblank */
  5909. I915_WRITE(CURBASE_IVB(pipe), base);
  5910. }
  5911. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5912. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5913. bool on)
  5914. {
  5915. struct drm_device *dev = crtc->dev;
  5916. struct drm_i915_private *dev_priv = dev->dev_private;
  5917. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5918. int pipe = intel_crtc->pipe;
  5919. int x = intel_crtc->cursor_x;
  5920. int y = intel_crtc->cursor_y;
  5921. u32 base = 0, pos = 0;
  5922. bool visible;
  5923. if (on)
  5924. base = intel_crtc->cursor_addr;
  5925. if (x >= intel_crtc->config.pipe_src_w)
  5926. base = 0;
  5927. if (y >= intel_crtc->config.pipe_src_h)
  5928. base = 0;
  5929. if (x < 0) {
  5930. if (x + intel_crtc->cursor_width <= 0)
  5931. base = 0;
  5932. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5933. x = -x;
  5934. }
  5935. pos |= x << CURSOR_X_SHIFT;
  5936. if (y < 0) {
  5937. if (y + intel_crtc->cursor_height <= 0)
  5938. base = 0;
  5939. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5940. y = -y;
  5941. }
  5942. pos |= y << CURSOR_Y_SHIFT;
  5943. visible = base != 0;
  5944. if (!visible && !intel_crtc->cursor_visible)
  5945. return;
  5946. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  5947. I915_WRITE(CURPOS_IVB(pipe), pos);
  5948. ivb_update_cursor(crtc, base);
  5949. } else {
  5950. I915_WRITE(CURPOS(pipe), pos);
  5951. if (IS_845G(dev) || IS_I865G(dev))
  5952. i845_update_cursor(crtc, base);
  5953. else
  5954. i9xx_update_cursor(crtc, base);
  5955. }
  5956. }
  5957. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5958. struct drm_file *file,
  5959. uint32_t handle,
  5960. uint32_t width, uint32_t height)
  5961. {
  5962. struct drm_device *dev = crtc->dev;
  5963. struct drm_i915_private *dev_priv = dev->dev_private;
  5964. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5965. struct drm_i915_gem_object *obj;
  5966. uint32_t addr;
  5967. int ret;
  5968. /* if we want to turn off the cursor ignore width and height */
  5969. if (!handle) {
  5970. DRM_DEBUG_KMS("cursor off\n");
  5971. addr = 0;
  5972. obj = NULL;
  5973. mutex_lock(&dev->struct_mutex);
  5974. goto finish;
  5975. }
  5976. /* Currently we only support 64x64 cursors */
  5977. if (width != 64 || height != 64) {
  5978. DRM_ERROR("we currently only support 64x64 cursors\n");
  5979. return -EINVAL;
  5980. }
  5981. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5982. if (&obj->base == NULL)
  5983. return -ENOENT;
  5984. if (obj->base.size < width * height * 4) {
  5985. DRM_ERROR("buffer is to small\n");
  5986. ret = -ENOMEM;
  5987. goto fail;
  5988. }
  5989. /* we only need to pin inside GTT if cursor is non-phy */
  5990. mutex_lock(&dev->struct_mutex);
  5991. if (!dev_priv->info->cursor_needs_physical) {
  5992. unsigned alignment;
  5993. if (obj->tiling_mode) {
  5994. DRM_ERROR("cursor cannot be tiled\n");
  5995. ret = -EINVAL;
  5996. goto fail_locked;
  5997. }
  5998. /* Note that the w/a also requires 2 PTE of padding following
  5999. * the bo. We currently fill all unused PTE with the shadow
  6000. * page and so we should always have valid PTE following the
  6001. * cursor preventing the VT-d warning.
  6002. */
  6003. alignment = 0;
  6004. if (need_vtd_wa(dev))
  6005. alignment = 64*1024;
  6006. ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
  6007. if (ret) {
  6008. DRM_ERROR("failed to move cursor bo into the GTT\n");
  6009. goto fail_locked;
  6010. }
  6011. ret = i915_gem_object_put_fence(obj);
  6012. if (ret) {
  6013. DRM_ERROR("failed to release fence for cursor");
  6014. goto fail_unpin;
  6015. }
  6016. addr = i915_gem_obj_ggtt_offset(obj);
  6017. } else {
  6018. int align = IS_I830(dev) ? 16 * 1024 : 256;
  6019. ret = i915_gem_attach_phys_object(dev, obj,
  6020. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  6021. align);
  6022. if (ret) {
  6023. DRM_ERROR("failed to attach phys object\n");
  6024. goto fail_locked;
  6025. }
  6026. addr = obj->phys_obj->handle->busaddr;
  6027. }
  6028. if (IS_GEN2(dev))
  6029. I915_WRITE(CURSIZE, (height << 12) | width);
  6030. finish:
  6031. if (intel_crtc->cursor_bo) {
  6032. if (dev_priv->info->cursor_needs_physical) {
  6033. if (intel_crtc->cursor_bo != obj)
  6034. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  6035. } else
  6036. i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
  6037. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  6038. }
  6039. mutex_unlock(&dev->struct_mutex);
  6040. intel_crtc->cursor_addr = addr;
  6041. intel_crtc->cursor_bo = obj;
  6042. intel_crtc->cursor_width = width;
  6043. intel_crtc->cursor_height = height;
  6044. if (intel_crtc->active)
  6045. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  6046. return 0;
  6047. fail_unpin:
  6048. i915_gem_object_unpin_from_display_plane(obj);
  6049. fail_locked:
  6050. mutex_unlock(&dev->struct_mutex);
  6051. fail:
  6052. drm_gem_object_unreference_unlocked(&obj->base);
  6053. return ret;
  6054. }
  6055. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  6056. {
  6057. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6058. intel_crtc->cursor_x = x;
  6059. intel_crtc->cursor_y = y;
  6060. if (intel_crtc->active)
  6061. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  6062. return 0;
  6063. }
  6064. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  6065. u16 *blue, uint32_t start, uint32_t size)
  6066. {
  6067. int end = (start + size > 256) ? 256 : start + size, i;
  6068. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6069. for (i = start; i < end; i++) {
  6070. intel_crtc->lut_r[i] = red[i] >> 8;
  6071. intel_crtc->lut_g[i] = green[i] >> 8;
  6072. intel_crtc->lut_b[i] = blue[i] >> 8;
  6073. }
  6074. intel_crtc_load_lut(crtc);
  6075. }
  6076. /* VESA 640x480x72Hz mode to set on the pipe */
  6077. static struct drm_display_mode load_detect_mode = {
  6078. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  6079. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  6080. };
  6081. static struct drm_framebuffer *
  6082. intel_framebuffer_create(struct drm_device *dev,
  6083. struct drm_mode_fb_cmd2 *mode_cmd,
  6084. struct drm_i915_gem_object *obj)
  6085. {
  6086. struct intel_framebuffer *intel_fb;
  6087. int ret;
  6088. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  6089. if (!intel_fb) {
  6090. drm_gem_object_unreference_unlocked(&obj->base);
  6091. return ERR_PTR(-ENOMEM);
  6092. }
  6093. ret = i915_mutex_lock_interruptible(dev);
  6094. if (ret)
  6095. goto err;
  6096. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  6097. mutex_unlock(&dev->struct_mutex);
  6098. if (ret)
  6099. goto err;
  6100. return &intel_fb->base;
  6101. err:
  6102. drm_gem_object_unreference_unlocked(&obj->base);
  6103. kfree(intel_fb);
  6104. return ERR_PTR(ret);
  6105. }
  6106. static u32
  6107. intel_framebuffer_pitch_for_width(int width, int bpp)
  6108. {
  6109. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  6110. return ALIGN(pitch, 64);
  6111. }
  6112. static u32
  6113. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  6114. {
  6115. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  6116. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  6117. }
  6118. static struct drm_framebuffer *
  6119. intel_framebuffer_create_for_mode(struct drm_device *dev,
  6120. struct drm_display_mode *mode,
  6121. int depth, int bpp)
  6122. {
  6123. struct drm_i915_gem_object *obj;
  6124. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  6125. obj = i915_gem_alloc_object(dev,
  6126. intel_framebuffer_size_for_mode(mode, bpp));
  6127. if (obj == NULL)
  6128. return ERR_PTR(-ENOMEM);
  6129. mode_cmd.width = mode->hdisplay;
  6130. mode_cmd.height = mode->vdisplay;
  6131. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  6132. bpp);
  6133. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  6134. return intel_framebuffer_create(dev, &mode_cmd, obj);
  6135. }
  6136. static struct drm_framebuffer *
  6137. mode_fits_in_fbdev(struct drm_device *dev,
  6138. struct drm_display_mode *mode)
  6139. {
  6140. #ifdef CONFIG_DRM_I915_FBDEV
  6141. struct drm_i915_private *dev_priv = dev->dev_private;
  6142. struct drm_i915_gem_object *obj;
  6143. struct drm_framebuffer *fb;
  6144. if (dev_priv->fbdev == NULL)
  6145. return NULL;
  6146. obj = dev_priv->fbdev->ifb.obj;
  6147. if (obj == NULL)
  6148. return NULL;
  6149. fb = &dev_priv->fbdev->ifb.base;
  6150. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  6151. fb->bits_per_pixel))
  6152. return NULL;
  6153. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  6154. return NULL;
  6155. return fb;
  6156. #else
  6157. return NULL;
  6158. #endif
  6159. }
  6160. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  6161. struct drm_display_mode *mode,
  6162. struct intel_load_detect_pipe *old)
  6163. {
  6164. struct intel_crtc *intel_crtc;
  6165. struct intel_encoder *intel_encoder =
  6166. intel_attached_encoder(connector);
  6167. struct drm_crtc *possible_crtc;
  6168. struct drm_encoder *encoder = &intel_encoder->base;
  6169. struct drm_crtc *crtc = NULL;
  6170. struct drm_device *dev = encoder->dev;
  6171. struct drm_framebuffer *fb;
  6172. int i = -1;
  6173. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6174. connector->base.id, drm_get_connector_name(connector),
  6175. encoder->base.id, drm_get_encoder_name(encoder));
  6176. /*
  6177. * Algorithm gets a little messy:
  6178. *
  6179. * - if the connector already has an assigned crtc, use it (but make
  6180. * sure it's on first)
  6181. *
  6182. * - try to find the first unused crtc that can drive this connector,
  6183. * and use that if we find one
  6184. */
  6185. /* See if we already have a CRTC for this connector */
  6186. if (encoder->crtc) {
  6187. crtc = encoder->crtc;
  6188. mutex_lock(&crtc->mutex);
  6189. old->dpms_mode = connector->dpms;
  6190. old->load_detect_temp = false;
  6191. /* Make sure the crtc and connector are running */
  6192. if (connector->dpms != DRM_MODE_DPMS_ON)
  6193. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  6194. return true;
  6195. }
  6196. /* Find an unused one (if possible) */
  6197. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  6198. i++;
  6199. if (!(encoder->possible_crtcs & (1 << i)))
  6200. continue;
  6201. if (!possible_crtc->enabled) {
  6202. crtc = possible_crtc;
  6203. break;
  6204. }
  6205. }
  6206. /*
  6207. * If we didn't find an unused CRTC, don't use any.
  6208. */
  6209. if (!crtc) {
  6210. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  6211. return false;
  6212. }
  6213. mutex_lock(&crtc->mutex);
  6214. intel_encoder->new_crtc = to_intel_crtc(crtc);
  6215. to_intel_connector(connector)->new_encoder = intel_encoder;
  6216. intel_crtc = to_intel_crtc(crtc);
  6217. old->dpms_mode = connector->dpms;
  6218. old->load_detect_temp = true;
  6219. old->release_fb = NULL;
  6220. if (!mode)
  6221. mode = &load_detect_mode;
  6222. /* We need a framebuffer large enough to accommodate all accesses
  6223. * that the plane may generate whilst we perform load detection.
  6224. * We can not rely on the fbcon either being present (we get called
  6225. * during its initialisation to detect all boot displays, or it may
  6226. * not even exist) or that it is large enough to satisfy the
  6227. * requested mode.
  6228. */
  6229. fb = mode_fits_in_fbdev(dev, mode);
  6230. if (fb == NULL) {
  6231. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  6232. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  6233. old->release_fb = fb;
  6234. } else
  6235. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  6236. if (IS_ERR(fb)) {
  6237. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  6238. mutex_unlock(&crtc->mutex);
  6239. return false;
  6240. }
  6241. if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  6242. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  6243. if (old->release_fb)
  6244. old->release_fb->funcs->destroy(old->release_fb);
  6245. mutex_unlock(&crtc->mutex);
  6246. return false;
  6247. }
  6248. /* let the connector get through one full cycle before testing */
  6249. intel_wait_for_vblank(dev, intel_crtc->pipe);
  6250. return true;
  6251. }
  6252. void intel_release_load_detect_pipe(struct drm_connector *connector,
  6253. struct intel_load_detect_pipe *old)
  6254. {
  6255. struct intel_encoder *intel_encoder =
  6256. intel_attached_encoder(connector);
  6257. struct drm_encoder *encoder = &intel_encoder->base;
  6258. struct drm_crtc *crtc = encoder->crtc;
  6259. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6260. connector->base.id, drm_get_connector_name(connector),
  6261. encoder->base.id, drm_get_encoder_name(encoder));
  6262. if (old->load_detect_temp) {
  6263. to_intel_connector(connector)->new_encoder = NULL;
  6264. intel_encoder->new_crtc = NULL;
  6265. intel_set_mode(crtc, NULL, 0, 0, NULL);
  6266. if (old->release_fb) {
  6267. drm_framebuffer_unregister_private(old->release_fb);
  6268. drm_framebuffer_unreference(old->release_fb);
  6269. }
  6270. mutex_unlock(&crtc->mutex);
  6271. return;
  6272. }
  6273. /* Switch crtc and encoder back off if necessary */
  6274. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  6275. connector->funcs->dpms(connector, old->dpms_mode);
  6276. mutex_unlock(&crtc->mutex);
  6277. }
  6278. static int i9xx_pll_refclk(struct drm_device *dev,
  6279. const struct intel_crtc_config *pipe_config)
  6280. {
  6281. struct drm_i915_private *dev_priv = dev->dev_private;
  6282. u32 dpll = pipe_config->dpll_hw_state.dpll;
  6283. if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
  6284. return dev_priv->vbt.lvds_ssc_freq * 1000;
  6285. else if (HAS_PCH_SPLIT(dev))
  6286. return 120000;
  6287. else if (!IS_GEN2(dev))
  6288. return 96000;
  6289. else
  6290. return 48000;
  6291. }
  6292. /* Returns the clock of the currently programmed mode of the given pipe. */
  6293. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  6294. struct intel_crtc_config *pipe_config)
  6295. {
  6296. struct drm_device *dev = crtc->base.dev;
  6297. struct drm_i915_private *dev_priv = dev->dev_private;
  6298. int pipe = pipe_config->cpu_transcoder;
  6299. u32 dpll = pipe_config->dpll_hw_state.dpll;
  6300. u32 fp;
  6301. intel_clock_t clock;
  6302. int refclk = i9xx_pll_refclk(dev, pipe_config);
  6303. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  6304. fp = pipe_config->dpll_hw_state.fp0;
  6305. else
  6306. fp = pipe_config->dpll_hw_state.fp1;
  6307. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  6308. if (IS_PINEVIEW(dev)) {
  6309. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  6310. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  6311. } else {
  6312. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  6313. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  6314. }
  6315. if (!IS_GEN2(dev)) {
  6316. if (IS_PINEVIEW(dev))
  6317. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  6318. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  6319. else
  6320. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  6321. DPLL_FPA01_P1_POST_DIV_SHIFT);
  6322. switch (dpll & DPLL_MODE_MASK) {
  6323. case DPLLB_MODE_DAC_SERIAL:
  6324. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  6325. 5 : 10;
  6326. break;
  6327. case DPLLB_MODE_LVDS:
  6328. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  6329. 7 : 14;
  6330. break;
  6331. default:
  6332. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  6333. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  6334. return;
  6335. }
  6336. if (IS_PINEVIEW(dev))
  6337. pineview_clock(refclk, &clock);
  6338. else
  6339. i9xx_clock(refclk, &clock);
  6340. } else {
  6341. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  6342. if (is_lvds) {
  6343. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  6344. DPLL_FPA01_P1_POST_DIV_SHIFT);
  6345. clock.p2 = 14;
  6346. } else {
  6347. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  6348. clock.p1 = 2;
  6349. else {
  6350. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  6351. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  6352. }
  6353. if (dpll & PLL_P2_DIVIDE_BY_4)
  6354. clock.p2 = 4;
  6355. else
  6356. clock.p2 = 2;
  6357. }
  6358. i9xx_clock(refclk, &clock);
  6359. }
  6360. /*
  6361. * This value includes pixel_multiplier. We will use
  6362. * port_clock to compute adjusted_mode.crtc_clock in the
  6363. * encoder's get_config() function.
  6364. */
  6365. pipe_config->port_clock = clock.dot;
  6366. }
  6367. int intel_dotclock_calculate(int link_freq,
  6368. const struct intel_link_m_n *m_n)
  6369. {
  6370. /*
  6371. * The calculation for the data clock is:
  6372. * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
  6373. * But we want to avoid losing precison if possible, so:
  6374. * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
  6375. *
  6376. * and the link clock is simpler:
  6377. * link_clock = (m * link_clock) / n
  6378. */
  6379. if (!m_n->link_n)
  6380. return 0;
  6381. return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
  6382. }
  6383. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  6384. struct intel_crtc_config *pipe_config)
  6385. {
  6386. struct drm_device *dev = crtc->base.dev;
  6387. /* read out port_clock from the DPLL */
  6388. i9xx_crtc_clock_get(crtc, pipe_config);
  6389. /*
  6390. * This value does not include pixel_multiplier.
  6391. * We will check that port_clock and adjusted_mode.crtc_clock
  6392. * agree once we know their relationship in the encoder's
  6393. * get_config() function.
  6394. */
  6395. pipe_config->adjusted_mode.crtc_clock =
  6396. intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
  6397. &pipe_config->fdi_m_n);
  6398. }
  6399. /** Returns the currently programmed mode of the given pipe. */
  6400. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  6401. struct drm_crtc *crtc)
  6402. {
  6403. struct drm_i915_private *dev_priv = dev->dev_private;
  6404. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6405. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  6406. struct drm_display_mode *mode;
  6407. struct intel_crtc_config pipe_config;
  6408. int htot = I915_READ(HTOTAL(cpu_transcoder));
  6409. int hsync = I915_READ(HSYNC(cpu_transcoder));
  6410. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  6411. int vsync = I915_READ(VSYNC(cpu_transcoder));
  6412. enum pipe pipe = intel_crtc->pipe;
  6413. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  6414. if (!mode)
  6415. return NULL;
  6416. /*
  6417. * Construct a pipe_config sufficient for getting the clock info
  6418. * back out of crtc_clock_get.
  6419. *
  6420. * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  6421. * to use a real value here instead.
  6422. */
  6423. pipe_config.cpu_transcoder = (enum transcoder) pipe;
  6424. pipe_config.pixel_multiplier = 1;
  6425. pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
  6426. pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
  6427. pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
  6428. i9xx_crtc_clock_get(intel_crtc, &pipe_config);
  6429. mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
  6430. mode->hdisplay = (htot & 0xffff) + 1;
  6431. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  6432. mode->hsync_start = (hsync & 0xffff) + 1;
  6433. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  6434. mode->vdisplay = (vtot & 0xffff) + 1;
  6435. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  6436. mode->vsync_start = (vsync & 0xffff) + 1;
  6437. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  6438. drm_mode_set_name(mode);
  6439. return mode;
  6440. }
  6441. static void intel_increase_pllclock(struct drm_crtc *crtc)
  6442. {
  6443. struct drm_device *dev = crtc->dev;
  6444. drm_i915_private_t *dev_priv = dev->dev_private;
  6445. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6446. int pipe = intel_crtc->pipe;
  6447. int dpll_reg = DPLL(pipe);
  6448. int dpll;
  6449. if (HAS_PCH_SPLIT(dev))
  6450. return;
  6451. if (!dev_priv->lvds_downclock_avail)
  6452. return;
  6453. dpll = I915_READ(dpll_reg);
  6454. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  6455. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  6456. assert_panel_unlocked(dev_priv, pipe);
  6457. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  6458. I915_WRITE(dpll_reg, dpll);
  6459. intel_wait_for_vblank(dev, pipe);
  6460. dpll = I915_READ(dpll_reg);
  6461. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  6462. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  6463. }
  6464. }
  6465. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  6466. {
  6467. struct drm_device *dev = crtc->dev;
  6468. drm_i915_private_t *dev_priv = dev->dev_private;
  6469. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6470. if (HAS_PCH_SPLIT(dev))
  6471. return;
  6472. if (!dev_priv->lvds_downclock_avail)
  6473. return;
  6474. /*
  6475. * Since this is called by a timer, we should never get here in
  6476. * the manual case.
  6477. */
  6478. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  6479. int pipe = intel_crtc->pipe;
  6480. int dpll_reg = DPLL(pipe);
  6481. int dpll;
  6482. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  6483. assert_panel_unlocked(dev_priv, pipe);
  6484. dpll = I915_READ(dpll_reg);
  6485. dpll |= DISPLAY_RATE_SELECT_FPA1;
  6486. I915_WRITE(dpll_reg, dpll);
  6487. intel_wait_for_vblank(dev, pipe);
  6488. dpll = I915_READ(dpll_reg);
  6489. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  6490. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  6491. }
  6492. }
  6493. void intel_mark_busy(struct drm_device *dev)
  6494. {
  6495. struct drm_i915_private *dev_priv = dev->dev_private;
  6496. hsw_package_c8_gpu_busy(dev_priv);
  6497. i915_update_gfx_val(dev_priv);
  6498. }
  6499. void intel_mark_idle(struct drm_device *dev)
  6500. {
  6501. struct drm_i915_private *dev_priv = dev->dev_private;
  6502. struct drm_crtc *crtc;
  6503. hsw_package_c8_gpu_idle(dev_priv);
  6504. if (!i915_powersave)
  6505. return;
  6506. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6507. if (!crtc->fb)
  6508. continue;
  6509. intel_decrease_pllclock(crtc);
  6510. }
  6511. if (dev_priv->info->gen >= 6)
  6512. gen6_rps_idle(dev->dev_private);
  6513. }
  6514. void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  6515. struct intel_ring_buffer *ring)
  6516. {
  6517. struct drm_device *dev = obj->base.dev;
  6518. struct drm_crtc *crtc;
  6519. if (!i915_powersave)
  6520. return;
  6521. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6522. if (!crtc->fb)
  6523. continue;
  6524. if (to_intel_framebuffer(crtc->fb)->obj != obj)
  6525. continue;
  6526. intel_increase_pllclock(crtc);
  6527. if (ring && intel_fbc_enabled(dev))
  6528. ring->fbc_dirty = true;
  6529. }
  6530. }
  6531. static void intel_crtc_destroy(struct drm_crtc *crtc)
  6532. {
  6533. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6534. struct drm_device *dev = crtc->dev;
  6535. struct intel_unpin_work *work;
  6536. unsigned long flags;
  6537. spin_lock_irqsave(&dev->event_lock, flags);
  6538. work = intel_crtc->unpin_work;
  6539. intel_crtc->unpin_work = NULL;
  6540. spin_unlock_irqrestore(&dev->event_lock, flags);
  6541. if (work) {
  6542. cancel_work_sync(&work->work);
  6543. kfree(work);
  6544. }
  6545. intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
  6546. drm_crtc_cleanup(crtc);
  6547. kfree(intel_crtc);
  6548. }
  6549. static void intel_unpin_work_fn(struct work_struct *__work)
  6550. {
  6551. struct intel_unpin_work *work =
  6552. container_of(__work, struct intel_unpin_work, work);
  6553. struct drm_device *dev = work->crtc->dev;
  6554. mutex_lock(&dev->struct_mutex);
  6555. intel_unpin_fb_obj(work->old_fb_obj);
  6556. drm_gem_object_unreference(&work->pending_flip_obj->base);
  6557. drm_gem_object_unreference(&work->old_fb_obj->base);
  6558. intel_update_fbc(dev);
  6559. mutex_unlock(&dev->struct_mutex);
  6560. BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  6561. atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  6562. kfree(work);
  6563. }
  6564. static void do_intel_finish_page_flip(struct drm_device *dev,
  6565. struct drm_crtc *crtc)
  6566. {
  6567. drm_i915_private_t *dev_priv = dev->dev_private;
  6568. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6569. struct intel_unpin_work *work;
  6570. unsigned long flags;
  6571. /* Ignore early vblank irqs */
  6572. if (intel_crtc == NULL)
  6573. return;
  6574. spin_lock_irqsave(&dev->event_lock, flags);
  6575. work = intel_crtc->unpin_work;
  6576. /* Ensure we don't miss a work->pending update ... */
  6577. smp_rmb();
  6578. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  6579. spin_unlock_irqrestore(&dev->event_lock, flags);
  6580. return;
  6581. }
  6582. /* and that the unpin work is consistent wrt ->pending. */
  6583. smp_rmb();
  6584. intel_crtc->unpin_work = NULL;
  6585. if (work->event)
  6586. drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  6587. drm_vblank_put(dev, intel_crtc->pipe);
  6588. spin_unlock_irqrestore(&dev->event_lock, flags);
  6589. wake_up_all(&dev_priv->pending_flip_queue);
  6590. queue_work(dev_priv->wq, &work->work);
  6591. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  6592. }
  6593. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  6594. {
  6595. drm_i915_private_t *dev_priv = dev->dev_private;
  6596. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  6597. do_intel_finish_page_flip(dev, crtc);
  6598. }
  6599. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  6600. {
  6601. drm_i915_private_t *dev_priv = dev->dev_private;
  6602. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  6603. do_intel_finish_page_flip(dev, crtc);
  6604. }
  6605. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  6606. {
  6607. drm_i915_private_t *dev_priv = dev->dev_private;
  6608. struct intel_crtc *intel_crtc =
  6609. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  6610. unsigned long flags;
  6611. /* NB: An MMIO update of the plane base pointer will also
  6612. * generate a page-flip completion irq, i.e. every modeset
  6613. * is also accompanied by a spurious intel_prepare_page_flip().
  6614. */
  6615. spin_lock_irqsave(&dev->event_lock, flags);
  6616. if (intel_crtc->unpin_work)
  6617. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  6618. spin_unlock_irqrestore(&dev->event_lock, flags);
  6619. }
  6620. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  6621. {
  6622. /* Ensure that the work item is consistent when activating it ... */
  6623. smp_wmb();
  6624. atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  6625. /* and that it is marked active as soon as the irq could fire. */
  6626. smp_wmb();
  6627. }
  6628. static int intel_gen2_queue_flip(struct drm_device *dev,
  6629. struct drm_crtc *crtc,
  6630. struct drm_framebuffer *fb,
  6631. struct drm_i915_gem_object *obj,
  6632. uint32_t flags)
  6633. {
  6634. struct drm_i915_private *dev_priv = dev->dev_private;
  6635. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6636. u32 flip_mask;
  6637. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6638. int ret;
  6639. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6640. if (ret)
  6641. goto err;
  6642. ret = intel_ring_begin(ring, 6);
  6643. if (ret)
  6644. goto err_unpin;
  6645. /* Can't queue multiple flips, so wait for the previous
  6646. * one to finish before executing the next.
  6647. */
  6648. if (intel_crtc->plane)
  6649. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6650. else
  6651. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6652. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6653. intel_ring_emit(ring, MI_NOOP);
  6654. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6655. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6656. intel_ring_emit(ring, fb->pitches[0]);
  6657. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6658. intel_ring_emit(ring, 0); /* aux display base address, unused */
  6659. intel_mark_page_flip_active(intel_crtc);
  6660. __intel_ring_advance(ring);
  6661. return 0;
  6662. err_unpin:
  6663. intel_unpin_fb_obj(obj);
  6664. err:
  6665. return ret;
  6666. }
  6667. static int intel_gen3_queue_flip(struct drm_device *dev,
  6668. struct drm_crtc *crtc,
  6669. struct drm_framebuffer *fb,
  6670. struct drm_i915_gem_object *obj,
  6671. uint32_t flags)
  6672. {
  6673. struct drm_i915_private *dev_priv = dev->dev_private;
  6674. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6675. u32 flip_mask;
  6676. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6677. int ret;
  6678. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6679. if (ret)
  6680. goto err;
  6681. ret = intel_ring_begin(ring, 6);
  6682. if (ret)
  6683. goto err_unpin;
  6684. if (intel_crtc->plane)
  6685. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6686. else
  6687. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6688. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6689. intel_ring_emit(ring, MI_NOOP);
  6690. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  6691. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6692. intel_ring_emit(ring, fb->pitches[0]);
  6693. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6694. intel_ring_emit(ring, MI_NOOP);
  6695. intel_mark_page_flip_active(intel_crtc);
  6696. __intel_ring_advance(ring);
  6697. return 0;
  6698. err_unpin:
  6699. intel_unpin_fb_obj(obj);
  6700. err:
  6701. return ret;
  6702. }
  6703. static int intel_gen4_queue_flip(struct drm_device *dev,
  6704. struct drm_crtc *crtc,
  6705. struct drm_framebuffer *fb,
  6706. struct drm_i915_gem_object *obj,
  6707. uint32_t flags)
  6708. {
  6709. struct drm_i915_private *dev_priv = dev->dev_private;
  6710. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6711. uint32_t pf, pipesrc;
  6712. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6713. int ret;
  6714. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6715. if (ret)
  6716. goto err;
  6717. ret = intel_ring_begin(ring, 4);
  6718. if (ret)
  6719. goto err_unpin;
  6720. /* i965+ uses the linear or tiled offsets from the
  6721. * Display Registers (which do not change across a page-flip)
  6722. * so we need only reprogram the base address.
  6723. */
  6724. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6725. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6726. intel_ring_emit(ring, fb->pitches[0]);
  6727. intel_ring_emit(ring,
  6728. (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
  6729. obj->tiling_mode);
  6730. /* XXX Enabling the panel-fitter across page-flip is so far
  6731. * untested on non-native modes, so ignore it for now.
  6732. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  6733. */
  6734. pf = 0;
  6735. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6736. intel_ring_emit(ring, pf | pipesrc);
  6737. intel_mark_page_flip_active(intel_crtc);
  6738. __intel_ring_advance(ring);
  6739. return 0;
  6740. err_unpin:
  6741. intel_unpin_fb_obj(obj);
  6742. err:
  6743. return ret;
  6744. }
  6745. static int intel_gen6_queue_flip(struct drm_device *dev,
  6746. struct drm_crtc *crtc,
  6747. struct drm_framebuffer *fb,
  6748. struct drm_i915_gem_object *obj,
  6749. uint32_t flags)
  6750. {
  6751. struct drm_i915_private *dev_priv = dev->dev_private;
  6752. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6753. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6754. uint32_t pf, pipesrc;
  6755. int ret;
  6756. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6757. if (ret)
  6758. goto err;
  6759. ret = intel_ring_begin(ring, 4);
  6760. if (ret)
  6761. goto err_unpin;
  6762. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6763. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6764. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  6765. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6766. /* Contrary to the suggestions in the documentation,
  6767. * "Enable Panel Fitter" does not seem to be required when page
  6768. * flipping with a non-native mode, and worse causes a normal
  6769. * modeset to fail.
  6770. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  6771. */
  6772. pf = 0;
  6773. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6774. intel_ring_emit(ring, pf | pipesrc);
  6775. intel_mark_page_flip_active(intel_crtc);
  6776. __intel_ring_advance(ring);
  6777. return 0;
  6778. err_unpin:
  6779. intel_unpin_fb_obj(obj);
  6780. err:
  6781. return ret;
  6782. }
  6783. static int intel_gen7_queue_flip(struct drm_device *dev,
  6784. struct drm_crtc *crtc,
  6785. struct drm_framebuffer *fb,
  6786. struct drm_i915_gem_object *obj,
  6787. uint32_t flags)
  6788. {
  6789. struct drm_i915_private *dev_priv = dev->dev_private;
  6790. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6791. struct intel_ring_buffer *ring;
  6792. uint32_t plane_bit = 0;
  6793. int len, ret;
  6794. ring = obj->ring;
  6795. if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
  6796. ring = &dev_priv->ring[BCS];
  6797. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6798. if (ret)
  6799. goto err;
  6800. switch(intel_crtc->plane) {
  6801. case PLANE_A:
  6802. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  6803. break;
  6804. case PLANE_B:
  6805. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  6806. break;
  6807. case PLANE_C:
  6808. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  6809. break;
  6810. default:
  6811. WARN_ONCE(1, "unknown plane in flip command\n");
  6812. ret = -ENODEV;
  6813. goto err_unpin;
  6814. }
  6815. len = 4;
  6816. if (ring->id == RCS)
  6817. len += 6;
  6818. ret = intel_ring_begin(ring, len);
  6819. if (ret)
  6820. goto err_unpin;
  6821. /* Unmask the flip-done completion message. Note that the bspec says that
  6822. * we should do this for both the BCS and RCS, and that we must not unmask
  6823. * more than one flip event at any time (or ensure that one flip message
  6824. * can be sent by waiting for flip-done prior to queueing new flips).
  6825. * Experimentation says that BCS works despite DERRMR masking all
  6826. * flip-done completion events and that unmasking all planes at once
  6827. * for the RCS also doesn't appear to drop events. Setting the DERRMR
  6828. * to zero does lead to lockups within MI_DISPLAY_FLIP.
  6829. */
  6830. if (ring->id == RCS) {
  6831. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  6832. intel_ring_emit(ring, DERRMR);
  6833. intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
  6834. DERRMR_PIPEB_PRI_FLIP_DONE |
  6835. DERRMR_PIPEC_PRI_FLIP_DONE));
  6836. intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
  6837. intel_ring_emit(ring, DERRMR);
  6838. intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
  6839. }
  6840. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  6841. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6842. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6843. intel_ring_emit(ring, (MI_NOOP));
  6844. intel_mark_page_flip_active(intel_crtc);
  6845. __intel_ring_advance(ring);
  6846. return 0;
  6847. err_unpin:
  6848. intel_unpin_fb_obj(obj);
  6849. err:
  6850. return ret;
  6851. }
  6852. static int intel_default_queue_flip(struct drm_device *dev,
  6853. struct drm_crtc *crtc,
  6854. struct drm_framebuffer *fb,
  6855. struct drm_i915_gem_object *obj,
  6856. uint32_t flags)
  6857. {
  6858. return -ENODEV;
  6859. }
  6860. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6861. struct drm_framebuffer *fb,
  6862. struct drm_pending_vblank_event *event,
  6863. uint32_t page_flip_flags)
  6864. {
  6865. struct drm_device *dev = crtc->dev;
  6866. struct drm_i915_private *dev_priv = dev->dev_private;
  6867. struct drm_framebuffer *old_fb = crtc->fb;
  6868. struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
  6869. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6870. struct intel_unpin_work *work;
  6871. unsigned long flags;
  6872. int ret;
  6873. /* Can't change pixel format via MI display flips. */
  6874. if (fb->pixel_format != crtc->fb->pixel_format)
  6875. return -EINVAL;
  6876. /*
  6877. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  6878. * Note that pitch changes could also affect these register.
  6879. */
  6880. if (INTEL_INFO(dev)->gen > 3 &&
  6881. (fb->offsets[0] != crtc->fb->offsets[0] ||
  6882. fb->pitches[0] != crtc->fb->pitches[0]))
  6883. return -EINVAL;
  6884. work = kzalloc(sizeof(*work), GFP_KERNEL);
  6885. if (work == NULL)
  6886. return -ENOMEM;
  6887. work->event = event;
  6888. work->crtc = crtc;
  6889. work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
  6890. INIT_WORK(&work->work, intel_unpin_work_fn);
  6891. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6892. if (ret)
  6893. goto free_work;
  6894. /* We borrow the event spin lock for protecting unpin_work */
  6895. spin_lock_irqsave(&dev->event_lock, flags);
  6896. if (intel_crtc->unpin_work) {
  6897. spin_unlock_irqrestore(&dev->event_lock, flags);
  6898. kfree(work);
  6899. drm_vblank_put(dev, intel_crtc->pipe);
  6900. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6901. return -EBUSY;
  6902. }
  6903. intel_crtc->unpin_work = work;
  6904. spin_unlock_irqrestore(&dev->event_lock, flags);
  6905. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  6906. flush_workqueue(dev_priv->wq);
  6907. ret = i915_mutex_lock_interruptible(dev);
  6908. if (ret)
  6909. goto cleanup;
  6910. /* Reference the objects for the scheduled work. */
  6911. drm_gem_object_reference(&work->old_fb_obj->base);
  6912. drm_gem_object_reference(&obj->base);
  6913. crtc->fb = fb;
  6914. work->pending_flip_obj = obj;
  6915. work->enable_stall_check = true;
  6916. atomic_inc(&intel_crtc->unpin_work_count);
  6917. intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  6918. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
  6919. if (ret)
  6920. goto cleanup_pending;
  6921. intel_disable_fbc(dev);
  6922. intel_mark_fb_busy(obj, NULL);
  6923. mutex_unlock(&dev->struct_mutex);
  6924. trace_i915_flip_request(intel_crtc->plane, obj);
  6925. return 0;
  6926. cleanup_pending:
  6927. atomic_dec(&intel_crtc->unpin_work_count);
  6928. crtc->fb = old_fb;
  6929. drm_gem_object_unreference(&work->old_fb_obj->base);
  6930. drm_gem_object_unreference(&obj->base);
  6931. mutex_unlock(&dev->struct_mutex);
  6932. cleanup:
  6933. spin_lock_irqsave(&dev->event_lock, flags);
  6934. intel_crtc->unpin_work = NULL;
  6935. spin_unlock_irqrestore(&dev->event_lock, flags);
  6936. drm_vblank_put(dev, intel_crtc->pipe);
  6937. free_work:
  6938. kfree(work);
  6939. return ret;
  6940. }
  6941. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6942. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6943. .load_lut = intel_crtc_load_lut,
  6944. };
  6945. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  6946. struct drm_crtc *crtc)
  6947. {
  6948. struct drm_device *dev;
  6949. struct drm_crtc *tmp;
  6950. int crtc_mask = 1;
  6951. WARN(!crtc, "checking null crtc?\n");
  6952. dev = crtc->dev;
  6953. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  6954. if (tmp == crtc)
  6955. break;
  6956. crtc_mask <<= 1;
  6957. }
  6958. if (encoder->possible_crtcs & crtc_mask)
  6959. return true;
  6960. return false;
  6961. }
  6962. /**
  6963. * intel_modeset_update_staged_output_state
  6964. *
  6965. * Updates the staged output configuration state, e.g. after we've read out the
  6966. * current hw state.
  6967. */
  6968. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  6969. {
  6970. struct intel_encoder *encoder;
  6971. struct intel_connector *connector;
  6972. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6973. base.head) {
  6974. connector->new_encoder =
  6975. to_intel_encoder(connector->base.encoder);
  6976. }
  6977. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6978. base.head) {
  6979. encoder->new_crtc =
  6980. to_intel_crtc(encoder->base.crtc);
  6981. }
  6982. }
  6983. /**
  6984. * intel_modeset_commit_output_state
  6985. *
  6986. * This function copies the stage display pipe configuration to the real one.
  6987. */
  6988. static void intel_modeset_commit_output_state(struct drm_device *dev)
  6989. {
  6990. struct intel_encoder *encoder;
  6991. struct intel_connector *connector;
  6992. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6993. base.head) {
  6994. connector->base.encoder = &connector->new_encoder->base;
  6995. }
  6996. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6997. base.head) {
  6998. encoder->base.crtc = &encoder->new_crtc->base;
  6999. }
  7000. }
  7001. static void
  7002. connected_sink_compute_bpp(struct intel_connector * connector,
  7003. struct intel_crtc_config *pipe_config)
  7004. {
  7005. int bpp = pipe_config->pipe_bpp;
  7006. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  7007. connector->base.base.id,
  7008. drm_get_connector_name(&connector->base));
  7009. /* Don't use an invalid EDID bpc value */
  7010. if (connector->base.display_info.bpc &&
  7011. connector->base.display_info.bpc * 3 < bpp) {
  7012. DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  7013. bpp, connector->base.display_info.bpc*3);
  7014. pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  7015. }
  7016. /* Clamp bpp to 8 on screens without EDID 1.4 */
  7017. if (connector->base.display_info.bpc == 0 && bpp > 24) {
  7018. DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  7019. bpp);
  7020. pipe_config->pipe_bpp = 24;
  7021. }
  7022. }
  7023. static int
  7024. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  7025. struct drm_framebuffer *fb,
  7026. struct intel_crtc_config *pipe_config)
  7027. {
  7028. struct drm_device *dev = crtc->base.dev;
  7029. struct intel_connector *connector;
  7030. int bpp;
  7031. switch (fb->pixel_format) {
  7032. case DRM_FORMAT_C8:
  7033. bpp = 8*3; /* since we go through a colormap */
  7034. break;
  7035. case DRM_FORMAT_XRGB1555:
  7036. case DRM_FORMAT_ARGB1555:
  7037. /* checked in intel_framebuffer_init already */
  7038. if (WARN_ON(INTEL_INFO(dev)->gen > 3))
  7039. return -EINVAL;
  7040. case DRM_FORMAT_RGB565:
  7041. bpp = 6*3; /* min is 18bpp */
  7042. break;
  7043. case DRM_FORMAT_XBGR8888:
  7044. case DRM_FORMAT_ABGR8888:
  7045. /* checked in intel_framebuffer_init already */
  7046. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  7047. return -EINVAL;
  7048. case DRM_FORMAT_XRGB8888:
  7049. case DRM_FORMAT_ARGB8888:
  7050. bpp = 8*3;
  7051. break;
  7052. case DRM_FORMAT_XRGB2101010:
  7053. case DRM_FORMAT_ARGB2101010:
  7054. case DRM_FORMAT_XBGR2101010:
  7055. case DRM_FORMAT_ABGR2101010:
  7056. /* checked in intel_framebuffer_init already */
  7057. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  7058. return -EINVAL;
  7059. bpp = 10*3;
  7060. break;
  7061. /* TODO: gen4+ supports 16 bpc floating point, too. */
  7062. default:
  7063. DRM_DEBUG_KMS("unsupported depth\n");
  7064. return -EINVAL;
  7065. }
  7066. pipe_config->pipe_bpp = bpp;
  7067. /* Clamp display bpp to EDID value */
  7068. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7069. base.head) {
  7070. if (!connector->new_encoder ||
  7071. connector->new_encoder->new_crtc != crtc)
  7072. continue;
  7073. connected_sink_compute_bpp(connector, pipe_config);
  7074. }
  7075. return bpp;
  7076. }
  7077. static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
  7078. {
  7079. DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
  7080. "type: 0x%x flags: 0x%x\n",
  7081. mode->crtc_clock,
  7082. mode->crtc_hdisplay, mode->crtc_hsync_start,
  7083. mode->crtc_hsync_end, mode->crtc_htotal,
  7084. mode->crtc_vdisplay, mode->crtc_vsync_start,
  7085. mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
  7086. }
  7087. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  7088. struct intel_crtc_config *pipe_config,
  7089. const char *context)
  7090. {
  7091. DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
  7092. context, pipe_name(crtc->pipe));
  7093. DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
  7094. DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  7095. pipe_config->pipe_bpp, pipe_config->dither);
  7096. DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  7097. pipe_config->has_pch_encoder,
  7098. pipe_config->fdi_lanes,
  7099. pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  7100. pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  7101. pipe_config->fdi_m_n.tu);
  7102. DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  7103. pipe_config->has_dp_encoder,
  7104. pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
  7105. pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
  7106. pipe_config->dp_m_n.tu);
  7107. DRM_DEBUG_KMS("requested mode:\n");
  7108. drm_mode_debug_printmodeline(&pipe_config->requested_mode);
  7109. DRM_DEBUG_KMS("adjusted mode:\n");
  7110. drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
  7111. intel_dump_crtc_timings(&pipe_config->adjusted_mode);
  7112. DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
  7113. DRM_DEBUG_KMS("pipe src size: %dx%d\n",
  7114. pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  7115. DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  7116. pipe_config->gmch_pfit.control,
  7117. pipe_config->gmch_pfit.pgm_ratios,
  7118. pipe_config->gmch_pfit.lvds_border_bits);
  7119. DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
  7120. pipe_config->pch_pfit.pos,
  7121. pipe_config->pch_pfit.size,
  7122. pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
  7123. DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  7124. DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  7125. }
  7126. static bool check_encoder_cloning(struct drm_crtc *crtc)
  7127. {
  7128. int num_encoders = 0;
  7129. bool uncloneable_encoders = false;
  7130. struct intel_encoder *encoder;
  7131. list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
  7132. base.head) {
  7133. if (&encoder->new_crtc->base != crtc)
  7134. continue;
  7135. num_encoders++;
  7136. if (!encoder->cloneable)
  7137. uncloneable_encoders = true;
  7138. }
  7139. return !(num_encoders > 1 && uncloneable_encoders);
  7140. }
  7141. static struct intel_crtc_config *
  7142. intel_modeset_pipe_config(struct drm_crtc *crtc,
  7143. struct drm_framebuffer *fb,
  7144. struct drm_display_mode *mode)
  7145. {
  7146. struct drm_device *dev = crtc->dev;
  7147. struct intel_encoder *encoder;
  7148. struct intel_crtc_config *pipe_config;
  7149. int plane_bpp, ret = -EINVAL;
  7150. bool retry = true;
  7151. if (!check_encoder_cloning(crtc)) {
  7152. DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  7153. return ERR_PTR(-EINVAL);
  7154. }
  7155. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  7156. if (!pipe_config)
  7157. return ERR_PTR(-ENOMEM);
  7158. drm_mode_copy(&pipe_config->adjusted_mode, mode);
  7159. drm_mode_copy(&pipe_config->requested_mode, mode);
  7160. pipe_config->cpu_transcoder =
  7161. (enum transcoder) to_intel_crtc(crtc)->pipe;
  7162. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  7163. /*
  7164. * Sanitize sync polarity flags based on requested ones. If neither
  7165. * positive or negative polarity is requested, treat this as meaning
  7166. * negative polarity.
  7167. */
  7168. if (!(pipe_config->adjusted_mode.flags &
  7169. (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
  7170. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
  7171. if (!(pipe_config->adjusted_mode.flags &
  7172. (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
  7173. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
  7174. /* Compute a starting value for pipe_config->pipe_bpp taking the source
  7175. * plane pixel format and any sink constraints into account. Returns the
  7176. * source plane bpp so that dithering can be selected on mismatches
  7177. * after encoders and crtc also have had their say. */
  7178. plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  7179. fb, pipe_config);
  7180. if (plane_bpp < 0)
  7181. goto fail;
  7182. /*
  7183. * Determine the real pipe dimensions. Note that stereo modes can
  7184. * increase the actual pipe size due to the frame doubling and
  7185. * insertion of additional space for blanks between the frame. This
  7186. * is stored in the crtc timings. We use the requested mode to do this
  7187. * computation to clearly distinguish it from the adjusted mode, which
  7188. * can be changed by the connectors in the below retry loop.
  7189. */
  7190. drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
  7191. pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
  7192. pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
  7193. encoder_retry:
  7194. /* Ensure the port clock defaults are reset when retrying. */
  7195. pipe_config->port_clock = 0;
  7196. pipe_config->pixel_multiplier = 1;
  7197. /* Fill in default crtc timings, allow encoders to overwrite them. */
  7198. drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
  7199. /* Pass our mode to the connectors and the CRTC to give them a chance to
  7200. * adjust it according to limitations or connector properties, and also
  7201. * a chance to reject the mode entirely.
  7202. */
  7203. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7204. base.head) {
  7205. if (&encoder->new_crtc->base != crtc)
  7206. continue;
  7207. if (!(encoder->compute_config(encoder, pipe_config))) {
  7208. DRM_DEBUG_KMS("Encoder config failure\n");
  7209. goto fail;
  7210. }
  7211. }
  7212. /* Set default port clock if not overwritten by the encoder. Needs to be
  7213. * done afterwards in case the encoder adjusts the mode. */
  7214. if (!pipe_config->port_clock)
  7215. pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
  7216. * pipe_config->pixel_multiplier;
  7217. ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  7218. if (ret < 0) {
  7219. DRM_DEBUG_KMS("CRTC fixup failed\n");
  7220. goto fail;
  7221. }
  7222. if (ret == RETRY) {
  7223. if (WARN(!retry, "loop in pipe configuration computation\n")) {
  7224. ret = -EINVAL;
  7225. goto fail;
  7226. }
  7227. DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  7228. retry = false;
  7229. goto encoder_retry;
  7230. }
  7231. pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
  7232. DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
  7233. plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  7234. return pipe_config;
  7235. fail:
  7236. kfree(pipe_config);
  7237. return ERR_PTR(ret);
  7238. }
  7239. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  7240. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  7241. static void
  7242. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  7243. unsigned *prepare_pipes, unsigned *disable_pipes)
  7244. {
  7245. struct intel_crtc *intel_crtc;
  7246. struct drm_device *dev = crtc->dev;
  7247. struct intel_encoder *encoder;
  7248. struct intel_connector *connector;
  7249. struct drm_crtc *tmp_crtc;
  7250. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  7251. /* Check which crtcs have changed outputs connected to them, these need
  7252. * to be part of the prepare_pipes mask. We don't (yet) support global
  7253. * modeset across multiple crtcs, so modeset_pipes will only have one
  7254. * bit set at most. */
  7255. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7256. base.head) {
  7257. if (connector->base.encoder == &connector->new_encoder->base)
  7258. continue;
  7259. if (connector->base.encoder) {
  7260. tmp_crtc = connector->base.encoder->crtc;
  7261. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  7262. }
  7263. if (connector->new_encoder)
  7264. *prepare_pipes |=
  7265. 1 << connector->new_encoder->new_crtc->pipe;
  7266. }
  7267. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7268. base.head) {
  7269. if (encoder->base.crtc == &encoder->new_crtc->base)
  7270. continue;
  7271. if (encoder->base.crtc) {
  7272. tmp_crtc = encoder->base.crtc;
  7273. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  7274. }
  7275. if (encoder->new_crtc)
  7276. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  7277. }
  7278. /* Check for any pipes that will be fully disabled ... */
  7279. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  7280. base.head) {
  7281. bool used = false;
  7282. /* Don't try to disable disabled crtcs. */
  7283. if (!intel_crtc->base.enabled)
  7284. continue;
  7285. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7286. base.head) {
  7287. if (encoder->new_crtc == intel_crtc)
  7288. used = true;
  7289. }
  7290. if (!used)
  7291. *disable_pipes |= 1 << intel_crtc->pipe;
  7292. }
  7293. /* set_mode is also used to update properties on life display pipes. */
  7294. intel_crtc = to_intel_crtc(crtc);
  7295. if (crtc->enabled)
  7296. *prepare_pipes |= 1 << intel_crtc->pipe;
  7297. /*
  7298. * For simplicity do a full modeset on any pipe where the output routing
  7299. * changed. We could be more clever, but that would require us to be
  7300. * more careful with calling the relevant encoder->mode_set functions.
  7301. */
  7302. if (*prepare_pipes)
  7303. *modeset_pipes = *prepare_pipes;
  7304. /* ... and mask these out. */
  7305. *modeset_pipes &= ~(*disable_pipes);
  7306. *prepare_pipes &= ~(*disable_pipes);
  7307. /*
  7308. * HACK: We don't (yet) fully support global modesets. intel_set_config
  7309. * obies this rule, but the modeset restore mode of
  7310. * intel_modeset_setup_hw_state does not.
  7311. */
  7312. *modeset_pipes &= 1 << intel_crtc->pipe;
  7313. *prepare_pipes &= 1 << intel_crtc->pipe;
  7314. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  7315. *modeset_pipes, *prepare_pipes, *disable_pipes);
  7316. }
  7317. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  7318. {
  7319. struct drm_encoder *encoder;
  7320. struct drm_device *dev = crtc->dev;
  7321. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  7322. if (encoder->crtc == crtc)
  7323. return true;
  7324. return false;
  7325. }
  7326. static void
  7327. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  7328. {
  7329. struct intel_encoder *intel_encoder;
  7330. struct intel_crtc *intel_crtc;
  7331. struct drm_connector *connector;
  7332. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  7333. base.head) {
  7334. if (!intel_encoder->base.crtc)
  7335. continue;
  7336. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  7337. if (prepare_pipes & (1 << intel_crtc->pipe))
  7338. intel_encoder->connectors_active = false;
  7339. }
  7340. intel_modeset_commit_output_state(dev);
  7341. /* Update computed state. */
  7342. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  7343. base.head) {
  7344. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  7345. }
  7346. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7347. if (!connector->encoder || !connector->encoder->crtc)
  7348. continue;
  7349. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  7350. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  7351. struct drm_property *dpms_property =
  7352. dev->mode_config.dpms_property;
  7353. connector->dpms = DRM_MODE_DPMS_ON;
  7354. drm_object_property_set_value(&connector->base,
  7355. dpms_property,
  7356. DRM_MODE_DPMS_ON);
  7357. intel_encoder = to_intel_encoder(connector->encoder);
  7358. intel_encoder->connectors_active = true;
  7359. }
  7360. }
  7361. }
  7362. static bool intel_fuzzy_clock_check(int clock1, int clock2)
  7363. {
  7364. int diff;
  7365. if (clock1 == clock2)
  7366. return true;
  7367. if (!clock1 || !clock2)
  7368. return false;
  7369. diff = abs(clock1 - clock2);
  7370. if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  7371. return true;
  7372. return false;
  7373. }
  7374. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  7375. list_for_each_entry((intel_crtc), \
  7376. &(dev)->mode_config.crtc_list, \
  7377. base.head) \
  7378. if (mask & (1 <<(intel_crtc)->pipe))
  7379. static bool
  7380. intel_pipe_config_compare(struct drm_device *dev,
  7381. struct intel_crtc_config *current_config,
  7382. struct intel_crtc_config *pipe_config)
  7383. {
  7384. #define PIPE_CONF_CHECK_X(name) \
  7385. if (current_config->name != pipe_config->name) { \
  7386. DRM_ERROR("mismatch in " #name " " \
  7387. "(expected 0x%08x, found 0x%08x)\n", \
  7388. current_config->name, \
  7389. pipe_config->name); \
  7390. return false; \
  7391. }
  7392. #define PIPE_CONF_CHECK_I(name) \
  7393. if (current_config->name != pipe_config->name) { \
  7394. DRM_ERROR("mismatch in " #name " " \
  7395. "(expected %i, found %i)\n", \
  7396. current_config->name, \
  7397. pipe_config->name); \
  7398. return false; \
  7399. }
  7400. #define PIPE_CONF_CHECK_FLAGS(name, mask) \
  7401. if ((current_config->name ^ pipe_config->name) & (mask)) { \
  7402. DRM_ERROR("mismatch in " #name "(" #mask ") " \
  7403. "(expected %i, found %i)\n", \
  7404. current_config->name & (mask), \
  7405. pipe_config->name & (mask)); \
  7406. return false; \
  7407. }
  7408. #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
  7409. if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
  7410. DRM_ERROR("mismatch in " #name " " \
  7411. "(expected %i, found %i)\n", \
  7412. current_config->name, \
  7413. pipe_config->name); \
  7414. return false; \
  7415. }
  7416. #define PIPE_CONF_QUIRK(quirk) \
  7417. ((current_config->quirks | pipe_config->quirks) & (quirk))
  7418. PIPE_CONF_CHECK_I(cpu_transcoder);
  7419. PIPE_CONF_CHECK_I(has_pch_encoder);
  7420. PIPE_CONF_CHECK_I(fdi_lanes);
  7421. PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
  7422. PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
  7423. PIPE_CONF_CHECK_I(fdi_m_n.link_m);
  7424. PIPE_CONF_CHECK_I(fdi_m_n.link_n);
  7425. PIPE_CONF_CHECK_I(fdi_m_n.tu);
  7426. PIPE_CONF_CHECK_I(has_dp_encoder);
  7427. PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
  7428. PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
  7429. PIPE_CONF_CHECK_I(dp_m_n.link_m);
  7430. PIPE_CONF_CHECK_I(dp_m_n.link_n);
  7431. PIPE_CONF_CHECK_I(dp_m_n.tu);
  7432. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
  7433. PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
  7434. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
  7435. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
  7436. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
  7437. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
  7438. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
  7439. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
  7440. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
  7441. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
  7442. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
  7443. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
  7444. PIPE_CONF_CHECK_I(pixel_multiplier);
  7445. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7446. DRM_MODE_FLAG_INTERLACE);
  7447. if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  7448. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7449. DRM_MODE_FLAG_PHSYNC);
  7450. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7451. DRM_MODE_FLAG_NHSYNC);
  7452. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7453. DRM_MODE_FLAG_PVSYNC);
  7454. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7455. DRM_MODE_FLAG_NVSYNC);
  7456. }
  7457. PIPE_CONF_CHECK_I(pipe_src_w);
  7458. PIPE_CONF_CHECK_I(pipe_src_h);
  7459. PIPE_CONF_CHECK_I(gmch_pfit.control);
  7460. /* pfit ratios are autocomputed by the hw on gen4+ */
  7461. if (INTEL_INFO(dev)->gen < 4)
  7462. PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
  7463. PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
  7464. PIPE_CONF_CHECK_I(pch_pfit.enabled);
  7465. if (current_config->pch_pfit.enabled) {
  7466. PIPE_CONF_CHECK_I(pch_pfit.pos);
  7467. PIPE_CONF_CHECK_I(pch_pfit.size);
  7468. }
  7469. PIPE_CONF_CHECK_I(ips_enabled);
  7470. PIPE_CONF_CHECK_I(double_wide);
  7471. PIPE_CONF_CHECK_I(shared_dpll);
  7472. PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  7473. PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  7474. PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  7475. PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  7476. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
  7477. PIPE_CONF_CHECK_I(pipe_bpp);
  7478. if (!IS_HASWELL(dev)) {
  7479. PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
  7480. PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
  7481. }
  7482. #undef PIPE_CONF_CHECK_X
  7483. #undef PIPE_CONF_CHECK_I
  7484. #undef PIPE_CONF_CHECK_FLAGS
  7485. #undef PIPE_CONF_CHECK_CLOCK_FUZZY
  7486. #undef PIPE_CONF_QUIRK
  7487. return true;
  7488. }
  7489. static void
  7490. check_connector_state(struct drm_device *dev)
  7491. {
  7492. struct intel_connector *connector;
  7493. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7494. base.head) {
  7495. /* This also checks the encoder/connector hw state with the
  7496. * ->get_hw_state callbacks. */
  7497. intel_connector_check_state(connector);
  7498. WARN(&connector->new_encoder->base != connector->base.encoder,
  7499. "connector's staged encoder doesn't match current encoder\n");
  7500. }
  7501. }
  7502. static void
  7503. check_encoder_state(struct drm_device *dev)
  7504. {
  7505. struct intel_encoder *encoder;
  7506. struct intel_connector *connector;
  7507. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7508. base.head) {
  7509. bool enabled = false;
  7510. bool active = false;
  7511. enum pipe pipe, tracked_pipe;
  7512. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  7513. encoder->base.base.id,
  7514. drm_get_encoder_name(&encoder->base));
  7515. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  7516. "encoder's stage crtc doesn't match current crtc\n");
  7517. WARN(encoder->connectors_active && !encoder->base.crtc,
  7518. "encoder's active_connectors set, but no crtc\n");
  7519. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7520. base.head) {
  7521. if (connector->base.encoder != &encoder->base)
  7522. continue;
  7523. enabled = true;
  7524. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  7525. active = true;
  7526. }
  7527. WARN(!!encoder->base.crtc != enabled,
  7528. "encoder's enabled state mismatch "
  7529. "(expected %i, found %i)\n",
  7530. !!encoder->base.crtc, enabled);
  7531. WARN(active && !encoder->base.crtc,
  7532. "active encoder with no crtc\n");
  7533. WARN(encoder->connectors_active != active,
  7534. "encoder's computed active state doesn't match tracked active state "
  7535. "(expected %i, found %i)\n", active, encoder->connectors_active);
  7536. active = encoder->get_hw_state(encoder, &pipe);
  7537. WARN(active != encoder->connectors_active,
  7538. "encoder's hw state doesn't match sw tracking "
  7539. "(expected %i, found %i)\n",
  7540. encoder->connectors_active, active);
  7541. if (!encoder->base.crtc)
  7542. continue;
  7543. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  7544. WARN(active && pipe != tracked_pipe,
  7545. "active encoder's pipe doesn't match"
  7546. "(expected %i, found %i)\n",
  7547. tracked_pipe, pipe);
  7548. }
  7549. }
  7550. static void
  7551. check_crtc_state(struct drm_device *dev)
  7552. {
  7553. drm_i915_private_t *dev_priv = dev->dev_private;
  7554. struct intel_crtc *crtc;
  7555. struct intel_encoder *encoder;
  7556. struct intel_crtc_config pipe_config;
  7557. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7558. base.head) {
  7559. bool enabled = false;
  7560. bool active = false;
  7561. memset(&pipe_config, 0, sizeof(pipe_config));
  7562. DRM_DEBUG_KMS("[CRTC:%d]\n",
  7563. crtc->base.base.id);
  7564. WARN(crtc->active && !crtc->base.enabled,
  7565. "active crtc, but not enabled in sw tracking\n");
  7566. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7567. base.head) {
  7568. if (encoder->base.crtc != &crtc->base)
  7569. continue;
  7570. enabled = true;
  7571. if (encoder->connectors_active)
  7572. active = true;
  7573. }
  7574. WARN(active != crtc->active,
  7575. "crtc's computed active state doesn't match tracked active state "
  7576. "(expected %i, found %i)\n", active, crtc->active);
  7577. WARN(enabled != crtc->base.enabled,
  7578. "crtc's computed enabled state doesn't match tracked enabled state "
  7579. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  7580. active = dev_priv->display.get_pipe_config(crtc,
  7581. &pipe_config);
  7582. /* hw state is inconsistent with the pipe A quirk */
  7583. if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  7584. active = crtc->active;
  7585. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7586. base.head) {
  7587. enum pipe pipe;
  7588. if (encoder->base.crtc != &crtc->base)
  7589. continue;
  7590. if (encoder->get_config &&
  7591. encoder->get_hw_state(encoder, &pipe))
  7592. encoder->get_config(encoder, &pipe_config);
  7593. }
  7594. WARN(crtc->active != active,
  7595. "crtc active state doesn't match with hw state "
  7596. "(expected %i, found %i)\n", crtc->active, active);
  7597. if (active &&
  7598. !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
  7599. WARN(1, "pipe state doesn't match!\n");
  7600. intel_dump_pipe_config(crtc, &pipe_config,
  7601. "[hw state]");
  7602. intel_dump_pipe_config(crtc, &crtc->config,
  7603. "[sw state]");
  7604. }
  7605. }
  7606. }
  7607. static void
  7608. check_shared_dpll_state(struct drm_device *dev)
  7609. {
  7610. drm_i915_private_t *dev_priv = dev->dev_private;
  7611. struct intel_crtc *crtc;
  7612. struct intel_dpll_hw_state dpll_hw_state;
  7613. int i;
  7614. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7615. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  7616. int enabled_crtcs = 0, active_crtcs = 0;
  7617. bool active;
  7618. memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  7619. DRM_DEBUG_KMS("%s\n", pll->name);
  7620. active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
  7621. WARN(pll->active > pll->refcount,
  7622. "more active pll users than references: %i vs %i\n",
  7623. pll->active, pll->refcount);
  7624. WARN(pll->active && !pll->on,
  7625. "pll in active use but not on in sw tracking\n");
  7626. WARN(pll->on && !pll->active,
  7627. "pll in on but not on in use in sw tracking\n");
  7628. WARN(pll->on != active,
  7629. "pll on state mismatch (expected %i, found %i)\n",
  7630. pll->on, active);
  7631. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7632. base.head) {
  7633. if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
  7634. enabled_crtcs++;
  7635. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  7636. active_crtcs++;
  7637. }
  7638. WARN(pll->active != active_crtcs,
  7639. "pll active crtcs mismatch (expected %i, found %i)\n",
  7640. pll->active, active_crtcs);
  7641. WARN(pll->refcount != enabled_crtcs,
  7642. "pll enabled crtcs mismatch (expected %i, found %i)\n",
  7643. pll->refcount, enabled_crtcs);
  7644. WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
  7645. sizeof(dpll_hw_state)),
  7646. "pll hw state mismatch\n");
  7647. }
  7648. }
  7649. void
  7650. intel_modeset_check_state(struct drm_device *dev)
  7651. {
  7652. check_connector_state(dev);
  7653. check_encoder_state(dev);
  7654. check_crtc_state(dev);
  7655. check_shared_dpll_state(dev);
  7656. }
  7657. void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
  7658. int dotclock)
  7659. {
  7660. /*
  7661. * FDI already provided one idea for the dotclock.
  7662. * Yell if the encoder disagrees.
  7663. */
  7664. WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
  7665. "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
  7666. pipe_config->adjusted_mode.crtc_clock, dotclock);
  7667. }
  7668. static int __intel_set_mode(struct drm_crtc *crtc,
  7669. struct drm_display_mode *mode,
  7670. int x, int y, struct drm_framebuffer *fb)
  7671. {
  7672. struct drm_device *dev = crtc->dev;
  7673. drm_i915_private_t *dev_priv = dev->dev_private;
  7674. struct drm_display_mode *saved_mode, *saved_hwmode;
  7675. struct intel_crtc_config *pipe_config = NULL;
  7676. struct intel_crtc *intel_crtc;
  7677. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  7678. int ret = 0;
  7679. saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
  7680. if (!saved_mode)
  7681. return -ENOMEM;
  7682. saved_hwmode = saved_mode + 1;
  7683. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  7684. &prepare_pipes, &disable_pipes);
  7685. *saved_hwmode = crtc->hwmode;
  7686. *saved_mode = crtc->mode;
  7687. /* Hack: Because we don't (yet) support global modeset on multiple
  7688. * crtcs, we don't keep track of the new mode for more than one crtc.
  7689. * Hence simply check whether any bit is set in modeset_pipes in all the
  7690. * pieces of code that are not yet converted to deal with mutliple crtcs
  7691. * changing their mode at the same time. */
  7692. if (modeset_pipes) {
  7693. pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
  7694. if (IS_ERR(pipe_config)) {
  7695. ret = PTR_ERR(pipe_config);
  7696. pipe_config = NULL;
  7697. goto out;
  7698. }
  7699. intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  7700. "[modeset]");
  7701. }
  7702. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  7703. intel_crtc_disable(&intel_crtc->base);
  7704. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  7705. if (intel_crtc->base.enabled)
  7706. dev_priv->display.crtc_disable(&intel_crtc->base);
  7707. }
  7708. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  7709. * to set it here already despite that we pass it down the callchain.
  7710. */
  7711. if (modeset_pipes) {
  7712. crtc->mode = *mode;
  7713. /* mode_set/enable/disable functions rely on a correct pipe
  7714. * config. */
  7715. to_intel_crtc(crtc)->config = *pipe_config;
  7716. }
  7717. /* Only after disabling all output pipelines that will be changed can we
  7718. * update the the output configuration. */
  7719. intel_modeset_update_state(dev, prepare_pipes);
  7720. if (dev_priv->display.modeset_global_resources)
  7721. dev_priv->display.modeset_global_resources(dev);
  7722. /* Set up the DPLL and any encoders state that needs to adjust or depend
  7723. * on the DPLL.
  7724. */
  7725. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  7726. ret = intel_crtc_mode_set(&intel_crtc->base,
  7727. x, y, fb);
  7728. if (ret)
  7729. goto done;
  7730. }
  7731. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  7732. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  7733. dev_priv->display.crtc_enable(&intel_crtc->base);
  7734. if (modeset_pipes) {
  7735. /* Store real post-adjustment hardware mode. */
  7736. crtc->hwmode = pipe_config->adjusted_mode;
  7737. /* Calculate and store various constants which
  7738. * are later needed by vblank and swap-completion
  7739. * timestamping. They are derived from true hwmode.
  7740. */
  7741. drm_calc_timestamping_constants(crtc);
  7742. }
  7743. /* FIXME: add subpixel order */
  7744. done:
  7745. if (ret && crtc->enabled) {
  7746. crtc->hwmode = *saved_hwmode;
  7747. crtc->mode = *saved_mode;
  7748. }
  7749. out:
  7750. kfree(pipe_config);
  7751. kfree(saved_mode);
  7752. return ret;
  7753. }
  7754. static int intel_set_mode(struct drm_crtc *crtc,
  7755. struct drm_display_mode *mode,
  7756. int x, int y, struct drm_framebuffer *fb)
  7757. {
  7758. int ret;
  7759. ret = __intel_set_mode(crtc, mode, x, y, fb);
  7760. if (ret == 0)
  7761. intel_modeset_check_state(crtc->dev);
  7762. return ret;
  7763. }
  7764. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  7765. {
  7766. intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  7767. }
  7768. #undef for_each_intel_crtc_masked
  7769. static void intel_set_config_free(struct intel_set_config *config)
  7770. {
  7771. if (!config)
  7772. return;
  7773. kfree(config->save_connector_encoders);
  7774. kfree(config->save_encoder_crtcs);
  7775. kfree(config);
  7776. }
  7777. static int intel_set_config_save_state(struct drm_device *dev,
  7778. struct intel_set_config *config)
  7779. {
  7780. struct drm_encoder *encoder;
  7781. struct drm_connector *connector;
  7782. int count;
  7783. config->save_encoder_crtcs =
  7784. kcalloc(dev->mode_config.num_encoder,
  7785. sizeof(struct drm_crtc *), GFP_KERNEL);
  7786. if (!config->save_encoder_crtcs)
  7787. return -ENOMEM;
  7788. config->save_connector_encoders =
  7789. kcalloc(dev->mode_config.num_connector,
  7790. sizeof(struct drm_encoder *), GFP_KERNEL);
  7791. if (!config->save_connector_encoders)
  7792. return -ENOMEM;
  7793. /* Copy data. Note that driver private data is not affected.
  7794. * Should anything bad happen only the expected state is
  7795. * restored, not the drivers personal bookkeeping.
  7796. */
  7797. count = 0;
  7798. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  7799. config->save_encoder_crtcs[count++] = encoder->crtc;
  7800. }
  7801. count = 0;
  7802. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7803. config->save_connector_encoders[count++] = connector->encoder;
  7804. }
  7805. return 0;
  7806. }
  7807. static void intel_set_config_restore_state(struct drm_device *dev,
  7808. struct intel_set_config *config)
  7809. {
  7810. struct intel_encoder *encoder;
  7811. struct intel_connector *connector;
  7812. int count;
  7813. count = 0;
  7814. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  7815. encoder->new_crtc =
  7816. to_intel_crtc(config->save_encoder_crtcs[count++]);
  7817. }
  7818. count = 0;
  7819. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  7820. connector->new_encoder =
  7821. to_intel_encoder(config->save_connector_encoders[count++]);
  7822. }
  7823. }
  7824. static bool
  7825. is_crtc_connector_off(struct drm_mode_set *set)
  7826. {
  7827. int i;
  7828. if (set->num_connectors == 0)
  7829. return false;
  7830. if (WARN_ON(set->connectors == NULL))
  7831. return false;
  7832. for (i = 0; i < set->num_connectors; i++)
  7833. if (set->connectors[i]->encoder &&
  7834. set->connectors[i]->encoder->crtc == set->crtc &&
  7835. set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
  7836. return true;
  7837. return false;
  7838. }
  7839. static void
  7840. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  7841. struct intel_set_config *config)
  7842. {
  7843. /* We should be able to check here if the fb has the same properties
  7844. * and then just flip_or_move it */
  7845. if (is_crtc_connector_off(set)) {
  7846. config->mode_changed = true;
  7847. } else if (set->crtc->fb != set->fb) {
  7848. /* If we have no fb then treat it as a full mode set */
  7849. if (set->crtc->fb == NULL) {
  7850. struct intel_crtc *intel_crtc =
  7851. to_intel_crtc(set->crtc);
  7852. if (intel_crtc->active && i915_fastboot) {
  7853. DRM_DEBUG_KMS("crtc has no fb, will flip\n");
  7854. config->fb_changed = true;
  7855. } else {
  7856. DRM_DEBUG_KMS("inactive crtc, full mode set\n");
  7857. config->mode_changed = true;
  7858. }
  7859. } else if (set->fb == NULL) {
  7860. config->mode_changed = true;
  7861. } else if (set->fb->pixel_format !=
  7862. set->crtc->fb->pixel_format) {
  7863. config->mode_changed = true;
  7864. } else {
  7865. config->fb_changed = true;
  7866. }
  7867. }
  7868. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  7869. config->fb_changed = true;
  7870. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  7871. DRM_DEBUG_KMS("modes are different, full mode set\n");
  7872. drm_mode_debug_printmodeline(&set->crtc->mode);
  7873. drm_mode_debug_printmodeline(set->mode);
  7874. config->mode_changed = true;
  7875. }
  7876. DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
  7877. set->crtc->base.id, config->mode_changed, config->fb_changed);
  7878. }
  7879. static int
  7880. intel_modeset_stage_output_state(struct drm_device *dev,
  7881. struct drm_mode_set *set,
  7882. struct intel_set_config *config)
  7883. {
  7884. struct drm_crtc *new_crtc;
  7885. struct intel_connector *connector;
  7886. struct intel_encoder *encoder;
  7887. int ro;
  7888. /* The upper layers ensure that we either disable a crtc or have a list
  7889. * of connectors. For paranoia, double-check this. */
  7890. WARN_ON(!set->fb && (set->num_connectors != 0));
  7891. WARN_ON(set->fb && (set->num_connectors == 0));
  7892. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7893. base.head) {
  7894. /* Otherwise traverse passed in connector list and get encoders
  7895. * for them. */
  7896. for (ro = 0; ro < set->num_connectors; ro++) {
  7897. if (set->connectors[ro] == &connector->base) {
  7898. connector->new_encoder = connector->encoder;
  7899. break;
  7900. }
  7901. }
  7902. /* If we disable the crtc, disable all its connectors. Also, if
  7903. * the connector is on the changing crtc but not on the new
  7904. * connector list, disable it. */
  7905. if ((!set->fb || ro == set->num_connectors) &&
  7906. connector->base.encoder &&
  7907. connector->base.encoder->crtc == set->crtc) {
  7908. connector->new_encoder = NULL;
  7909. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  7910. connector->base.base.id,
  7911. drm_get_connector_name(&connector->base));
  7912. }
  7913. if (&connector->new_encoder->base != connector->base.encoder) {
  7914. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  7915. config->mode_changed = true;
  7916. }
  7917. }
  7918. /* connector->new_encoder is now updated for all connectors. */
  7919. /* Update crtc of enabled connectors. */
  7920. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7921. base.head) {
  7922. if (!connector->new_encoder)
  7923. continue;
  7924. new_crtc = connector->new_encoder->base.crtc;
  7925. for (ro = 0; ro < set->num_connectors; ro++) {
  7926. if (set->connectors[ro] == &connector->base)
  7927. new_crtc = set->crtc;
  7928. }
  7929. /* Make sure the new CRTC will work with the encoder */
  7930. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  7931. new_crtc)) {
  7932. return -EINVAL;
  7933. }
  7934. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  7935. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  7936. connector->base.base.id,
  7937. drm_get_connector_name(&connector->base),
  7938. new_crtc->base.id);
  7939. }
  7940. /* Check for any encoders that needs to be disabled. */
  7941. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7942. base.head) {
  7943. list_for_each_entry(connector,
  7944. &dev->mode_config.connector_list,
  7945. base.head) {
  7946. if (connector->new_encoder == encoder) {
  7947. WARN_ON(!connector->new_encoder->new_crtc);
  7948. goto next_encoder;
  7949. }
  7950. }
  7951. encoder->new_crtc = NULL;
  7952. next_encoder:
  7953. /* Only now check for crtc changes so we don't miss encoders
  7954. * that will be disabled. */
  7955. if (&encoder->new_crtc->base != encoder->base.crtc) {
  7956. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  7957. config->mode_changed = true;
  7958. }
  7959. }
  7960. /* Now we've also updated encoder->new_crtc for all encoders. */
  7961. return 0;
  7962. }
  7963. static int intel_crtc_set_config(struct drm_mode_set *set)
  7964. {
  7965. struct drm_device *dev;
  7966. struct drm_mode_set save_set;
  7967. struct intel_set_config *config;
  7968. int ret;
  7969. BUG_ON(!set);
  7970. BUG_ON(!set->crtc);
  7971. BUG_ON(!set->crtc->helper_private);
  7972. /* Enforce sane interface api - has been abused by the fb helper. */
  7973. BUG_ON(!set->mode && set->fb);
  7974. BUG_ON(set->fb && set->num_connectors == 0);
  7975. if (set->fb) {
  7976. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  7977. set->crtc->base.id, set->fb->base.id,
  7978. (int)set->num_connectors, set->x, set->y);
  7979. } else {
  7980. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  7981. }
  7982. dev = set->crtc->dev;
  7983. ret = -ENOMEM;
  7984. config = kzalloc(sizeof(*config), GFP_KERNEL);
  7985. if (!config)
  7986. goto out_config;
  7987. ret = intel_set_config_save_state(dev, config);
  7988. if (ret)
  7989. goto out_config;
  7990. save_set.crtc = set->crtc;
  7991. save_set.mode = &set->crtc->mode;
  7992. save_set.x = set->crtc->x;
  7993. save_set.y = set->crtc->y;
  7994. save_set.fb = set->crtc->fb;
  7995. /* Compute whether we need a full modeset, only an fb base update or no
  7996. * change at all. In the future we might also check whether only the
  7997. * mode changed, e.g. for LVDS where we only change the panel fitter in
  7998. * such cases. */
  7999. intel_set_config_compute_mode_changes(set, config);
  8000. ret = intel_modeset_stage_output_state(dev, set, config);
  8001. if (ret)
  8002. goto fail;
  8003. if (config->mode_changed) {
  8004. ret = intel_set_mode(set->crtc, set->mode,
  8005. set->x, set->y, set->fb);
  8006. } else if (config->fb_changed) {
  8007. intel_crtc_wait_for_pending_flips(set->crtc);
  8008. ret = intel_pipe_set_base(set->crtc,
  8009. set->x, set->y, set->fb);
  8010. }
  8011. if (ret) {
  8012. DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
  8013. set->crtc->base.id, ret);
  8014. fail:
  8015. intel_set_config_restore_state(dev, config);
  8016. /* Try to restore the config */
  8017. if (config->mode_changed &&
  8018. intel_set_mode(save_set.crtc, save_set.mode,
  8019. save_set.x, save_set.y, save_set.fb))
  8020. DRM_ERROR("failed to restore config after modeset failure\n");
  8021. }
  8022. out_config:
  8023. intel_set_config_free(config);
  8024. return ret;
  8025. }
  8026. static const struct drm_crtc_funcs intel_crtc_funcs = {
  8027. .cursor_set = intel_crtc_cursor_set,
  8028. .cursor_move = intel_crtc_cursor_move,
  8029. .gamma_set = intel_crtc_gamma_set,
  8030. .set_config = intel_crtc_set_config,
  8031. .destroy = intel_crtc_destroy,
  8032. .page_flip = intel_crtc_page_flip,
  8033. };
  8034. static void intel_cpu_pll_init(struct drm_device *dev)
  8035. {
  8036. if (HAS_DDI(dev))
  8037. intel_ddi_pll_init(dev);
  8038. }
  8039. static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
  8040. struct intel_shared_dpll *pll,
  8041. struct intel_dpll_hw_state *hw_state)
  8042. {
  8043. uint32_t val;
  8044. val = I915_READ(PCH_DPLL(pll->id));
  8045. hw_state->dpll = val;
  8046. hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
  8047. hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
  8048. return val & DPLL_VCO_ENABLE;
  8049. }
  8050. static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
  8051. struct intel_shared_dpll *pll)
  8052. {
  8053. I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
  8054. I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
  8055. }
  8056. static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
  8057. struct intel_shared_dpll *pll)
  8058. {
  8059. /* PCH refclock must be enabled first */
  8060. assert_pch_refclk_enabled(dev_priv);
  8061. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  8062. /* Wait for the clocks to stabilize. */
  8063. POSTING_READ(PCH_DPLL(pll->id));
  8064. udelay(150);
  8065. /* The pixel multiplier can only be updated once the
  8066. * DPLL is enabled and the clocks are stable.
  8067. *
  8068. * So write it again.
  8069. */
  8070. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  8071. POSTING_READ(PCH_DPLL(pll->id));
  8072. udelay(200);
  8073. }
  8074. static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
  8075. struct intel_shared_dpll *pll)
  8076. {
  8077. struct drm_device *dev = dev_priv->dev;
  8078. struct intel_crtc *crtc;
  8079. /* Make sure no transcoder isn't still depending on us. */
  8080. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  8081. if (intel_crtc_to_shared_dpll(crtc) == pll)
  8082. assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
  8083. }
  8084. I915_WRITE(PCH_DPLL(pll->id), 0);
  8085. POSTING_READ(PCH_DPLL(pll->id));
  8086. udelay(200);
  8087. }
  8088. static char *ibx_pch_dpll_names[] = {
  8089. "PCH DPLL A",
  8090. "PCH DPLL B",
  8091. };
  8092. static void ibx_pch_dpll_init(struct drm_device *dev)
  8093. {
  8094. struct drm_i915_private *dev_priv = dev->dev_private;
  8095. int i;
  8096. dev_priv->num_shared_dpll = 2;
  8097. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8098. dev_priv->shared_dplls[i].id = i;
  8099. dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
  8100. dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
  8101. dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
  8102. dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
  8103. dev_priv->shared_dplls[i].get_hw_state =
  8104. ibx_pch_dpll_get_hw_state;
  8105. }
  8106. }
  8107. static void intel_shared_dpll_init(struct drm_device *dev)
  8108. {
  8109. struct drm_i915_private *dev_priv = dev->dev_private;
  8110. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  8111. ibx_pch_dpll_init(dev);
  8112. else
  8113. dev_priv->num_shared_dpll = 0;
  8114. BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
  8115. DRM_DEBUG_KMS("%i shared PLLs initialized\n",
  8116. dev_priv->num_shared_dpll);
  8117. }
  8118. static void intel_crtc_init(struct drm_device *dev, int pipe)
  8119. {
  8120. drm_i915_private_t *dev_priv = dev->dev_private;
  8121. struct intel_crtc *intel_crtc;
  8122. int i;
  8123. intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
  8124. if (intel_crtc == NULL)
  8125. return;
  8126. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  8127. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  8128. for (i = 0; i < 256; i++) {
  8129. intel_crtc->lut_r[i] = i;
  8130. intel_crtc->lut_g[i] = i;
  8131. intel_crtc->lut_b[i] = i;
  8132. }
  8133. /* Swap pipes & planes for FBC on pre-965 */
  8134. intel_crtc->pipe = pipe;
  8135. intel_crtc->plane = pipe;
  8136. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  8137. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  8138. intel_crtc->plane = !pipe;
  8139. }
  8140. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  8141. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  8142. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  8143. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  8144. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  8145. }
  8146. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  8147. struct drm_file *file)
  8148. {
  8149. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  8150. struct drm_mode_object *drmmode_obj;
  8151. struct intel_crtc *crtc;
  8152. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  8153. return -ENODEV;
  8154. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  8155. DRM_MODE_OBJECT_CRTC);
  8156. if (!drmmode_obj) {
  8157. DRM_ERROR("no such CRTC id\n");
  8158. return -EINVAL;
  8159. }
  8160. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  8161. pipe_from_crtc_id->pipe = crtc->pipe;
  8162. return 0;
  8163. }
  8164. static int intel_encoder_clones(struct intel_encoder *encoder)
  8165. {
  8166. struct drm_device *dev = encoder->base.dev;
  8167. struct intel_encoder *source_encoder;
  8168. int index_mask = 0;
  8169. int entry = 0;
  8170. list_for_each_entry(source_encoder,
  8171. &dev->mode_config.encoder_list, base.head) {
  8172. if (encoder == source_encoder)
  8173. index_mask |= (1 << entry);
  8174. /* Intel hw has only one MUX where enocoders could be cloned. */
  8175. if (encoder->cloneable && source_encoder->cloneable)
  8176. index_mask |= (1 << entry);
  8177. entry++;
  8178. }
  8179. return index_mask;
  8180. }
  8181. static bool has_edp_a(struct drm_device *dev)
  8182. {
  8183. struct drm_i915_private *dev_priv = dev->dev_private;
  8184. if (!IS_MOBILE(dev))
  8185. return false;
  8186. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  8187. return false;
  8188. if (IS_GEN5(dev) &&
  8189. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  8190. return false;
  8191. return true;
  8192. }
  8193. static void intel_setup_outputs(struct drm_device *dev)
  8194. {
  8195. struct drm_i915_private *dev_priv = dev->dev_private;
  8196. struct intel_encoder *encoder;
  8197. bool dpd_is_edp = false;
  8198. intel_lvds_init(dev);
  8199. if (!IS_ULT(dev))
  8200. intel_crt_init(dev);
  8201. if (HAS_DDI(dev)) {
  8202. int found;
  8203. /* Haswell uses DDI functions to detect digital outputs */
  8204. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  8205. /* DDI A only supports eDP */
  8206. if (found)
  8207. intel_ddi_init(dev, PORT_A);
  8208. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  8209. * register */
  8210. found = I915_READ(SFUSE_STRAP);
  8211. if (found & SFUSE_STRAP_DDIB_DETECTED)
  8212. intel_ddi_init(dev, PORT_B);
  8213. if (found & SFUSE_STRAP_DDIC_DETECTED)
  8214. intel_ddi_init(dev, PORT_C);
  8215. if (found & SFUSE_STRAP_DDID_DETECTED)
  8216. intel_ddi_init(dev, PORT_D);
  8217. } else if (HAS_PCH_SPLIT(dev)) {
  8218. int found;
  8219. dpd_is_edp = intel_dpd_is_edp(dev);
  8220. if (has_edp_a(dev))
  8221. intel_dp_init(dev, DP_A, PORT_A);
  8222. if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  8223. /* PCH SDVOB multiplex with HDMIB */
  8224. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  8225. if (!found)
  8226. intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  8227. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  8228. intel_dp_init(dev, PCH_DP_B, PORT_B);
  8229. }
  8230. if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  8231. intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  8232. if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  8233. intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  8234. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  8235. intel_dp_init(dev, PCH_DP_C, PORT_C);
  8236. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  8237. intel_dp_init(dev, PCH_DP_D, PORT_D);
  8238. } else if (IS_VALLEYVIEW(dev)) {
  8239. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
  8240. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
  8241. PORT_B);
  8242. if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
  8243. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
  8244. }
  8245. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
  8246. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
  8247. PORT_C);
  8248. if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
  8249. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
  8250. PORT_C);
  8251. }
  8252. intel_dsi_init(dev);
  8253. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  8254. bool found = false;
  8255. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  8256. DRM_DEBUG_KMS("probing SDVOB\n");
  8257. found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  8258. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  8259. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  8260. intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  8261. }
  8262. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  8263. intel_dp_init(dev, DP_B, PORT_B);
  8264. }
  8265. /* Before G4X SDVOC doesn't have its own detect register */
  8266. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  8267. DRM_DEBUG_KMS("probing SDVOC\n");
  8268. found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  8269. }
  8270. if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  8271. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  8272. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  8273. intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  8274. }
  8275. if (SUPPORTS_INTEGRATED_DP(dev))
  8276. intel_dp_init(dev, DP_C, PORT_C);
  8277. }
  8278. if (SUPPORTS_INTEGRATED_DP(dev) &&
  8279. (I915_READ(DP_D) & DP_DETECTED))
  8280. intel_dp_init(dev, DP_D, PORT_D);
  8281. } else if (IS_GEN2(dev))
  8282. intel_dvo_init(dev);
  8283. if (SUPPORTS_TV(dev))
  8284. intel_tv_init(dev);
  8285. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  8286. encoder->base.possible_crtcs = encoder->crtc_mask;
  8287. encoder->base.possible_clones =
  8288. intel_encoder_clones(encoder);
  8289. }
  8290. intel_init_pch_refclk(dev);
  8291. drm_helper_move_panel_connectors_to_head(dev);
  8292. }
  8293. void intel_framebuffer_fini(struct intel_framebuffer *fb)
  8294. {
  8295. drm_framebuffer_cleanup(&fb->base);
  8296. drm_gem_object_unreference_unlocked(&fb->obj->base);
  8297. }
  8298. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  8299. {
  8300. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  8301. intel_framebuffer_fini(intel_fb);
  8302. kfree(intel_fb);
  8303. }
  8304. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  8305. struct drm_file *file,
  8306. unsigned int *handle)
  8307. {
  8308. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  8309. struct drm_i915_gem_object *obj = intel_fb->obj;
  8310. return drm_gem_handle_create(file, &obj->base, handle);
  8311. }
  8312. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  8313. .destroy = intel_user_framebuffer_destroy,
  8314. .create_handle = intel_user_framebuffer_create_handle,
  8315. };
  8316. int intel_framebuffer_init(struct drm_device *dev,
  8317. struct intel_framebuffer *intel_fb,
  8318. struct drm_mode_fb_cmd2 *mode_cmd,
  8319. struct drm_i915_gem_object *obj)
  8320. {
  8321. int pitch_limit;
  8322. int ret;
  8323. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  8324. if (obj->tiling_mode == I915_TILING_Y) {
  8325. DRM_DEBUG("hardware does not support tiling Y\n");
  8326. return -EINVAL;
  8327. }
  8328. if (mode_cmd->pitches[0] & 63) {
  8329. DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
  8330. mode_cmd->pitches[0]);
  8331. return -EINVAL;
  8332. }
  8333. if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
  8334. pitch_limit = 32*1024;
  8335. } else if (INTEL_INFO(dev)->gen >= 4) {
  8336. if (obj->tiling_mode)
  8337. pitch_limit = 16*1024;
  8338. else
  8339. pitch_limit = 32*1024;
  8340. } else if (INTEL_INFO(dev)->gen >= 3) {
  8341. if (obj->tiling_mode)
  8342. pitch_limit = 8*1024;
  8343. else
  8344. pitch_limit = 16*1024;
  8345. } else
  8346. /* XXX DSPC is limited to 4k tiled */
  8347. pitch_limit = 8*1024;
  8348. if (mode_cmd->pitches[0] > pitch_limit) {
  8349. DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
  8350. obj->tiling_mode ? "tiled" : "linear",
  8351. mode_cmd->pitches[0], pitch_limit);
  8352. return -EINVAL;
  8353. }
  8354. if (obj->tiling_mode != I915_TILING_NONE &&
  8355. mode_cmd->pitches[0] != obj->stride) {
  8356. DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  8357. mode_cmd->pitches[0], obj->stride);
  8358. return -EINVAL;
  8359. }
  8360. /* Reject formats not supported by any plane early. */
  8361. switch (mode_cmd->pixel_format) {
  8362. case DRM_FORMAT_C8:
  8363. case DRM_FORMAT_RGB565:
  8364. case DRM_FORMAT_XRGB8888:
  8365. case DRM_FORMAT_ARGB8888:
  8366. break;
  8367. case DRM_FORMAT_XRGB1555:
  8368. case DRM_FORMAT_ARGB1555:
  8369. if (INTEL_INFO(dev)->gen > 3) {
  8370. DRM_DEBUG("unsupported pixel format: %s\n",
  8371. drm_get_format_name(mode_cmd->pixel_format));
  8372. return -EINVAL;
  8373. }
  8374. break;
  8375. case DRM_FORMAT_XBGR8888:
  8376. case DRM_FORMAT_ABGR8888:
  8377. case DRM_FORMAT_XRGB2101010:
  8378. case DRM_FORMAT_ARGB2101010:
  8379. case DRM_FORMAT_XBGR2101010:
  8380. case DRM_FORMAT_ABGR2101010:
  8381. if (INTEL_INFO(dev)->gen < 4) {
  8382. DRM_DEBUG("unsupported pixel format: %s\n",
  8383. drm_get_format_name(mode_cmd->pixel_format));
  8384. return -EINVAL;
  8385. }
  8386. break;
  8387. case DRM_FORMAT_YUYV:
  8388. case DRM_FORMAT_UYVY:
  8389. case DRM_FORMAT_YVYU:
  8390. case DRM_FORMAT_VYUY:
  8391. if (INTEL_INFO(dev)->gen < 5) {
  8392. DRM_DEBUG("unsupported pixel format: %s\n",
  8393. drm_get_format_name(mode_cmd->pixel_format));
  8394. return -EINVAL;
  8395. }
  8396. break;
  8397. default:
  8398. DRM_DEBUG("unsupported pixel format: %s\n",
  8399. drm_get_format_name(mode_cmd->pixel_format));
  8400. return -EINVAL;
  8401. }
  8402. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  8403. if (mode_cmd->offsets[0] != 0)
  8404. return -EINVAL;
  8405. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  8406. intel_fb->obj = obj;
  8407. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  8408. if (ret) {
  8409. DRM_ERROR("framebuffer init failed %d\n", ret);
  8410. return ret;
  8411. }
  8412. return 0;
  8413. }
  8414. static struct drm_framebuffer *
  8415. intel_user_framebuffer_create(struct drm_device *dev,
  8416. struct drm_file *filp,
  8417. struct drm_mode_fb_cmd2 *mode_cmd)
  8418. {
  8419. struct drm_i915_gem_object *obj;
  8420. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  8421. mode_cmd->handles[0]));
  8422. if (&obj->base == NULL)
  8423. return ERR_PTR(-ENOENT);
  8424. return intel_framebuffer_create(dev, mode_cmd, obj);
  8425. }
  8426. #ifndef CONFIG_DRM_I915_FBDEV
  8427. static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
  8428. {
  8429. }
  8430. #endif
  8431. static const struct drm_mode_config_funcs intel_mode_funcs = {
  8432. .fb_create = intel_user_framebuffer_create,
  8433. .output_poll_changed = intel_fbdev_output_poll_changed,
  8434. };
  8435. /* Set up chip specific display functions */
  8436. static void intel_init_display(struct drm_device *dev)
  8437. {
  8438. struct drm_i915_private *dev_priv = dev->dev_private;
  8439. if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
  8440. dev_priv->display.find_dpll = g4x_find_best_dpll;
  8441. else if (IS_VALLEYVIEW(dev))
  8442. dev_priv->display.find_dpll = vlv_find_best_dpll;
  8443. else if (IS_PINEVIEW(dev))
  8444. dev_priv->display.find_dpll = pnv_find_best_dpll;
  8445. else
  8446. dev_priv->display.find_dpll = i9xx_find_best_dpll;
  8447. if (HAS_DDI(dev)) {
  8448. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  8449. dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  8450. dev_priv->display.crtc_enable = haswell_crtc_enable;
  8451. dev_priv->display.crtc_disable = haswell_crtc_disable;
  8452. dev_priv->display.off = haswell_crtc_off;
  8453. dev_priv->display.update_plane = ironlake_update_plane;
  8454. } else if (HAS_PCH_SPLIT(dev)) {
  8455. dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  8456. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  8457. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  8458. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  8459. dev_priv->display.off = ironlake_crtc_off;
  8460. dev_priv->display.update_plane = ironlake_update_plane;
  8461. } else if (IS_VALLEYVIEW(dev)) {
  8462. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8463. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8464. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  8465. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8466. dev_priv->display.off = i9xx_crtc_off;
  8467. dev_priv->display.update_plane = i9xx_update_plane;
  8468. } else {
  8469. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8470. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8471. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  8472. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8473. dev_priv->display.off = i9xx_crtc_off;
  8474. dev_priv->display.update_plane = i9xx_update_plane;
  8475. }
  8476. /* Returns the core display clock speed */
  8477. if (IS_VALLEYVIEW(dev))
  8478. dev_priv->display.get_display_clock_speed =
  8479. valleyview_get_display_clock_speed;
  8480. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  8481. dev_priv->display.get_display_clock_speed =
  8482. i945_get_display_clock_speed;
  8483. else if (IS_I915G(dev))
  8484. dev_priv->display.get_display_clock_speed =
  8485. i915_get_display_clock_speed;
  8486. else if (IS_I945GM(dev) || IS_845G(dev))
  8487. dev_priv->display.get_display_clock_speed =
  8488. i9xx_misc_get_display_clock_speed;
  8489. else if (IS_PINEVIEW(dev))
  8490. dev_priv->display.get_display_clock_speed =
  8491. pnv_get_display_clock_speed;
  8492. else if (IS_I915GM(dev))
  8493. dev_priv->display.get_display_clock_speed =
  8494. i915gm_get_display_clock_speed;
  8495. else if (IS_I865G(dev))
  8496. dev_priv->display.get_display_clock_speed =
  8497. i865_get_display_clock_speed;
  8498. else if (IS_I85X(dev))
  8499. dev_priv->display.get_display_clock_speed =
  8500. i855_get_display_clock_speed;
  8501. else /* 852, 830 */
  8502. dev_priv->display.get_display_clock_speed =
  8503. i830_get_display_clock_speed;
  8504. if (HAS_PCH_SPLIT(dev)) {
  8505. if (IS_GEN5(dev)) {
  8506. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  8507. dev_priv->display.write_eld = ironlake_write_eld;
  8508. } else if (IS_GEN6(dev)) {
  8509. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  8510. dev_priv->display.write_eld = ironlake_write_eld;
  8511. } else if (IS_IVYBRIDGE(dev)) {
  8512. /* FIXME: detect B0+ stepping and use auto training */
  8513. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  8514. dev_priv->display.write_eld = ironlake_write_eld;
  8515. dev_priv->display.modeset_global_resources =
  8516. ivb_modeset_global_resources;
  8517. } else if (IS_HASWELL(dev)) {
  8518. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  8519. dev_priv->display.write_eld = haswell_write_eld;
  8520. dev_priv->display.modeset_global_resources =
  8521. haswell_modeset_global_resources;
  8522. }
  8523. } else if (IS_G4X(dev)) {
  8524. dev_priv->display.write_eld = g4x_write_eld;
  8525. }
  8526. /* Default just returns -ENODEV to indicate unsupported */
  8527. dev_priv->display.queue_flip = intel_default_queue_flip;
  8528. switch (INTEL_INFO(dev)->gen) {
  8529. case 2:
  8530. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  8531. break;
  8532. case 3:
  8533. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  8534. break;
  8535. case 4:
  8536. case 5:
  8537. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  8538. break;
  8539. case 6:
  8540. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  8541. break;
  8542. case 7:
  8543. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  8544. break;
  8545. }
  8546. }
  8547. /*
  8548. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  8549. * resume, or other times. This quirk makes sure that's the case for
  8550. * affected systems.
  8551. */
  8552. static void quirk_pipea_force(struct drm_device *dev)
  8553. {
  8554. struct drm_i915_private *dev_priv = dev->dev_private;
  8555. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  8556. DRM_INFO("applying pipe a force quirk\n");
  8557. }
  8558. /*
  8559. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  8560. */
  8561. static void quirk_ssc_force_disable(struct drm_device *dev)
  8562. {
  8563. struct drm_i915_private *dev_priv = dev->dev_private;
  8564. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  8565. DRM_INFO("applying lvds SSC disable quirk\n");
  8566. }
  8567. /*
  8568. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  8569. * brightness value
  8570. */
  8571. static void quirk_invert_brightness(struct drm_device *dev)
  8572. {
  8573. struct drm_i915_private *dev_priv = dev->dev_private;
  8574. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  8575. DRM_INFO("applying inverted panel brightness quirk\n");
  8576. }
  8577. /*
  8578. * Some machines (Dell XPS13) suffer broken backlight controls if
  8579. * BLM_PCH_PWM_ENABLE is set.
  8580. */
  8581. static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
  8582. {
  8583. struct drm_i915_private *dev_priv = dev->dev_private;
  8584. dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
  8585. DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
  8586. }
  8587. struct intel_quirk {
  8588. int device;
  8589. int subsystem_vendor;
  8590. int subsystem_device;
  8591. void (*hook)(struct drm_device *dev);
  8592. };
  8593. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  8594. struct intel_dmi_quirk {
  8595. void (*hook)(struct drm_device *dev);
  8596. const struct dmi_system_id (*dmi_id_list)[];
  8597. };
  8598. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  8599. {
  8600. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  8601. return 1;
  8602. }
  8603. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  8604. {
  8605. .dmi_id_list = &(const struct dmi_system_id[]) {
  8606. {
  8607. .callback = intel_dmi_reverse_brightness,
  8608. .ident = "NCR Corporation",
  8609. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  8610. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  8611. },
  8612. },
  8613. { } /* terminating entry */
  8614. },
  8615. .hook = quirk_invert_brightness,
  8616. },
  8617. };
  8618. static struct intel_quirk intel_quirks[] = {
  8619. /* HP Mini needs pipe A force quirk (LP: #322104) */
  8620. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  8621. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  8622. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  8623. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  8624. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  8625. /* 830 needs to leave pipe A & dpll A up */
  8626. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8627. /* Lenovo U160 cannot use SSC on LVDS */
  8628. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  8629. /* Sony Vaio Y cannot use SSC on LVDS */
  8630. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  8631. /*
  8632. * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
  8633. * seem to use inverted backlight PWM.
  8634. */
  8635. { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
  8636. /* Dell XPS13 HD Sandy Bridge */
  8637. { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
  8638. /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
  8639. { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
  8640. };
  8641. static void intel_init_quirks(struct drm_device *dev)
  8642. {
  8643. struct pci_dev *d = dev->pdev;
  8644. int i;
  8645. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  8646. struct intel_quirk *q = &intel_quirks[i];
  8647. if (d->device == q->device &&
  8648. (d->subsystem_vendor == q->subsystem_vendor ||
  8649. q->subsystem_vendor == PCI_ANY_ID) &&
  8650. (d->subsystem_device == q->subsystem_device ||
  8651. q->subsystem_device == PCI_ANY_ID))
  8652. q->hook(dev);
  8653. }
  8654. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  8655. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  8656. intel_dmi_quirks[i].hook(dev);
  8657. }
  8658. }
  8659. /* Disable the VGA plane that we never use */
  8660. static void i915_disable_vga(struct drm_device *dev)
  8661. {
  8662. struct drm_i915_private *dev_priv = dev->dev_private;
  8663. u8 sr1;
  8664. u32 vga_reg = i915_vgacntrl_reg(dev);
  8665. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8666. outb(SR01, VGA_SR_INDEX);
  8667. sr1 = inb(VGA_SR_DATA);
  8668. outb(sr1 | 1<<5, VGA_SR_DATA);
  8669. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8670. udelay(300);
  8671. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  8672. POSTING_READ(vga_reg);
  8673. }
  8674. static void i915_enable_vga_mem(struct drm_device *dev)
  8675. {
  8676. /* Enable VGA memory on Intel HD */
  8677. if (HAS_PCH_SPLIT(dev)) {
  8678. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8679. outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
  8680. vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
  8681. VGA_RSRC_LEGACY_MEM |
  8682. VGA_RSRC_NORMAL_IO |
  8683. VGA_RSRC_NORMAL_MEM);
  8684. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8685. }
  8686. }
  8687. void i915_disable_vga_mem(struct drm_device *dev)
  8688. {
  8689. /* Disable VGA memory on Intel HD */
  8690. if (HAS_PCH_SPLIT(dev)) {
  8691. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8692. outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
  8693. vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
  8694. VGA_RSRC_NORMAL_IO |
  8695. VGA_RSRC_NORMAL_MEM);
  8696. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8697. }
  8698. }
  8699. void intel_modeset_init_hw(struct drm_device *dev)
  8700. {
  8701. struct drm_i915_private *dev_priv = dev->dev_private;
  8702. intel_prepare_ddi(dev);
  8703. intel_init_clock_gating(dev);
  8704. /* Enable the CRI clock source so we can get at the display */
  8705. if (IS_VALLEYVIEW(dev))
  8706. I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
  8707. DPLL_INTEGRATED_CRI_CLK_VLV);
  8708. intel_init_dpio(dev);
  8709. mutex_lock(&dev->struct_mutex);
  8710. intel_enable_gt_powersave(dev);
  8711. mutex_unlock(&dev->struct_mutex);
  8712. }
  8713. void intel_modeset_suspend_hw(struct drm_device *dev)
  8714. {
  8715. intel_suspend_hw(dev);
  8716. }
  8717. void intel_modeset_init(struct drm_device *dev)
  8718. {
  8719. struct drm_i915_private *dev_priv = dev->dev_private;
  8720. int i, j, ret;
  8721. drm_mode_config_init(dev);
  8722. dev->mode_config.min_width = 0;
  8723. dev->mode_config.min_height = 0;
  8724. dev->mode_config.preferred_depth = 24;
  8725. dev->mode_config.prefer_shadow = 1;
  8726. dev->mode_config.funcs = &intel_mode_funcs;
  8727. intel_init_quirks(dev);
  8728. intel_init_pm(dev);
  8729. if (INTEL_INFO(dev)->num_pipes == 0)
  8730. return;
  8731. intel_init_display(dev);
  8732. if (IS_GEN2(dev)) {
  8733. dev->mode_config.max_width = 2048;
  8734. dev->mode_config.max_height = 2048;
  8735. } else if (IS_GEN3(dev)) {
  8736. dev->mode_config.max_width = 4096;
  8737. dev->mode_config.max_height = 4096;
  8738. } else {
  8739. dev->mode_config.max_width = 8192;
  8740. dev->mode_config.max_height = 8192;
  8741. }
  8742. dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  8743. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  8744. INTEL_INFO(dev)->num_pipes,
  8745. INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  8746. for_each_pipe(i) {
  8747. intel_crtc_init(dev, i);
  8748. for (j = 0; j < dev_priv->num_plane; j++) {
  8749. ret = intel_plane_init(dev, i, j);
  8750. if (ret)
  8751. DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  8752. pipe_name(i), sprite_name(i, j), ret);
  8753. }
  8754. }
  8755. intel_cpu_pll_init(dev);
  8756. intel_shared_dpll_init(dev);
  8757. /* Just disable it once at startup */
  8758. i915_disable_vga(dev);
  8759. intel_setup_outputs(dev);
  8760. /* Just in case the BIOS is doing something questionable. */
  8761. intel_disable_fbc(dev);
  8762. }
  8763. static void
  8764. intel_connector_break_all_links(struct intel_connector *connector)
  8765. {
  8766. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8767. connector->base.encoder = NULL;
  8768. connector->encoder->connectors_active = false;
  8769. connector->encoder->base.crtc = NULL;
  8770. }
  8771. static void intel_enable_pipe_a(struct drm_device *dev)
  8772. {
  8773. struct intel_connector *connector;
  8774. struct drm_connector *crt = NULL;
  8775. struct intel_load_detect_pipe load_detect_temp;
  8776. /* We can't just switch on the pipe A, we need to set things up with a
  8777. * proper mode and output configuration. As a gross hack, enable pipe A
  8778. * by enabling the load detect pipe once. */
  8779. list_for_each_entry(connector,
  8780. &dev->mode_config.connector_list,
  8781. base.head) {
  8782. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  8783. crt = &connector->base;
  8784. break;
  8785. }
  8786. }
  8787. if (!crt)
  8788. return;
  8789. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  8790. intel_release_load_detect_pipe(crt, &load_detect_temp);
  8791. }
  8792. static bool
  8793. intel_check_plane_mapping(struct intel_crtc *crtc)
  8794. {
  8795. struct drm_device *dev = crtc->base.dev;
  8796. struct drm_i915_private *dev_priv = dev->dev_private;
  8797. u32 reg, val;
  8798. if (INTEL_INFO(dev)->num_pipes == 1)
  8799. return true;
  8800. reg = DSPCNTR(!crtc->plane);
  8801. val = I915_READ(reg);
  8802. if ((val & DISPLAY_PLANE_ENABLE) &&
  8803. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  8804. return false;
  8805. return true;
  8806. }
  8807. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  8808. {
  8809. struct drm_device *dev = crtc->base.dev;
  8810. struct drm_i915_private *dev_priv = dev->dev_private;
  8811. u32 reg;
  8812. /* Clear any frame start delays used for debugging left by the BIOS */
  8813. reg = PIPECONF(crtc->config.cpu_transcoder);
  8814. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  8815. /* We need to sanitize the plane -> pipe mapping first because this will
  8816. * disable the crtc (and hence change the state) if it is wrong. Note
  8817. * that gen4+ has a fixed plane -> pipe mapping. */
  8818. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  8819. struct intel_connector *connector;
  8820. bool plane;
  8821. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  8822. crtc->base.base.id);
  8823. /* Pipe has the wrong plane attached and the plane is active.
  8824. * Temporarily change the plane mapping and disable everything
  8825. * ... */
  8826. plane = crtc->plane;
  8827. crtc->plane = !plane;
  8828. dev_priv->display.crtc_disable(&crtc->base);
  8829. crtc->plane = plane;
  8830. /* ... and break all links. */
  8831. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8832. base.head) {
  8833. if (connector->encoder->base.crtc != &crtc->base)
  8834. continue;
  8835. intel_connector_break_all_links(connector);
  8836. }
  8837. WARN_ON(crtc->active);
  8838. crtc->base.enabled = false;
  8839. }
  8840. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  8841. crtc->pipe == PIPE_A && !crtc->active) {
  8842. /* BIOS forgot to enable pipe A, this mostly happens after
  8843. * resume. Force-enable the pipe to fix this, the update_dpms
  8844. * call below we restore the pipe to the right state, but leave
  8845. * the required bits on. */
  8846. intel_enable_pipe_a(dev);
  8847. }
  8848. /* Adjust the state of the output pipe according to whether we
  8849. * have active connectors/encoders. */
  8850. intel_crtc_update_dpms(&crtc->base);
  8851. if (crtc->active != crtc->base.enabled) {
  8852. struct intel_encoder *encoder;
  8853. /* This can happen either due to bugs in the get_hw_state
  8854. * functions or because the pipe is force-enabled due to the
  8855. * pipe A quirk. */
  8856. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  8857. crtc->base.base.id,
  8858. crtc->base.enabled ? "enabled" : "disabled",
  8859. crtc->active ? "enabled" : "disabled");
  8860. crtc->base.enabled = crtc->active;
  8861. /* Because we only establish the connector -> encoder ->
  8862. * crtc links if something is active, this means the
  8863. * crtc is now deactivated. Break the links. connector
  8864. * -> encoder links are only establish when things are
  8865. * actually up, hence no need to break them. */
  8866. WARN_ON(crtc->active);
  8867. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  8868. WARN_ON(encoder->connectors_active);
  8869. encoder->base.crtc = NULL;
  8870. }
  8871. }
  8872. }
  8873. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  8874. {
  8875. struct intel_connector *connector;
  8876. struct drm_device *dev = encoder->base.dev;
  8877. /* We need to check both for a crtc link (meaning that the
  8878. * encoder is active and trying to read from a pipe) and the
  8879. * pipe itself being active. */
  8880. bool has_active_crtc = encoder->base.crtc &&
  8881. to_intel_crtc(encoder->base.crtc)->active;
  8882. if (encoder->connectors_active && !has_active_crtc) {
  8883. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  8884. encoder->base.base.id,
  8885. drm_get_encoder_name(&encoder->base));
  8886. /* Connector is active, but has no active pipe. This is
  8887. * fallout from our resume register restoring. Disable
  8888. * the encoder manually again. */
  8889. if (encoder->base.crtc) {
  8890. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  8891. encoder->base.base.id,
  8892. drm_get_encoder_name(&encoder->base));
  8893. encoder->disable(encoder);
  8894. }
  8895. /* Inconsistent output/port/pipe state happens presumably due to
  8896. * a bug in one of the get_hw_state functions. Or someplace else
  8897. * in our code, like the register restore mess on resume. Clamp
  8898. * things to off as a safer default. */
  8899. list_for_each_entry(connector,
  8900. &dev->mode_config.connector_list,
  8901. base.head) {
  8902. if (connector->encoder != encoder)
  8903. continue;
  8904. intel_connector_break_all_links(connector);
  8905. }
  8906. }
  8907. /* Enabled encoders without active connectors will be fixed in
  8908. * the crtc fixup. */
  8909. }
  8910. void i915_redisable_vga(struct drm_device *dev)
  8911. {
  8912. struct drm_i915_private *dev_priv = dev->dev_private;
  8913. u32 vga_reg = i915_vgacntrl_reg(dev);
  8914. /* This function can be called both from intel_modeset_setup_hw_state or
  8915. * at a very early point in our resume sequence, where the power well
  8916. * structures are not yet restored. Since this function is at a very
  8917. * paranoid "someone might have enabled VGA while we were not looking"
  8918. * level, just check if the power well is enabled instead of trying to
  8919. * follow the "don't touch the power well if we don't need it" policy
  8920. * the rest of the driver uses. */
  8921. if (HAS_POWER_WELL(dev) &&
  8922. (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
  8923. return;
  8924. if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
  8925. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  8926. i915_disable_vga(dev);
  8927. i915_disable_vga_mem(dev);
  8928. }
  8929. }
  8930. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  8931. {
  8932. struct drm_i915_private *dev_priv = dev->dev_private;
  8933. enum pipe pipe;
  8934. struct intel_crtc *crtc;
  8935. struct intel_encoder *encoder;
  8936. struct intel_connector *connector;
  8937. int i;
  8938. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8939. base.head) {
  8940. memset(&crtc->config, 0, sizeof(crtc->config));
  8941. crtc->active = dev_priv->display.get_pipe_config(crtc,
  8942. &crtc->config);
  8943. crtc->base.enabled = crtc->active;
  8944. crtc->primary_enabled = crtc->active;
  8945. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  8946. crtc->base.base.id,
  8947. crtc->active ? "enabled" : "disabled");
  8948. }
  8949. /* FIXME: Smash this into the new shared dpll infrastructure. */
  8950. if (HAS_DDI(dev))
  8951. intel_ddi_setup_hw_pll_state(dev);
  8952. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8953. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8954. pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
  8955. pll->active = 0;
  8956. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8957. base.head) {
  8958. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  8959. pll->active++;
  8960. }
  8961. pll->refcount = pll->active;
  8962. DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
  8963. pll->name, pll->refcount, pll->on);
  8964. }
  8965. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8966. base.head) {
  8967. pipe = 0;
  8968. if (encoder->get_hw_state(encoder, &pipe)) {
  8969. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8970. encoder->base.crtc = &crtc->base;
  8971. if (encoder->get_config)
  8972. encoder->get_config(encoder, &crtc->config);
  8973. } else {
  8974. encoder->base.crtc = NULL;
  8975. }
  8976. encoder->connectors_active = false;
  8977. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
  8978. encoder->base.base.id,
  8979. drm_get_encoder_name(&encoder->base),
  8980. encoder->base.crtc ? "enabled" : "disabled",
  8981. pipe_name(pipe));
  8982. }
  8983. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8984. base.head) {
  8985. if (connector->get_hw_state(connector)) {
  8986. connector->base.dpms = DRM_MODE_DPMS_ON;
  8987. connector->encoder->connectors_active = true;
  8988. connector->base.encoder = &connector->encoder->base;
  8989. } else {
  8990. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8991. connector->base.encoder = NULL;
  8992. }
  8993. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  8994. connector->base.base.id,
  8995. drm_get_connector_name(&connector->base),
  8996. connector->base.encoder ? "enabled" : "disabled");
  8997. }
  8998. }
  8999. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  9000. * and i915 state tracking structures. */
  9001. void intel_modeset_setup_hw_state(struct drm_device *dev,
  9002. bool force_restore)
  9003. {
  9004. struct drm_i915_private *dev_priv = dev->dev_private;
  9005. enum pipe pipe;
  9006. struct intel_crtc *crtc;
  9007. struct intel_encoder *encoder;
  9008. int i;
  9009. intel_modeset_readout_hw_state(dev);
  9010. /*
  9011. * Now that we have the config, copy it to each CRTC struct
  9012. * Note that this could go away if we move to using crtc_config
  9013. * checking everywhere.
  9014. */
  9015. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  9016. base.head) {
  9017. if (crtc->active && i915_fastboot) {
  9018. intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
  9019. DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
  9020. crtc->base.base.id);
  9021. drm_mode_debug_printmodeline(&crtc->base.mode);
  9022. }
  9023. }
  9024. /* HW state is read out, now we need to sanitize this mess. */
  9025. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  9026. base.head) {
  9027. intel_sanitize_encoder(encoder);
  9028. }
  9029. for_each_pipe(pipe) {
  9030. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  9031. intel_sanitize_crtc(crtc);
  9032. intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
  9033. }
  9034. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  9035. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  9036. if (!pll->on || pll->active)
  9037. continue;
  9038. DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  9039. pll->disable(dev_priv, pll);
  9040. pll->on = false;
  9041. }
  9042. if (IS_HASWELL(dev))
  9043. ilk_wm_get_hw_state(dev);
  9044. if (force_restore) {
  9045. i915_redisable_vga(dev);
  9046. /*
  9047. * We need to use raw interfaces for restoring state to avoid
  9048. * checking (bogus) intermediate states.
  9049. */
  9050. for_each_pipe(pipe) {
  9051. struct drm_crtc *crtc =
  9052. dev_priv->pipe_to_crtc_mapping[pipe];
  9053. __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  9054. crtc->fb);
  9055. }
  9056. } else {
  9057. intel_modeset_update_staged_output_state(dev);
  9058. }
  9059. intel_modeset_check_state(dev);
  9060. drm_mode_config_reset(dev);
  9061. }
  9062. void intel_modeset_gem_init(struct drm_device *dev)
  9063. {
  9064. intel_modeset_init_hw(dev);
  9065. intel_setup_overlay(dev);
  9066. intel_modeset_setup_hw_state(dev, false);
  9067. }
  9068. void intel_modeset_cleanup(struct drm_device *dev)
  9069. {
  9070. struct drm_i915_private *dev_priv = dev->dev_private;
  9071. struct drm_crtc *crtc;
  9072. struct drm_connector *connector;
  9073. /*
  9074. * Interrupts and polling as the first thing to avoid creating havoc.
  9075. * Too much stuff here (turning of rps, connectors, ...) would
  9076. * experience fancy races otherwise.
  9077. */
  9078. drm_irq_uninstall(dev);
  9079. cancel_work_sync(&dev_priv->hotplug_work);
  9080. /*
  9081. * Due to the hpd irq storm handling the hotplug work can re-arm the
  9082. * poll handlers. Hence disable polling after hpd handling is shut down.
  9083. */
  9084. drm_kms_helper_poll_fini(dev);
  9085. mutex_lock(&dev->struct_mutex);
  9086. intel_unregister_dsm_handler();
  9087. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  9088. /* Skip inactive CRTCs */
  9089. if (!crtc->fb)
  9090. continue;
  9091. intel_increase_pllclock(crtc);
  9092. }
  9093. intel_disable_fbc(dev);
  9094. i915_enable_vga_mem(dev);
  9095. intel_disable_gt_powersave(dev);
  9096. ironlake_teardown_rc6(dev);
  9097. mutex_unlock(&dev->struct_mutex);
  9098. /* flush any delayed tasks or pending work */
  9099. flush_scheduled_work();
  9100. /* destroy backlight, if any, before the connectors */
  9101. intel_panel_destroy_backlight(dev);
  9102. /* destroy the sysfs files before encoders/connectors */
  9103. list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  9104. drm_sysfs_connector_remove(connector);
  9105. drm_mode_config_cleanup(dev);
  9106. intel_cleanup_overlay(dev);
  9107. }
  9108. /*
  9109. * Return which encoder is currently attached for connector.
  9110. */
  9111. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  9112. {
  9113. return &intel_attached_encoder(connector)->base;
  9114. }
  9115. void intel_connector_attach_encoder(struct intel_connector *connector,
  9116. struct intel_encoder *encoder)
  9117. {
  9118. connector->encoder = encoder;
  9119. drm_mode_connector_attach_encoder(&connector->base,
  9120. &encoder->base);
  9121. }
  9122. /*
  9123. * set vga decode state - true == enable VGA decode
  9124. */
  9125. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  9126. {
  9127. struct drm_i915_private *dev_priv = dev->dev_private;
  9128. u16 gmch_ctrl;
  9129. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  9130. if (state)
  9131. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  9132. else
  9133. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  9134. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  9135. return 0;
  9136. }
  9137. struct intel_display_error_state {
  9138. u32 power_well_driver;
  9139. int num_transcoders;
  9140. struct intel_cursor_error_state {
  9141. u32 control;
  9142. u32 position;
  9143. u32 base;
  9144. u32 size;
  9145. } cursor[I915_MAX_PIPES];
  9146. struct intel_pipe_error_state {
  9147. u32 source;
  9148. } pipe[I915_MAX_PIPES];
  9149. struct intel_plane_error_state {
  9150. u32 control;
  9151. u32 stride;
  9152. u32 size;
  9153. u32 pos;
  9154. u32 addr;
  9155. u32 surface;
  9156. u32 tile_offset;
  9157. } plane[I915_MAX_PIPES];
  9158. struct intel_transcoder_error_state {
  9159. enum transcoder cpu_transcoder;
  9160. u32 conf;
  9161. u32 htotal;
  9162. u32 hblank;
  9163. u32 hsync;
  9164. u32 vtotal;
  9165. u32 vblank;
  9166. u32 vsync;
  9167. } transcoder[4];
  9168. };
  9169. struct intel_display_error_state *
  9170. intel_display_capture_error_state(struct drm_device *dev)
  9171. {
  9172. drm_i915_private_t *dev_priv = dev->dev_private;
  9173. struct intel_display_error_state *error;
  9174. int transcoders[] = {
  9175. TRANSCODER_A,
  9176. TRANSCODER_B,
  9177. TRANSCODER_C,
  9178. TRANSCODER_EDP,
  9179. };
  9180. int i;
  9181. if (INTEL_INFO(dev)->num_pipes == 0)
  9182. return NULL;
  9183. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  9184. if (error == NULL)
  9185. return NULL;
  9186. if (HAS_POWER_WELL(dev))
  9187. error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  9188. for_each_pipe(i) {
  9189. if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
  9190. error->cursor[i].control = I915_READ(CURCNTR(i));
  9191. error->cursor[i].position = I915_READ(CURPOS(i));
  9192. error->cursor[i].base = I915_READ(CURBASE(i));
  9193. } else {
  9194. error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
  9195. error->cursor[i].position = I915_READ(CURPOS_IVB(i));
  9196. error->cursor[i].base = I915_READ(CURBASE_IVB(i));
  9197. }
  9198. error->plane[i].control = I915_READ(DSPCNTR(i));
  9199. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  9200. if (INTEL_INFO(dev)->gen <= 3) {
  9201. error->plane[i].size = I915_READ(DSPSIZE(i));
  9202. error->plane[i].pos = I915_READ(DSPPOS(i));
  9203. }
  9204. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  9205. error->plane[i].addr = I915_READ(DSPADDR(i));
  9206. if (INTEL_INFO(dev)->gen >= 4) {
  9207. error->plane[i].surface = I915_READ(DSPSURF(i));
  9208. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  9209. }
  9210. error->pipe[i].source = I915_READ(PIPESRC(i));
  9211. }
  9212. error->num_transcoders = INTEL_INFO(dev)->num_pipes;
  9213. if (HAS_DDI(dev_priv->dev))
  9214. error->num_transcoders++; /* Account for eDP. */
  9215. for (i = 0; i < error->num_transcoders; i++) {
  9216. enum transcoder cpu_transcoder = transcoders[i];
  9217. error->transcoder[i].cpu_transcoder = cpu_transcoder;
  9218. error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  9219. error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  9220. error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  9221. error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  9222. error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  9223. error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  9224. error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  9225. }
  9226. /* In the code above we read the registers without checking if the power
  9227. * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
  9228. * prevent the next I915_WRITE from detecting it and printing an error
  9229. * message. */
  9230. intel_uncore_clear_errors(dev);
  9231. return error;
  9232. }
  9233. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  9234. void
  9235. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  9236. struct drm_device *dev,
  9237. struct intel_display_error_state *error)
  9238. {
  9239. int i;
  9240. if (!error)
  9241. return;
  9242. err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  9243. if (HAS_POWER_WELL(dev))
  9244. err_printf(m, "PWR_WELL_CTL2: %08x\n",
  9245. error->power_well_driver);
  9246. for_each_pipe(i) {
  9247. err_printf(m, "Pipe [%d]:\n", i);
  9248. err_printf(m, " SRC: %08x\n", error->pipe[i].source);
  9249. err_printf(m, "Plane [%d]:\n", i);
  9250. err_printf(m, " CNTR: %08x\n", error->plane[i].control);
  9251. err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  9252. if (INTEL_INFO(dev)->gen <= 3) {
  9253. err_printf(m, " SIZE: %08x\n", error->plane[i].size);
  9254. err_printf(m, " POS: %08x\n", error->plane[i].pos);
  9255. }
  9256. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  9257. err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  9258. if (INTEL_INFO(dev)->gen >= 4) {
  9259. err_printf(m, " SURF: %08x\n", error->plane[i].surface);
  9260. err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  9261. }
  9262. err_printf(m, "Cursor [%d]:\n", i);
  9263. err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  9264. err_printf(m, " POS: %08x\n", error->cursor[i].position);
  9265. err_printf(m, " BASE: %08x\n", error->cursor[i].base);
  9266. }
  9267. for (i = 0; i < error->num_transcoders; i++) {
  9268. err_printf(m, " CPU transcoder: %c\n",
  9269. transcoder_name(error->transcoder[i].cpu_transcoder));
  9270. err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
  9271. err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
  9272. err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
  9273. err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
  9274. err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
  9275. err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
  9276. err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
  9277. }
  9278. }