ci13xxx_udc.c 72 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/irq.h>
  60. #include <linux/kernel.h>
  61. #include <linux/slab.h>
  62. #include <linux/pm_runtime.h>
  63. #include <linux/usb/ch9.h>
  64. #include <linux/usb/gadget.h>
  65. #include <linux/usb/otg.h>
  66. #include "ci13xxx_udc.h"
  67. /******************************************************************************
  68. * DEFINE
  69. *****************************************************************************/
  70. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  71. /* ctrl register bank access */
  72. static DEFINE_SPINLOCK(udc_lock);
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* UDC descriptor */
  91. static struct ci13xxx *_udc;
  92. /* Interrupt statistics */
  93. #define ISR_MASK 0x1F
  94. static struct {
  95. u32 test;
  96. u32 ui;
  97. u32 uei;
  98. u32 pci;
  99. u32 uri;
  100. u32 sli;
  101. u32 none;
  102. struct {
  103. u32 cnt;
  104. u32 buf[ISR_MASK+1];
  105. u32 idx;
  106. } hndl;
  107. } isr_statistics;
  108. /**
  109. * ffs_nr: find first (least significant) bit set
  110. * @x: the word to search
  111. *
  112. * This function returns bit number (instead of position)
  113. */
  114. static int ffs_nr(u32 x)
  115. {
  116. int n = ffs(x);
  117. return n ? n-1 : 32;
  118. }
  119. /******************************************************************************
  120. * HW block
  121. *****************************************************************************/
  122. /* register bank descriptor */
  123. static struct {
  124. unsigned lpm; /* is LPM? */
  125. void __iomem *abs; /* bus map offset */
  126. void __iomem *cap; /* bus map offset + CAP offset + CAP data */
  127. size_t size; /* bank size */
  128. } hw_bank;
  129. /* MSM specific */
  130. #define ABS_AHBBURST (0x0090UL)
  131. #define ABS_AHBMODE (0x0098UL)
  132. /* UDC register map */
  133. #define ABS_CAPLENGTH (0x100UL)
  134. #define ABS_HCCPARAMS (0x108UL)
  135. #define ABS_DCCPARAMS (0x124UL)
  136. #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
  137. /* offset to CAPLENTGH (addr + data) */
  138. #define CAP_USBCMD (0x000UL)
  139. #define CAP_USBSTS (0x004UL)
  140. #define CAP_USBINTR (0x008UL)
  141. #define CAP_DEVICEADDR (0x014UL)
  142. #define CAP_ENDPTLISTADDR (0x018UL)
  143. #define CAP_PORTSC (0x044UL)
  144. #define CAP_DEVLC (0x084UL)
  145. #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
  146. #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
  147. #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
  148. #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
  149. #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
  150. #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
  151. #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
  152. #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
  153. /* maximum number of enpoints: valid only after hw_device_reset() */
  154. static unsigned hw_ep_max;
  155. /**
  156. * hw_ep_bit: calculates the bit number
  157. * @num: endpoint number
  158. * @dir: endpoint direction
  159. *
  160. * This function returns bit number
  161. */
  162. static inline int hw_ep_bit(int num, int dir)
  163. {
  164. return num + (dir ? 16 : 0);
  165. }
  166. static int ep_to_bit(int n)
  167. {
  168. int fill = 16 - hw_ep_max / 2;
  169. if (n >= hw_ep_max / 2)
  170. n += fill;
  171. return n;
  172. }
  173. /**
  174. * hw_aread: reads from register bitfield
  175. * @addr: address relative to bus map
  176. * @mask: bitfield mask
  177. *
  178. * This function returns register bitfield data
  179. */
  180. static u32 hw_aread(u32 addr, u32 mask)
  181. {
  182. return ioread32(addr + hw_bank.abs) & mask;
  183. }
  184. /**
  185. * hw_awrite: writes to register bitfield
  186. * @addr: address relative to bus map
  187. * @mask: bitfield mask
  188. * @data: new data
  189. */
  190. static void hw_awrite(u32 addr, u32 mask, u32 data)
  191. {
  192. iowrite32(hw_aread(addr, ~mask) | (data & mask),
  193. addr + hw_bank.abs);
  194. }
  195. /**
  196. * hw_cread: reads from register bitfield
  197. * @addr: address relative to CAP offset plus content
  198. * @mask: bitfield mask
  199. *
  200. * This function returns register bitfield data
  201. */
  202. static u32 hw_cread(u32 addr, u32 mask)
  203. {
  204. return ioread32(addr + hw_bank.cap) & mask;
  205. }
  206. /**
  207. * hw_cwrite: writes to register bitfield
  208. * @addr: address relative to CAP offset plus content
  209. * @mask: bitfield mask
  210. * @data: new data
  211. */
  212. static void hw_cwrite(u32 addr, u32 mask, u32 data)
  213. {
  214. iowrite32(hw_cread(addr, ~mask) | (data & mask),
  215. addr + hw_bank.cap);
  216. }
  217. /**
  218. * hw_ctest_and_clear: tests & clears register bitfield
  219. * @addr: address relative to CAP offset plus content
  220. * @mask: bitfield mask
  221. *
  222. * This function returns register bitfield data
  223. */
  224. static u32 hw_ctest_and_clear(u32 addr, u32 mask)
  225. {
  226. u32 reg = hw_cread(addr, mask);
  227. iowrite32(reg, addr + hw_bank.cap);
  228. return reg;
  229. }
  230. /**
  231. * hw_ctest_and_write: tests & writes register bitfield
  232. * @addr: address relative to CAP offset plus content
  233. * @mask: bitfield mask
  234. * @data: new data
  235. *
  236. * This function returns register bitfield data
  237. */
  238. static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
  239. {
  240. u32 reg = hw_cread(addr, ~0);
  241. iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
  242. return (reg & mask) >> ffs_nr(mask);
  243. }
  244. static int hw_device_init(void __iomem *base)
  245. {
  246. u32 reg;
  247. /* bank is a module variable */
  248. hw_bank.abs = base;
  249. hw_bank.cap = hw_bank.abs;
  250. hw_bank.cap += ABS_CAPLENGTH;
  251. hw_bank.cap += ioread8(hw_bank.cap);
  252. reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
  253. hw_bank.lpm = reg;
  254. hw_bank.size = hw_bank.cap - hw_bank.abs;
  255. hw_bank.size += CAP_LAST;
  256. hw_bank.size /= sizeof(u32);
  257. reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
  258. hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  259. if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
  260. return -ENODEV;
  261. /* setup lock mode ? */
  262. /* ENDPTSETUPSTAT is '0' by default */
  263. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  264. return 0;
  265. }
  266. /**
  267. * hw_device_reset: resets chip (execute without interruption)
  268. * @base: register base address
  269. *
  270. * This function returns an error code
  271. */
  272. static int hw_device_reset(struct ci13xxx *udc)
  273. {
  274. /* should flush & stop before reset */
  275. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
  276. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  277. hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
  278. while (hw_cread(CAP_USBCMD, USBCMD_RST))
  279. udelay(10); /* not RTOS friendly */
  280. if (udc->udc_driver->notify_event)
  281. udc->udc_driver->notify_event(udc,
  282. CI13XXX_CONTROLLER_RESET_EVENT);
  283. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  284. hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  285. /* USBMODE should be configured step by step */
  286. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  287. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  288. hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
  289. if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  290. pr_err("cannot enter in device mode");
  291. pr_err("lpm = %i", hw_bank.lpm);
  292. return -ENODEV;
  293. }
  294. return 0;
  295. }
  296. /**
  297. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  298. * without interruption)
  299. * @dma: 0 => disable, !0 => enable and set dma engine
  300. *
  301. * This function returns an error code
  302. */
  303. static int hw_device_state(u32 dma)
  304. {
  305. if (dma) {
  306. hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
  307. /* interrupt, error, port change, reset, sleep/suspend */
  308. hw_cwrite(CAP_USBINTR, ~0,
  309. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  310. hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
  311. } else {
  312. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  313. hw_cwrite(CAP_USBINTR, ~0, 0);
  314. }
  315. return 0;
  316. }
  317. /**
  318. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  319. * @num: endpoint number
  320. * @dir: endpoint direction
  321. *
  322. * This function returns an error code
  323. */
  324. static int hw_ep_flush(int num, int dir)
  325. {
  326. int n = hw_ep_bit(num, dir);
  327. do {
  328. /* flush any pending transfer */
  329. hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
  330. while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
  331. cpu_relax();
  332. } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
  333. return 0;
  334. }
  335. /**
  336. * hw_ep_disable: disables endpoint (execute without interruption)
  337. * @num: endpoint number
  338. * @dir: endpoint direction
  339. *
  340. * This function returns an error code
  341. */
  342. static int hw_ep_disable(int num, int dir)
  343. {
  344. hw_ep_flush(num, dir);
  345. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
  346. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  347. return 0;
  348. }
  349. /**
  350. * hw_ep_enable: enables endpoint (execute without interruption)
  351. * @num: endpoint number
  352. * @dir: endpoint direction
  353. * @type: endpoint type
  354. *
  355. * This function returns an error code
  356. */
  357. static int hw_ep_enable(int num, int dir, int type)
  358. {
  359. u32 mask, data;
  360. if (dir) {
  361. mask = ENDPTCTRL_TXT; /* type */
  362. data = type << ffs_nr(mask);
  363. mask |= ENDPTCTRL_TXS; /* unstall */
  364. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  365. data |= ENDPTCTRL_TXR;
  366. mask |= ENDPTCTRL_TXE; /* enable */
  367. data |= ENDPTCTRL_TXE;
  368. } else {
  369. mask = ENDPTCTRL_RXT; /* type */
  370. data = type << ffs_nr(mask);
  371. mask |= ENDPTCTRL_RXS; /* unstall */
  372. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  373. data |= ENDPTCTRL_RXR;
  374. mask |= ENDPTCTRL_RXE; /* enable */
  375. data |= ENDPTCTRL_RXE;
  376. }
  377. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
  378. return 0;
  379. }
  380. /**
  381. * hw_ep_get_halt: return endpoint halt status
  382. * @num: endpoint number
  383. * @dir: endpoint direction
  384. *
  385. * This function returns 1 if endpoint halted
  386. */
  387. static int hw_ep_get_halt(int num, int dir)
  388. {
  389. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  390. return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
  391. }
  392. /**
  393. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  394. * interruption)
  395. * @n: endpoint number
  396. *
  397. * This function returns setup status
  398. */
  399. static int hw_test_and_clear_setup_status(int n)
  400. {
  401. n = ep_to_bit(n);
  402. return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
  403. }
  404. /**
  405. * hw_ep_prime: primes endpoint (execute without interruption)
  406. * @num: endpoint number
  407. * @dir: endpoint direction
  408. * @is_ctrl: true if control endpoint
  409. *
  410. * This function returns an error code
  411. */
  412. static int hw_ep_prime(int num, int dir, int is_ctrl)
  413. {
  414. int n = hw_ep_bit(num, dir);
  415. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  416. return -EAGAIN;
  417. hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
  418. while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  419. cpu_relax();
  420. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  421. return -EAGAIN;
  422. /* status shoult be tested according with manual but it doesn't work */
  423. return 0;
  424. }
  425. /**
  426. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  427. * without interruption)
  428. * @num: endpoint number
  429. * @dir: endpoint direction
  430. * @value: true => stall, false => unstall
  431. *
  432. * This function returns an error code
  433. */
  434. static int hw_ep_set_halt(int num, int dir, int value)
  435. {
  436. if (value != 0 && value != 1)
  437. return -EINVAL;
  438. do {
  439. u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
  440. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  441. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  442. /* data toggle - reserved for EP0 but it's in ESS */
  443. hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
  444. } while (value != hw_ep_get_halt(num, dir));
  445. return 0;
  446. }
  447. /**
  448. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  449. * interruption)
  450. * @n: interrupt bit
  451. *
  452. * This function returns an error code
  453. */
  454. static int hw_intr_clear(int n)
  455. {
  456. if (n >= REG_BITS)
  457. return -EINVAL;
  458. hw_cwrite(CAP_USBINTR, BIT(n), 0);
  459. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  460. return 0;
  461. }
  462. /**
  463. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  464. * interruption)
  465. * @n: interrupt bit
  466. *
  467. * This function returns an error code
  468. */
  469. static int hw_intr_force(int n)
  470. {
  471. if (n >= REG_BITS)
  472. return -EINVAL;
  473. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  474. hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
  475. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  476. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
  477. return 0;
  478. }
  479. /**
  480. * hw_is_port_high_speed: test if port is high speed
  481. *
  482. * This function returns true if high speed port
  483. */
  484. static int hw_port_is_high_speed(void)
  485. {
  486. return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
  487. hw_cread(CAP_PORTSC, PORTSC_HSP);
  488. }
  489. /**
  490. * hw_port_test_get: reads port test mode value
  491. *
  492. * This function returns port test mode value
  493. */
  494. static u8 hw_port_test_get(void)
  495. {
  496. return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  497. }
  498. /**
  499. * hw_port_test_set: writes port test mode (execute without interruption)
  500. * @mode: new value
  501. *
  502. * This function returns an error code
  503. */
  504. static int hw_port_test_set(u8 mode)
  505. {
  506. const u8 TEST_MODE_MAX = 7;
  507. if (mode > TEST_MODE_MAX)
  508. return -EINVAL;
  509. hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  510. return 0;
  511. }
  512. /**
  513. * hw_read_intr_enable: returns interrupt enable register
  514. *
  515. * This function returns register data
  516. */
  517. static u32 hw_read_intr_enable(void)
  518. {
  519. return hw_cread(CAP_USBINTR, ~0);
  520. }
  521. /**
  522. * hw_read_intr_status: returns interrupt status register
  523. *
  524. * This function returns register data
  525. */
  526. static u32 hw_read_intr_status(void)
  527. {
  528. return hw_cread(CAP_USBSTS, ~0);
  529. }
  530. /**
  531. * hw_register_read: reads all device registers (execute without interruption)
  532. * @buf: destination buffer
  533. * @size: buffer size
  534. *
  535. * This function returns number of registers read
  536. */
  537. static size_t hw_register_read(u32 *buf, size_t size)
  538. {
  539. unsigned i;
  540. if (size > hw_bank.size)
  541. size = hw_bank.size;
  542. for (i = 0; i < size; i++)
  543. buf[i] = hw_aread(i * sizeof(u32), ~0);
  544. return size;
  545. }
  546. /**
  547. * hw_register_write: writes to register
  548. * @addr: register address
  549. * @data: register value
  550. *
  551. * This function returns an error code
  552. */
  553. static int hw_register_write(u16 addr, u32 data)
  554. {
  555. /* align */
  556. addr /= sizeof(u32);
  557. if (addr >= hw_bank.size)
  558. return -EINVAL;
  559. /* align */
  560. addr *= sizeof(u32);
  561. hw_awrite(addr, ~0, data);
  562. return 0;
  563. }
  564. /**
  565. * hw_test_and_clear_complete: test & clear complete status (execute without
  566. * interruption)
  567. * @n: endpoint number
  568. *
  569. * This function returns complete status
  570. */
  571. static int hw_test_and_clear_complete(int n)
  572. {
  573. n = ep_to_bit(n);
  574. return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
  575. }
  576. /**
  577. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  578. * without interruption)
  579. *
  580. * This function returns active interrutps
  581. */
  582. static u32 hw_test_and_clear_intr_active(void)
  583. {
  584. u32 reg = hw_read_intr_status() & hw_read_intr_enable();
  585. hw_cwrite(CAP_USBSTS, ~0, reg);
  586. return reg;
  587. }
  588. /**
  589. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  590. * interruption)
  591. *
  592. * This function returns guard value
  593. */
  594. static int hw_test_and_clear_setup_guard(void)
  595. {
  596. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
  597. }
  598. /**
  599. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  600. * interruption)
  601. *
  602. * This function returns guard value
  603. */
  604. static int hw_test_and_set_setup_guard(void)
  605. {
  606. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  607. }
  608. /**
  609. * hw_usb_set_address: configures USB address (execute without interruption)
  610. * @value: new USB address
  611. *
  612. * This function returns an error code
  613. */
  614. static int hw_usb_set_address(u8 value)
  615. {
  616. /* advance */
  617. hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  618. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  619. return 0;
  620. }
  621. /**
  622. * hw_usb_reset: restart device after a bus reset (execute without
  623. * interruption)
  624. *
  625. * This function returns an error code
  626. */
  627. static int hw_usb_reset(void)
  628. {
  629. hw_usb_set_address(0);
  630. /* ESS flushes only at end?!? */
  631. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
  632. /* clear setup token semaphores */
  633. hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
  634. /* clear complete status */
  635. hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
  636. /* wait until all bits cleared */
  637. while (hw_cread(CAP_ENDPTPRIME, ~0))
  638. udelay(10); /* not RTOS friendly */
  639. /* reset all endpoints ? */
  640. /* reset internal status and wait for further instructions
  641. no need to verify the port reset status (ESS does it) */
  642. return 0;
  643. }
  644. /******************************************************************************
  645. * DBG block
  646. *****************************************************************************/
  647. /**
  648. * show_device: prints information about device capabilities and status
  649. *
  650. * Check "device.h" for details
  651. */
  652. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  653. char *buf)
  654. {
  655. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  656. struct usb_gadget *gadget = &udc->gadget;
  657. int n = 0;
  658. dbg_trace("[%s] %p\n", __func__, buf);
  659. if (attr == NULL || buf == NULL) {
  660. dev_err(dev, "[%s] EINVAL\n", __func__);
  661. return 0;
  662. }
  663. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  664. gadget->speed);
  665. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  666. gadget->is_dualspeed);
  667. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  668. gadget->is_otg);
  669. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  670. gadget->is_a_peripheral);
  671. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  672. gadget->b_hnp_enable);
  673. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  674. gadget->a_hnp_support);
  675. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  676. gadget->a_alt_hnp_support);
  677. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  678. (gadget->name ? gadget->name : ""));
  679. return n;
  680. }
  681. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  682. /**
  683. * show_driver: prints information about attached gadget (if any)
  684. *
  685. * Check "device.h" for details
  686. */
  687. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  688. char *buf)
  689. {
  690. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  691. struct usb_gadget_driver *driver = udc->driver;
  692. int n = 0;
  693. dbg_trace("[%s] %p\n", __func__, buf);
  694. if (attr == NULL || buf == NULL) {
  695. dev_err(dev, "[%s] EINVAL\n", __func__);
  696. return 0;
  697. }
  698. if (driver == NULL)
  699. return scnprintf(buf, PAGE_SIZE,
  700. "There is no gadget attached!\n");
  701. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  702. (driver->function ? driver->function : ""));
  703. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  704. driver->speed);
  705. return n;
  706. }
  707. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  708. /* Maximum event message length */
  709. #define DBG_DATA_MSG 64UL
  710. /* Maximum event messages */
  711. #define DBG_DATA_MAX 128UL
  712. /* Event buffer descriptor */
  713. static struct {
  714. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  715. unsigned idx; /* index */
  716. unsigned tty; /* print to console? */
  717. rwlock_t lck; /* lock */
  718. } dbg_data = {
  719. .idx = 0,
  720. .tty = 0,
  721. .lck = __RW_LOCK_UNLOCKED(lck)
  722. };
  723. /**
  724. * dbg_dec: decrements debug event index
  725. * @idx: buffer index
  726. */
  727. static void dbg_dec(unsigned *idx)
  728. {
  729. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  730. }
  731. /**
  732. * dbg_inc: increments debug event index
  733. * @idx: buffer index
  734. */
  735. static void dbg_inc(unsigned *idx)
  736. {
  737. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  738. }
  739. /**
  740. * dbg_print: prints the common part of the event
  741. * @addr: endpoint address
  742. * @name: event name
  743. * @status: status
  744. * @extra: extra information
  745. */
  746. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  747. {
  748. struct timeval tval;
  749. unsigned int stamp;
  750. unsigned long flags;
  751. write_lock_irqsave(&dbg_data.lck, flags);
  752. do_gettimeofday(&tval);
  753. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  754. stamp = stamp * 1000000 + tval.tv_usec;
  755. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  756. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  757. stamp, addr, name, status, extra);
  758. dbg_inc(&dbg_data.idx);
  759. write_unlock_irqrestore(&dbg_data.lck, flags);
  760. if (dbg_data.tty != 0)
  761. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  762. stamp, addr, name, status, extra);
  763. }
  764. /**
  765. * dbg_done: prints a DONE event
  766. * @addr: endpoint address
  767. * @td: transfer descriptor
  768. * @status: status
  769. */
  770. static void dbg_done(u8 addr, const u32 token, int status)
  771. {
  772. char msg[DBG_DATA_MSG];
  773. scnprintf(msg, sizeof(msg), "%d %02X",
  774. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  775. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  776. dbg_print(addr, "DONE", status, msg);
  777. }
  778. /**
  779. * dbg_event: prints a generic event
  780. * @addr: endpoint address
  781. * @name: event name
  782. * @status: status
  783. */
  784. static void dbg_event(u8 addr, const char *name, int status)
  785. {
  786. if (name != NULL)
  787. dbg_print(addr, name, status, "");
  788. }
  789. /*
  790. * dbg_queue: prints a QUEUE event
  791. * @addr: endpoint address
  792. * @req: USB request
  793. * @status: status
  794. */
  795. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  796. {
  797. char msg[DBG_DATA_MSG];
  798. if (req != NULL) {
  799. scnprintf(msg, sizeof(msg),
  800. "%d %d", !req->no_interrupt, req->length);
  801. dbg_print(addr, "QUEUE", status, msg);
  802. }
  803. }
  804. /**
  805. * dbg_setup: prints a SETUP event
  806. * @addr: endpoint address
  807. * @req: setup request
  808. */
  809. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  810. {
  811. char msg[DBG_DATA_MSG];
  812. if (req != NULL) {
  813. scnprintf(msg, sizeof(msg),
  814. "%02X %02X %04X %04X %d", req->bRequestType,
  815. req->bRequest, le16_to_cpu(req->wValue),
  816. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  817. dbg_print(addr, "SETUP", 0, msg);
  818. }
  819. }
  820. /**
  821. * show_events: displays the event buffer
  822. *
  823. * Check "device.h" for details
  824. */
  825. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  826. char *buf)
  827. {
  828. unsigned long flags;
  829. unsigned i, j, n = 0;
  830. dbg_trace("[%s] %p\n", __func__, buf);
  831. if (attr == NULL || buf == NULL) {
  832. dev_err(dev, "[%s] EINVAL\n", __func__);
  833. return 0;
  834. }
  835. read_lock_irqsave(&dbg_data.lck, flags);
  836. i = dbg_data.idx;
  837. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  838. n += strlen(dbg_data.buf[i]);
  839. if (n >= PAGE_SIZE) {
  840. n -= strlen(dbg_data.buf[i]);
  841. break;
  842. }
  843. }
  844. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  845. j += scnprintf(buf + j, PAGE_SIZE - j,
  846. "%s", dbg_data.buf[i]);
  847. read_unlock_irqrestore(&dbg_data.lck, flags);
  848. return n;
  849. }
  850. /**
  851. * store_events: configure if events are going to be also printed to console
  852. *
  853. * Check "device.h" for details
  854. */
  855. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  856. const char *buf, size_t count)
  857. {
  858. unsigned tty;
  859. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  860. if (attr == NULL || buf == NULL) {
  861. dev_err(dev, "[%s] EINVAL\n", __func__);
  862. goto done;
  863. }
  864. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  865. dev_err(dev, "<1|0>: enable|disable console log\n");
  866. goto done;
  867. }
  868. dbg_data.tty = tty;
  869. dev_info(dev, "tty = %u", dbg_data.tty);
  870. done:
  871. return count;
  872. }
  873. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  874. /**
  875. * show_inters: interrupt status, enable status and historic
  876. *
  877. * Check "device.h" for details
  878. */
  879. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  880. char *buf)
  881. {
  882. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  883. unsigned long flags;
  884. u32 intr;
  885. unsigned i, j, n = 0;
  886. dbg_trace("[%s] %p\n", __func__, buf);
  887. if (attr == NULL || buf == NULL) {
  888. dev_err(dev, "[%s] EINVAL\n", __func__);
  889. return 0;
  890. }
  891. spin_lock_irqsave(udc->lock, flags);
  892. n += scnprintf(buf + n, PAGE_SIZE - n,
  893. "status = %08x\n", hw_read_intr_status());
  894. n += scnprintf(buf + n, PAGE_SIZE - n,
  895. "enable = %08x\n", hw_read_intr_enable());
  896. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  897. isr_statistics.test);
  898. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  899. isr_statistics.ui);
  900. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  901. isr_statistics.uei);
  902. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  903. isr_statistics.pci);
  904. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  905. isr_statistics.uri);
  906. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  907. isr_statistics.sli);
  908. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  909. isr_statistics.none);
  910. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  911. isr_statistics.hndl.cnt);
  912. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  913. i &= ISR_MASK;
  914. intr = isr_statistics.hndl.buf[i];
  915. if (USBi_UI & intr)
  916. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  917. intr &= ~USBi_UI;
  918. if (USBi_UEI & intr)
  919. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  920. intr &= ~USBi_UEI;
  921. if (USBi_PCI & intr)
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  923. intr &= ~USBi_PCI;
  924. if (USBi_URI & intr)
  925. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  926. intr &= ~USBi_URI;
  927. if (USBi_SLI & intr)
  928. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  929. intr &= ~USBi_SLI;
  930. if (intr)
  931. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  932. if (isr_statistics.hndl.buf[i])
  933. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  934. }
  935. spin_unlock_irqrestore(udc->lock, flags);
  936. return n;
  937. }
  938. /**
  939. * store_inters: enable & force or disable an individual interrutps
  940. * (to be used for test purposes only)
  941. *
  942. * Check "device.h" for details
  943. */
  944. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  945. const char *buf, size_t count)
  946. {
  947. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  948. unsigned long flags;
  949. unsigned en, bit;
  950. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  951. if (attr == NULL || buf == NULL) {
  952. dev_err(dev, "[%s] EINVAL\n", __func__);
  953. goto done;
  954. }
  955. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  956. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  957. goto done;
  958. }
  959. spin_lock_irqsave(udc->lock, flags);
  960. if (en) {
  961. if (hw_intr_force(bit))
  962. dev_err(dev, "invalid bit number\n");
  963. else
  964. isr_statistics.test++;
  965. } else {
  966. if (hw_intr_clear(bit))
  967. dev_err(dev, "invalid bit number\n");
  968. }
  969. spin_unlock_irqrestore(udc->lock, flags);
  970. done:
  971. return count;
  972. }
  973. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  974. /**
  975. * show_port_test: reads port test mode
  976. *
  977. * Check "device.h" for details
  978. */
  979. static ssize_t show_port_test(struct device *dev,
  980. struct device_attribute *attr, char *buf)
  981. {
  982. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  983. unsigned long flags;
  984. unsigned mode;
  985. dbg_trace("[%s] %p\n", __func__, buf);
  986. if (attr == NULL || buf == NULL) {
  987. dev_err(dev, "[%s] EINVAL\n", __func__);
  988. return 0;
  989. }
  990. spin_lock_irqsave(udc->lock, flags);
  991. mode = hw_port_test_get();
  992. spin_unlock_irqrestore(udc->lock, flags);
  993. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  994. }
  995. /**
  996. * store_port_test: writes port test mode
  997. *
  998. * Check "device.h" for details
  999. */
  1000. static ssize_t store_port_test(struct device *dev,
  1001. struct device_attribute *attr,
  1002. const char *buf, size_t count)
  1003. {
  1004. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1005. unsigned long flags;
  1006. unsigned mode;
  1007. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1008. if (attr == NULL || buf == NULL) {
  1009. dev_err(dev, "[%s] EINVAL\n", __func__);
  1010. goto done;
  1011. }
  1012. if (sscanf(buf, "%u", &mode) != 1) {
  1013. dev_err(dev, "<mode>: set port test mode");
  1014. goto done;
  1015. }
  1016. spin_lock_irqsave(udc->lock, flags);
  1017. if (hw_port_test_set(mode))
  1018. dev_err(dev, "invalid mode\n");
  1019. spin_unlock_irqrestore(udc->lock, flags);
  1020. done:
  1021. return count;
  1022. }
  1023. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1024. show_port_test, store_port_test);
  1025. /**
  1026. * show_qheads: DMA contents of all queue heads
  1027. *
  1028. * Check "device.h" for details
  1029. */
  1030. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1031. char *buf)
  1032. {
  1033. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1034. unsigned long flags;
  1035. unsigned i, j, n = 0;
  1036. dbg_trace("[%s] %p\n", __func__, buf);
  1037. if (attr == NULL || buf == NULL) {
  1038. dev_err(dev, "[%s] EINVAL\n", __func__);
  1039. return 0;
  1040. }
  1041. spin_lock_irqsave(udc->lock, flags);
  1042. for (i = 0; i < hw_ep_max/2; i++) {
  1043. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1044. struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
  1045. n += scnprintf(buf + n, PAGE_SIZE - n,
  1046. "EP=%02i: RX=%08X TX=%08X\n",
  1047. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1048. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1049. n += scnprintf(buf + n, PAGE_SIZE - n,
  1050. " %04X: %08X %08X\n", j,
  1051. *((u32 *)mEpRx->qh.ptr + j),
  1052. *((u32 *)mEpTx->qh.ptr + j));
  1053. }
  1054. }
  1055. spin_unlock_irqrestore(udc->lock, flags);
  1056. return n;
  1057. }
  1058. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1059. /**
  1060. * show_registers: dumps all registers
  1061. *
  1062. * Check "device.h" for details
  1063. */
  1064. #define DUMP_ENTRIES 512
  1065. static ssize_t show_registers(struct device *dev,
  1066. struct device_attribute *attr, char *buf)
  1067. {
  1068. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1069. unsigned long flags;
  1070. u32 *dump;
  1071. unsigned i, k, n = 0;
  1072. dbg_trace("[%s] %p\n", __func__, buf);
  1073. if (attr == NULL || buf == NULL) {
  1074. dev_err(dev, "[%s] EINVAL\n", __func__);
  1075. return 0;
  1076. }
  1077. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1078. if (!dump) {
  1079. dev_err(dev, "%s: out of memory\n", __func__);
  1080. return 0;
  1081. }
  1082. spin_lock_irqsave(udc->lock, flags);
  1083. k = hw_register_read(dump, DUMP_ENTRIES);
  1084. spin_unlock_irqrestore(udc->lock, flags);
  1085. for (i = 0; i < k; i++) {
  1086. n += scnprintf(buf + n, PAGE_SIZE - n,
  1087. "reg[0x%04X] = 0x%08X\n",
  1088. i * (unsigned)sizeof(u32), dump[i]);
  1089. }
  1090. kfree(dump);
  1091. return n;
  1092. }
  1093. /**
  1094. * store_registers: writes value to register address
  1095. *
  1096. * Check "device.h" for details
  1097. */
  1098. static ssize_t store_registers(struct device *dev,
  1099. struct device_attribute *attr,
  1100. const char *buf, size_t count)
  1101. {
  1102. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1103. unsigned long addr, data, flags;
  1104. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1105. if (attr == NULL || buf == NULL) {
  1106. dev_err(dev, "[%s] EINVAL\n", __func__);
  1107. goto done;
  1108. }
  1109. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1110. dev_err(dev, "<addr> <data>: write data to register address");
  1111. goto done;
  1112. }
  1113. spin_lock_irqsave(udc->lock, flags);
  1114. if (hw_register_write(addr, data))
  1115. dev_err(dev, "invalid address range\n");
  1116. spin_unlock_irqrestore(udc->lock, flags);
  1117. done:
  1118. return count;
  1119. }
  1120. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1121. show_registers, store_registers);
  1122. /**
  1123. * show_requests: DMA contents of all requests currently queued (all endpts)
  1124. *
  1125. * Check "device.h" for details
  1126. */
  1127. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1128. char *buf)
  1129. {
  1130. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1131. unsigned long flags;
  1132. struct list_head *ptr = NULL;
  1133. struct ci13xxx_req *req = NULL;
  1134. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1135. dbg_trace("[%s] %p\n", __func__, buf);
  1136. if (attr == NULL || buf == NULL) {
  1137. dev_err(dev, "[%s] EINVAL\n", __func__);
  1138. return 0;
  1139. }
  1140. spin_lock_irqsave(udc->lock, flags);
  1141. for (i = 0; i < hw_ep_max; i++)
  1142. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1143. {
  1144. req = list_entry(ptr, struct ci13xxx_req, queue);
  1145. n += scnprintf(buf + n, PAGE_SIZE - n,
  1146. "EP=%02i: TD=%08X %s\n",
  1147. i % hw_ep_max/2, (u32)req->dma,
  1148. ((i < hw_ep_max/2) ? "RX" : "TX"));
  1149. for (j = 0; j < qSize; j++)
  1150. n += scnprintf(buf + n, PAGE_SIZE - n,
  1151. " %04X: %08X\n", j,
  1152. *((u32 *)req->ptr + j));
  1153. }
  1154. spin_unlock_irqrestore(udc->lock, flags);
  1155. return n;
  1156. }
  1157. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1158. /**
  1159. * dbg_create_files: initializes the attribute interface
  1160. * @dev: device
  1161. *
  1162. * This function returns an error code
  1163. */
  1164. __maybe_unused static int dbg_create_files(struct device *dev)
  1165. {
  1166. int retval = 0;
  1167. if (dev == NULL)
  1168. return -EINVAL;
  1169. retval = device_create_file(dev, &dev_attr_device);
  1170. if (retval)
  1171. goto done;
  1172. retval = device_create_file(dev, &dev_attr_driver);
  1173. if (retval)
  1174. goto rm_device;
  1175. retval = device_create_file(dev, &dev_attr_events);
  1176. if (retval)
  1177. goto rm_driver;
  1178. retval = device_create_file(dev, &dev_attr_inters);
  1179. if (retval)
  1180. goto rm_events;
  1181. retval = device_create_file(dev, &dev_attr_port_test);
  1182. if (retval)
  1183. goto rm_inters;
  1184. retval = device_create_file(dev, &dev_attr_qheads);
  1185. if (retval)
  1186. goto rm_port_test;
  1187. retval = device_create_file(dev, &dev_attr_registers);
  1188. if (retval)
  1189. goto rm_qheads;
  1190. retval = device_create_file(dev, &dev_attr_requests);
  1191. if (retval)
  1192. goto rm_registers;
  1193. return 0;
  1194. rm_registers:
  1195. device_remove_file(dev, &dev_attr_registers);
  1196. rm_qheads:
  1197. device_remove_file(dev, &dev_attr_qheads);
  1198. rm_port_test:
  1199. device_remove_file(dev, &dev_attr_port_test);
  1200. rm_inters:
  1201. device_remove_file(dev, &dev_attr_inters);
  1202. rm_events:
  1203. device_remove_file(dev, &dev_attr_events);
  1204. rm_driver:
  1205. device_remove_file(dev, &dev_attr_driver);
  1206. rm_device:
  1207. device_remove_file(dev, &dev_attr_device);
  1208. done:
  1209. return retval;
  1210. }
  1211. /**
  1212. * dbg_remove_files: destroys the attribute interface
  1213. * @dev: device
  1214. *
  1215. * This function returns an error code
  1216. */
  1217. __maybe_unused static int dbg_remove_files(struct device *dev)
  1218. {
  1219. if (dev == NULL)
  1220. return -EINVAL;
  1221. device_remove_file(dev, &dev_attr_requests);
  1222. device_remove_file(dev, &dev_attr_registers);
  1223. device_remove_file(dev, &dev_attr_qheads);
  1224. device_remove_file(dev, &dev_attr_port_test);
  1225. device_remove_file(dev, &dev_attr_inters);
  1226. device_remove_file(dev, &dev_attr_events);
  1227. device_remove_file(dev, &dev_attr_driver);
  1228. device_remove_file(dev, &dev_attr_device);
  1229. return 0;
  1230. }
  1231. /******************************************************************************
  1232. * UTIL block
  1233. *****************************************************************************/
  1234. /**
  1235. * _usb_addr: calculates endpoint address from direction & number
  1236. * @ep: endpoint
  1237. */
  1238. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1239. {
  1240. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1241. }
  1242. /**
  1243. * _hardware_queue: configures a request at hardware level
  1244. * @gadget: gadget
  1245. * @mEp: endpoint
  1246. *
  1247. * This function returns an error code
  1248. */
  1249. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1250. {
  1251. unsigned i;
  1252. int ret = 0;
  1253. unsigned length = mReq->req.length;
  1254. trace("%p, %p", mEp, mReq);
  1255. /* don't queue twice */
  1256. if (mReq->req.status == -EALREADY)
  1257. return -EALREADY;
  1258. mReq->req.status = -EALREADY;
  1259. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1260. mReq->req.dma = \
  1261. dma_map_single(mEp->device, mReq->req.buf,
  1262. length, mEp->dir ? DMA_TO_DEVICE :
  1263. DMA_FROM_DEVICE);
  1264. if (mReq->req.dma == 0)
  1265. return -ENOMEM;
  1266. mReq->map = 1;
  1267. }
  1268. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1269. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1270. &mReq->zdma);
  1271. if (mReq->zptr == NULL) {
  1272. if (mReq->map) {
  1273. dma_unmap_single(mEp->device, mReq->req.dma,
  1274. length, mEp->dir ? DMA_TO_DEVICE :
  1275. DMA_FROM_DEVICE);
  1276. mReq->req.dma = DMA_ADDR_INVALID;
  1277. mReq->map = 0;
  1278. }
  1279. return -ENOMEM;
  1280. }
  1281. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1282. mReq->zptr->next = TD_TERMINATE;
  1283. mReq->zptr->token = TD_STATUS_ACTIVE;
  1284. if (!mReq->req.no_interrupt)
  1285. mReq->zptr->token |= TD_IOC;
  1286. }
  1287. /*
  1288. * TD configuration
  1289. * TODO - handle requests which spawns into several TDs
  1290. */
  1291. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1292. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1293. mReq->ptr->token &= TD_TOTAL_BYTES;
  1294. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1295. if (mReq->zptr) {
  1296. mReq->ptr->next = mReq->zdma;
  1297. } else {
  1298. mReq->ptr->next = TD_TERMINATE;
  1299. if (!mReq->req.no_interrupt)
  1300. mReq->ptr->token |= TD_IOC;
  1301. }
  1302. mReq->ptr->page[0] = mReq->req.dma;
  1303. for (i = 1; i < 5; i++)
  1304. mReq->ptr->page[i] =
  1305. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1306. if (!list_empty(&mEp->qh.queue)) {
  1307. struct ci13xxx_req *mReqPrev;
  1308. int n = hw_ep_bit(mEp->num, mEp->dir);
  1309. int tmp_stat;
  1310. mReqPrev = list_entry(mEp->qh.queue.prev,
  1311. struct ci13xxx_req, queue);
  1312. if (mReqPrev->zptr)
  1313. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1314. else
  1315. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1316. wmb();
  1317. if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  1318. goto done;
  1319. do {
  1320. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1321. tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
  1322. } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
  1323. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
  1324. if (tmp_stat)
  1325. goto done;
  1326. }
  1327. /* QH configuration */
  1328. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1329. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1330. mEp->qh.ptr->cap |= QH_ZLT;
  1331. wmb(); /* synchronize before ep prime */
  1332. ret = hw_ep_prime(mEp->num, mEp->dir,
  1333. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1334. done:
  1335. return ret;
  1336. }
  1337. /**
  1338. * _hardware_dequeue: handles a request at hardware level
  1339. * @gadget: gadget
  1340. * @mEp: endpoint
  1341. *
  1342. * This function returns an error code
  1343. */
  1344. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1345. {
  1346. trace("%p, %p", mEp, mReq);
  1347. if (mReq->req.status != -EALREADY)
  1348. return -EINVAL;
  1349. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1350. return -EBUSY;
  1351. if (mReq->zptr) {
  1352. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1353. return -EBUSY;
  1354. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1355. mReq->zptr = NULL;
  1356. }
  1357. mReq->req.status = 0;
  1358. if (mReq->map) {
  1359. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1360. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1361. mReq->req.dma = DMA_ADDR_INVALID;
  1362. mReq->map = 0;
  1363. }
  1364. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1365. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1366. mReq->req.status = -1;
  1367. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1368. mReq->req.status = -1;
  1369. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1370. mReq->req.status = -1;
  1371. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1372. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1373. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1374. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1375. return mReq->req.actual;
  1376. }
  1377. /**
  1378. * _ep_nuke: dequeues all endpoint requests
  1379. * @mEp: endpoint
  1380. *
  1381. * This function returns an error code
  1382. * Caller must hold lock
  1383. */
  1384. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1385. __releases(mEp->lock)
  1386. __acquires(mEp->lock)
  1387. {
  1388. trace("%p", mEp);
  1389. if (mEp == NULL)
  1390. return -EINVAL;
  1391. hw_ep_flush(mEp->num, mEp->dir);
  1392. while (!list_empty(&mEp->qh.queue)) {
  1393. /* pop oldest request */
  1394. struct ci13xxx_req *mReq = \
  1395. list_entry(mEp->qh.queue.next,
  1396. struct ci13xxx_req, queue);
  1397. list_del_init(&mReq->queue);
  1398. mReq->req.status = -ESHUTDOWN;
  1399. if (mReq->req.complete != NULL) {
  1400. spin_unlock(mEp->lock);
  1401. mReq->req.complete(&mEp->ep, &mReq->req);
  1402. spin_lock(mEp->lock);
  1403. }
  1404. }
  1405. return 0;
  1406. }
  1407. /**
  1408. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1409. * @gadget: gadget
  1410. *
  1411. * This function returns an error code
  1412. */
  1413. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1414. {
  1415. struct usb_ep *ep;
  1416. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1417. unsigned long flags;
  1418. trace("%p", gadget);
  1419. if (gadget == NULL)
  1420. return -EINVAL;
  1421. spin_lock_irqsave(udc->lock, flags);
  1422. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1423. udc->remote_wakeup = 0;
  1424. udc->suspended = 0;
  1425. spin_unlock_irqrestore(udc->lock, flags);
  1426. /* flush all endpoints */
  1427. gadget_for_each_ep(ep, gadget) {
  1428. usb_ep_fifo_flush(ep);
  1429. }
  1430. usb_ep_fifo_flush(&udc->ep0out.ep);
  1431. usb_ep_fifo_flush(&udc->ep0in.ep);
  1432. udc->driver->disconnect(gadget);
  1433. /* make sure to disable all endpoints */
  1434. gadget_for_each_ep(ep, gadget) {
  1435. usb_ep_disable(ep);
  1436. }
  1437. if (udc->status != NULL) {
  1438. usb_ep_free_request(&udc->ep0in.ep, udc->status);
  1439. udc->status = NULL;
  1440. }
  1441. return 0;
  1442. }
  1443. /******************************************************************************
  1444. * ISR block
  1445. *****************************************************************************/
  1446. /**
  1447. * isr_reset_handler: USB reset interrupt handler
  1448. * @udc: UDC device
  1449. *
  1450. * This function resets USB engine after a bus reset occurred
  1451. */
  1452. static void isr_reset_handler(struct ci13xxx *udc)
  1453. __releases(udc->lock)
  1454. __acquires(udc->lock)
  1455. {
  1456. int retval;
  1457. trace("%p", udc);
  1458. if (udc == NULL) {
  1459. err("EINVAL");
  1460. return;
  1461. }
  1462. dbg_event(0xFF, "BUS RST", 0);
  1463. spin_unlock(udc->lock);
  1464. retval = _gadget_stop_activity(&udc->gadget);
  1465. if (retval)
  1466. goto done;
  1467. retval = hw_usb_reset();
  1468. if (retval)
  1469. goto done;
  1470. udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
  1471. if (udc->status == NULL)
  1472. retval = -ENOMEM;
  1473. spin_lock(udc->lock);
  1474. done:
  1475. if (retval)
  1476. err("error: %i", retval);
  1477. }
  1478. /**
  1479. * isr_get_status_complete: get_status request complete function
  1480. * @ep: endpoint
  1481. * @req: request handled
  1482. *
  1483. * Caller must release lock
  1484. */
  1485. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1486. {
  1487. trace("%p, %p", ep, req);
  1488. if (ep == NULL || req == NULL) {
  1489. err("EINVAL");
  1490. return;
  1491. }
  1492. kfree(req->buf);
  1493. usb_ep_free_request(ep, req);
  1494. }
  1495. /**
  1496. * isr_get_status_response: get_status request response
  1497. * @udc: udc struct
  1498. * @setup: setup request packet
  1499. *
  1500. * This function returns an error code
  1501. */
  1502. static int isr_get_status_response(struct ci13xxx *udc,
  1503. struct usb_ctrlrequest *setup)
  1504. __releases(mEp->lock)
  1505. __acquires(mEp->lock)
  1506. {
  1507. struct ci13xxx_ep *mEp = &udc->ep0in;
  1508. struct usb_request *req = NULL;
  1509. gfp_t gfp_flags = GFP_ATOMIC;
  1510. int dir, num, retval;
  1511. trace("%p, %p", mEp, setup);
  1512. if (mEp == NULL || setup == NULL)
  1513. return -EINVAL;
  1514. spin_unlock(mEp->lock);
  1515. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1516. spin_lock(mEp->lock);
  1517. if (req == NULL)
  1518. return -ENOMEM;
  1519. req->complete = isr_get_status_complete;
  1520. req->length = 2;
  1521. req->buf = kzalloc(req->length, gfp_flags);
  1522. if (req->buf == NULL) {
  1523. retval = -ENOMEM;
  1524. goto err_free_req;
  1525. }
  1526. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1527. /* Assume that device is bus powered for now. */
  1528. *((u16 *)req->buf) = _udc->remote_wakeup << 1;
  1529. retval = 0;
  1530. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1531. == USB_RECIP_ENDPOINT) {
  1532. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1533. TX : RX;
  1534. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1535. *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
  1536. }
  1537. /* else do nothing; reserved for future use */
  1538. spin_unlock(mEp->lock);
  1539. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1540. spin_lock(mEp->lock);
  1541. if (retval)
  1542. goto err_free_buf;
  1543. return 0;
  1544. err_free_buf:
  1545. kfree(req->buf);
  1546. err_free_req:
  1547. spin_unlock(mEp->lock);
  1548. usb_ep_free_request(&mEp->ep, req);
  1549. spin_lock(mEp->lock);
  1550. return retval;
  1551. }
  1552. /**
  1553. * isr_setup_status_complete: setup_status request complete function
  1554. * @ep: endpoint
  1555. * @req: request handled
  1556. *
  1557. * Caller must release lock. Put the port in test mode if test mode
  1558. * feature is selected.
  1559. */
  1560. static void
  1561. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1562. {
  1563. struct ci13xxx *udc = req->context;
  1564. unsigned long flags;
  1565. trace("%p, %p", ep, req);
  1566. spin_lock_irqsave(udc->lock, flags);
  1567. if (udc->test_mode)
  1568. hw_port_test_set(udc->test_mode);
  1569. spin_unlock_irqrestore(udc->lock, flags);
  1570. }
  1571. /**
  1572. * isr_setup_status_phase: queues the status phase of a setup transation
  1573. * @udc: udc struct
  1574. *
  1575. * This function returns an error code
  1576. */
  1577. static int isr_setup_status_phase(struct ci13xxx *udc)
  1578. __releases(mEp->lock)
  1579. __acquires(mEp->lock)
  1580. {
  1581. int retval;
  1582. struct ci13xxx_ep *mEp;
  1583. trace("%p", udc);
  1584. mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
  1585. udc->status->context = udc;
  1586. udc->status->complete = isr_setup_status_complete;
  1587. spin_unlock(mEp->lock);
  1588. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1589. spin_lock(mEp->lock);
  1590. return retval;
  1591. }
  1592. /**
  1593. * isr_tr_complete_low: transaction complete low level handler
  1594. * @mEp: endpoint
  1595. *
  1596. * This function returns an error code
  1597. * Caller must hold lock
  1598. */
  1599. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1600. __releases(mEp->lock)
  1601. __acquires(mEp->lock)
  1602. {
  1603. struct ci13xxx_req *mReq, *mReqTemp;
  1604. struct ci13xxx_ep *mEpTemp = mEp;
  1605. int uninitialized_var(retval);
  1606. trace("%p", mEp);
  1607. if (list_empty(&mEp->qh.queue))
  1608. return -EINVAL;
  1609. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1610. queue) {
  1611. retval = _hardware_dequeue(mEp, mReq);
  1612. if (retval < 0)
  1613. break;
  1614. list_del_init(&mReq->queue);
  1615. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1616. if (mReq->req.complete != NULL) {
  1617. spin_unlock(mEp->lock);
  1618. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1619. mReq->req.length)
  1620. mEpTemp = &_udc->ep0in;
  1621. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1622. spin_lock(mEp->lock);
  1623. }
  1624. }
  1625. if (retval == -EBUSY)
  1626. retval = 0;
  1627. if (retval < 0)
  1628. dbg_event(_usb_addr(mEp), "DONE", retval);
  1629. return retval;
  1630. }
  1631. /**
  1632. * isr_tr_complete_handler: transaction complete interrupt handler
  1633. * @udc: UDC descriptor
  1634. *
  1635. * This function handles traffic events
  1636. */
  1637. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1638. __releases(udc->lock)
  1639. __acquires(udc->lock)
  1640. {
  1641. unsigned i;
  1642. u8 tmode = 0;
  1643. trace("%p", udc);
  1644. if (udc == NULL) {
  1645. err("EINVAL");
  1646. return;
  1647. }
  1648. for (i = 0; i < hw_ep_max; i++) {
  1649. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1650. int type, num, dir, err = -EINVAL;
  1651. struct usb_ctrlrequest req;
  1652. if (mEp->desc == NULL)
  1653. continue; /* not configured */
  1654. if (hw_test_and_clear_complete(i)) {
  1655. err = isr_tr_complete_low(mEp);
  1656. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1657. if (err > 0) /* needs status phase */
  1658. err = isr_setup_status_phase(udc);
  1659. if (err < 0) {
  1660. dbg_event(_usb_addr(mEp),
  1661. "ERROR", err);
  1662. spin_unlock(udc->lock);
  1663. if (usb_ep_set_halt(&mEp->ep))
  1664. err("error: ep_set_halt");
  1665. spin_lock(udc->lock);
  1666. }
  1667. }
  1668. }
  1669. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1670. !hw_test_and_clear_setup_status(i))
  1671. continue;
  1672. if (i != 0) {
  1673. warn("ctrl traffic received at endpoint");
  1674. continue;
  1675. }
  1676. /*
  1677. * Flush data and handshake transactions of previous
  1678. * setup packet.
  1679. */
  1680. _ep_nuke(&udc->ep0out);
  1681. _ep_nuke(&udc->ep0in);
  1682. /* read_setup_packet */
  1683. do {
  1684. hw_test_and_set_setup_guard();
  1685. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1686. } while (!hw_test_and_clear_setup_guard());
  1687. type = req.bRequestType;
  1688. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1689. dbg_setup(_usb_addr(mEp), &req);
  1690. switch (req.bRequest) {
  1691. case USB_REQ_CLEAR_FEATURE:
  1692. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1693. le16_to_cpu(req.wValue) ==
  1694. USB_ENDPOINT_HALT) {
  1695. if (req.wLength != 0)
  1696. break;
  1697. num = le16_to_cpu(req.wIndex);
  1698. dir = num & USB_ENDPOINT_DIR_MASK;
  1699. num &= USB_ENDPOINT_NUMBER_MASK;
  1700. if (dir) /* TX */
  1701. num += hw_ep_max/2;
  1702. if (!udc->ci13xxx_ep[num].wedge) {
  1703. spin_unlock(udc->lock);
  1704. err = usb_ep_clear_halt(
  1705. &udc->ci13xxx_ep[num].ep);
  1706. spin_lock(udc->lock);
  1707. if (err)
  1708. break;
  1709. }
  1710. err = isr_setup_status_phase(udc);
  1711. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1712. le16_to_cpu(req.wValue) ==
  1713. USB_DEVICE_REMOTE_WAKEUP) {
  1714. if (req.wLength != 0)
  1715. break;
  1716. udc->remote_wakeup = 0;
  1717. err = isr_setup_status_phase(udc);
  1718. } else {
  1719. goto delegate;
  1720. }
  1721. break;
  1722. case USB_REQ_GET_STATUS:
  1723. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1724. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1725. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1726. goto delegate;
  1727. if (le16_to_cpu(req.wLength) != 2 ||
  1728. le16_to_cpu(req.wValue) != 0)
  1729. break;
  1730. err = isr_get_status_response(udc, &req);
  1731. break;
  1732. case USB_REQ_SET_ADDRESS:
  1733. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1734. goto delegate;
  1735. if (le16_to_cpu(req.wLength) != 0 ||
  1736. le16_to_cpu(req.wIndex) != 0)
  1737. break;
  1738. err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
  1739. if (err)
  1740. break;
  1741. err = isr_setup_status_phase(udc);
  1742. break;
  1743. case USB_REQ_SET_FEATURE:
  1744. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1745. le16_to_cpu(req.wValue) ==
  1746. USB_ENDPOINT_HALT) {
  1747. if (req.wLength != 0)
  1748. break;
  1749. num = le16_to_cpu(req.wIndex);
  1750. dir = num & USB_ENDPOINT_DIR_MASK;
  1751. num &= USB_ENDPOINT_NUMBER_MASK;
  1752. if (dir) /* TX */
  1753. num += hw_ep_max/2;
  1754. spin_unlock(udc->lock);
  1755. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1756. spin_lock(udc->lock);
  1757. if (!err)
  1758. isr_setup_status_phase(udc);
  1759. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1760. if (req.wLength != 0)
  1761. break;
  1762. switch (le16_to_cpu(req.wValue)) {
  1763. case USB_DEVICE_REMOTE_WAKEUP:
  1764. udc->remote_wakeup = 1;
  1765. err = isr_setup_status_phase(udc);
  1766. break;
  1767. case USB_DEVICE_TEST_MODE:
  1768. tmode = le16_to_cpu(req.wIndex) >> 8;
  1769. switch (tmode) {
  1770. case TEST_J:
  1771. case TEST_K:
  1772. case TEST_SE0_NAK:
  1773. case TEST_PACKET:
  1774. case TEST_FORCE_EN:
  1775. udc->test_mode = tmode;
  1776. err = isr_setup_status_phase(
  1777. udc);
  1778. break;
  1779. default:
  1780. break;
  1781. }
  1782. default:
  1783. goto delegate;
  1784. }
  1785. } else {
  1786. goto delegate;
  1787. }
  1788. break;
  1789. default:
  1790. delegate:
  1791. if (req.wLength == 0) /* no data phase */
  1792. udc->ep0_dir = TX;
  1793. spin_unlock(udc->lock);
  1794. err = udc->driver->setup(&udc->gadget, &req);
  1795. spin_lock(udc->lock);
  1796. break;
  1797. }
  1798. if (err < 0) {
  1799. dbg_event(_usb_addr(mEp), "ERROR", err);
  1800. spin_unlock(udc->lock);
  1801. if (usb_ep_set_halt(&mEp->ep))
  1802. err("error: ep_set_halt");
  1803. spin_lock(udc->lock);
  1804. }
  1805. }
  1806. }
  1807. /******************************************************************************
  1808. * ENDPT block
  1809. *****************************************************************************/
  1810. /**
  1811. * ep_enable: configure endpoint, making it usable
  1812. *
  1813. * Check usb_ep_enable() at "usb_gadget.h" for details
  1814. */
  1815. static int ep_enable(struct usb_ep *ep,
  1816. const struct usb_endpoint_descriptor *desc)
  1817. {
  1818. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1819. int retval = 0;
  1820. unsigned long flags;
  1821. trace("%p, %p", ep, desc);
  1822. if (ep == NULL || desc == NULL)
  1823. return -EINVAL;
  1824. spin_lock_irqsave(mEp->lock, flags);
  1825. /* only internal SW should enable ctrl endpts */
  1826. mEp->desc = desc;
  1827. if (!list_empty(&mEp->qh.queue))
  1828. warn("enabling a non-empty endpoint!");
  1829. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1830. mEp->num = usb_endpoint_num(desc);
  1831. mEp->type = usb_endpoint_type(desc);
  1832. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1833. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1834. mEp->qh.ptr->cap = 0;
  1835. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1836. mEp->qh.ptr->cap |= QH_IOS;
  1837. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1838. mEp->qh.ptr->cap &= ~QH_MULT;
  1839. else
  1840. mEp->qh.ptr->cap &= ~QH_ZLT;
  1841. mEp->qh.ptr->cap |=
  1842. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1843. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1844. /*
  1845. * Enable endpoints in the HW other than ep0 as ep0
  1846. * is always enabled
  1847. */
  1848. if (mEp->num)
  1849. retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
  1850. spin_unlock_irqrestore(mEp->lock, flags);
  1851. return retval;
  1852. }
  1853. /**
  1854. * ep_disable: endpoint is no longer usable
  1855. *
  1856. * Check usb_ep_disable() at "usb_gadget.h" for details
  1857. */
  1858. static int ep_disable(struct usb_ep *ep)
  1859. {
  1860. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1861. int direction, retval = 0;
  1862. unsigned long flags;
  1863. trace("%p", ep);
  1864. if (ep == NULL)
  1865. return -EINVAL;
  1866. else if (mEp->desc == NULL)
  1867. return -EBUSY;
  1868. spin_lock_irqsave(mEp->lock, flags);
  1869. /* only internal SW should disable ctrl endpts */
  1870. direction = mEp->dir;
  1871. do {
  1872. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1873. retval |= _ep_nuke(mEp);
  1874. retval |= hw_ep_disable(mEp->num, mEp->dir);
  1875. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1876. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1877. } while (mEp->dir != direction);
  1878. mEp->desc = NULL;
  1879. spin_unlock_irqrestore(mEp->lock, flags);
  1880. return retval;
  1881. }
  1882. /**
  1883. * ep_alloc_request: allocate a request object to use with this endpoint
  1884. *
  1885. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1886. */
  1887. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1888. {
  1889. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1890. struct ci13xxx_req *mReq = NULL;
  1891. trace("%p, %i", ep, gfp_flags);
  1892. if (ep == NULL) {
  1893. err("EINVAL");
  1894. return NULL;
  1895. }
  1896. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1897. if (mReq != NULL) {
  1898. INIT_LIST_HEAD(&mReq->queue);
  1899. mReq->req.dma = DMA_ADDR_INVALID;
  1900. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1901. &mReq->dma);
  1902. if (mReq->ptr == NULL) {
  1903. kfree(mReq);
  1904. mReq = NULL;
  1905. }
  1906. }
  1907. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1908. return (mReq == NULL) ? NULL : &mReq->req;
  1909. }
  1910. /**
  1911. * ep_free_request: frees a request object
  1912. *
  1913. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1914. */
  1915. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1916. {
  1917. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1918. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1919. unsigned long flags;
  1920. trace("%p, %p", ep, req);
  1921. if (ep == NULL || req == NULL) {
  1922. err("EINVAL");
  1923. return;
  1924. } else if (!list_empty(&mReq->queue)) {
  1925. err("EBUSY");
  1926. return;
  1927. }
  1928. spin_lock_irqsave(mEp->lock, flags);
  1929. if (mReq->ptr)
  1930. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1931. kfree(mReq);
  1932. dbg_event(_usb_addr(mEp), "FREE", 0);
  1933. spin_unlock_irqrestore(mEp->lock, flags);
  1934. }
  1935. /**
  1936. * ep_queue: queues (submits) an I/O request to an endpoint
  1937. *
  1938. * Check usb_ep_queue()* at usb_gadget.h" for details
  1939. */
  1940. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1941. gfp_t __maybe_unused gfp_flags)
  1942. {
  1943. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1944. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1945. int retval = 0;
  1946. unsigned long flags;
  1947. trace("%p, %p, %X", ep, req, gfp_flags);
  1948. if (ep == NULL || req == NULL || mEp->desc == NULL)
  1949. return -EINVAL;
  1950. spin_lock_irqsave(mEp->lock, flags);
  1951. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1952. if (req->length)
  1953. mEp = (_udc->ep0_dir == RX) ?
  1954. &_udc->ep0out : &_udc->ep0in;
  1955. if (!list_empty(&mEp->qh.queue)) {
  1956. _ep_nuke(mEp);
  1957. retval = -EOVERFLOW;
  1958. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1959. }
  1960. }
  1961. /* first nuke then test link, e.g. previous status has not sent */
  1962. if (!list_empty(&mReq->queue)) {
  1963. retval = -EBUSY;
  1964. err("request already in queue");
  1965. goto done;
  1966. }
  1967. if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
  1968. req->length = (4 * CI13XXX_PAGE_SIZE);
  1969. retval = -EMSGSIZE;
  1970. warn("request length truncated");
  1971. }
  1972. dbg_queue(_usb_addr(mEp), req, retval);
  1973. /* push request */
  1974. mReq->req.status = -EINPROGRESS;
  1975. mReq->req.actual = 0;
  1976. retval = _hardware_enqueue(mEp, mReq);
  1977. if (retval == -EALREADY) {
  1978. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1979. retval = 0;
  1980. }
  1981. if (!retval)
  1982. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1983. done:
  1984. spin_unlock_irqrestore(mEp->lock, flags);
  1985. return retval;
  1986. }
  1987. /**
  1988. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1989. *
  1990. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1991. */
  1992. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1993. {
  1994. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1995. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1996. unsigned long flags;
  1997. trace("%p, %p", ep, req);
  1998. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1999. mEp->desc == NULL || list_empty(&mReq->queue) ||
  2000. list_empty(&mEp->qh.queue))
  2001. return -EINVAL;
  2002. spin_lock_irqsave(mEp->lock, flags);
  2003. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  2004. hw_ep_flush(mEp->num, mEp->dir);
  2005. /* pop request */
  2006. list_del_init(&mReq->queue);
  2007. if (mReq->map) {
  2008. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2009. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2010. mReq->req.dma = DMA_ADDR_INVALID;
  2011. mReq->map = 0;
  2012. }
  2013. req->status = -ECONNRESET;
  2014. if (mReq->req.complete != NULL) {
  2015. spin_unlock(mEp->lock);
  2016. mReq->req.complete(&mEp->ep, &mReq->req);
  2017. spin_lock(mEp->lock);
  2018. }
  2019. spin_unlock_irqrestore(mEp->lock, flags);
  2020. return 0;
  2021. }
  2022. /**
  2023. * ep_set_halt: sets the endpoint halt feature
  2024. *
  2025. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2026. */
  2027. static int ep_set_halt(struct usb_ep *ep, int value)
  2028. {
  2029. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2030. int direction, retval = 0;
  2031. unsigned long flags;
  2032. trace("%p, %i", ep, value);
  2033. if (ep == NULL || mEp->desc == NULL)
  2034. return -EINVAL;
  2035. spin_lock_irqsave(mEp->lock, flags);
  2036. #ifndef STALL_IN
  2037. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2038. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2039. !list_empty(&mEp->qh.queue)) {
  2040. spin_unlock_irqrestore(mEp->lock, flags);
  2041. return -EAGAIN;
  2042. }
  2043. #endif
  2044. direction = mEp->dir;
  2045. do {
  2046. dbg_event(_usb_addr(mEp), "HALT", value);
  2047. retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
  2048. if (!value)
  2049. mEp->wedge = 0;
  2050. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2051. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2052. } while (mEp->dir != direction);
  2053. spin_unlock_irqrestore(mEp->lock, flags);
  2054. return retval;
  2055. }
  2056. /**
  2057. * ep_set_wedge: sets the halt feature and ignores clear requests
  2058. *
  2059. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2060. */
  2061. static int ep_set_wedge(struct usb_ep *ep)
  2062. {
  2063. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2064. unsigned long flags;
  2065. trace("%p", ep);
  2066. if (ep == NULL || mEp->desc == NULL)
  2067. return -EINVAL;
  2068. spin_lock_irqsave(mEp->lock, flags);
  2069. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2070. mEp->wedge = 1;
  2071. spin_unlock_irqrestore(mEp->lock, flags);
  2072. return usb_ep_set_halt(ep);
  2073. }
  2074. /**
  2075. * ep_fifo_flush: flushes contents of a fifo
  2076. *
  2077. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2078. */
  2079. static void ep_fifo_flush(struct usb_ep *ep)
  2080. {
  2081. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2082. unsigned long flags;
  2083. trace("%p", ep);
  2084. if (ep == NULL) {
  2085. err("%02X: -EINVAL", _usb_addr(mEp));
  2086. return;
  2087. }
  2088. spin_lock_irqsave(mEp->lock, flags);
  2089. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2090. hw_ep_flush(mEp->num, mEp->dir);
  2091. spin_unlock_irqrestore(mEp->lock, flags);
  2092. }
  2093. /**
  2094. * Endpoint-specific part of the API to the USB controller hardware
  2095. * Check "usb_gadget.h" for details
  2096. */
  2097. static const struct usb_ep_ops usb_ep_ops = {
  2098. .enable = ep_enable,
  2099. .disable = ep_disable,
  2100. .alloc_request = ep_alloc_request,
  2101. .free_request = ep_free_request,
  2102. .queue = ep_queue,
  2103. .dequeue = ep_dequeue,
  2104. .set_halt = ep_set_halt,
  2105. .set_wedge = ep_set_wedge,
  2106. .fifo_flush = ep_fifo_flush,
  2107. };
  2108. /******************************************************************************
  2109. * GADGET block
  2110. *****************************************************************************/
  2111. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2112. {
  2113. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2114. unsigned long flags;
  2115. int gadget_ready = 0;
  2116. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2117. return -EOPNOTSUPP;
  2118. spin_lock_irqsave(udc->lock, flags);
  2119. udc->vbus_active = is_active;
  2120. if (udc->driver)
  2121. gadget_ready = 1;
  2122. spin_unlock_irqrestore(udc->lock, flags);
  2123. if (gadget_ready) {
  2124. if (is_active) {
  2125. pm_runtime_get_sync(&_gadget->dev);
  2126. hw_device_reset(udc);
  2127. hw_device_state(udc->ep0out.qh.dma);
  2128. } else {
  2129. hw_device_state(0);
  2130. if (udc->udc_driver->notify_event)
  2131. udc->udc_driver->notify_event(udc,
  2132. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2133. _gadget_stop_activity(&udc->gadget);
  2134. pm_runtime_put_sync(&_gadget->dev);
  2135. }
  2136. }
  2137. return 0;
  2138. }
  2139. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2140. {
  2141. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2142. unsigned long flags;
  2143. int ret = 0;
  2144. trace();
  2145. spin_lock_irqsave(udc->lock, flags);
  2146. if (!udc->remote_wakeup) {
  2147. ret = -EOPNOTSUPP;
  2148. trace("remote wakeup feature is not enabled\n");
  2149. goto out;
  2150. }
  2151. if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
  2152. ret = -EINVAL;
  2153. trace("port is not suspended\n");
  2154. goto out;
  2155. }
  2156. hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2157. out:
  2158. spin_unlock_irqrestore(udc->lock, flags);
  2159. return ret;
  2160. }
  2161. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2162. {
  2163. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2164. if (udc->transceiver)
  2165. return otg_set_power(udc->transceiver, mA);
  2166. return -ENOTSUPP;
  2167. }
  2168. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2169. int (*bind)(struct usb_gadget *));
  2170. static int ci13xxx_stop(struct usb_gadget_driver *driver);
  2171. /**
  2172. * Device operations part of the API to the USB controller hardware,
  2173. * which don't involve endpoints (or i/o)
  2174. * Check "usb_gadget.h" for details
  2175. */
  2176. static const struct usb_gadget_ops usb_gadget_ops = {
  2177. .vbus_session = ci13xxx_vbus_session,
  2178. .wakeup = ci13xxx_wakeup,
  2179. .vbus_draw = ci13xxx_vbus_draw,
  2180. .start = ci13xxx_start,
  2181. .stop = ci13xxx_stop,
  2182. };
  2183. /**
  2184. * ci13xxx_start: register a gadget driver
  2185. * @driver: the driver being registered
  2186. * @bind: the driver's bind callback
  2187. *
  2188. * Check ci13xxx_start() at <linux/usb/gadget.h> for details.
  2189. * Interrupts are enabled here.
  2190. */
  2191. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2192. int (*bind)(struct usb_gadget *))
  2193. {
  2194. struct ci13xxx *udc = _udc;
  2195. unsigned long flags;
  2196. int i, j;
  2197. int retval = -ENOMEM;
  2198. trace("%p", driver);
  2199. if (driver == NULL ||
  2200. bind == NULL ||
  2201. driver->setup == NULL ||
  2202. driver->disconnect == NULL)
  2203. return -EINVAL;
  2204. else if (udc == NULL)
  2205. return -ENODEV;
  2206. else if (udc->driver != NULL)
  2207. return -EBUSY;
  2208. /* alloc resources */
  2209. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2210. sizeof(struct ci13xxx_qh),
  2211. 64, CI13XXX_PAGE_SIZE);
  2212. if (udc->qh_pool == NULL)
  2213. return -ENOMEM;
  2214. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2215. sizeof(struct ci13xxx_td),
  2216. 64, CI13XXX_PAGE_SIZE);
  2217. if (udc->td_pool == NULL) {
  2218. dma_pool_destroy(udc->qh_pool);
  2219. udc->qh_pool = NULL;
  2220. return -ENOMEM;
  2221. }
  2222. spin_lock_irqsave(udc->lock, flags);
  2223. info("hw_ep_max = %d", hw_ep_max);
  2224. udc->gadget.dev.driver = NULL;
  2225. retval = 0;
  2226. for (i = 0; i < hw_ep_max/2; i++) {
  2227. for (j = RX; j <= TX; j++) {
  2228. int k = i + j * hw_ep_max/2;
  2229. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2230. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2231. (j == TX) ? "in" : "out");
  2232. mEp->lock = udc->lock;
  2233. mEp->device = &udc->gadget.dev;
  2234. mEp->td_pool = udc->td_pool;
  2235. mEp->ep.name = mEp->name;
  2236. mEp->ep.ops = &usb_ep_ops;
  2237. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2238. INIT_LIST_HEAD(&mEp->qh.queue);
  2239. spin_unlock_irqrestore(udc->lock, flags);
  2240. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2241. &mEp->qh.dma);
  2242. spin_lock_irqsave(udc->lock, flags);
  2243. if (mEp->qh.ptr == NULL)
  2244. retval = -ENOMEM;
  2245. else
  2246. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2247. /* skip ep0 out and in endpoints */
  2248. if (i == 0)
  2249. continue;
  2250. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2251. }
  2252. }
  2253. if (retval)
  2254. goto done;
  2255. spin_unlock_irqrestore(udc->lock, flags);
  2256. udc->ep0out.ep.desc = &ctrl_endpt_out_desc;
  2257. retval = usb_ep_enable(&udc->ep0out.ep);
  2258. if (retval)
  2259. return retval;
  2260. udc->ep0in.ep.desc = &ctrl_endpt_in_desc;
  2261. retval = usb_ep_enable(&udc->ep0in.ep);
  2262. if (retval)
  2263. return retval;
  2264. spin_lock_irqsave(udc->lock, flags);
  2265. udc->gadget.ep0 = &udc->ep0in.ep;
  2266. /* bind gadget */
  2267. driver->driver.bus = NULL;
  2268. udc->gadget.dev.driver = &driver->driver;
  2269. spin_unlock_irqrestore(udc->lock, flags);
  2270. retval = bind(&udc->gadget); /* MAY SLEEP */
  2271. spin_lock_irqsave(udc->lock, flags);
  2272. if (retval) {
  2273. udc->gadget.dev.driver = NULL;
  2274. goto done;
  2275. }
  2276. udc->driver = driver;
  2277. pm_runtime_get_sync(&udc->gadget.dev);
  2278. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2279. if (udc->vbus_active) {
  2280. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2281. hw_device_reset(udc);
  2282. } else {
  2283. pm_runtime_put_sync(&udc->gadget.dev);
  2284. goto done;
  2285. }
  2286. }
  2287. retval = hw_device_state(udc->ep0out.qh.dma);
  2288. if (retval)
  2289. pm_runtime_put_sync(&udc->gadget.dev);
  2290. done:
  2291. spin_unlock_irqrestore(udc->lock, flags);
  2292. return retval;
  2293. }
  2294. /**
  2295. * ci13xxx_stop: unregister a gadget driver
  2296. *
  2297. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2298. */
  2299. static int ci13xxx_stop(struct usb_gadget_driver *driver)
  2300. {
  2301. struct ci13xxx *udc = _udc;
  2302. unsigned long i, flags;
  2303. trace("%p", driver);
  2304. if (driver == NULL ||
  2305. driver->unbind == NULL ||
  2306. driver->setup == NULL ||
  2307. driver->disconnect == NULL ||
  2308. driver != udc->driver)
  2309. return -EINVAL;
  2310. spin_lock_irqsave(udc->lock, flags);
  2311. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2312. udc->vbus_active) {
  2313. hw_device_state(0);
  2314. if (udc->udc_driver->notify_event)
  2315. udc->udc_driver->notify_event(udc,
  2316. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2317. spin_unlock_irqrestore(udc->lock, flags);
  2318. _gadget_stop_activity(&udc->gadget);
  2319. spin_lock_irqsave(udc->lock, flags);
  2320. pm_runtime_put(&udc->gadget.dev);
  2321. }
  2322. /* unbind gadget */
  2323. spin_unlock_irqrestore(udc->lock, flags);
  2324. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2325. spin_lock_irqsave(udc->lock, flags);
  2326. udc->gadget.dev.driver = NULL;
  2327. /* free resources */
  2328. for (i = 0; i < hw_ep_max; i++) {
  2329. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2330. if (!list_empty(&mEp->ep.ep_list))
  2331. list_del_init(&mEp->ep.ep_list);
  2332. if (mEp->qh.ptr != NULL)
  2333. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2334. }
  2335. udc->gadget.ep0 = NULL;
  2336. udc->driver = NULL;
  2337. spin_unlock_irqrestore(udc->lock, flags);
  2338. if (udc->td_pool != NULL) {
  2339. dma_pool_destroy(udc->td_pool);
  2340. udc->td_pool = NULL;
  2341. }
  2342. if (udc->qh_pool != NULL) {
  2343. dma_pool_destroy(udc->qh_pool);
  2344. udc->qh_pool = NULL;
  2345. }
  2346. return 0;
  2347. }
  2348. /******************************************************************************
  2349. * BUS block
  2350. *****************************************************************************/
  2351. /**
  2352. * udc_irq: global interrupt handler
  2353. *
  2354. * This function returns IRQ_HANDLED if the IRQ has been handled
  2355. * It locks access to registers
  2356. */
  2357. static irqreturn_t udc_irq(void)
  2358. {
  2359. struct ci13xxx *udc = _udc;
  2360. irqreturn_t retval;
  2361. u32 intr;
  2362. trace();
  2363. if (udc == NULL) {
  2364. err("ENODEV");
  2365. return IRQ_HANDLED;
  2366. }
  2367. spin_lock(udc->lock);
  2368. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2369. if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
  2370. USBMODE_CM_DEVICE) {
  2371. spin_unlock(udc->lock);
  2372. return IRQ_NONE;
  2373. }
  2374. }
  2375. intr = hw_test_and_clear_intr_active();
  2376. if (intr) {
  2377. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2378. isr_statistics.hndl.idx &= ISR_MASK;
  2379. isr_statistics.hndl.cnt++;
  2380. /* order defines priority - do NOT change it */
  2381. if (USBi_URI & intr) {
  2382. isr_statistics.uri++;
  2383. isr_reset_handler(udc);
  2384. }
  2385. if (USBi_PCI & intr) {
  2386. isr_statistics.pci++;
  2387. udc->gadget.speed = hw_port_is_high_speed() ?
  2388. USB_SPEED_HIGH : USB_SPEED_FULL;
  2389. if (udc->suspended && udc->driver->resume) {
  2390. spin_unlock(udc->lock);
  2391. udc->driver->resume(&udc->gadget);
  2392. spin_lock(udc->lock);
  2393. udc->suspended = 0;
  2394. }
  2395. }
  2396. if (USBi_UEI & intr)
  2397. isr_statistics.uei++;
  2398. if (USBi_UI & intr) {
  2399. isr_statistics.ui++;
  2400. isr_tr_complete_handler(udc);
  2401. }
  2402. if (USBi_SLI & intr) {
  2403. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2404. udc->driver->suspend) {
  2405. udc->suspended = 1;
  2406. spin_unlock(udc->lock);
  2407. udc->driver->suspend(&udc->gadget);
  2408. spin_lock(udc->lock);
  2409. }
  2410. isr_statistics.sli++;
  2411. }
  2412. retval = IRQ_HANDLED;
  2413. } else {
  2414. isr_statistics.none++;
  2415. retval = IRQ_NONE;
  2416. }
  2417. spin_unlock(udc->lock);
  2418. return retval;
  2419. }
  2420. /**
  2421. * udc_release: driver release function
  2422. * @dev: device
  2423. *
  2424. * Currently does nothing
  2425. */
  2426. static void udc_release(struct device *dev)
  2427. {
  2428. trace("%p", dev);
  2429. if (dev == NULL)
  2430. err("EINVAL");
  2431. }
  2432. /**
  2433. * udc_probe: parent probe must call this to initialize UDC
  2434. * @dev: parent device
  2435. * @regs: registers base address
  2436. * @name: driver name
  2437. *
  2438. * This function returns an error code
  2439. * No interrupts active, the IRQ has not been requested yet
  2440. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2441. */
  2442. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2443. void __iomem *regs)
  2444. {
  2445. struct ci13xxx *udc;
  2446. int retval = 0;
  2447. trace("%p, %p, %p", dev, regs, driver->name);
  2448. if (dev == NULL || regs == NULL || driver == NULL ||
  2449. driver->name == NULL)
  2450. return -EINVAL;
  2451. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2452. if (udc == NULL)
  2453. return -ENOMEM;
  2454. udc->lock = &udc_lock;
  2455. udc->regs = regs;
  2456. udc->udc_driver = driver;
  2457. udc->gadget.ops = &usb_gadget_ops;
  2458. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2459. udc->gadget.is_dualspeed = 1;
  2460. udc->gadget.is_otg = 0;
  2461. udc->gadget.name = driver->name;
  2462. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2463. udc->gadget.ep0 = NULL;
  2464. dev_set_name(&udc->gadget.dev, "gadget");
  2465. udc->gadget.dev.dma_mask = dev->dma_mask;
  2466. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2467. udc->gadget.dev.parent = dev;
  2468. udc->gadget.dev.release = udc_release;
  2469. retval = hw_device_init(regs);
  2470. if (retval < 0)
  2471. goto free_udc;
  2472. udc->transceiver = otg_get_transceiver();
  2473. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2474. if (udc->transceiver == NULL) {
  2475. retval = -ENODEV;
  2476. goto free_udc;
  2477. }
  2478. }
  2479. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2480. retval = hw_device_reset(udc);
  2481. if (retval)
  2482. goto put_transceiver;
  2483. }
  2484. retval = device_register(&udc->gadget.dev);
  2485. if (retval) {
  2486. put_device(&udc->gadget.dev);
  2487. goto put_transceiver;
  2488. }
  2489. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2490. retval = dbg_create_files(&udc->gadget.dev);
  2491. #endif
  2492. if (retval)
  2493. goto unreg_device;
  2494. if (udc->transceiver) {
  2495. retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
  2496. if (retval)
  2497. goto remove_dbg;
  2498. }
  2499. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2500. if (retval)
  2501. goto remove_trans;
  2502. pm_runtime_no_callbacks(&udc->gadget.dev);
  2503. pm_runtime_enable(&udc->gadget.dev);
  2504. _udc = udc;
  2505. return retval;
  2506. remove_trans:
  2507. if (udc->transceiver) {
  2508. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2509. otg_put_transceiver(udc->transceiver);
  2510. }
  2511. err("error = %i", retval);
  2512. remove_dbg:
  2513. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2514. dbg_remove_files(&udc->gadget.dev);
  2515. #endif
  2516. unreg_device:
  2517. device_unregister(&udc->gadget.dev);
  2518. put_transceiver:
  2519. if (udc->transceiver)
  2520. otg_put_transceiver(udc->transceiver);
  2521. free_udc:
  2522. kfree(udc);
  2523. _udc = NULL;
  2524. return retval;
  2525. }
  2526. /**
  2527. * udc_remove: parent remove must call this to remove UDC
  2528. *
  2529. * No interrupts active, the IRQ has been released
  2530. */
  2531. static void udc_remove(void)
  2532. {
  2533. struct ci13xxx *udc = _udc;
  2534. if (udc == NULL) {
  2535. err("EINVAL");
  2536. return;
  2537. }
  2538. usb_del_gadget_udc(&udc->gadget);
  2539. if (udc->transceiver) {
  2540. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2541. otg_put_transceiver(udc->transceiver);
  2542. }
  2543. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2544. dbg_remove_files(&udc->gadget.dev);
  2545. #endif
  2546. device_unregister(&udc->gadget.dev);
  2547. kfree(udc);
  2548. _udc = NULL;
  2549. }